Semiconductor device and manufacturing method thereof

Abstract

To enable suppression of occurrence of burrs on the back surface.SOLUTION: A semiconductor device 10 includes spacer portions 24a and 24b which are provided at the four corners of a metal plate 23 in plan view so as to protrude downward from the lower surface of the metal plate 23, respectively. Even when such an insulated circuit board 20 is accommodate in a cavity and sealed with a sealing member 50, the intrusion of the sealing member 50 into the four corners of the back surface of the insulated circuit board 20 is suppressed. Therefore, occurrence of burrs at the four corners of the back surface of the insulated circuit board 20 is suppressed. By suppressing the occurrence of burrs, deterioration in heat dissipation of the semiconductor device 10 is suppressed, and increase in the manufacturing cost of the semiconductor device 10 is also suppressed. Therefore, deterioration in reliability of the semiconductor device 10 is prevented.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] The semiconductor device includes a power device and is used as a power conversion device. The power device is, for example, an insulated gate bipolar transistor (IGBT) or a power metal oxide semiconductor field effect transistor (MOSFET). In the semiconductor device, a semiconductor chip including the power device and an insulating circuit board are sealed with a sealing member.

[0003] In manufacturing a semiconductor device, first, an insulating circuit board with a semiconductor chip bonded thereto is placed in a cavity within a predetermined mold. A sealing material is injected into the cavity to fill it. The mold is then removed to obtain a semiconductor device in which the semiconductor chip and insulating circuit board are sealed with the sealing material. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-267469 Summary of the Invention [Problem to be solved by the invention]

[0005] An insulating circuit board with a semiconductor chip bonded to it may warp downward due to heat generated when it is sealed with a sealing material. This creates gaps between the warped insulating circuit board and the surface where the cavity is located. The gaps are particularly large at the four corners of the insulating circuit board. The sealing material filled into the cavity also seeps into these gaps. Once the sealing material is filled and solidified, the sealing material that has entered the gaps turns into burrs. Because burrs have low thermal conductivity, semiconductor devices with burrs on their undersides have reduced heat dissipation. Furthermore, removing the burrs increases manufacturing costs. If the burrs are not properly removed, the remaining burrs can cause excessive stress in the semiconductor device. Therefore, the burrs reduce the reliability of the semiconductor device.

[0006] The present invention has been made in view of the above points, and has as its object to provide a semiconductor device in which the generation of burrs on the back surface is suppressed, and a method for manufacturing the semiconductor device. [Means for solving the problem]

[0007] According to one aspect of the present invention, there is provided an insulating circuit board in which a semiconductor chip, a rectangular metal plate, a rectangular insulating plate, and a circuit pattern are laminated in this order, the semiconductor chip being disposed on the circuit pattern on the front surface, and the insulating circuit board being warped downwardly convexly with the metal plate on the back surface facing downward; and an insulating circuit board in which four corners of the metal plate are provided in a plan view so as to protrude downward, and the insulating circuit board being warped downwardly convexly in a side view. The back surface of the metal plate The insulating circuit board has a spacer portion that is flush with the center portion or that protrudes below the center portion, and a sealing member that seals the front surface of the insulating circuit board, the side portion of the insulating circuit board, and the spacer side portion that faces outward from the spacer portion. The spacer portion has an annular shape in a plan view, is centered at the center of the metal plate, and is formed on the outer edge of the metal plate so as to surround the center. A semiconductor device is provided.

[0008] According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device using an insulating circuit board, the insulating circuit board being formed by stacking a rectangular metal plate, a rectangular insulating plate, and a circuit pattern in this order, with a semiconductor chip disposed on the circuit pattern on its front surface, and warping downwardly convexly with the metal plate on its back surface facing downward, and a mold including an arrangement surface on which the insulating circuit board is disposed and having a storage area for accommodating the insulating circuit board; an arrangement step of arranging the insulating circuit board on the arrangement surface of the mold with spacers disposed at four corners of the metal plate; and a sealing step of injecting a sealing material toward the insulating circuit board from an injection port provided in the mold above the front surface of the insulating circuit board while heating the inside of the storage area, thereby filling the storage area and sealing the insulating circuit board. and in the sealing step, the insulating circuit board is pressed against the arrangement surface of the mold by the sealing member, so that the back surface of the insulating circuit board comes into contact with the arrangement surface. A method for manufacturing a semiconductor device is provided. [Effects of the Invention]

[0009] According to the disclosed technique, the occurrence of burrs is suppressed, the deterioration of heat dissipation properties is prevented, and the deterioration of reliability of the semiconductor device can be suppressed. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment; [Figure 2] 1 is a side cross-sectional view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 2 is a rear view of the semiconductor device according to the first embodiment. [Figure 4] 1A to 1C are plan views (part 1) illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 5] 1A to 1C are side cross-sectional views (part 1) illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 6] 4 is a plan view (part 2) illustrating the manufacturing process of the semiconductor device according to the first embodiment; FIG. [Figure 7] 5A to 5C are side cross-sectional views (part 2) illustrating the manufacturing process of the semiconductor device according to the first embodiment. [Figure 8] 1 is a side cross-sectional view of a semiconductor device to which a heat dissipation unit according to a first embodiment is attached. [Figure 9] FIG. 10 is a rear view of the semiconductor device according to the first modification of the first embodiment. [Figure 10] FIG. 10 is a side cross-sectional view of a semiconductor device according to a first modification of the first embodiment. [Figure 11] FIG. 10 is a rear view of the semiconductor device according to the second modification of the first embodiment. [Figure 12] FIG. 10 is a side cross-sectional view of a semiconductor device according to a second modification of the first embodiment. [Figure 13] FIG. 10 is a side cross-sectional view of a semiconductor device according to a third modification of the first embodiment. [Figure 14] FIG. 4 is a side cross-sectional view of a semiconductor device according to a modified example 4-1 of the first embodiment. [Figure 15] FIG. 4 is a rear view of the semiconductor device according to the modified example 4-1 of the first embodiment. [Figure 16] 4A to 4C are cross-sectional views (part 1) illustrating a manufacturing process of a semiconductor device according to a modification 4-1 of the first embodiment. [Figure 17] 4A to 4C are cross-sectional views (part 2) illustrating a manufacturing process of the semiconductor device according to the modification 4-1 of the first embodiment. [Figure 18] 4A to 4C are cross-sectional views (part 3) illustrating a manufacturing process of the semiconductor device according to the modification 4-1 of the first embodiment. [Figure 19] FIG. 4 is a rear view (part 1) of the semiconductor device according to the modified example 4-2 of the first embodiment. [Figure 20] FIG. 4 is a rear view (part 2) of the semiconductor device according to the modified example 4-2 of the first embodiment. [Figure 21] FIG. 11 is a side cross-sectional view of a semiconductor device according to a fifth modified example of the first embodiment. [Figure 22] FIG. 10 is a side cross-sectional view of a semiconductor device according to a second embodiment. [Figure 23] 10A to 10C are side cross-sectional views showing a manufacturing process of a semiconductor device according to a second embodiment. [Figure 24] FIG. 10 is a side cross-sectional view of a semiconductor device to which a heat dissipation unit according to a second embodiment is attached. [Figure 25] FIG. 10 is a side cross-sectional view of a semiconductor device according to a modified example of the second embodiment. [Figure 26]10A to 10C are side cross-sectional views showing a manufacturing process of a semiconductor device according to a modified example of the second DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "upper surface" refer to the surface facing upward (+Z direction) in the semiconductor device 10 of FIGS. 1 to 3. Similarly, "up" refers to the upward direction (+Z direction) in the semiconductor device 10 of FIGS. 1 to 3. The terms "back surface" and "lower surface" refer to the surface facing downward (-Z direction) in the semiconductor device 10 of FIGS. 1 to 3. Similarly, "lower" refers to the downward direction (-Z direction) in the semiconductor device 10 of FIGS. 1 to 3. Similar directions will be used in other drawings as necessary. The terms "front surface," "upper surface," "upper," "back surface," "lower surface," "lower," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "upper" and "lower" do not necessarily refer to the vertical direction relative to the ground. In other words, the "upper" and "lower" directions are not limited to the direction of gravity. In the following description, the term "main component" refers to a component containing 80 vol% or more of a component.

[0012] [First embodiment] Hereinafter, a semiconductor device according to a first embodiment will be described with reference to the drawings using FIGS. 1 to 3. FIG. 1 is a plan view of the semiconductor device according to the first embodiment, FIG. 2 is a side cross-sectional view of the semiconductor device according to the first embodiment, and FIG. 3 is a rear view of the semiconductor device according to the first embodiment. FIG. 1 is a perspective plan view of a semiconductor device 10. FIG. 2 is a cross-sectional view taken along dashed dotted line YY in FIG. 1.

[0013] The semiconductor device 10 includes an insulating circuit board 20, semiconductor chips 31 and 32, lead frames 40, 41a to 41j, 43, and 44, bonding wires 45, and a sealing member 50. The semiconductor chips 31 and 32 are arranged on the front surface (upper surface) of the insulating circuit board 20. The semiconductor chips 31 and 32 and the front surface and side portions of the insulating circuit board 20 are sealed with the sealing member 50. The insulating circuit board 20 is warped downward with its back surface facing downward. The warping of the insulating circuit board 20 will be described later. The insulating circuit board 20 has spacers 24a to 24d at its four corners, each protruding downward.

[0014] Insulated circuit board 20 has a rectangular shape in a plan view. Insulated circuit board 20 includes insulating plate 21, circuit patterns 22a and 22b provided on the front surface (upper surface) of insulating plate 21, and metal plate 23 provided on the back surface (lower surface) of insulating plate 21. Semiconductor chips 31 and 32 are mechanically and electrically connected to the front surfaces (upper surfaces) of circuit patterns 22a and 22b by solder 33a.

[0015] The insulating plate 21 has a rectangular shape in a plan view. The corners of the insulating plate 21 may be rounded or C-chamfered. The insulating plate 21 is made of ceramics with good thermal conductivity. The ceramics may be made of a material containing aluminum oxide, aluminum nitride, or silicon nitride as a main component, for example. The thickness of the insulating plate 21 is 0.2 mm or more and 2.0 mm or less.

[0016] Circuit patterns 22a and 22b are formed over the entire surface of insulating plate 21 except for the edges. Preferably, in a plan view, the ends of circuit patterns 22a and 22b on the outer periphery of insulating plate 21 overlap the end of metal plate 23 on the outer periphery of insulating plate 21. This maintains a stress balance between insulating circuit board 20 and metal plate 23 on the back surface of insulating plate 21. Damage to insulating plate 21, such as excessive warping and cracking, is suppressed.

[0017] The thickness of the circuit patterns 22a and 22b is 0.1 mm or more and 2.0 mm or less. The circuit patterns 22a and 22b are made of a metal with excellent conductivity. Such a metal is, for example, copper, aluminum, or an alloy containing at least one of these. The surfaces of the circuit patterns 22a and 22b may be plated to improve corrosion resistance. Examples of plating materials used in this case include nickel, nickel-phosphorus alloy, and nickel-boron alloy. The circuit patterns 22a and 22b for the insulating plate 21 are obtained by forming a metal plate on the front surface of the insulating plate 21 and then subjecting the metal plate to etching or other processing. Alternatively, the circuit patterns 22a and 22b may be cut out from a metal plate in advance and then pressure-bonded to the front surface of the insulating plate 21. Note that the circuit patterns 22a and 22b are merely examples. The number, shape, size, and other characteristics of the circuit patterns may be appropriately selected as needed.

[0018] The metal plate 23 has a rectangular shape in a plan view. The corners may be rounded or C-chamfered. The metal plate 23 is smaller than the insulating plate 21 and is formed on the entire surface of the insulating plate 21 except for the edges. The metal plate 23 is mainly composed of a metal with excellent thermal conductivity. The metal is, for example, copper, aluminum, or an alloy containing at least one of these. The thickness of the metal plate 23 is 0.1 mm or more and 2.0 mm or less. The metal plate 23 may be plated to improve its corrosion resistance. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy.

[0019] Examples of such an insulating circuit board 20 include a DCB (Direct Copper Bonding) board and an AMB (Active Metal Brazed) board. When semiconductor chips 31 and 32 are joined to circuit patterns 22a and 22b of the insulating circuit board 20 with solder 33a, a heat treatment is performed. In the insulating circuit board 20, the insulating plate 21, circuit patterns 22a and 22b, and metal plate 23 have different thermal expansion coefficients. When heated, the insulating circuit board 20 warps so that the center of metal plate 23 is convex downward (in the -Z direction) (see, for example, the insulating circuit board 20 in FIG. 5).

[0020] Furthermore, spacers 24a to 24d are formed at the four corners of the rear surface of the metal plate 23 of the insulating circuit board 20, protruding downward (in the -Z direction). Each of the spacers 24a to 24d has a rectangular shape in a plan view (XY plane). Each of the spacers 24a to 24d has a rectangular shape in a cross-sectional view (XZ plane or YZ plane). Each of the spacers 24a to 24d may be a quadrangular prism. The spacers 24a to 24d are provided at the four corners of the metal plate 23 so that one corner of each spacer coincides with a corner of the metal plate 23 and two sides constituting the corner correspond to the sides of the metal plate 23. Therefore, the shape of the spacers 24a to 24d in a plan view (XY plane) is not limited to a rectangular shape, as long as they have two orthogonal sides that correspond to an area including the corner of the metal plate 23. Examples of the spacers 24a to 24d include an L-shape and a right-angled triangle shape. Various modifications of the spacer portions 24a to 24d will be described later.

[0021] Alternatively, spacers 24a-24d are formed protruding downward (in the -Z direction) near the four corners of the rear surface of metal plate 23 of insulating circuit board 20. The outer edges of spacers 24a-24d are formed on the rear surface of metal plate 23 of insulating circuit board 20 at least outside the areas corresponding to the bonding areas of semiconductor chips 31 and 32 when viewed from above. In this case, it is sufficient if they have two sides parallel to the two sides that form the corners of metal plate 23. Examples of such spacers 24a-24d include rectangular, L-shaped, and right-angled triangular shapes.

[0022] The height of the spacers 24a to 24d is equal to or greater than the warpage Hc of the insulating circuit board 20 and equal to or less than the warpage Hc+200 μm. As shown in FIG. 2, the warpage Hc is the height from position P0, which is the center of the insulating circuit board 20 that is warped downward, to position P1, which is the edge of the insulating circuit board 20 (metal plate 23). The warpage Hc is the height from position P0, which is the lowest position (in the -Z direction) on the back surface of the metal plate 23, to position P1, which is the highest position (in the +Z direction), with the XY plane, which is the front surface of the semiconductor chips 31 and 32, serving as the reference plane. The warpage Hc depends on the material of the insulating circuit board 20 and other factors. For example, the warpage Hc is equal to or greater than 50 μm and equal to or less than 200 μm. 2 shows a case where the back surfaces of spacer portions 24a to 24d formed at the four corners of insulating circuit board 20 are substantially flush with the center of the back surface of insulating circuit board 20. Furthermore, the front surfaces (surfaces that come into contact with metal plate 23) of spacer portions 24a to 24d may be inclined in accordance with the warping of metal plate 23. This allows the back surfaces of spacer portions 24a to 24d provided at the four corners of the back surface of insulating circuit board 20 to be kept substantially horizontal.

[0023] The spacer portions 24a to 24d are made of a material with excellent thermal conductivity. Such a material is, for example, primarily composed of metal or ceramic. Such a metal is, for example, copper, aluminum, tin, or an alloy containing at least one of these. Preferably, such a metal is the same type as the metal plate 23. Furthermore, the spacer portions 24a to 24d may be formed integrally with the metal plate 23. Such ceramic is, for example, a material primarily composed of aluminum oxide, aluminum nitride, or silicon nitride. The surfaces of the spacer portions 24a to 24d may be plated to improve corrosion resistance. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy.

[0024] The semiconductor chips 31 and 32 include switching elements made of silicon or silicon carbide. The switching elements are, for example, IGBTs or power MOSFETs. If the semiconductor chips 31 and 32 are IGBTs, they have a collector electrode as a main electrode on their back surfaces. Furthermore, the front surfaces of the semiconductor chips 31 and 32 have a gate electrode as a control electrode and an emitter electrode as a main electrode, respectively. If the semiconductor chips 31 and 32 are power MOSFETs, they have a drain electrode as a main electrode on their back surfaces. Furthermore, the front surfaces of the semiconductor chips 31 and 32 have a gate electrode as a control electrode and a source electrode as a main electrode, respectively. The back surfaces of the semiconductor chips 31 and 32 are mechanically and electrically bonded to the circuit patterns 22a and 22b via solder 33a. Lead frames 42 and 44 are mechanically and electrically bonded to the main electrodes on the front surfaces of the semiconductor chips 31 and 32 via solder 33b. Furthermore, bonding wires 45 are mechanically and electrically joined to the control electrodes on the front surfaces of the semiconductor chips 31 and 32 as appropriate.

[0025] Alternatively, the semiconductor chips 31 and 32 include diodes made of silicon or silicon carbide. The diodes are, for example, FWDs (Free Wheeling Diodes) such as SBDs (Schottky Barrier Diodes) and PiN (P-intrinsic-N) diodes. The semiconductor chips 31 and 32 each have an output electrode (cathode electrode) as a main electrode on the back surface and an input electrode (anode electrode) as a main electrode on the front surface. The back surfaces of the semiconductor chips 31 and 32 are mechanically and electrically bonded to the circuit patterns 22a and 22b via solder 33a. Lead frames 42 and 44 are also mechanically and electrically bonded to the main electrodes on the front surfaces of the semiconductor chips 31 and 32 via solder 33b.

[0026] Furthermore, instead of the semiconductor chips 31 and 32, an RC (Reverse-Conducting)-IGBT having both the functions of an IGBT and an FWD may be used. Furthermore, auxiliary emitter electrodes may be provided on the front surfaces of the semiconductor chips 31 and 32 as control electrodes. Furthermore, temperature sensing electrodes and current sensing electrodes may be provided on the front surfaces of the semiconductor chips 31 and 32 as control electrodes. In this case, bonding wires 45 are mechanically and electrically joined to the respective control electrodes as appropriate. Furthermore, the first embodiment merely illustrates the case where two sets of semiconductor chips 31 and 32 are provided. The number of sets is not limited to two, and any number of sets may be provided depending on the specifications of the semiconductor device 10.

[0027] Lead frames 40, 41a to 41j, 43, One end of the lead frame 44 is electrically connected to the semiconductor chips 31 and 32 inside the sealing member 50. 43, 44 is the other end individually The other end of the lead frame 43 may be a positive input terminal (P terminal). The other end of the lead frame 44 may be a negative input terminal (N terminal). The lead frames 40, 41a to 41j, and 42 to 44 are made of a metal with excellent conductivity. Examples of such metals include copper, aluminum, and alloys containing at least one of these. The surfaces of the lead frames 40, 41a to 41j, and 42 to 44 may be plated to improve corrosion resistance. Examples of the plating material used include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0028] One end of the lead frame 40 is joined to the circuit pattern 22b inside the sealing member 50 via solder 33b as a joining member. The joining member is not limited to solder 33b, but may be a sintered body. Alternatively, one end of the lead frame 40 is directly joined to the circuit pattern 22b inside the sealing member 50 by, for example, laser welding or ultrasonic welding. The other end of the lead frame 40 extends outward (in the +X direction) from the sealing side surface 50e of the sealing member 50. The other end of the lead frame 40 may be an external connection terminal (output terminal) connected to an external device (not shown). The other end of the lead frame 40 is located above (in the +Z direction) one end of the lead frame 40. The lead frame 40 has an intermediate portion connecting the one end and the other end. The intermediate portion extends vertically upward (in the +Z direction) or diagonally upward from the one end and is connected to the other end. Furthermore, the other end of the lead frame 40 is located above (in the +Z direction) the front surfaces of the semiconductor chips 31 and 32.

[0029] One end of each of the lead frames 41a to 41d is electrically connected to the semiconductor chip 32 via a bonding wire 45 inside the sealing member 50. The other end of each of the lead frames 41a to 41d extends from the sealing side surface 50e of the sealing member 50 to the outside (+X direction). The other end of each of the lead frames 41a to 41d may be an external connection terminal (control terminal) connected to an external device (not shown). One end of each of the lead frames 41f to 41j is electrically connected to the semiconductor chip 31 via a bonding wire 45 inside the sealing member 50. The other end of each of the lead frames 41f to 41j extends from the sealing side surface 50e of the sealing member 50 to the outside (+X direction). The one end and the other end of each of the lead frames 41a to 41d and 41f to 41j may be at the same height (Z direction). In other words, the lead frames 41a to 41d and 41f to 41j may be straight in a side view. The other ends of the lead frames 41a to 41d and the lead frames 41f to 41j may be located above the front surfaces of the semiconductor chips 31 and 32 (in the +Z direction).

[0030] The lead frame 42 is sealed with a sealing member 50. One end of the lead frame 42 is joined to the main electrode of the semiconductor chip 31 via solder 33b as a joining member. The other end of the lead frame 42 is mechanically and electrically joined to the circuit pattern 22b via solder 33b as a joining member. The joining member is not limited to solder 33b, and may be a sintered body. Alternatively, the other end of the lead frame 42 is directly joined to the circuit pattern 22b by, for example, laser welding or ultrasonic welding.

[0031] One end of the lead frame 43 is electrically and mechanically connected to the circuit pattern 22a inside the sealing member 50 via solder 33b as a joining member. The joining member is not limited to solder 33b, and may be a sintered body. Alternatively, one end of the lead frame 43 is directly joined to the circuit pattern 22a inside the sealing member 50 by, for example, laser welding or ultrasonic welding. The other end of the lead frame 43 extends outward (in the -X direction) from the sealing side surface 50d of the sealing member 50. The other end of the lead frame 43 may be an external connection terminal (P terminal) that is connected to an external device (not shown).

[0032] One end of the lead frame 44 is mechanically and electrically joined to the main electrode of the semiconductor chip 32 inside the sealing member 50 via solder 33b as a joining member. The joining member is not limited to solder 33b, and may be a sintered body. The other end of the lead frame 44 extends outward (in the -X direction) from the sealing side surface 50d of the sealing member 50. The other end of the lead frame 44 may be an external connection terminal (N terminal) that is connected to an external device (not shown).

[0033] The other end of each of the lead frames 43, 44 is located higher (in the +Z direction) than one end of each of the lead frames 43, 44. Each of the lead frames 43, 44 has an intermediate portion connecting one end to the other end. The intermediate portion extends vertically upward (in the +Z direction) or diagonally upward from the one end of each of the lead frames 43, 44 and is connected to the other end of each of the lead frames 43, 44. Furthermore, the other end of each of the lead frames 43, 44 is located higher (in the +Z direction) than the front surfaces of the semiconductor chips 31, 32. Note that the lead frames 40, 41a to 41j, 42, 43, and 44 are merely examples. The shape, size, extension direction, etc. may be selected appropriately as needed.

[0034] The bonding wire 45 is mainly composed of a metal with excellent conductivity. The metal may be, for example, aluminum, copper, or an alloy containing at least one of these. The bonding wire 45 is made of copper or a copper alloy. The diameter of the bonding wire 45 is preferably 25 μm or more and 1 mm or less.

[0035] The sealing member 50 has a rectangular parallelepiped shape. The sealing member 50 has a sealing top surface 50a, sealing side surfaces 50b to 50e, and a sealing bottom surface 50f. The joints between the sealing side surfaces 50b to 50e may be rounded. The sealing member 50 seals the insulating circuit board 20, the semiconductor chips 31 and 32, and the lead frames 40, 41a to 41j, and 42 to 44. The sealing member 50 seals parts of the lead frames 40, 41a to 41j, 43, and 44. The sealing member 50 seals the entire periphery of the side surfaces of the insulating circuit board 20 as well as the outward-facing sides (spacer sides) of the spacer portions 24a to 24d. In the first embodiment, the sealing bottom surface 50f is flush with the bottom surfaces of the spacer portions 24a to 24d and the center of the back surface of the insulating circuit board 20.

[0036] Such a sealing member 50 includes a thermosetting resin and a filler contained in the thermosetting resin. The thermosetting resin is, for example, an epoxy resin, a phenolic resin, or a maleimide resin. An example of such a sealing member is an epoxy resin containing a filler. The filler is an inorganic material. Examples of inorganic materials include silicon oxide, aluminum oxide, boron nitride, and aluminum nitride.

[0037] Next, a manufacturing method of the semiconductor device 10 will be described with reference to FIGS. 4 to 7. FIGS. 4 and 6 are plan views showing the manufacturing process of the semiconductor device of the first embodiment, and FIGS. 5 and 7 are side cross-sectional views showing the manufacturing process of the semiconductor device of the first embodiment. Note that in FIGS. 5 to 7, the frame portion of the tie bar 46, which will be described later, is omitted. Also, FIG. 5 is a side cross-sectional view taken along the dashed dotted line XX in FIG. 6, and FIG. 6 is a plan cross-sectional view taken along the dashed dotted line XX in FIG. 5. FIG. 7 corresponds to the side cross-sectional view of FIG. 6.

[0038] First, the components of the semiconductor device 10 are prepared. The components include, for example, an insulating circuit board 20, semiconductor chips 31 and 32, lead frames 40, 41a to 41j, 42 to 44, and spacers 24a to 24d. When the semiconductor chips 31 and 32 are bonded to the circuit patterns 22a and 22b of the insulating circuit board 20 via solder 33a, heating causes downward warping of the insulating circuit board 20, as described above. The lead frames 40, 41a to 41j, 43, and 44 are integrally connected by tie bars 46, which are frame-shaped members. The lead frames 40, 42 to 44 are bonded to the insulating circuit board 20 and the semiconductor chips 31 and 32 as shown in FIG. 4, and the semiconductor chips 31 and 32 are mechanically and electrically bonded to the locations corresponding to the lead frames 41a to 41j with bonding wires 45. The semiconductor chips 31 and 32 and the lead frames 40 and 42 are then bonded to the insulating circuit board 20 and the semiconductor chips 31 and 32. ~ The insulating circuit board 20 to which 44 is bonded may be warped downward (in the -Z direction). The amount of warping Hc in this case is smaller than the amount of warping Hc after resin sealing. The amount of warping Hc depends on the material of the insulating circuit board 20, but is, for example, 10 μm or more and 150 μm or less.

[0039] Next, the insulating circuit board 20 to which the semiconductor chips 31, 32 and the lead frames 40, 41a-41j, 42-44 have been joined in this manner is set in a sealing mold 60, as shown in FIGS. 5 and 6. The sealing mold 60 is mainly composed of a material that is hard and heat-resistant and has a small thermal expansion coefficient. Such a material is, for example, steel. The sealing mold 60 is, for example, cubic in shape and has a mold top surface 60a, mold side surfaces 60b-60e, and a mold bottom surface 60f. The sealing mold 60 is heated to a predetermined temperature at which the sealing resin hardens. The predetermined temperature is, for example, 100°C or higher and 200°C or lower.

[0040] The sealing mold 60 includes an upper mold 61 and a lower mold 62 that can be separated by mold side surfaces 60b to 60e. The upper mold 61 and the lower mold 62 each have a recess formed so that they do not penetrate the bottom. A space (cavity 63b) is formed inside by combining the recesses of the upper mold 61 and the lower mold 62. The upper mold 61 is composed of a frame portion and an upper cover portion. The back surface of the frame portion of the upper mold 61 (the surface that comes into contact with the lower mold 62) is provided with grooves that serve as a gate 63a through which the sealing member 50 is introduced and an outlet (not shown) through which excess resin is discharged. The lower mold 62 is composed of a frame portion that faces the frame portion of the upper mold 61 and a lower bottom portion. The bottom surface of the recess of the lower mold 62 has a placement surface 63c on which the insulating circuit board 20 is placed. The placement surface 63c is flat (parallel to the XY plane). The front surface of the frame portion of the lower die 62 (the surface that comes into contact with the upper die 61) is provided with grooves in which the lead frames 40, 41a to 41j, 43, 44 and tie bars 46 are placed.

[0041] The insulating circuit board 20 is placed in the recess of the lower mold 62, and the upper mold 61 is placed on the lower mold 62, thereby storing the semiconductor chips 31, 32 and the insulating circuit board 20 in the cavity 63b. At this time, the lead frames 40, 41a to 41j, 43, 44 and tie bars 46 are placed in the grooves on the front surface of the frame part of the lower mold 62, and the insulating circuit board 20 is placed on the placement surface 63c.

[0042] Furthermore, lower mold 62 has four press holes formed at positions facing the four corners of metal plate 23 of insulating circuit board 20. Of the four press holes, press holes 62a and 62b along mold side surfaces 60b and 60c are shown in FIG. 5. Spacer portions 24a to 24d are respectively arranged on the press holes on arrangement surface 63c. Press pins are provided in the press holes of lower mold 62 so as to be movable in the Z direction. Note that FIG. 5 shows press pins 64a and 64b provided in press holes 62a and 62b. The press pins are initially housed in the press holes and are controlled to protrude simultaneously at a predetermined speed from all press holes at a predetermined timing. After the sealing member 50 has hardened, the insulating circuit board 20 and semiconductor chips 31, 32, etc. sealed with the sealing member 50 can be removed from the lower mold 62 by protruding the pressure pins 64a, 64b upward (in the +Z direction) from the bottom surface of the lower mold 62.

[0043] Furthermore, when the insulating circuit board 20 is placed on the placement surface 63c of the lower mold 62, spacers 24a to 24d are provided at the four corners of the metal plate 23. At this time, the tips of the pressing pins 64a and 64b are flush with the placement surface 63c of the lower mold 62. That is, the spacers 24a to 24d are positioned above the pressing holes 62a and 62b in the placement surface 63c, respectively. Alternatively, the tips of the pressing pins 64a and 64b may be protruded a predetermined amount from the placement surface 63c of the lower mold 62 so that the spacers 24a to 24d are hooked onto the tips of the pressing pins 64a and 64b. This prevents misalignment of the spacers 24a to 24d and tilting of the insulating circuit board 20 when the sealing member 50 is injected, thereby enabling stable sealing of the insulating circuit board 20.

[0044] Furthermore, the upper mold 61 is formed with a gate 63a at least above (in the +Z direction) the semiconductor chips 31, 32 when the insulating circuit board 20 is set. In the case of FIG. 5, the gate 63a is provided above the portion of the upper mold 61 that corresponds to the lead frame 40. In FIG. 5, the gate 63a is parallel to the X direction and communicates with the cavity 63b. Furthermore, as shown in FIG. 6, the gate 63a is formed at the upper mold 61. Left sideand the tie bar 46 is located at the approximate center of the lead frame 40. To oppose is formed.

[0045] In this manner, the molds are opened to separate the upper mold 61 and the lower mold 62, and the insulating circuit board 20 is set in the lower mold 62. The upper mold 61 is then clamped to cover the lower mold 62, and the insulating circuit board 20 is set in the cavity 63b of the sealing mold 60. At this time, the insulating circuit board 20 is heated by the sealing mold 60, causing it to warp downward. Note that the spacer portions 24a to 24d arranged at the four corners of the insulating circuit board 20 are in direct contact with the mounting surface 63c, and the metal plate 23 of the insulating circuit board 20, except for the four corners, is slightly raised from the mounting surface 63c. In this case, the raised portion between the center of the metal plate 23 and the mounting surface 63c is, for example, 10 μm or more and 200 μm or less.

[0046] The encapsulating mold 60 is maintained at a predetermined temperature, and uncured encapsulating material 50 is injected through the gate 63a. The gate 63a is formed between the lead frames 43 and 44. The encapsulating material 50 injected through the gate 63a fills the cavity 63b along the dashed arrows shown in FIGS. 5 and 6. That is, the encapsulating material 50 injected through the gate 63a is injected into the cavity 63b from between the lead frames 43 and 44. The encapsulating material 50 then flows from above onto the insulating circuit board 20 and the semiconductor chips 31 and 32, moving from the mold side surface 60d toward the mold side surface 60e. As the encapsulating material 50 moves in this manner, it also spreads toward the mold side surfaces 60b and 60c. In this way, the encapsulating material 50 encapsulates the insulating circuit board 20 and the semiconductor chips 31 and 32. That is, the insulating circuit board 20 and the semiconductor chips 31 and 32 are pressed toward the placement surface 63c by the encapsulating material 50. As a result, the back surface of metal plate 23 of insulating circuit board 20, which had been floating above arrangement surface 63c, is pressed against arrangement surface 63c, and an area including the center of the back surface of metal plate 23 of insulating circuit board 20 comes into contact with arrangement surface 63c.

[0047] Furthermore, when sealing member 50 is injected into cavity 63b, it reaches the side portions of insulating circuit board 20 and fills the spaces between the side portions of insulating circuit board 20 and cavity 63b, as shown by the dashed lines in Fig. 7. At this time, although insulating circuit board 20 is warped downward, spacers 24a to 24d are provided at the four corners of metal plate 23. In addition, insulating circuit board 20 is pressed against mounting surface 63c by sealing member 50. Sealing member 50 that has filled the spaces between the side portions of insulating circuit board 20 and cavity 63b cannot get into the spaces between the mounting surface 63c and the four corners of the warped insulating circuit board 20 (see Fig. 3).

[0048] If the spacers 24a to 24d were not provided, the four corners of the insulating circuit board 20 would be warped upward (in the +Z direction), creating gaps between the four corners of the metal plate 23 and the mounting surface 63c. The sealing member 50 would penetrate through these gaps. Furthermore, the intrusion of the sealing member 50 through these gaps would press the insulating circuit board 20 upward (in the +Z direction), potentially causing the sealing member 50 to penetrate near the center of the insulating circuit board 20. If the sealing member 50 solidifies in this state, the sealing member 50 in the gaps would become burrs. Because burrs have low thermal conductivity, a semiconductor device 10 with burrs on its underside would have poor heat dissipation. In particular, if the sealing member 50 solidifies in this state, near the center of the insulating circuit board 20, which corresponds to the underside of the semiconductor chips 31 and 32, the semiconductor chips 31 and 32 could be damaged by overheating during operation of the semiconductor device 10. Furthermore, removing the burrs would require a complex process, increasing manufacturing costs. Therefore, burrs reduce the reliability of the semiconductor device 10. Even when the spacers 24a-24d are provided, the sealing member 50 may, in some cases, penetrate into the sides of the spacers 24a-24d. However, because the sealing member 50 flows onto the insulating circuit board 20 from above and presses the insulating circuit board 20 against the placement surface 63c, the sealing member 50 does not penetrate into the center of the metal plate 23 that contacts the underside of the semiconductor chips 31 and 32. Even if burrs are generated, they are small enough not to significantly reduce the reliability of the semiconductor device 10. Therefore, the sealing member 50 seals the sides of the insulating circuit board 20 and the outward-facing sides (spacer sides) of the spacers 24a-24d.

[0049] After the sealing member 50 is injected and the sealing member 50 is in a cured or semi-cured state, the sealing mold 60 is opened and the pressure pins 64a and 64b are protruded. As a result, the semiconductor device 10 in which the insulating circuit board 20 and the semiconductor chips 31 and 32 are sealed is removed from the sealing mold 60. Finally, excess resin remaining on the gate 63a and the discharge port is removed, and the tie bars 46 are cut off, thereby obtaining the semiconductor device 10 shown in FIGS. 1 to 3.

[0050] Next, a case where a heat dissipation unit is attached to the back surface (sealing bottom surface 50f) of such a semiconductor device 10 will be described with reference to Fig. 8. Fig. 8 is a side cross-sectional view of a semiconductor device to which the heat dissipation unit of the first embodiment is attached. Fig. 8 shows a case where a heat dissipation unit is attached to the semiconductor device 10 corresponding to the side cross-sectional view of Fig. 2.

[0051] A heat dissipation unit 56 is provided on the back surface of the semiconductor device 10 via a thermal interface material (TIM) 55. The semiconductor device 10 and the heat dissipation unit 56 may be fastened together with bolts (not shown). The heat dissipation unit 56 is made of a metal with excellent thermal conductivity. Examples of such metals include aluminum, iron, silver, copper, or an alloy containing at least one of these. The heat dissipation unit 56 may be, for example, a fin, a heat sink composed of multiple fins, or a water-cooled cooling device. Note that FIG. 8 illustrates an example in which heat dissipation fins are attached. The surface of the heat dissipation unit 56 may be plated to improve corrosion resistance. Examples of plating materials used in this case include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy. The TIM 55 is a thermal grease or a heat dissipation sheet. The thermal grease is, for example, silicone mixed with a filler. The filler may be, for example, ceramic or metal. The heat dissipation sheet may be, for example, a graphite sheet, an acrylic sheet, or a silicone sheet mixed with a filler. The filler may also be, for example, ceramic or metal. Note that the TIM 55 is not limited to these, and may also be metal such as solder or brazing material.

[0052] Even if the rear surface of the semiconductor device 10 is warped and not flat due to the spacers 24a to 24d, forming the TIM 55 on the rear surface of the semiconductor device 10 enables bonding while suppressing gaps between the rear surface of the semiconductor device 10 and the front surface of the heat dissipation unit 56. Therefore, the heat dissipation unit 56 can be properly attached to the rear surface of the semiconductor device 10.

[0053] The semiconductor device 10 includes an insulating circuit board 20 in which semiconductor chips 31 and 32, a rectangular metal plate 23, a rectangular insulating plate 21, and circuit patterns 22a and 22b are stacked in this order, with the semiconductor chips 31 and 32 disposed on the circuit patterns 22a and 22b on the front surface, and which is warped downwardly with the metal plate 23 on the back surface facing downward. Furthermore, the semiconductor device 10 includes spacers 24a to 24d protruding downward from the four corners of the metal plate 23 in a plan view. Even when the insulating circuit board 20 is housed in a cavity 63b and sealed with a sealing member 50, the sealing member 50 is prevented from entering the four corners of the back surface of the insulating circuit board 20. Therefore, burrs are prevented from occurring at the four corners of the back surface of the insulating circuit board 20. Suppressing burrs prevents a decrease in the heat dissipation performance of the semiconductor device 10 and an increase in the manufacturing cost of the semiconductor device 10. This prevents a decrease in the reliability of the semiconductor device 10.

[0054] Furthermore, a heat dissipation unit 56 can be attached to the back surface of the semiconductor device 10 via a TIM 55. Even if the back surface of the semiconductor device 10 is not flat due to warping and the spacers 24a to 24d, the use of the TIM 55 ensures reliable bonding to the heat dissipation unit 56. This improves the heat dissipation performance of the semiconductor device 10. Various forms of the spacer portions 24a to 24d will be described below.

[0055] [Variation 1] In Modification 1, a case in which spacer portions are provided along the outer edges (including the four corners) of metal plate 23 of insulating circuit board 20 will be described with reference to FIGS. 9 and 10. FIG. 9 is a rear view of the semiconductor device of Modification 1 of the first embodiment, and FIG. 10 is a side cross-sectional view of the semiconductor device of Modification 1 of the first embodiment. Note that FIG. 10 is a cross-sectional view taken along dashed dotted line YY in FIG. 9. Note that the same components as those in semiconductor device 10 are denoted by the same reference numerals.

[0056] In semiconductor device 10a, spacer portion 24 is formed in a ring shape along the outer edge of metal plate 23 of insulating circuit board 20, surrounding the center of metal plate 23. Spacer portion 24 may be formed on each side of the outer edge of metal plate 23, or may be formed in a ring shape integrally with metal plate 23, surrounding the center of metal plate 23. Variations 1 shows an example in which the spacer portions 24 are formed on each side of the outer edge of the metal plate 23.

[0057] Furthermore, spacer portion 24 has a height that follows the warp of insulating circuit board 20. That is, as shown in Fig. 10, spacer portion 24 is configured to be higher in a side view from a portion corresponding to the center of metal plate 23 toward the portions corresponding to the four corners of metal plate 23. In this case, the height refers to the height from arrangement surface 63c to metal plate 23 when spacer portion 24 is arranged on arrangement surface 63c.

[0058] When fabricating the semiconductor device 10a, the insulating circuit board 20 is placed on the mounting surface 63c of the lower mold 62 of the sealing mold 60 via the spacers 24 (see FIG. 5). In this case, too, the spacers 24 are supported at the four corners of the metal plate 23 of the insulating circuit board 20. The sealing member 50 is injected through the gate 63a to fill the cavity 63b. The insulating circuit board 20 and the semiconductor chips 31 and 32 are pressed toward the mounting surface 63c by the sealing member 50, and the back surface of the metal plate 23 of the insulating circuit board 20 is pressed against the mounting surface 63c, so that a region including the center of the back surface of the metal plate 23 of the insulating circuit board 20 comes into contact with the mounting surface 63c. Therefore, the intrusion of the sealing member 50 between the metal plate 23 and the mounting surface 63c is more effectively suppressed than in the case of fabricating the semiconductor device 10. The semiconductor device 10a fabricated in this manner is more reliably suppressed from generating burrs and reducing reliability than the semiconductor device 10.

[0059] [Variation 2] In Modification 2, a case in which more spacer portions are provided on the outer edge of metal plate 23 of insulating circuit board 20 than in semiconductor device 10 will be described with reference to FIGS. 11 and 12. FIG. 11 is a rear view of the semiconductor device of Modification 2 of the first embodiment, and FIG. 12 is a side cross-sectional view of the semiconductor device of Modification 2 of the first embodiment. Note that FIG. 12 is a cross-sectional view taken along dashed dotted line YY in FIG. 11. Note that the same components as those in semiconductor device 10 are denoted by the same reference numerals.

[0060] In semiconductor device 10b, unlike semiconductor device 10, spacer portions 24f-24i are formed at the center of the outer edge of metal plate 23 of insulating circuit board 20 between spacer portions 24a-24d. Note that Modification 2 illustrates a case where one spacer portion 24f-24i is formed on each of the outer edge of metal plate 23 of insulating circuit board 20 between spacer portions 24a-24d. The number is not limited to one, and two or more may be provided. Alternatively, a different number of spacer portions may be formed on outer edge portions where greater warping occurs in insulating circuit board 20 than on other outer edge portions.

[0061] Furthermore, spacer portions 24a to 24d and 24f to 24i have a height that conforms to the warpage of insulating circuit board 20. That is, as shown in Fig. 12, spacer portions 24a to 24d are configured to be higher than spacer portions 24f to 24i in a side view. In this case, the height refers to the height from arrangement surface 63c to metal plate 23 when spacer portions 24a to 24d and 24f to 24i are arranged on arrangement surface 63c.

[0062] Semiconductor Devices 10b When manufacturing the sealing mold 60, a spacer portion is attached to the arrangement surface 63c of the lower mold 62. 24a~24d, 24f~24i The insulating circuit board 20 is placed through the spacers 24a to 24d and 24f to 24i. The lower mold 62 is provided with pressure holes and pressure pins according to the spacer portions 24a to 24d and 24f to 24i to be placed.

[0063] In this case, too, sealing member 50 is injected through gate 63a to fill cavity 63b. The insulating circuit board 20 and semiconductor chips 31, 32 are pressed toward mounting surface 63c by sealing member 50, and the back surface of metal plate 23 of insulating circuit board 20 is pressed against mounting surface 63c, so that an area including the center of the back surface of metal plate 23 of insulating circuit board 20 comes into contact with mounting surface 63c. Therefore, the intrusion of sealing member 50 between metal plate 23 and mounting surface 63c is more effectively suppressed than in the case of manufacturing semiconductor device 10. In semiconductor device 10b manufactured in this manner, the generation of burrs is more reliably suppressed than in the case of semiconductor device 10, and a decrease in reliability is suppressed.

[0064] [Variation 3] In Modification 3, a case in which spacers are formed integrally with metal plate 23 at the outer edge of metal plate 23 of insulating circuit board 20 will be described with reference to FIG. 13. FIG. 13 is a side cross-sectional view of a semiconductor device according to Modification 3 of the first embodiment. Note that FIG. 13 corresponds to the position of the cross section in FIG. 2. Note that the same components as those in semiconductor device 10 are denoted by the same reference numerals.

[0065] Spacer portions 24a to 24d are formed integrally with metal plate 23 at the four corners of metal plate 23 of insulating circuit board 20 of semiconductor device 10c. Spacer portions 24a to 24d are obtained by half-etching the main surface of metal plate 23 so that protrusions remain at the four corners of metal plate 23. Furthermore, the spacers for metal plate 23 of insulating circuit board 20 are not limited to spacer portions 24a to 24d, and may be annular spacer portions as in Modification 1, or may be a plurality of spacer portions formed between the four corners of metal plate 23 as in Modification 2.

[0066] When manufacturing such a semiconductor device 10c, the spacers 24a to 24d provide the same effect as that of the semiconductor device 10.

[0067] [Variation 4-1] In Modification 4-1, a case in which a spacer portion composed of a plurality of fine protrusions is provided along the outer edge of metal plate 23 of insulating circuit board 20 will be described with reference to FIGS. 14 and 15. FIG. 14 is a side cross-sectional view of a semiconductor device according to Modification 4-1 of the first embodiment, and FIG. 15 is a rear view of the semiconductor device according to Modification 4-1 of the first embodiment. Note that FIG. 14 corresponds to the position of the cross section in FIG. 2. Note that the same components as those in semiconductor device 10 are designated by the same reference numerals.

[0068] In semiconductor device 10d, spacer portion 24 is formed along the outer edge of metal plate 23 of insulating circuit board 20, surrounding the center of metal plate 23. Spacer portion 24 is composed of a plurality of fine protrusions formed along the outer edge of metal plate 23 of insulating circuit board 20. The tip of each fine protrusion is crushed into a round shape. As shown in FIG. 15 , a plurality of such fine protrusions are formed along the outer edge of metal plate 23 of insulating circuit board 20, surrounding the center of metal plate 23.

[0069] In semiconductor device 10d, sealing member 50 seals the entire periphery of the side of insulating circuit board 20 as well as the side of the fine protrusions (spacer side) facing outward of spacer portion 24. In semiconductor device 10d as well, sealing bottom surface 50f is flush with the tip of spacer portion 24 and the center of the back surface of insulating circuit board 20.

[0070] Next, a method for manufacturing such a semiconductor device 10d will be described with reference to Figures 16 to 18. Figures 16 to 18 are cross-sectional views showing the manufacturing process of a semiconductor device according to Modification 4-1 of the first embodiment.

[0071] First, multiple thorn-like micro-protrusions are formed by metal processing along the outer edge of metal plate 23 of insulating circuit board 20 (see FIG. 14 for the formation positions). That is, each micro-protrusion has a sharp, high, spire-like tip. The metal processing in this case is performed by, for example, texturing, laser processing, or sandblasting. Furthermore, the multiple spire-like micro-protrusions are formed so that their tips point toward the center, taking into account warping of insulating circuit board 20.

[0072] To such insulating circuit board 20, as shown in FIG. 4, semiconductor chips 31 and 32, lead frames 40, 41a to 41j, 43 and 44 connected to tie bars 46, and lead frame 42 are joined.

[0073] Next, the insulating circuit board 20 to which the lead frames 40, 41a to 41j, 42 to 44, etc. have been joined in this manner is set in a sealing mold 60, as shown in Fig. 16. The entire back surface of the insulating circuit board 20 (metal plate 23) housed in the cavity 63b is raised above the placement surface 63c by the plurality of spacer portions 24. Note that the lower mold 62 of the sealing mold 60 of modification 4-1 is not provided with pressing holes or pressing pins.

[0074] Molten sealing member 50 is injected from gate 63a into sealing mold 60 in which insulating circuit board 20 has been set in this way. Heat causes downward warping of insulating circuit board 20.

[0075] The sealing member 50 injected from the gate 63a fills the cavity 63b along the dashed arrows shown in FIG. 17 (see FIG. 6 for a plan view). As described in FIGS. 5 and 6 for the first embodiment, the insulating circuit board 20 and semiconductor chips 31, 32 are pressed toward the mounting surface 63c by the sealing member 50. As a result, the multiple spire-shaped micro-projections of the spacer portion 24 are crushed, as shown in FIG. 18. The back surface of the metal plate 23 of the insulating circuit board 20, which had been floating above the mounting surface 63c, is pressed against the mounting surface 63c, and an area including the center of the back surface of the metal plate 23 of the insulating circuit board 20 comes into contact with the mounting surface 63c. The crushed micro-projections are packed together, filling the gaps between the micro-projections.

[0076] Furthermore, when the sealing member 50 is injected into the cavity 63b, it reaches the side portions of the insulating circuit board 20 and fills the gap between the side portions of the insulating circuit board 20 and the cavity 63b, as described in FIG. 7 of the first embodiment. At this time, although the insulating circuit board 20 is warped downward, the spacer portions 24 are provided on the outer edge of the metal plate 23. The insulating circuit board 20 is also pressed against the mounting surface 63c by the sealing member 50. The multiple spire-shaped micro-projections of the spacer portions 24 are further crushed, as shown in FIG. 18. The sealing member 50 filling the gap between the side portions of the insulating circuit board 20 and the cavity 63b cannot enter between the four corners of the warped insulating circuit board 20 and the mounting surface 63c. Therefore, the sealing member 50 seals the side portions of the insulating circuit board 20 and the outward-facing sides of the micro-projections of the spacer portions 24. In this way, the insulating circuit board 20 and the semiconductor chips 31, 32 etc. are sealed, and by cutting off the excess frame parts such as the tie bars 46, the semiconductor device 10d shown in FIGS. 14 and 15 is obtained.

[0077] Note that Modification 4-1 merely illustrates a case in which a plurality of fine protrusions are formed as spacer portions 24 along the outer edge of metal plate 23 of insulating circuit board 20. However, this is not limiting, and a plurality of fine protrusions may be formed as spacer portions 24 in each of the four corner regions of metal plate 23 of insulating circuit board 20, as shown in Fig. 3. Alternatively, as described in Modification 2, a plurality of fine protrusions may be formed as spacer portions 24 in the four corner regions and in multiple regions between the four corners of metal plate 23 of insulating circuit board 20.

[0078] [Variation 4-2] In Modification 4-2, a case in which a plurality of convex portions having a different shape from the plurality of fine protrusions of Modification 4-1 are formed on the outer edge of metal plate 23 of insulating circuit board 20 by metal processing will be described with reference to Figures 19 and 20. Figures 19 and 20 are rear views of a semiconductor device of Modification 4-2 of the first embodiment. Note that the same components as those in semiconductor device 10 are assigned the same reference numerals.

[0079] In the semiconductor device 10d shown in FIG. 19, the spacer portions 24 are annular protrusions formed along the outer edge of the back surface of the metal plate 23 and surrounding the center of the metal plate 23. The tips of each protrusion are crushed and rounded. Note that FIG. 19 shows, as an example, a case in which the protrusions are formed in three rows. The number of rows is not limited to three, and two or more rows may be used. Furthermore, similar to the first modification, the spacer portions 24 have a height that conforms to the warpage of the insulating circuit board 20. That is, the spacer portions 24 are configured to be higher from the portion corresponding to the center of the metal plate 23 toward the portions corresponding to the four corners of the metal plate 23 in a side view. Furthermore, in the semiconductor device 10d shown in FIG. 19, the cross sections of the multiple annular protrusions formed along the outer edge of the metal plate 23 of the insulating circuit board 20 before encapsulation have spire-shaped tips.

[0080] 19, the spacer portion 24 of the semiconductor device 10d shown in FIG. 20 has annular, dashed-line protrusions formed along the outer edge of the back surface of the metal plate 23 and surrounding the center of the metal plate 23. Note that FIG. 20 shows an example in which three rows of such protrusions are formed. In addition, in FIG. 20, the outermost protrusions are formed so that their continuations correspond to the defective portions of the innermost protrusions, and the innermost protrusions are formed at the corners of the metal plate 23. That is, in FIG. 20, the spacer portion 24 has multiple protrusions formed in a staggered pattern. The semiconductor device 10d of FIG. 20 also has multiple annular protrusions formed on the outer edge of the metal plate 23 of the insulating circuit board 20 before encapsulation, each with a spire-shaped tip in cross section.

[0081] 19 and 20, when the insulating circuit board 20 to which the lead frames 40, 41a to 41j, 42 to 44, etc. are joined is set in the sealing mold 60, the entire back surface of the insulating circuit board 20 (metal plate 23) is lifted from the placement surface 63c by the spacer portions 24 (see FIG. 16), as in the case of the modified example 4-1. -2The lower die 62 of the sealing mold 60 is not provided with a pressing hole or a pressing pin. When the sealing member 50 is injected from the gate 63a, the insulating circuit board 20 and the semiconductor chips 31, 32 are pressed toward the arrangement surface 63c by the sealing member 50. As a result, the multiple spire-shaped protrusions of the spacer portion 24 are crushed (see FIG. 18). The back surface of the metal plate 23 of the insulating circuit board 20, which had been floating above the arrangement surface 63c, is pressed against the arrangement surface 63c, and an area including the center of the back surface of the metal plate 23 of the insulating circuit board 20 comes into contact with the arrangement surface 63c. In addition, the crushed multiple Convex part are densely packed together, filling the gaps between the protrusions.

[0082] Furthermore, when sealing member 50 is injected into cavity 63b, as explained in Fig. 7 of the first embodiment, sealing member 50 seals the side of insulating circuit board 20 and the side of the convex portion facing outward of spacer portion 24. In this way, insulating circuit board 20 and semiconductor chips 31, 32, etc. are sealed, and by cutting off excess frame portions such as tie bars 46, semiconductor device 10d is obtained.

[0083] [Variation 5] In Modification 5, a case where a spacer portion formed of a particle group formed by agglomerating a plurality of particles is provided along the outer edge of metal plate 23 of insulating circuit board 20 will be described with reference to FIG. 21. FIG. 21 is a side cross-sectional view of a semiconductor device according to Modification 5 of the first embodiment. Note that FIG. 21 corresponds to the position of the cross section in FIG. 2. Note that the same components as those in semiconductor device 10 are denoted by the same reference numerals.

[0084] In semiconductor device 10e, spacer portion 24 is formed along the outer edge of metal plate 23 of insulating circuit board 20, surrounding the center of metal plate 23. Spacer portion 24 is a particle group formed along the outer edge of metal plate 23 of insulating circuit board 20, in which a plurality of particles are aggregated.

[0085] In semiconductor device 10e, sealing member 50 seals the entire periphery of the side of insulating circuit board 20 as well as the side of the particle group facing outward (spacer side) of spacer portion 24. In semiconductor device 10e as well, sealing bottom surface 50f is flush with the tip of spacer portion 24 and the center of the back surface of insulating circuit board 20.

[0086] Furthermore, Modification 5 merely illustrates a case in which particle groups are formed along the outer edge of metal plate 23 of insulating circuit board 20 as spacer portion 24. However, this is not limiting, and particle groups may be formed in each of the four corner regions of metal plate 23 of insulating circuit board 20 as spacer portion 24, as shown in Fig. 3. Alternatively, as described in Modification 2, particle groups may be formed in each of the four corner regions and multiple regions between the four corners of metal plate 23 of insulating circuit board 20 as spacer portion 24.

[0087] The spacer portion 24 on the outer edge of the rear surface of the metal plate 23 is formed by spraying a plurality of particles. The particles are metal or elastic material. The metal is, for example, copper, aluminum, or an alloy containing at least one of these. The elastic material is, for example, silicone rubber.

[0088] 21, a plurality of particles are sprayed in a circular pattern along the outer edge of the back surface of the metal plate 23 of the insulating circuit board 20 to form the spacer portion 24. When the insulating circuit board 20, to which the lead frames 40, 41a-41j, 42-44, etc. are joined and on which the spacer portion 24 is formed, is set in the sealing mold 60, the entire back surface of the insulating circuit board 20 (metal plate 23) is raised above the mounting surface 63c by the spacer portion 24 (see FIG. 16). The lower mold 62 of the sealing mold 60 of the fifth modification does not have any pressing holes or pressing pins. Furthermore, heating causes the insulating circuit board 20 to warp downward. Furthermore, when the sealing member 50 is injected through the gate 63a, the sealing member 50 presses the insulating circuit board 20 and the semiconductor chips 31 and 32 toward the mounting surface 63c. As a result, the back surface of metal plate 23 of insulating circuit board 20, which had been floating above arrangement surface 63c, is pressed against arrangement surface 63c, and an area including the center of the back surface of metal plate 23 of insulating circuit board 20 comes into contact with arrangement surface 63c.

[0089] Furthermore, when the sealing member 50 is injected into the cavity 63b, as explained in Fig. 7 of the first embodiment, the sealing member 50 seals the side of the insulating circuit board 20 and the side of the particles facing outward of the spacer portion 24. In this way, the insulating circuit board 20 and the semiconductor chips 31, 32, etc. are sealed, and the excess frame portions, such as the tie bars 46, are cut off to obtain the semiconductor device 10e.

[0090] [Second embodiment] A semiconductor device according to the second embodiment will be described with reference to Fig. 22. Fig. 22 is a side cross-sectional view of the semiconductor device according to the second embodiment. Note that Fig. 22 is a side cross-sectional view corresponding to Fig. 2. In addition, in the semiconductor device according to the second embodiment, the same components as those in the semiconductor device 10 according to the first embodiment are denoted by the same reference numerals.

[0091] In the semiconductor device 10f, the spacer portions 24a to 24d in the semiconductor device 10 protrude downward (in the -Z direction) beyond the sealing bottom surface 50f and the center of the metal plate 23. The spacer portions 24a to 24d are made of the same material as the spacer portions 24a to 24d in the semiconductor device 10. However, the spacer portions 24a to 24d are configured to be longer than the spacer portions 24a to 24d in the semiconductor device 10. The other configurations of the semiconductor device 10f are also similar to those of the semiconductor device 10.

[0092] Next, a manufacturing method of semiconductor device 10f will be described with reference to Figure 23. Figure 23 is a side cross-sectional view showing a manufacturing process of a semiconductor device according to the second embodiment. As in the first embodiment, lead frame 42 is bonded to semiconductor chips 31 and 32 bonded to insulating circuit board 20, and lead frames 40, 43, and 44 connected to tie bar 46 are bonded to insulating circuit board 20 as shown in Figure 4. Then, lead frames 41a to 41j connected to tie bar 46 are mechanically and electrically connected to semiconductor chips 31 and 32 by bonding wires 45.

[0093] Next, the insulating circuit board 20 to which the lead frames 40, 41a to 41j, 42 to 44, etc. have been joined in this manner is set in a sealing mold 60 via the spacers 24a to 24d. The sealing mold 60 has a configuration similar to that of the first embodiment. However, recesses 63d are formed in the mounting surface 63c of the lower mold 62 at locations corresponding to the spacers 24a to 24d. That is, pressure holes 62a and 62b are formed in the bottom of the recess 63d. The opening area of ​​the recess 63d corresponds to the area of ​​the spacers 24a to 24d in a plan view. The depth of the recess 63d is the depth to which the spacers 24a to 24d are inserted when the center of the metal plate 23 of the insulating circuit board 20 contacts the mounting surface 63c. Note that pressure pins 64a and 64b are disposed in the pressure holes 62a and 62b. The tips of the pressing pins 64a and 64b are arranged so as to be at the same level as or lower than the bottom of the recess 63d (in the -Z direction).

[0094] When insulating circuit board 20, to which lead frames 40, 41a to 41j, 42 to 44, etc. are joined, is placed on placement surface 63c of lower mold 62, spacers 24a to 24d are provided at the four corners of metal plate 23. That is, as shown in FIG. 23 , spacers 24a to 24d fit into recesses 63d in placement surface 63c. At this time, spacers 24a to 24d cause metal plate 23 of insulating circuit board 20, other than the four corners, to be slightly raised from placement surface 63c. At this time, the raised distance between the center of metal plate 23 and placement surface 63c is, for example, 10 μm or more and 200 μm or less.

[0095] From this state, the sealing member 50 is injected into the cavity 63b from the gate 63a in the same manner as in the first embodiment. The injected sealing member 50 presses the insulating circuit board 20 toward the placement surface 63c, sealing the side of the insulating circuit board 20. The sealing member 50 further seals the recess 63d. from The outward-facing sides (spacer sides) of the protruding spacer portions 24a to 24d are sealed. After sealing, the pressing pins 64a and 64b are moved upward, allowing the insulating circuit board 20 and other components sealed with the sealing member 50 to be removed from the lower mold 62. In this manner, the insulating circuit board 20 and the semiconductor chips 31 and 32 are sealed, and the excess frame portions such as the tie bars 46 are cut off to obtain the semiconductor device 10f shown in FIG.

[0096] Next, a case where a heat dissipation unit 56 is attached to the back surface (sealing bottom surface 50f) of such a semiconductor device 10f will be described with reference to Fig. 24. Fig. 24 is a side cross-sectional view of a semiconductor device to which a heat dissipation unit according to the second embodiment is attached. Fig. 24 shows a case where a heat dissipation unit is attached to the semiconductor device 10f corresponding to the side cross-sectional view of Fig. 22.

[0097] A heat dissipation unit 56 is provided on the back surface of the semiconductor device 10f via a TIM 55. The heat dissipation unit 56 is configured similarly to the heat dissipation unit 56 of the first embodiment. However, the heat dissipation unit 56 has alignment portions 56a formed at positions corresponding to the spacer portions 24a to 24d of the semiconductor device 10f. The alignment portions 56a are formed in a recessed shape sized to fit the spacer portions 24a to 24d.

[0098] The TIM 55 is applied to the rear surface of such a semiconductor device 10f. Alternatively, the TIM 55 may be applied to the placement area of ​​the heat dissipation unit 56 for the semiconductor device 10f, avoiding the alignment portion 56a. At this time, the spacer portions 24a to 24d protrude from the TIM 55. When attaching the semiconductor device 10f to the heat dissipation unit 56, the spacer portions 24a to 24d are fitted into the alignment portion 56a. This allows the semiconductor device 10f to be reliably placed on the heat dissipation unit 56. Furthermore, the semiconductor device 10f placed in this manner is prevented from shifting from the heat dissipation unit 56. This allows the heat dissipation unit 56 to be properly and reliably attached to the rear surface of the semiconductor device 10f.

[0099] [Variations] In this modified example, a case where a sealing mold different from that of the second embodiment is used will be described. First, the semiconductor device of the modified example will be described with reference to FIG. 25. FIG. 25 is a side cross-sectional view of a semiconductor device of the modified example of the second embodiment. Note that FIG. 25 is a side cross-sectional view corresponding to FIG. 2. Furthermore, in the semiconductor device of the modified example, the same components as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals.

[0100] In the semiconductor device 10g, the sealing bottom surface 50f is located higher than the bottom surfaces of the spacer portions 24a to 24d and the center of the downwardly curved metal plate 23. The other configurations of the semiconductor device 10g are similar to those of the semiconductor device 10.

[0101] Next, a manufacturing method of semiconductor device 10g will be described with reference to Figure 26. Figure 26 is a side cross-sectional view showing a manufacturing process of a semiconductor device according to a modification of the second embodiment. As in the first embodiment, lead frame 42 is bonded to semiconductor chips 31 and 32 bonded to insulating circuit board 20, and lead frames 40, 43, and 44 connected to tie bar 46 are bonded to insulating circuit board 20 as shown in Figure 4. Then, lead frames 41a to 41j connected to tie bar 46 are electrically and mechanically connected to semiconductor chips 31 and 32 by bonding wires 45.

[0102] Next, the insulating circuit board 20 to which the lead frames 40, 41a to 41j, 42 to 44, etc. have been joined in this manner is set in the sealing mold 60 via the spacers 24a to 24d. The sealing mold 60 has the same configuration as in the first embodiment. However, a recess 63e is formed in the area of ​​the placement surface 63c of the lower mold 62 where the insulating circuit board 20 is to be placed. The recess 63e is cubic. At the four corners in plan view of the recess 63e, there are provided pressing holes (pressing pins 64a in FIG. 26) through which pressing pins are inserted. ,64b The pressure holes 62a and 62b (shown in the figure) through which the pressure plates 62 are inserted are formed.

[0103] When insulating circuit board 20, to which lead frames 40, 41a to 41j, 42 to 44, etc. are joined, is placed on placement surface 63c of lower mold 62, spacers 24a to 24d are provided at the four corners of metal plate 23. That is, as shown in FIG. 26 , spacers 24a to 24d are positioned at the four corners of recess 63e in placement surface 63c. At this time, spacers 24a to 24d cause metal plate 23 of insulating circuit board 20, other than the four corners, to be slightly raised from the bottom surface of recess 63e. At this time, the raised distance between the center of metal plate 23 and placement surface 63c is, for example, 10 μm or more and 200 μm or less.

[0104] From this state, sealing member 50 is injected into cavity 63b through gate 63a in the same manner as in the first embodiment. The injected sealing member 50 presses insulating circuit board 20 toward placement surface 63c, sealing the sides of insulating circuit board 20. Sealing member 50 also seals the outward-facing sides (spacer sides) of spacer portions 24a-24d protruding from recess 63e. In this manner, insulating circuit board 20 and semiconductor chips 31, 32, etc. are sealed, and by cutting off excess frame portions such as tie bars 46, semiconductor device 10g shown in FIG. 25 is obtained.

[0105] 24, for such a semiconductor device 10g, the spacers 24a to 24d are fitted into the alignment portion 56a via the TIM 55. This allows the semiconductor device 10g to be reliably placed on the heat dissipation unit 56. Furthermore, the semiconductor device 10g placed in this manner is prevented from shifting from the heat dissipation unit 56. This allows the heat dissipation unit 56 to be properly and reliably attached to the back surface of the semiconductor device 10g.

[0106] The second embodiment is not limited to the spacer portions 24a to 24d attached to the four corners of the metal plate 23. The spacer portions in the first to fifth modifications of the first embodiment can also be applied. In this case, the recesses formed in the lower mold 62 of the sealing mold 60 can be made different depending on the shape of the spacer portions. [Explanation of symbols]

[0107] 10, 10a to 10g Semiconductor device 20 Insulated circuit board 21 Insulating plate 22a, 22b Circuit pattern 23 Metal plate 24, 24a to 24i Spacer part 31,32 Semiconductor chips 33a, 33b solder 40, 41a to 41j, 42 to 44 Lead frame 45 Bonding Wire 46 Tie bar 50 Sealing member 50a Sealing top surface 50b~50e Sealing side 50f sealed bottom 55 Thermal Interface Material (TIM) 56 Heat dissipation unit 56a Alignment part 60 Sealing mold 60a Mold top surface 60b~60e Mold side 60f mold bottom 61 Upper mold 62 Lower mold 62a, 62b Pressing holes Gate 63a 63b cavity 63c Placement plane 63d, 63e recess 64a, 64b Press pin

Claims

1. A semiconductor chip; an insulating circuit board in which a rectangular metal plate, a rectangular insulating plate, and a circuit pattern are laminated in this order, the semiconductor chip is disposed on the circuit pattern on the front surface, and the insulating circuit board is warped downward convexly with the metal plate on the back surface facing downward; spacer portions provided at four corners of the metal plate so as to protrude downward in a plan view, and which are flush with the center of the back surface of the metal plate of the insulating circuit board, which is warped downwardly in a convex shape in a side view, or which protrude below the center; a sealing member that seals the front surface of the insulating circuit board, a side portion of the insulating circuit board, and a spacer side portion that faces outward from the spacer portion; and the spacer portion has an annular shape in a plan view, is centered at the center of the metal plate, and is formed on the outer edge of the metal plate so as to surround the center. Semiconductor device.

2. The sealing bottom surface of the sealing member is flush with the center portion. The semiconductor device according to claim 1 .

3. a spacer bottom surface of the spacer portion protrudes below the sealing bottom surface of the sealing member; The semiconductor device according to claim 2 .

4. the spacer portion is formed along the outer edge portion including the four corners of the metal plate to surround the center portion.

4. The semiconductor device according to claim 1.

5. The spacer portion is formed at least one on the outer edge portion between the four corners of the metal plate in addition to the four corners.

4. The semiconductor device according to claim 1.

6. The height of the spacer portion is configured to increase as it approaches the four corners.

6. The semiconductor device according to claim 4.

7. the spacer portion is integrally formed with the metal plate, 7. The semiconductor device according to claim 1.

8. The spacer portion is formed by a plurality of fine protrusions.

8. The semiconductor device according to claim 1.

9. the spacer portion has an annular thin line shape in a plan view, and is formed in plurality on the outer edge portion of the metal plate so as to surround the center of the metal plate, the center being the center; 8. The semiconductor device according to claim 1.

10. The spacer portions are each formed in a dashed line shape and are formed in a zigzag pattern on the outer edge portion of the metal plate so as to surround the center portion.

8. The semiconductor device according to claim 1.

11. the spacer portion is formed by a particle group formed by agglomeration of a plurality of particles sprayed onto the metal plate, 11. The semiconductor device according to claim 1, wherein the first insulating film is a semiconductor material.

12. The insulating circuit board further includes a heat dissipation unit installed on a back surface of the metal plate of the insulating circuit board, the back surface including the spacer portion, via a thermal interface material.

12. The semiconductor device according to claim 1.

13. a heat dissipation unit having an alignment portion formed thereon that corresponds to the spacer portion, the heat dissipation unit being installed on the back surface of the metal plate of the insulating circuit board including the spacer portion, with the spacer portion fitted into the alignment portion via a thermal interface material; 12. The semiconductor device according to claim 1.

14. a preparation step of preparing an insulating circuit board having a rectangular metal plate, a rectangular insulating plate, and a circuit pattern laminated in this order, a semiconductor chip disposed on the circuit pattern on its front surface, and warped downwardly convexly with the metal plate on its back surface facing downward, and a mold including a placement surface on which the insulating circuit board is disposed and a storage area for storing the insulating circuit board; a placement step of placing the insulating circuit board on the placement surface of the mold via spacer portions at four corners of the metal plate; a sealing step of injecting a sealing material toward the insulating circuit board from an injection port provided in the mold above the front surface of the insulating circuit board to fill the storage area while heating the inside of the storage area, thereby sealing the insulating circuit board; and In the sealing step, the insulating circuit board is pressed against the arrangement surface of the mold by the sealing member, and the back surface of the insulating circuit board comes into contact with the arrangement surface. A method for manufacturing a semiconductor device.

15. a pressing hole is provided on the placement surface of the mold, In the arranging step, the spacer portion is arranged on the pressing hole of the arrangement surface. The method for manufacturing a semiconductor device according to claim 14.

16. In the sealing step, the injected sealing material is applied to the front surface side of the insulating circuit board, thereby pressing the back surface of the spacer of the spacer portion against the arrangement surface of the mold. The method for manufacturing a semiconductor device according to claim 14.

17. the spacer portions are formed by a plurality of spire-shaped minute protrusions at the four corners of the metal plate of the insulating circuit board prepared in the preparing step, The method for manufacturing a semiconductor device according to claim 14 or 16.

18. In the sealing step, as the sealing material is injected, the insulating circuit board is pressed against the placement surface, crushing the spacer portion. The method for manufacturing a semiconductor device according to claim 17.

19. recesses are formed on the placement surface of the mold so as to correspond to the four corners of the metal plate when the insulating circuit board is placed on the placement surface of the mold, In the placing step, the insulating circuit board is placed on the placement surface by fitting the spacer portions into the recesses. The method for manufacturing a semiconductor device according to claim 14 or 16.

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