Isolated DC / DC converter and control method for isolated DC / DC converter

Abstract

In an isolated DC / DC converter that performs intermittent operation using a transformer and an inverter, the inverter output voltage is corrected to achieve desired operating characteristics. A corrected inverter output voltage command is generated, which holds a value for the dead time plus minimum ON time from the timing when the inverter operation command switches from ON to OFF, and then sets it to 0. Alternatively, a corrected inverter output voltage command is generated, which inverts the polarity of the value when the inverter operation command switches from ON to OFF, holds the value for the dead time plus minimum ON time, and then sets it to 0. The inverter is controlled based on the corrected inverter output voltage command.

Description

[Technical Field]

[0001] The present invention relates to a power transmission technology in an isolated DC / DC converter using a transformer and an inverter, and more particularly to a control method for intermittent operation in which a period in which an inverter outputs voltage and a period in which no voltage is output are repeated. [Background technology]

[0002] An isolated DC / DC converter, as shown in Fig. 1, is known as a circuit that generates another isolated DC voltage source from a DC voltage source, using the insulation of a transformer 3. As shown in Fig. 1, an inverter 2 is provided on the primary side of the transformer 3, and a rectifier 4 is provided on the secondary side of the transformer 3. The output voltage of the inverter 2 is applied to the primary side of the transformer 3, and the voltage waveform is pulsed.

[0003] There are two methods for controlling inverter 2, which varies the power transmitted from the primary side to the secondary side: one is to vary the pulse width (duty) of the pulse voltage, which is the inverter output voltage, and the other is to perform intermittent operation by setting a period during which the output of inverter 2 is paused while keeping the pulse width constant, thereby varying the pulse density.

[0004] Of these two methods, the method that controls the pulse density determines the amount of power that can be transmitted per pulse. If the ratio of the inverter operating period to the inverter idle period is small, the pulse density is low, and the average power that can be transmitted from the primary side to the secondary side is small.

[0005] On the other hand, when the ratio of the inverter operating period is large, the pulse density is high and the power that can be transmitted from the primary side to the secondary side on average is large. The difference in transmitted power due to differences in pulse density is shown in Figure 2. Note that the inverter output voltage is either +V1, 0, or -V1 relative to the voltage V1 of the first DC voltage source 1 in Figure 1. The inverter output voltage is ±V1 during the inverter operating period and 0 during the inverter non-operating period.

[0006] In the configuration of Figure 1, if the average voltage applied to transformer 3 is not zero, the excitation current of transformer 3 continues to increase or decrease, causing a biased magnetization phenomenon in which the iron core of transformer 3 becomes magnetically saturated. To prevent this, Patent Documents 1 to 4 take the following measures.

[0007] Patent Document 1: The inverter output voltage pattern is controlled so that the inverter enters a pause period at the timing when the excitation current becomes zero.

[0008] Patent Documents 2 and 3: A mechanism is provided to measure the waveform of the voltage applied to the transformer and the magnetic flux of the transformer core, and the pulse width of the inverter output voltage is controlled according to the measured values.

[0009] Patent Document 4: The positive and negative polarities of the inverter output voltage are switched for each operating period. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-130997 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-144303 [Patent Document 3] Japanese Patent Application Publication No. 5-344715 [Patent Document 4] Japanese Patent Application Laid-Open No. 2024-000954 Summary of the Invention [Problem to be solved by the invention]

[0011] In the case of Patent Document 1, the timing at which the excitation current becomes 0 occurs only twice per pulse period, making it difficult to achieve high-precision control such as matching the inverter operation period with a desired time.

[0012] Fig. 3 shows an example of waveforms when the inverter is controlled so as to enter an inverter idle period when the excitation current becomes zero in the configuration of Fig. 1, as in Patent Document 1. As mentioned above, there are only two times per pulse period when the excitation current becomes zero, so there is a timing constraint. If this constraint is ignored and the inverter idle period is entered at a timing when the excitation current does not become zero, a direct current may be superimposed on the excitation current, as shown in Fig. 4, causing biased magnetization.

[0013] In the cases of Patent Documents 2 and 3, an additional mechanism for measuring voltage and magnetic flux is required, and furthermore, the control becomes complicated because the pulse width must be controlled simultaneously with the pulse density.

[0014] In Patent Document 4, the inverter output voltage is output with the positive and negative polarities reversed for each operating period. If the duration of two consecutive operating periods is the same, the magnetic flux in the transformer can be canceled out for each of the two operating periods. However, if the duration of each operating period differs, the magnetic flux in the transformer cannot be canceled out and remains, and as this accumulates, there is a risk of a magnetic bias phenomenon occurring, in which the transformer core becomes magnetically saturated.

[0015] In addition, variations may occur in the rise characteristics of the secondary side DC voltage when switching from an inverter idle period to an inverter operating period, and variations may occur in the fall characteristics of the secondary side DC voltage when switching from an inverter operating period to an inverter idle period.

[0016] As described above, in an isolated DC / DC converter that performs intermittent operation using a transformer and an inverter, the challenge is to correct the inverter output voltage to achieve desired operating characteristics. [Means for solving the problem]

[0017] The present invention has been devised in view of the above-mentioned problems in the related art, and one aspect thereof is an isolated DC / DC converter that applies pulse density control through intermittent operation, comprising: a first DC voltage source; an inverter whose DC side is connected to the first DC voltage source; a transformer whose primary winding is connected to the AC side of the inverter; a rectifier connected to a secondary winding of the transformer; and a second DC voltage source connected to the DC side of the rectifier, wherein the inverter generates a corrected inverter output voltage command that holds a value from the timing when an inverter operation command switches from ON to OFF for a period of a dead time plus a minimum ON time and then sets it to 0, or that inverts the polarity of the value at the timing when the inverter operation command switches from ON to OFF, holds the value for a period of a dead time plus a minimum ON time, and then sets it to 0, and controls the inverter based on the corrected inverter output voltage command.

[0018] In one aspect, the inverter generates a delayed inverter operation command by delaying the inverter operation command by a dead time plus a minimum ON time, generates a delayed inverter output voltage command based on the delayed inverter operation command, and corrects the delayed inverter output voltage command to become 0 after holding its value for the dead time plus a minimum ON time from the timing at which the inverter operation command switches from ON to OFF, thereby generating the corrected inverter output voltage command.

[0019] In one aspect, the inverter control unit generates a pre-delay inverter output voltage command based on the inverter operation command, generates a delayed inverter output voltage command by delaying the pre-delay inverter output voltage command by a dead time plus a minimum ON time, compares the pre-delay inverter output voltage command with the delayed inverter output voltage command at the timing when the inverter operation command switches from ON to OFF, and if the pre-delay inverter output voltage command and the delayed inverter output voltage command match, sets the delayed inverter output voltage command as the corrected inverter output voltage command, and if the pre-delay inverter output voltage command and the delayed inverter output voltage command do not match, corrects the delayed inverter output voltage command by inverting the polarity of the value at the timing when the inverter operation command switches from ON to OFF, holding it for a dead time plus a minimum ON time, and then becoming 0, thereby generating the corrected inverter output voltage command. [Effects of the Invention]

[0020] According to the present invention, in an isolated DC / DC converter that performs intermittent operation using a transformer and an inverter, it is possible to correct the inverter output voltage to achieve desired operating characteristics. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a schematic diagram showing an example of an isolated DC / DC converter. [Figure 2] FIG. 10 is a graph showing transmitted power relative to pulse density. [Figure 3] FIG. 10 is a diagram showing an example of waveforms when the inverter is stopped at the timing when the excitation current becomes 0. [Figure 4] FIG. 10 is a diagram showing an example of waveforms when the inverter is stopped at a timing when the excitation current is not zero. [Figure 5] FIG. 1 is a diagram showing a circuit configuration of an isolated DC / DC converter according to a first embodiment. [Figure 6] FIG. 10 is a diagram showing an example of waveforms when State 3 is applied to the inverter idle period and the inverter idle period is short. [Figure 7]3A and 3B are diagrams showing waveforms of an inverter output voltage and an excitation current in the first embodiment. [Figure 8] FIG. 10 is a diagram showing the circuit configuration of an isolated DC / DC converter according to a second embodiment. [Figure 9] FIG. 10 is a diagram showing an example of an inverter output voltage waveform when the inverter operation period is twice as long as the inverter pulse period. [Figure 10] FIG. 10 is a diagram showing an example of a secondary side DC voltage waveform under the conditions of FIG. 9; [Figure 11] 10A and 10B are diagrams showing an inverter output voltage pattern and an excitation current waveform in the third embodiment. [Figure 12] FIG. 10 is a diagram showing secondary-side DC voltage characteristics at the time of switching from an inverter operating period to an inverter idle period. [Figure 13] 10 is a diagram showing an example of waveforms in a fourth embodiment when a pre-delay inverter operation command is changed from ON to OFF after a minimum ON time has elapsed since the pre-delay inverter output voltage command entered state 1 or 2. FIG. [Figure 14] 10 is a diagram showing an example of waveforms in a fourth embodiment when a pre-delay inverter operation command is changed from ON to OFF before the minimum ON time has elapsed after the pre-delay inverter output voltage command has entered state 1 or 2. FIG. [Figure 15] FIG. 10 is a diagram showing an example of waveforms in a fourth embodiment when a pre-delay inverter operation command changes from ON to OFF while the pre-delay inverter output voltage command is in state 3. [Figure 16] 10 is a diagram showing an example of waveforms in a fifth embodiment when an inverter operation command is changed from ON to OFF after a minimum ON time has elapsed since the pre-delay inverter output voltage command entered state 1 or 2. FIG. [Figure 17] 10 is a diagram showing an example of waveforms in a fifth embodiment when an inverter operation command is changed from ON to OFF before the minimum ON time has elapsed after the pre-delay inverter output voltage command has entered state 1 or 2. FIG. [Figure 18] FIG. 10 is a diagram showing an example of waveforms in a fifth embodiment when an inverter operation command changes from ON to OFF while the pre-delay inverter output voltage command is in state 3. DETAILED DESCRIPTION OF THE INVENTION

[0022] Examples 1 to 5 of the isolated DC / DC converter of the present invention will be described in detail below with reference to Figures 5 to 18. Note that the "desired operating characteristics" mean suppression of transformer bias magnetization in Examples 1 and 2, suppression of transformer bias magnetization and suppression of variations in the rise characteristics of the secondary side DC voltage in Example 3, and suppression of variations in the fall characteristics of the secondary side DC voltage in Examples 4 and 5.

[0023] [Example 1] 5 shows the circuit configuration of an isolated DC / DC converter to which the control method of the present embodiment 1 is applied. First, the circuit configuration of the isolated DC / DC converter in the present embodiment 1 will be described with reference to FIG.

[0024] A single-phase full-bridge inverter 2 is connected to a first DC voltage source 1. Specifically, first and second U-phase switching elements S1 and S2 are connected in series between one end and the other end of the first DC voltage source 1. Furthermore, third and fourth V-phase switching elements S3 and S4 are connected in series between one end and the other end of the first DC voltage source 1.

[0025] The connection point between the first and second switching elements S1 and S2 is connected to one end of the primary winding of the transformer 3. The connection point between the third and fourth switching elements S3 and S4 is connected to the other end of the primary winding of the transformer 3.

[0026] A single-phase rectifier 4 is connected to the secondary winding of the transformer 3. Specifically, one end of the secondary winding of the transformer 3 is connected to the junction of the first and second diodes D1 and D2 of the rectifier 4, and the other end of the secondary winding of the transformer 3 is connected to the junction of the third and fourth diodes D3 and D4 of the rectifier 4.

[0027] The first and third diodes D1 and D3 are connected to one end of a second DC voltage source 5, and the second and fourth diodes D2 and D4 are connected to the other end of the second DC voltage source 5. A load 6 is connected in parallel to the second DC voltage source 5.

[0028] The inverter 2 connected to the first DC voltage source 1 is a single-phase full-bridge circuit, and the inter-phase voltage Vuv between the U and V phases of the single-phase full-bridge circuit is applied to the primary winding of the transformer 3. A rectifier 4 is connected to the secondary winding of the transformer 3 to convert it into DC. This makes it possible to generate a second DC voltage source 5 that is isolated from the first DC voltage source 1 at the input section of the inverter 2.

[0029] Inverter 2 of the single-phase full-bridge circuit has four switching states (State 1 to State 4) as shown in Table 1. Note that although State 4 lists two switching states, the inverter output voltage is 0 in either switching state, so they are treated as one switching state without distinction.

[0030] [Table 1]

[0031] During the inverter operation period, the output voltage of inverter 2 is alternately switched between +V1 and -V1 by alternately switching between state 1 and state 2. When switching between these states, it is generally necessary to insert dead time, which corresponds to state 3. Meanwhile, during the inverter rest period, there are two methods: state 3 or state 4.

[0032] When State 3 is applied as an inverter idle period, inverter 2 operates as a rectifier during State 3. When switching from the inverter operation period to State 3 as an inverter idle period while the excitation current is not zero, the excitation current flows to first DC voltage source 1 or second DC voltage source 5, causing the energy charged in the excitation inductance of transformer 3 to be discharged to first DC voltage source 1 or second DC voltage source 5, and the excitation current attenuates.

[0033] If the inverter idle period is short and the next inverter operation period occurs before the energy stored in the excitation inductance of transformer 3 is completely discharged, DC will be superimposed on the excitation current, causing bias magnetization, as shown in Figure 6.

[0034] When State 4 is applied as the inverter idle period, if the inverter operation period switches to the inverter idle period while the excitation current is not zero, the excitation inductance of transformer 3 is short-circuited by the switching element of inverter 2 on the primary side. As a result, ignoring circuit loss, the excitation current during the inverter operation period is maintained as shown in Figure 4.

[0035] In the first embodiment, State 4 is applied during the inverter idle period to maintain the excitation current. The switching states during the inverter operation periods immediately before and after the inverter idle period are made the same, and the sum of the pulse widths during the inverter operation periods immediately before and after the inverter idle period is made to match the pulse width during normal operation during the inverter operation period.

[0036] This makes it possible to suppress changes in the excitation current to the same range as when the inverter is stopped at the timing when the excitation current becomes zero, as shown in Figure 3. This method does not require the constraint on the inverter operation period as in Patent Document 1, or the additional voltage and magnetic flux measurement mechanism as in Patent Documents 2 and 3. In addition, there is no need to match the time widths of two consecutive operation periods, which is a constraint in Patent Document 4.

[0037] The method for deriving an operation pattern according to the first embodiment is summarized below. An example of a waveform is shown in FIG.

[0038] Period 1: Inverter operation period During the inverter operation period, if the dead time is ignored and the pulse period is Tpulse, the inverter will alternate between State 1 and State 2 in Table 1 for a time of 0.5 x Tpulse (0.5 period). This results in operation where the inverter output voltage has a constant duty of 50%.

[0039] When switching from an inverter operating period to an inverter resting period, the shortfall in output time for 0.5 cycles, "Tshort", is calculated and recorded using the following formula (1) based on the switching state (state 1 or state 2) in the previous inverter operating period and the output time in that state (Tbefore).

[0040]

number

[0041] Period 2: Inverter off period During the inverter idle period, the excitation current from the previous inverter operation period is maintained by setting the inverter to state 4 in Table 1. In state 4, the first and third switching elements S1 and S3 are on and the second and fourth switching elements S2 and S4 are off, or the second and fourth switching elements S2 and S4 are on and the first and third switching elements S1 and S3 are off.

[0042] Period 3: Next inverter operation period The initial switching state when the inverter resumes operation shall be the same as the state during the inverter operation period immediately before the inverter pause period. After that, the inverter will resume operation by alternating between state 1 and state 2. At this time, the time (pulse width) of the initial switching state upon recovery shall be "Tshort" calculated and recorded in "Period 1: Inverter operation period".

[0043] This results in an inverter pause period where the excitation current is maintained being inserted into the excitation current waveform when the inverter output voltage is operated at a constant duty of 50% without intermittent operation.As a result, without restricting the length of the inverter operation period, the excitation current can be kept within the same range of change as when the inverter is operated continuously, and asymmetric magnetization can be suppressed.

[0044] As described above, according to the present embodiment 1, by applying a switching state (state 4 in Table 1) that can maintain the excitation current during the inverter pause period, it is no longer necessary to end the inverter operation period at the timing when the excitation current becomes 0, as was the case in Patent Document 1, and bias magnetization can be suppressed during any inverter operation period.

[0045] Furthermore, by calculating and recording the pulse width required for the next inverter operation period when the inverter operation period ends, it is possible to adjust the pulse width for the next inverter operation period without information on the applied voltage of the transformer 3 or the magnetic flux of the transformer 3, eliminating the need for the additional mechanisms for measuring voltage and magnetic flux as in Patent Documents 2 and 3. Also, there is no need to match the time widths of two consecutive operation periods, which is a restriction in Patent Document 4.

[0046] (Conditions under which circuit loss can be ignored) If the primary-side equivalent series resistance component associated with the windings and circuit element wiring of transformer 3 is ESR1, the primary-side winding inductance is L1, and the primary-side current is I1, then the secondary side is essentially open during the period corresponding to the inverter idle period in State 4, and therefore the following equation (2) is established.

[0047]

number

[0048] Therefore, when the fluctuation of the secondary voltage can be ignored, if the current at t=0 immediately after the transition to the pause period is I0, the following equation (3) holds.

[0049]

number

[0050] In other words, the condition for the above attenuation to be negligible is that the quiescent period t must be sufficiently smaller than L1 / ESR1, which corresponds to the primary-side time constant. Conversely, even if L1 divided by the quiescent period t is sufficiently larger than the primary-side equivalent series resistance component ESR1, this also constitutes a condition for attenuation to be negligible and circuit loss to be negligible. As long as the primary-side equivalent series resistance component ESR1 is small enough to satisfy this condition, it will suffice. This condition is satisfied in normal designs.

[0051] [Example 2] The difference between the first embodiment and the second embodiment is that the transformer 3, the inverter 2, and the rectifier 4 are changed from single-phase to three-phase. The circuit system in the second embodiment is shown in FIG.

[0052] Specifically, first and second U-phase switching elements S1 and S2 are connected in series between one end and the other end of first DC voltage source 1. Furthermore, third and fourth V-phase switching elements S3 and S4 are connected in series between one end and the other end of first DC voltage source 1. Furthermore, fifth and sixth W-phase switching elements S5 and S6 are connected in series between one end and the other end of first DC voltage source 1.

[0053] The connection point of the first and second switching elements S1 and S2, the connection point of the third and fourth switching elements S3 and S4, and the connection point of the fifth and sixth switching elements S5 and S6 are connected to a transformer 3.

[0054] The secondary winding of the transformer 3 is connected to the junction of the first and second diodes D1 and D2, the junction of the third and fourth diodes D3 and D4, and the junction of the fifth and sixth diodes D5 and D6.

[0055] The first, third, and fifth diodes D1, D3, and D5 are connected to one end of a second DC voltage source 5, and the second, fourth, and sixth diodes D2, D4, and D6 are connected to the other end of the second DC voltage source 5. A load 6 is connected in parallel to the second DC voltage source 5.

[0056] The U-phase to V-phase line voltage, the V-phase to W-phase line voltage, and the W-phase to U-phase line voltage are denoted by Vuv, Vvw, and Vwu, respectively.

[0057] In the case of the three-phase inverter of Figure 8, there are eight switching states (State 1 to State 8) as shown in Table 2. Note that although two switching states are listed for State 8, the inverter output voltages are all 0 in either switching state, so they are treated as a single switching state without distinction. In State 8, the first, third, and fifth switching elements S1, S3, and S5 are on and the second, fourth, and sixth switching elements S2, S4, and S6 are off, or the second, fourth, and sixth switching elements S2, S4, and S6 are on and the first, third, and fifth switching elements S1, S3, and S5 are off.

[0058] During the inverter operation period, a 50% duty pulse is output from each phase of inverter 2, with the timing shifted by 1 / 3 of the pulse period between phases (phase difference of 120 degrees).As a result, states 1 to 6 in Table 2 are output in sequence, each for 1 / 6 of the pulse period.

[0059] [Table 2]

[0060] Next, the operation during the inverter off period will be described.

[0061] In the single-phase full-bridge circuit of the first embodiment, in state 4 in Table 1, the exciting inductance of the transformer 3 is short-circuited by the switching element of the inverter 2 on the primary side.

[0062] Similarly, in the case of the three-phase inverter of the second embodiment, in state 8 in Table 2, the exciting inductance of the transformer 3 is short-circuited by the switching element of the inverter 2 on the primary side.

[0063] In this way, as in Example 1, by selecting state 8 in Table 2 during the inverter pause period, the excitation current during the inverter pause period can be maintained. The initial switching state when the inverter resumes operation is the same as the switching state during the inverter operation period immediately before the inverter pause period. After that, states 1 to 6 are output in sequence, each for 1 / 6 of the pulse period. At this time, the time for the initial switching state upon recovery is set to "Tshort," which is calculated and recorded during the inverter operation period immediately before the inverter pause period.

[0064] Therefore, an inverter pause period in which the excitation current is maintained is inserted into the excitation current waveform when the inverter output voltage is operated at a constant duty without intermittent operation. As a result, the excitation current can be kept within the same range of change as when the inverter is operated continuously without restricting the length of the inverter operation period, and asymmetric magnetization can be suppressed.

[0065] As described above, according to the second embodiment, the same effects as those of the first embodiment can be achieved even in the case of a three-phase inverter.

[0066] [Example 3] The first and second embodiments solve the problems described in Patent Documents 1 to 4. However, the rise characteristics of the secondary side DC voltage change depending on the condition of the first pulse width during the inverter operation period.

[0067] Fig. 9 shows the inverter output voltage waveform when the inverter operation period is twice as long as the inverter pulse period, and Fig. 10 shows an example of the secondary DC voltage waveform. The narrower the initial pulse width of the inverter operation period, the slower the rise of the secondary voltage tends to be. As a result, when the purpose is to supply voltage to devices such as ICs that switch operation according to a voltage threshold, there is a problem in that the operating characteristics of the device are affected.

[0068] In the third embodiment, similarly to the first embodiment, it is assumed that the transformer 3, the inverter 2, and the rectifier 4 are single-phase.

[0069] This embodiment 3 is similar to embodiment 1 in that the excitation current is maintained by using state 4 during the inverter pause period. The difference from embodiment 1 is that the first pulse width during the inverter operation period is fixed to 0.5 times the pulse period, regardless of the conditions during the previous inverter operation period.

[0070] Because the first pulse width of the inverter operation period is fixed at 0.5 times the pulse period, the excitation current of transformer 3 at the end of the inverter operation period relative to the start of the inverter operation period has a positive offset if the first pulse of the inverter operation period is positive, and a negative offset if the first pulse of the inverter operation period is negative, as shown in Table 3. Note that if the inverter operation period is an integer multiple of the pulse period, the excitation current of transformer 3 will be the same at the start and end of the inverter operation period.

[0071] [Table 3]

[0072] By utilizing the above characteristics and appropriately selecting the polarity of the first pulse during the inverter operation period, DC bias magnetization can be suppressed. The method for deriving the operation pattern according to this third embodiment is summarized below.

[0073] Period 1: Inverter operation period During the inverter operation period, ignoring dead time, the pulse period is Tpulse, and state 1 and state 2 in Table 1 are repeated alternately for a time of 0.5 x Tpulse (0.5 period), thereby operating the inverter output voltage at a constant duty of 50%.

[0074] The first pulse width during the inverter operation period is set to 0.5×Tpulse, and the voltage polarity is the same as the polarity selected during the previous inverter operation period in the following process. Also, measure the length Tout of the inverter operation period, and based on Table 4, obtain the positive-polarity pulse width required to match the excitation current at the start of the inverter operation period (remove the excitation current offset) from the relationship between the length Tout of the inverter operation period and the pulse period Tpulse. Note that when the required positive-polarity pulse width is negative, it means the negative-polarity pulse width. Also, N in Table 4 represents an integer of 0 or more.

[0075] N×Tpulse≦Tout<N×Tpulse + 0.5×Tpulse in Table 4 indicates the case where the inverter operation period ends with the same pulse polarity as the first pulse polarity during the inverter operation period. In this case, when the first pulse polarity during the inverter operation period is positive, -(Tout - N×Tpulse) is taken as the required positive-polarity pulse width, and when the first pulse polarity during the inverter operation period is negative, (Tout - N×Tpulse) is taken as the required positive-polarity pulse width.

[0076] N×Tpulse + 0.5×Tpulse≦Tout<(N + 1)×Tpulse in Table 4 indicates the case where the inverter operation period ends with a pulse polarity different from the first pulse polarity during the inverter operation period. In this case, when the first pulse polarity during the inverter operation period is positive, -((N + 1)×Tpulse - Tout) is taken as the required positive-polarity pulse width, and when the first pulse polarity during the inverter operation period is negative, ((N + 1)×Tpulse - Tout) is taken as the required positive-polarity pulse width.

[0077]

Table 4

[0080] Period 3: Next inverter operation period Based on the range of the integrated value Tsum, the first pulse polarity of the (next) inverter operation period upon recovery is selected so that the direction is such that the current magnetic flux in the iron core of the transformer 3 is suppressed during the next inverter operation period. Specifically, the first switching state (pulse polarity) upon recovery of the inverter operation is determined according to Table 5.

[0081] [Table 5]

[0082] That is, if the integrated value Tsum is less than -0.5 x pulse period, the polarity of the first pulse in the next inverter operation period will be negative. If the integrated value Tsum is greater than -0.5 x pulse period and less than 0.5 x pulse period, the polarity of the first pulse in the next inverter operation period will be the inverse of the polarity of the first pulse in the current inverter operation period. If the integrated value Tsum is greater than 0.5 x pulse period, the polarity of the first pulse in the next inverter operation period will be positive.

[0083] Furthermore, the first pulse width during the inverter operation period upon recovery is set to 0.5×Tpulse, the same as the previous time.

[0084] 11 shows the inverter output voltage pattern and excitation current waveform according to Example 3. Initially, the integral value Tsum of the required positive pulse width is zero.

[0085] During the first inverter operation period, the first pulse polarity is positive, and since the inverter operation period ends with the same pulse polarity as the first pulse polarity (N×Tpulse≦Tout<N×Tpulse+0.5×Tpulse), the integrated value Tsum becomes -(Tout - N×Tpulse). Since the integrated value Tsum does not exceed -0.5×Tpulse, the first pulse polarity in the second inverter operation period is inverted from the first pulse polarity in the first inverter operation period to a negative polarity.

[0086] During the second inverter operation period, the first pulse polarity is negative, and since the inverter operation period ends with a pulse polarity different from the first pulse polarity (N×Tpulse+0.5×Tpulse≦Tout<(N + 1)×Tpulse), ((N + 1)×Tpulse)-Tout) is added to the integrated value Tsum. Since the integrated value Tsum does not exceed -0.5×Tpulse, the first pulse polarity in the third inverter operation period is inverted from the first pulse polarity in the second inverter operation period to a positive polarity.

[0087] During the third inverter operation period, the first pulse polarity is positive, and since the inverter operation period ends with the same pulse polarity as the first pulse polarity (N×Tpulse≦Tout<N×Tpulse+0.5×Tpulse), -(Tout - N×Tpulse) is added to the integrated value Tsum. Since the integrated value Tsum exceeds -0.5×Tpulse, the first pulse polarity in the fourth inverter operation period becomes negative.

[0088] During the fourth inverter operation period, the first pulse polarity is negative, and since the inverter operation period ends with a pulse polarity different from the first pulse polarity (N×Tpulse+0.5×Tpulse≦Tout<(N + 1)×Tpulse), ((N + 1)×Tpulse)-Tout) is added to the integrated value Tsum. Since the integrated value Tsum exceeds -0.5×Tpulse, the first pulse polarity in the fifth inverter operation period becomes negative.

[0089] The fifth inverter operation period starts with a negative first pulse polarity and ends with the same pulse polarity as the first pulse polarity (N×Tpulse≦Tout<N×Tpulse+0.5×Tpulse), so (Tout-N×Tpulse) is added to the integrated value Tsum.

[0090] As described above, according to the third embodiment, by applying a switching pattern (state 4 in Table 1) that can maintain the exciting current during the inverter off period, it is not necessary to end the inverter operation period at the timing when the exciting current becomes 0 as in Patent Document 1, and flux bias can be suppressed in any inverter operation period.

[0091] Also, according to the third embodiment, by deriving and integrating the positive pulse width required for exciting current offset removal and selecting the first pulse polarity in the next inverter operation period based on this integrated value, the exciting current in the next inverter operation period can be made in a direction to suppress the offset, and the exciting current can be suppressed.

[0092] Also, according to the third embodiment, since operation control can be performed without the flux information of the core of the transformer 3, the additional flux measurement mechanisms in Patent Documents 2 and 3 are not required.

[0093] Also, since the first pulse width during the inverter operation period is fixed, the rising characteristics of the secondary-side DC voltage during the inverter operation period can be made consistent for each inverter operation period, and in power supply to an IC or the like having characteristics depending on a threshold value, the influence of variations in the voltage rising characteristics can be suppressed.

[0094] In the third embodiment, the range of the exciting current that can be obtained is twice that in the first embodiment. As a result, the magnetic flux generated in the transformer 3 can also be twice that in the first embodiment. Therefore, since the range of the exciting current that can be obtained is narrow in the first embodiment, it is suitable when it is desired to miniaturize the transformer 3. On the other hand, the third embodiment is suitable for devices in which it is desired to suppress the influence of variations in the voltage rising characteristics.

[0095] [Example 4] The main circuit of the present embodiment 4 is the same as that of embodiment 1. In embodiment 3, when performing intermittent operation in which the inverter is operated and stopped, the first pulse width of the inverter output voltage Vuv during the inverter operation period is fixed, thereby making the rise characteristics of the secondary side DC voltage uniform when switching from the inverter stop period to the inverter operation period.

[0096] In the third embodiment, when switching from an inverter operating period to an inverter non-operating period, variations occur in the falling characteristics of the secondary side DC voltage due to the influence of the dead time and minimum ON time of the inverter.

[0097] Here, "dead time" refers to the time during which a pair of series-connected switching elements of inverter 2 are simultaneously turned off to prevent a short circuit caused by the pair of switching elements being simultaneously turned on (the control signal being turned on at the same time). Also, "minimum ON time" refers to the minimum ON time allowed by the control signal for turning on inverter 2.

[0098] The principle behind the occurrence of variations in the falling characteristics of the secondary side DC voltage will be explained using Figure 12. In Figure 12, the switching element state is State 1 in Table 1 when the inverter output voltage is +V1, State 2 when the inverter output voltage is -V1, State 3 during the zero voltage period while the inverter is operating, and State 4 during the inverter rest period.

[0099] (1) When the inverter operation command changes from ON to OFF after the minimum ON time has elapsed since the state became 1 or 2 As shown in FIG. 12(1), the inverter output voltage is +V1 or −V1 until just before switching from the inverter operating period to the inverter idle period, and from the switching timing the inverter output voltage becomes 0 and the secondary side DC voltage begins to drop.

[0100] (2) When the inverter operation command changes from ON to OFF before the minimum ON time has elapsed after entering state 1 or 2 As shown in (2) of Figure 12, the minimum ON time has not yet elapsed immediately after switching from the inverter operating period to the inverter pause period, so inverter 2 waits for the minimum ON time to elapse before pausing (minimum ON time processing). As a result, the inverter output voltage becomes 0 with a delay from the switching timing, and the secondary side DC voltage begins to drop.

[0101] (3) When the inverter operation command changes from ON to OFF during state 3 As shown in (3) of Figure 12, inverter 2 is already in dead time immediately before switching from the inverter operating period to the inverter pause period, so the inverter output voltage becomes 0 from the moment the dead time begins. Therefore, the inverter output voltage becomes 0 before the switching timing, and the secondary side DC voltage begins to decrease.

[0102] Depending on which of the above three patterns is satisfied, the falling characteristics of the secondary side DC voltage when switching from the inverter operating period to the inverter non-operating period differ.

[0103] In Patent Document 1, magnetic saturation of the transformer core is suppressed by using an inverter output voltage pattern that causes the inverter to enter an inverter pause period when the excitation current becomes 0. With this method, the excitation current becomes 0 only twice per pulse cycle, making it difficult to switch from the inverter operating period to the inverter pause period at any desired timing.

[0104] In the fourth embodiment, the switching element pattern is corrected so that dead time and minimum ON time processing do not occur at the timing of switching from the inverter operating period to the inverter idle period. As a result, the secondary DC voltage command always starts to decrease from the timing of switching from the inverter operating period to the inverter idle period, as in "(1) The inverter operation command changes from ON to OFF after the minimum ON time has elapsed since entering states 1 and 2" in Fig. 12.

[0105] The fourth embodiment aims to suppress variations in the fall characteristics of the secondary-side DC voltage. By combining the third embodiment, which suppresses variations in the rise characteristics of the secondary-side DC voltage, with the fourth embodiment, which suppresses variations in the fall characteristics, it becomes possible to output the secondary-side DC voltage for the same period as the ON time of the inverter operation command. As a result, it is possible to make the rise and fall characteristics of the secondary-side DC voltage uniform when the ON time of the inverter operation command is arbitrarily varied.

[0106] In the fourth embodiment, a method of delaying the switching timing (maintaining the immediately preceding state) will be described.

[0107] As shown in Figures 13 to 15, a delayed inverter operation command is generated by delaying the inverter operation command by the "dead time + minimum ON time." A delayed inverter output voltage command is generated based on the delayed inverter operation command. Specifically, a signal that alternately outputs +V1 and -V1 while the delayed inverter operation command is ON becomes the delayed inverter output voltage command. A signal that corrects this delayed inverter output voltage command becomes the corrected inverter output voltage command. When inverter 2 is controlled based on the corrected inverter output voltage command, an inverter output voltage waveform is generated, and the secondary side DC voltage waveform decreases from the moment the inverter output voltage waveform becomes 0.

[0108] This section explains how to correct the delayed inverter output voltage command to a corrected inverter output voltage command. The delayed inverter output voltage command is held at a value for the period from the timing when the inverter operation command switches from ON to OFF to the dead time + minimum ON time (until the delayed inverter operation command switches from ON to OFF), and then corrected to 0 to generate the corrected inverter output voltage command. For other periods, the delayed inverter output voltage command and the corrected inverter output voltage command are the same. This makes it possible to supply secondary DC voltage for the same period as the operation time of the inverter operation command, without being affected by the dead time or minimum ON time.

[0109] (1) Before delay, the inverter output voltage command (not shown) changes to state 1 or 2, and after the minimum ON time has elapsed, the inverter operation command changes from ON to OFF. As shown in Figure 13, there is no change between the delayed inverter output voltage command and the corrected inverter output voltage command. The secondary DC voltage starts to decrease from the timing when the delayed inverter operation command is turned OFF (switching from the inverter operation period to the inverter pause period).

[0110] (2) Before the minimum ON time has elapsed since the inverter output voltage command before delay (not shown) has become state 1 or 2, the inverter operation command is turned ON to OFF. For reference, Figure 14 shows the inverter output voltage waveform based on the delayed inverter output voltage command. As shown in Figure 14, in the inverter output voltage waveform based on the delayed inverter output voltage command, the minimum ON time processing continues at the timing when the delayed inverter operation command is turned OFF. Therefore, with a delayed inverter output voltage command, it was necessary to extend the inverter operation period from the delayed inverter operation command value to ensure the minimum ON time.

[0111] The corrected inverter output voltage command holds its value for the period from when the inverter operation command switches from ON to OFF until the delayed inverter operation command switches from ON to OFF, and then becomes 0. This avoids the minimum ON time, and the secondary DC voltage begins to decrease from the time when the delayed inverter operation command switches OFF (switching from the inverter operation period to the inverter pause period).

[0112] In addition, due to the effect of the correction from the delayed inverter output voltage command to the corrected inverter output voltage command, the period of states 1 and 2 immediately before the inverter operation stops is extended by up to "dead time + minimum ON time" compared to normal, and the absolute value of the excitation current of transformer 3 also increases accordingly.

[0113] (3) Before the delay, the inverter output voltage command (not shown) is in state 3, and the inverter operation command changes from ON to OFF. For reference, the inverter output voltage waveform based on the delayed inverter output voltage command is shown in Figure 15. As shown in Figure 15, the inverter output voltage waveform based on the delayed inverter output voltage command becomes 0 before the delayed inverter operation command is turned OFF due to the influence of dead time, and the timing at which the secondary side DC voltage drops also occurs earlier than the timing at which the delayed inverter operation command is turned OFF.

[0114] The corrected inverter output voltage command holds its value for the period from when the inverter operation command switches from ON to OFF until the delayed inverter operation command switches from ON to OFF, and then becomes 0. As a result, the secondary DC voltage starts to decrease from the time when the delayed inverter operation command switches OFF (switching from the inverter operation period to the inverter pause period).

[0115] In addition, due to the effect of the correction from the delayed inverter output voltage command to the corrected inverter output voltage command, the period of states 1 and 2 immediately before the inverter operation stops is extended by up to "dead time + minimum ON time" compared to normal, and the absolute value of the excitation current of transformer 3 also increases accordingly.

[0116] As described above, according to the fourth embodiment, by correcting the inverter output voltage command, it is possible to avoid the occurrence of dead time and minimum ON time processing when switching from the inverter operating period to the inverter idle period, and it is possible to reduce the secondary-side DC voltage from the timing of switching from the inverter operating period to the inverter idle period. This makes it possible to suppress variations in the falling characteristics of the secondary-side DC voltage.

[0117] [Example 5] In the fifth embodiment, a method for suppressing variations in the falling characteristics of the secondary side DC voltage will be described, similar to the fourth embodiment. In the fifth embodiment, a method for advancing the switching timing (immediate switching) will be described.

[0118] As shown in Figures 16 to 18, a pre-delay inverter output voltage command is generated based on the inverter operation command, and a delayed inverter output voltage command is generated by delaying the pre-delay inverter output voltage command by the "dead time + minimum ON time." The delayed inverter output voltage command is corrected to generate a corrected inverter output voltage command. When inverter 2 is controlled based on the corrected inverter output voltage command, the inverter output voltage waveform is generated, and the secondary side DC voltage waveform decreases from the moment the inverter output voltage waveform becomes zero.

[0119] The method for correcting the delayed inverter output voltage command to a corrected inverter output voltage command is explained below. The corrected inverter output voltage command is generated so that the delayed inverter output voltage command is set to 0 after holding its value for the dead time + minimum ON time from the timing when the inverter operation command switches from ON to OFF, or the polarity of the value is reversed at the timing when the inverter operation command switches from ON to OFF and held for the dead time + minimum ON time before being set to 0. For other periods, the delayed inverter output voltage command and the corrected inverter output voltage command are the same.

[0120] A method for correcting the delayed inverter output voltage command to the corrected inverter output voltage command will be specifically described below. When the inverter operation command is switched to OFF, the pre-delay inverter output voltage command and the post-delay inverter output voltage command are compared.

[0121] If they match, the delayed inverter output voltage command is used as the corrected inverter output voltage command. In other words, the corrected inverter output voltage command holds its value for the dead time plus the minimum ON time from the time the inverter operation command switches from ON to OFF, and then becomes 0.

[0122] On the other hand, if the comparison results in a mismatch, the delayed inverter output voltage command is corrected to 0 after immediately reversing the polarity of the value at the timing when the inverter operation command switches from ON to OFF and maintaining it for the "dead time + minimum ON time," thereby generating a corrected inverter output voltage command.

[0123] This allows the secondary DC voltage to be supplied for the same duration as the inverter operation command, without being affected by dead time or minimum ON time. For reference, Figures 17 and 18 also show the inverter output voltage waveform based on the delayed inverter output voltage command.

[0124] (1) Before delay, the inverter output voltage command changes to state 1 or 2, and then after the minimum ON time has elapsed, the inverter operation command changes from ON to OFF. As shown in Figure 16, the pre-delay inverter output voltage command generated based on the inverter operation command and the delayed inverter output voltage command match at the timing when the inverter operation command is switched OFF. Therefore, the delayed inverter output voltage command becomes the corrected inverter output voltage command as is. In other words, the corrected inverter output voltage command is a signal that becomes 0 after being held for the dead time + minimum ON time from the timing when the inverter operation command is switched from ON to OFF. Inverter 2 is operated based on the corrected inverter output voltage command. In this case, the secondary-side DC voltage begins to decrease after the dead time + minimum ON time has elapsed since the inverter operation command was switched from ON to OFF (switching from the inverter operation period to the inverter pause period).

[0125] (2) Before the delay, the inverter output voltage command changes from ON to OFF before the minimum ON time has elapsed after the inverter output voltage command changes to state 1 or 2. As shown in Figure 17, when the inverter operation command is switched OFF, the pre-delay inverter output voltage command generated based on the inverter operation command and the post-delay inverter output voltage command do not match. Therefore, the corrected inverter output voltage command immediately reverses its polarity when the inverter operation command is switched OFF, and is held for the "dead time + minimum ON time", before becoming 0.

[0126] As a result, dead time and minimum ON time processing occurs from the moment the inverter operation command is switched OFF, and once these are completed (the moment the inverter operation period switches to the inverter pause period), the secondary side DC voltage begins to decrease.

[0127] In addition, due to the effect of the correction from the delayed inverter output voltage command to the corrected inverter output voltage command, the period of states 1 and 2 immediately before the inverter operation stops is shortened by up to "dead time + minimum ON time" compared to normal, and the switching frequency of the switching elements that make up inverter 2 increases.

[0128] (3) Before the delay, the inverter output voltage command is in state 3, and the inverter operation command is turned ON to OFF. As shown in Figure 18, when the inverter operation command is switched OFF, the pre-delay inverter output voltage command generated based on the inverter operation command and the post-delay inverter output voltage command do not match. Therefore, the corrected inverter output voltage command immediately reverses its polarity when the inverter operation command is switched OFF, and is held for the "dead time + minimum ON time", before being set to 0.

[0129] As a result, dead time and minimum ON time processing occurs from the moment the inverter operation command is switched OFF, and once these are completed (the moment the inverter operation period switches to the inverter pause period), the secondary side DC voltage begins to decrease.

[0130] Note that due to the effect of the correction from the delayed inverter output voltage command to the corrected inverter output voltage command, the period of states 1 and 2 immediately before the inverter operation stops is shortened by up to "dead time + minimum ON time" compared to normal, and the switching frequency of the switching elements that make up the inverter increases.

[0131] As described above, the fifth embodiment has the same effects as the fourth embodiment.

[0132] Note that if there is a margin in the excitation current determined by the characteristics of the transformer's magnetic core material, its relationship with the drive frequency, dimensional constraints, etc., the configuration of Example 4 is more suitable. If there is a margin in the switching frequency determined by the characteristics of the switching elements and the allowable range of switching loss, the configuration of Example 5 is more suitable. Alternatively, the difficulty of designing to expand either allowable range can be compared, and an Example corresponding to the side that is easier to change can be selected.

[0133] Although the present invention has been described in detail above only with respect to the specific examples, it will be apparent to those skilled in the art that various modifications and variations are possible within the scope of the technical concept of the present invention, and it is natural that such modifications and variations fall within the scope of the claims.

[0134] In the third embodiment, the threshold value to be compared with the integrated value is set to 0.5 times the pulse period, but it may be set to a value other than 0.5. However, when the threshold value is greater than 0.5 times the pulse period, the range that the excitation current can take becomes wider than when the threshold value is 0.5 times the pulse period. [Explanation of symbols]

[0135] 1...first DC voltage source, 2...inverter, 3...transformer, 4...rectifier, 5...second DC voltage source, 6...load, S1 to S6...first to sixth switching elements, D1 to D6...first to sixth diodes

Claims

1. An isolated DC / DC converter that applies pulse density control through intermittent operation, a first DC voltage source; an inverter having a DC side connected to the first DC voltage source; a transformer having a primary winding connected to the AC side of the inverter; a rectifier connected to a secondary winding of the transformer; a second DC voltage source connected to the DC side of the rectifier; Equipped with The inverter is an isolated DC / DC converter generating a corrected inverter output voltage command that holds a value for a period of a dead time plus a minimum ON time from the timing when an inverter operation command switches from ON to OFF and then sets the value to 0, or that inverts the polarity of the value at the timing when the inverter operation command switches from ON to OFF, holds the value for a period of a dead time plus a minimum ON time, and then sets the value to 0, and controls the inverter based on the corrected inverter output voltage command.

2. The inverter is A delayed inverter operation command is generated by delaying the inverter operation command by a dead time plus a minimum ON time. generating a delayed inverter output voltage command based on the delayed inverter operation command; 2. The isolated DC / DC converter according to claim 1, wherein the delayed inverter output voltage command is corrected to become 0 after holding its value for a period of a dead time plus a minimum ON time from the timing at which the inverter operation command switches from ON to OFF, thereby generating the corrected inverter output voltage command.

3. The inverter control unit generating a pre-delay inverter output voltage command based on the inverter operation command; generating a delayed inverter output voltage command by delaying the pre-delay inverter output voltage command by a dead time plus a minimum ON time; At a timing when the inverter operation command is switched from ON to OFF, the pre-delay inverter output voltage command is compared with the post-delay inverter output voltage command; When the pre-delay inverter output voltage command and the delayed inverter output voltage command match, the delayed inverter output voltage command is set as the corrected inverter output voltage command, 2. The isolated DC / DC converter according to claim 1, wherein, when the pre-delay inverter output voltage command and the delayed inverter output voltage command do not match, the delayed inverter output voltage command is corrected so that its polarity is inverted at the timing when the inverter operation command switches from ON to OFF, and the delayed inverter output voltage command is held for a period of a dead time plus a minimum ON time, and then becomes 0, thereby generating the corrected inverter output voltage command.

4. 1. A control method for an isolated DC / DC converter that employs pulse density control through intermittent operation, the method comprising: a first DC voltage source; an inverter having a DC side connected to the first DC voltage source; a transformer having a primary winding connected to the AC side of the inverter; a rectifier connected to a secondary winding of the transformer; and a second DC voltage source connected to the DC side of the rectifier, the method comprising: The inverter a corrected inverter output voltage command is generated, the corrected inverter output voltage command being set to 0 after holding the value for a period of a dead time plus a minimum ON time from the timing when an inverter operation command switches from ON to OFF, or the polarity of the corrected inverter output voltage command is reversed at the timing when the inverter operation command switches from ON to OFF, the corrected inverter output voltage command being held for a period of a dead time plus a minimum ON time, and then set to 0; and the inverter is controlled based on the corrected inverter output voltage command.

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