Data processor core, data processor, data processor device, data processing method, electronic device, computer program, and storage medium

Abstract

To provide a data processor core having high matrix calculation capability, a data processor, a data processor device, a data processing method, an electronic device, a computer program and a storage medium.SOLUTION: A processor core includes control means which is arranged so as to create a preheating command in response to detection of a calculation command to be processed, and a calculation means array including at least one calculation means sub-array, wherein the calculation means sub-array receives a preheating command to instruct the calculation means sub-array to execute read operation and calculation operation, comes into a preheating state on the basis of the preheating command, and switches from the preheating state to a calculation state in response to reception of a target command corresponding to the calculation command to be processed.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to the field of artificial intelligence, in particular to the field of integrated circuit technology and chip technology. More specifically, the present disclosure provides a data processor core, a data processor, a data processor device, a data processing method, an electronic device, a computer program, and a storage medium. [Background technology]

[0002] With the development of artificial intelligence technology, the application scenarios of artificial intelligence chips are increasing. AI chips have many multiply-accumulate (MAC) arrays and have strong matrix calculation capabilities. Summary of the Invention

[0003] The present disclosure provides a data processor core, a data processor, a data processor device, a data processing method, an electronic device, and a storage medium.

[0004] According to one aspect of the present disclosure, there is provided a data processor core including: control means arranged to generate a preheat command in response to detecting a computational command to be processed; and a computational means array including at least one computational means sub-array, the computational means sub-array arranged to receive a preheat command instructing the computational means sub-array to perform a read operation and a computational operation, enter a preheat state based on the preheat command, and switch from the preheat state to a computational state in response to receiving a target command corresponding to the computational command to be processed.

[0005] According to another aspect of the present disclosure, there is provided a data processor including at least one data processor core as provided herein.

[0006] According to another aspect of the present disclosure, there is provided a data processing device including a data processor as provided herein.

[0007] According to another aspect of the present disclosure, there is provided an electronic device including a data processing device as provided herein.

[0008] According to one aspect of the present disclosure, there is provided a data processing method, the method including receiving a preheat command generated upon detecting a computation command to be processed, the preheat command instructing a computation means sub-array to perform a read operation and a computation operation; entering a preheat state based on the preheat command; and switching from the preheat state to a computation state in response to receiving a target command corresponding to the computation command to be processed.

[0009] According to another aspect of the present disclosure, there is provided an electronic device including at least one processor and a memory communicatively coupled to the at least one processor, the memory storing instructions executable by the at least one processor, the instructions being executed by the at least one processor such that the at least one processor can perform a method provided in the present disclosure.

[0010] According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium having stored thereon computer instructions for causing a computer to perform a method provided in the present disclosure.

[0011] According to another aspect of the present disclosure, there is provided a computer program which, when executed by a processor, implements the methods provided in the present disclosure.

[0012] It should be understood that the contents described in this section are not intended to identify key features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will be readily apparent from the following specification. [Brief explanation of the drawings]

[0013] The drawings are for a better understanding of the invention and are not intended to limit the disclosure.

[0014] [Figure 1]FIG. 1 is a schematic diagram of the current and voltage of an artificial intelligence chip according to one embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic block diagram of a data processor core according to one embodiment of the present disclosure. [Figure 3A] FIG. 3A is a schematic diagram of a computing device sub-array in a preheated state according to one embodiment of the present disclosure. [Figure 3B] FIG. 3B is a schematic diagram of a computing means sub-array in a computing state according to one embodiment of the present disclosure. [Figure 4A] FIG. 4A is a schematic diagram of a computing means array according to one embodiment of the present disclosure. [Figure 4B] FIG. 4B is a schematic diagram of a group of computing means in a preheating state according to one embodiment of the present disclosure. [Figure 4C] FIG. 4C is a schematic diagram of a group of computing means in a preheating state according to one embodiment of the present disclosure. [Figure 4D] FIG. 4D is a schematic diagram of a group of computing means in a preheating state according to one embodiment of the present disclosure. [Figure 4E] FIG. 4E is a schematic diagram of a group of computing means in a preheating state according to one embodiment of the present disclosure. [Figure 4F] FIG. 4F is a schematic diagram of a computing means array in a computing state according to one embodiment of the present disclosure. [Figure 5] FIG. 5 is a schematic diagram of voltages and currents for a chip including a data processor core according to one embodiment of the present disclosure. [Figure 6] FIG. 6 is a schematic diagram of a data processor according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a schematic diagram of a data processing device according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a schematic flowchart of a data processing method according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a block diagram of an electronic device to which a data processing method according to an embodiment of the present disclosure can be applied. DETAILED DESCRIPTION OF THE INVENTION

[0015]

[0023] The following description of exemplary embodiments of the present disclosure will be made with reference to the drawings, and for ease of understanding, various details of the embodiments of the present disclosure will be included, which are merely illustrative. Therefore, as will be understood by those skilled in the art, various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for clarity and conciseness, the following description will omit descriptions of known functions and structures.

[0016] The computing power of an AI chip may be proportional to the number of resources in the computing means array. The higher the computing power of the chip, the higher the computing resources required. As a result, a chip with high computing power has a high driving current and power consumption. In addition, the operating frequency of the chip may be high, even greater than 1 gigahertz (GHz). The chip can reach peak power consumption or peak current in a short time. However, because the driving current response speed of the chip's power supply is relatively slow, further explanation will be given below with reference to FIG. 1.

[0017] FIG. 1 is a schematic diagram of the current and voltage of an artificial intelligence chip according to one embodiment of the present disclosure.

[0018] As shown in Figure 1, when the peak power consumption of a chip is determined, when the chip quickly switches from idle current to operating current, the chip's computing power approaches or reaches its peak computing power, but the chip's power supply voltage suddenly decreases (e.g., decreases to voltage VL11). When the chip quickly switches from operating current to idle current, the chip's computing power becomes nearly zero, but the chip's power supply voltage suddenly increases (e.g., increases to voltage VH11). Both sudden increases and decreases in power supply voltage can have adverse effects on the chip's circuitry. For example, a sudden increase in power supply voltage can destroy the circuit. A sudden decrease in power supply voltage can prevent the circuit from obtaining sufficient voltage, preventing the circuit from operating normally and potentially resulting in incorrect calculation results.

[0019] In some embodiments, to avoid sudden voltage increases or decreases, all computing means on a chip can be divided into blocks, resulting in multiple computing means arrays. The computing means can be a multiply-accumulate computing means. The computing means array can be configured to perform a calculation in response to receiving a pulse signal. When not receiving a pulse signal, the computing means array can be in an idle state. In the idle state, the computing means array does not perform a read operation, a calculation operation, or a write operation. The power consumption of the computing means array can be standby power consumption. The standby power consumption is small and smaller than the peak power consumption. This allows for block-by-block startup, preventing the computing power of the chip from quickly reaching its peak computing power. However, block-by-block startup will affect the computing power of the chip. This is because multiple computing means arrays on a chip are started up block by block, and during the startup process, the multiple computing means arrays are started up sequentially, limiting the computing power, lengthening the overall chip's computing time, and degrading performance.

[0020] Based on this, to provide chip longevity and keep the chip's computing power high, the present disclosure provides a data processor core, as further described below.

[0021] FIG. 2 is a schematic block diagram of a data processor core according to one embodiment of the present disclosure.

[0022] As shown in FIG. 2, the data processor core 20 may include a control means 201 and a computing means array 202 .

[0023] The control means 201 may be configured to generate a pre-heat command in response to detecting a computation command to be processed. In an embodiment of the present disclosure, the computation command to be processed may be a command related to a deep learning model and related to matrix calculation. For example, the control means generates a pre-heat command after receiving the computation command to be processed.

[0024] The computing means array 202 may include at least one computing means subarray. The computing means subarray may be configured to receive a preheat command, enter a preheat state in response to the preheat command, and switch from the preheat state to a computing state in response to receiving a target command corresponding to the computing command to be processed.

[0025] In the embodiments of the present disclosure, the calculation means array may be various calculation means arrays such as a multiply-accumulate means array, a multiplying means array or a convolution means array.

[0026] In an embodiment of the present disclosure, the preheat command can instruct the computing means subarray to perform read operations and computation operations. For example, the preheat command may instruct the computing means subarray to perform read operations and computation operations, and may instruct the computing means subarray not to perform write operations.

[0027] In an embodiment of the present disclosure, a target command can be determined based on a command to be processed. For example, the command to be processed can correspond to a processor core or a computing means array. The target command can correspond to a computing means sub-array. The array corresponding to the command to be processed can be divided to determine a sub-array corresponding to the target command.

[0028] According to an embodiment of the present disclosure, a sub-array of computing means enters a pre-heating state in response to a pre-heating command, gradually allowing the computing cores of the entire chip to reach or approach their peak power consumption. This reduces sudden changes in the chip's power consumption when processing a computing command, preventing a sudden increase in power consumption and a sudden drop in voltage, which helps improve the performance and lifespan of the chip. Furthermore, the voltage of the chip is relatively stable before receiving a target command, which improves the accuracy of calculation, thereby maintaining the chip's computing power at a high level and improving the accuracy of the calculation results.

[0029] As can be appreciated, the above describes the processor core of the present disclosure, and the following further describes the preheat and computation states of the present disclosure.

[0030] In the embodiment of the present disclosure, when the control means does not detect any computation command to be processed, the computation means sub-array is in an idle state, in which the computation means sub-array does not perform any read or computation operations.

[0031] In an embodiment of the present disclosure, when the control unit does not detect a calculation command to be processed, the calculation unit may receive a pre-heating command generated by the control unit. The pre-heating command may correspond to the first data. This will be further described below in conjunction with FIG. 3A.

[0032] FIG. 3A is a schematic diagram of a computing device sub-array in a preheated state according to one embodiment of the present disclosure.

[0033] In an embodiment of the present disclosure, the computing means subarray may be configured to read first data and enter a preheating state. A computing operation may be performed based on the first data. As shown in FIG. 3A , the computing means subarray 3021 may read the first data. Based on the first data D31, the computing means subarray 3021 may perform a computing operation to obtain a first computing result corresponding to the preheating command. The first computing result does not need to be written to a register or address space. During the process of performing the read operation and the computing operation, the computing means subarray 3021 may be in a preheating state. As can be understood, the state of the computing means subarray may include an idle state and an operating state. In an embodiment of the present disclosure, the operating state may include a preheating state. The preheating state may be an operating state in which a read operation and a computing operation are performed based on the first data. According to an embodiment of the present disclosure, the read operation and the computing operation are performed based on the first data, thereby gradually increasing the power consumption of the chip and conveniently realizing the preheating state.

[0034] As can be appreciated, the preheating aspect of the present disclosure has been described above, and the calculation aspect of the present disclosure will be further described below.

[0035] FIG. 3B is a schematic diagram of a computing means sub-array in a computing state according to one embodiment of the present disclosure.

[0036] In an embodiment of the present disclosure, the target command corresponds to the second data, and the target command instructs the computing means sub-array to perform a read operation, a computation operation, and a write operation. For example, the second data may be a sub-array associated with the computation command to be processed.

[0037] In an embodiment of the present disclosure, the computing means sub-array may be arranged to read the second data. As shown in Figure 3B, the computing means sub-array 3021 in the preheating state can read the second data D32.

[0038] In an embodiment of the present disclosure, the calculation means sub-array may be further configured to overwrite a result obtained by performing a calculation operation based on the first data with second data corresponding to the target command. For example, the second data D32 may overwrite the first calculation result described above. According to an embodiment of the present disclosure, overwriting the first calculation result corresponding to the preheat command with the second data can efficiently process the target command and save the calculation resources of the processor core.

[0039] In the embodiment of the present disclosure, the calculation means subarray may be further configured to perform a calculation operation based on the second data to obtain a target calculation result. For example, based on the second data D32, the calculation means subarray 3021 can perform a calculation operation to obtain a second calculation result corresponding to the target command as the target calculation result.

[0040] In an embodiment of the present disclosure, the computing means subarray may be further configured to write the target computation result to an address space corresponding to the target command and switch from the preheating state to the computation state. For example, the target command may correspond to address space Addr31. The target computation result may be written to address space Addr31. In the process of performing the read operation, the computation operation, and the write operation, the computing means subarray 3021 may be in the computation state. As can be understood, the state of the computing means subarray may include an idle state and an operating state. In an embodiment of the present disclosure, the operating state may further include a computation state. The computation state may perform the operating states of the read operation, the computation operation, and the write operation based on the second data.

[0041] As can be appreciated, the preheating state and operating state calculation means sub-arrays of the present disclosure have been described above, and the first data and second data of the present disclosure will be further described below.

[0042] In the embodiments of the present disclosure, the data type of the first data and the data type of the second data may be the same. For example, if the second data is floating-point data, the first data may be floating-point data. Also, for example, if the second data is fixed-point data, the first data may be fixed-point data.

[0043] In an embodiment of the present disclosure, the scale difference between the first data and the second data is less than or equal to a predetermined scale difference threshold. For example, if the scale of the second data is [n, c, h, w], the scale of the first data may be [n, c, h, w], where n, c, h, and w may be positive integers. According to an embodiment of the present disclosure, the type and scale of the first data and the second data are identical or similar, so that the computing means subarray can quickly adapt to the data type of the actual computing command, further improving the computing power of the chip and improving computing efficiency.

[0044] As can be appreciated, the above describes the first data and second data of the present disclosure, and below further describes the control means and computing means sub-arrays of the present disclosure.

[0045] In the embodiment of the present disclosure, the computing means array may include M computing means groups. The computing means groups may include at least one computing means sub-array. M may be an integer equal to or greater than 1. The following description will be given with reference to FIG. 4A.

[0046] FIG. 4A is a schematic diagram of a computing means array according to one embodiment of the present disclosure.

[0047] 4A, the computing means array 402 may include computing means subarray 40201, computing means subarray 40202, computing means subarray 40203, computing means subarray 40204, computing means subarray 40205, computing means subarray 40206, computing means subarray 40207, computing means subarray 40208, computing means subarray 40209, computing means subarray 40210, computing means subarray 40211, computing means subarray 40212, computing means subarray 40213, computing means subarray 40214, computing means subarray 40215, and computing means subarray 40216. It can be understood that for detailed descriptions of the computing means subarrays 40201 to 40216, reference can be made to the above-mentioned computing means subarray 3021, and detailed descriptions thereof will be omitted in the present disclosure.

[0048] 4A, the computing means array may include four computing means groups. The first computing means group may include computing means subarray 40201 to computing means subarray 40204. The second computing means group may include computing means subarray 40205 to computing means subarray 40208. The third computing means group may include computing means subarray 40209 to computing means subarray 40212. The fourth computing means group may include computing means subarray 40213 to computing means subarray 40216. As can be seen, in this embodiment, M=4.

[0049] As shown in FIG. 4A, the calculation means subarrays 40201 to 40216 may be in an idle state.

[0050] In an embodiment of the present disclosure, the control means may be arranged to generate a preheat command in response to detecting a computation command to be processed. The control means may then be arranged to output the preheat command to at least one computation means sub-array, as further described below with reference to Figures 4B to 4E.

[0051] 4B to 4E are schematic diagrams of a group of computing means in a preheating state according to an embodiment of the present disclosure.

[0052] In an embodiment of the present disclosure, the control means may be configured to output a preheat command to the m-th calculation means group of the M calculation means groups. For example, four preheat commands may be output to four calculation means subarrays of the first calculation means group, respectively. The calculation means subarrays 40201 to 40204 each receive a preheat command and can each enter a preheat state based on the preheat command. The calculation means subarrays 40201 to 40204 in the preheat state are shown in FIG. 4B.

[0053] In the preheat state, the sum of the first power consumptions for the computing means subarrays 40201 to 40204 may be, for example, 20% of the peak power consumption of the computing means array 402.

[0054] In an embodiment of the present disclosure, the control means may be further configured to output a preheat command to the (m+1)th computing means group of the M computing means groups in response to determining that N computing means subarrays in the (m)th computing means group enter a preheat state. m may be an integer greater than or equal to 1 and less than M. For example, after determining that four computing means subarrays in the first computing means group enter a preheat state, the control means may output a preheat command to four computing means subarrays in the second computing means group. The computing means subarrays 40205 to 40208 each receive a preheat command and enter a preheat state based on the preheat command. The computing means subarrays 40205 to 40208 in the preheat state are shown in FIG. 4C. According to an embodiment of the present disclosure, the preheat command can be sequentially provided to different computing means subarrays, thereby realizing an increase in power consumption, avoiding abrupt changes in power consumption, and preventing excessively low voltage.

[0055] In the preheating state, the sum of the first power consumptions of the computing means subarrays 40201 to 40208 may be, for example, 40% of the peak power consumption of the computing means array 402.

[0056] Next, after determining that the four computing means subarrays of the second computing means group have entered the preheat state, the control means may output a preheat command to the four computing means subarrays of the third computing means group. The computing means subarrays 40209 to 40212 each receive the preheat command and each enter the preheat state based on the preheat command. The computing means subarrays 40209 to 40212 in the preheat state are shown in FIG. 4D.

[0057] In the preheating state, the sum of the first power consumptions of the computing means subarrays 40201 to 40212 may be, for example, 60% of the peak power consumption of the computing means array 402.

[0058] Next, after determining that the four computing means subarrays of the third computing means group have entered the preheat state, the control means may output a preheat command to the four computing means subarrays of the fourth computing means group. The computing means subarrays 40213 to 40216 each receive the preheat command and each enter the preheat state based on the preheat command. The computing means subarrays 40213 to 40216 in the preheat state are shown in FIG. 4E.

[0059] In the preheat state, the sum of the first power consumptions for the computing means subarrays 40201 to 40216 may be, for example, 80% of the peak power consumption of the computing means array 402. As can be understood, the sum of the first power consumptions is an example, and in some other embodiments, in the preheat state, the sum of the first power consumptions for the computing means subarrays 40201 to 40216 may be, for example, equal to the peak power consumption of the computing means array 402.

[0060] As can be seen, above we describe several computing means sub-arrays entering a preheat state, and below we describe several forms of switching to a computing state.

[0061] FIG. 4F is a schematic diagram of a computing means array in a computing state according to one embodiment of the present disclosure.

[0062] In an embodiment of the present disclosure, the control means may be further configured to, in response to determining that the number of computing means subarrays in the preheating state is equal to or greater than a predetermined number threshold, output a target command to at least one target computing means subarray in the preheating state. For example, the predetermined number threshold may be related to the number of computing means subarrays in the computing means array. As shown in FIG. 4E , the computing means array 402 includes 16 computing means subarrays. The predetermined number threshold may be, for example, 12 or 16. For example, assuming that the predetermined number threshold is 16, after all of the computing means subarrays 40201 to 40216 enter the preheating state, the control means outputs a target command to each of the computing means subarrays 40201 to 40216, and the computing means subarrays 40201 to 40216 read second data, perform a calculation operation, and perform a write operation according to the respective target commands, and enter the calculation state. The computing means sub-arrays 40201 to 40216 in the computing state are shown in FIG. 4F.

[0063] In an embodiment of the present disclosure, the power consumption difference between the first power consumption corresponding to the preheating state and the second power consumption corresponding to the computing state is less than or equal to a predetermined power consumption difference threshold. For example, in the computing state, for the computing means subarrays 40201 to 40216, the sum of the second power consumptions may be, for example, 100% of the peak power consumption of the computing means array 402. The predetermined power consumption difference threshold may be, for example, 25%, and the power consumption difference (20%) between the sum of the second power consumptions and the sum of the first power consumptions is less than the predetermined power consumption difference threshold (25%).

[0064] For the sake of understanding, the above description of the present disclosure takes the control means 201 and the computing means array 202 as examples, but the present disclosure is not limited thereto, and there may be at least one control means and at least one computing means array, as will be further described below.

[0065] In the embodiments of the present disclosure, there may be a plurality of control means, a plurality of computing means arrays, and a control means may correspond to one computing means array. For example, the plurality of control means may include a first control means and a second control means. The plurality of computing means arrays may include a first computing means array and a second computing means array. The first control means may correspond to the first computing means array and generate a preheat command for the first computing means array. The second control means may correspond to the second computing means array and generate a preheat command for the second computing means array.

[0066] In some other embodiments of the present disclosure, the control means may correspond to multiple calculation means arrays, and multiple control means may correspond to one calculation means array, and the present disclosure is not limited thereto.

[0067] As can be appreciated, the control means and computing means array of the present disclosure have been described above, and the control means of the present disclosure will now be further described.

[0068] In an embodiment of the present disclosure, the control means may be further configured to, in response to determining that the target command has been executed, output a preheat command to a target computing means subarray in at least one computing state among the computing means subarrays. For example, the control means may output a preheat command to the computing means subarrays 40201 to 40216 so that the computing means subarrays 40201 to 40216 are switched from the computing state to the preheat state, respectively.

[0069] In an embodiment of the present disclosure, the control means may be further configured to output a predetermined command to the m-th calculation means group of the M calculation means groups. For example, four predetermined commands may be output to four calculation means subarrays of the first calculation means group, respectively. The calculation means subarrays 40201 to 40204 each receive the predetermined command and can switch from the preheating state to the idle state based on the predetermined command.

[0070] In an embodiment of the present disclosure, the control means may be further configured to output a predetermined command to the (m+1)th computing means group of the M computing means groups in response to determining that N computing means subarrays in the mth computing means group have been switched to the idle state. For example, after determining that four computing means subarrays in the first computing means group have been switched to the idle state, the control means may output a predetermined command to four computing means subarrays in the second computing means group. The computing means subarrays 40205 to 40208 may each receive the predetermined command and switch to the idle state based on the predetermined command.

[0071] Next, after determining that the four computing means subarrays of the second computing means group have been switched to the idle state, the control means may output a predetermined command to the four computing means subarrays of the third computing means group. The computing means subarrays 40209 to 40212 each receive the predetermined command and switch to the idle state based on the predetermined command.

[0072] Next, after determining that the four computing means subarrays of the third computing means group have switched to the idle state, the control means may output a predetermined command to the four computing means subarrays of the fourth computing means group. The computing means subarrays 40213 to 40216 each receive the predetermined command and switch to the idle state based on the preheating command. According to an embodiment of the present disclosure, the computing means arrays can be controlled to gradually reduce their power consumption from a predetermined value to standby power consumption. This can further reduce sudden changes in the chip's power consumption after completing a calculation, preventing a large and sudden drop in power consumption and a sudden increase in voltage, further improving the performance and lifespan of the chip.

[0073] As can be appreciated, the preheat command of the present disclosure has been further described above, and the voltages and currents of a chip including a data processor core of the present disclosure will now be described.

[0074] FIG. 5 is a schematic diagram of voltages and currents for a chip including a data processor core according to one embodiment of the present disclosure.

[0075] As described above, when the peak power consumption of the chip is determined, when the idle current is quickly switched to the operating current, the chip's computing power approaches or reaches the peak computing power, but the chip's power supply voltage drops sharply to voltage VL51.

[0076] 5, when the peak power consumption of a chip including, for example, processor core 20 is determined, the chip is gradually switched from an idle current to an operating current based on a preheat command. As the chip's computing power approaches or reaches the peak computing power, the supply voltage of the chip power supply is suddenly reduced to voltage VL52.

[0077] As shown in Figure 5, voltage VL52 is greater than voltage VL51, which significantly reduces the voltage fluctuation range of the chip when the chip gradually switches from idle current to working current based on the preheat command, which helps improve the performance and lifespan of the chip.

[0078] Also, as described above, when the operating current is quickly switched to the idle current, the chip's computing power becomes almost zero, but the chip power supply voltage increases rapidly to VH51.

[0079] 5, when the peak power consumption of a chip including, for example, processor core 20 is determined, the chip gradually switches from operating current to idle current based on the preheat command. When the computing power of the chip is nearly zero, the power supply voltage of the chip power supply also rapidly increases to voltage VH52.

[0080] 5, the voltage VH52 is smaller than the voltage VH51, which significantly reduces the voltage fluctuation range of the chip when the chip gradually switches from the operating current to the idle current based on the preheat command and the predetermined command, thereby improving the performance and lifespan of the chip.

[0081] As can be appreciated, the foregoing describes a data processor core of the present disclosure, and the following describes a data processor that includes the data processor core.

[0082] FIG. 6 is a schematic diagram of a data processor according to an embodiment of the present disclosure.

[0083] 6, a data processor P600 may include at least one data processor core 60. The data processor core 60 may be, for example, the data processor core 20 described above.

[0084] As can be appreciated, the disclosure has been described above as a data processor, and hereinafter as a data processing device that includes a data processor.

[0085] FIG. 7 is a schematic diagram of a data processing device according to an embodiment of the present disclosure.

[0086] 7, the data processing device 700 may include a data processor P700. The data processor P700 may be, for example, the data processor P600 described above.

[0087] As can be appreciated, the foregoing describes a data processing device of the present disclosure, and the following describes an electronic device that includes the data processing device.

[0088] FIG. 8 is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0089] 8, an electronic device 8000 may include a data processing device 800. The data processing device 800 may be, for example, the data processing device 700 described above.

[0090] For purposes of understanding, the electronic device of the present disclosure has been described above, and the data processing method of the present disclosure will now be described.

[0091] FIG. 9 is a schematic flowchart of a data processing method according to an embodiment of the present disclosure.

[0092] As shown in FIG. 9, the method 900 may include operations S910 to S930.

[0093] In operation S910, a preheat command is received. In an embodiment of the present disclosure, the preheat command is generated when a calculation command to be processed is detected.

[0094] In operation S920, a preheat state is entered based on a preheat command.

[0095] In operation S930, switch from the preheat state to the calculation state in response to receiving a target command corresponding to the calculation command to be processed.

[0096] In an embodiment of the present disclosure, the method 900 can be implemented using the above-described computing means sub-array.

[0097] In an embodiment of the present disclosure, the preheat command instructs the computing means sub-array to perform a read operation and a computing operation. For example, the preheat command may be generated by the control means described above.

[0098] In some embodiments, the preheat command corresponds to the first data.

[0099] In some embodiments, entering the preheat state based on the preheat command includes reading first data and entering the preheat state. Performing a calculation operation based on the first data.

[0100] In some embodiments, the target command corresponds to the second data, and the target command instructs the computing means sub-array to perform a read operation, a computation operation, and a write operation.

[0101] In some embodiments, switching from the preheat state to the calculation state includes reading second data and switching from the preheat state to the calculation state. Performing a calculation operation based on the second data to obtain a target calculation result. The target calculation result is written to an address space corresponding to the target command.

[0102] In some embodiments, the method 900 further includes overwriting the results obtained by performing the computational operation based on the first data with second data corresponding to the target command.

[0103] In some embodiments, a target command is output to a target computing means subarray in at least one computing means subarray in a preheat state when it is determined that the number of computing means subarrays in a preheat state is equal to or greater than a predetermined number threshold.

[0104] In some embodiments, the computing means array includes M computing means groups, each of which includes at least one computing means sub-array, where M is an integer greater than or equal to one.

[0105] In some embodiments, the method 900 further includes outputting a preheat command to an m-th group of computing means of the M group of computing means, and outputting a preheat command to an m+1-th group of computing means of the M group of computing means in response to N computing means subarrays in the m-th group of computing means determining to enter the preheat state, where m is an integer greater than or equal to 1 and less than M.

[0106] In some embodiments, a power consumption difference between the first power consumption corresponding to the preheat state and the second power consumption corresponding to the calculation state is less than or equal to a predetermined power consumption difference threshold.

[0107] In some embodiments, the preheat command corresponds to first data, the target command corresponds to second data, the data type of the first data matches the data type of the second data, and a magnitude difference between the first data and the second data is less than or equal to a predetermined magnitude difference threshold.

[0108] In the technical solution disclosed herein, the collection, storage, use, processing, transmission, provision, disclosure and application of such user personal information shall all comply with the provisions of relevant laws and regulations, adopt necessary confidentiality measures, and not violate public order and morals.

[0109] According to embodiments of the present disclosure, the present disclosure further provides an electronic device, a readable storage medium, and a computer program product.

[0110] 10 shows an exemplary block diagram for implementing an example electronic device 1000 according to an embodiment of the present disclosure. The electronic device is intended to represent various types of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. The electronic device may also represent various types of mobile devices, such as personal digital assistants, mobile phones, smartphones, wearable devices, and other similar computing devices. The components, their connections and relationships, and their functions shown herein are merely exemplary and do not limit the implementation of the present disclosure as described and / or claimed herein.

[0111] 10, electronic device 1000 includes a computing means 1001, which can perform various appropriate operations and processes based on a computer program stored in a read-only memory (ROM) 1002 or loaded from a storage means 1008 into a random access memory (RAM) 1003. RAM 1003 can further store various programs and data necessary for the operation of electronic device 1000. The computing means 1001, ROM 1002, and RAM 1003 are interconnected via a bus 1004. An input / output (I / O) interface 1005 is also connected to bus 1004.

[0112] The multiple components in the electronic device 1000 are connected to an I / O interface 1005, and include input means 1006 such as a keyboard, a mouse, etc., output means 1007 such as various types of displays, speakers, etc., storage means 1008 such as a magnetic disk, an optical disk, etc., and communication means 1009 such as a network card, a modem, a wireless communication transceiver, etc. The communication means 1009 enables the electronic device 1000 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunications networks.

[0113] The computing means 1001 may be various general-purpose and / or specialized processing modules having processing and computing capabilities. Some examples of the computing means 1001 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various machine learning model algorithm computing means, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing means 1001 executes each of the methods and processes described above, such as the data processing methods. For example, in some embodiments, the data processing methods may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage means 1008. In some embodiments, some or all of the computer program may be loaded and / or installed into the electronic device 1000 via the ROM 1002 and / or the communication means 1009. When the computer program is loaded into the RAM 1003 and executed by the computing means 1001, it may perform one or more steps of the data processing methods described above. Alternatively, in another embodiment, the computing means 1001 may be configured to perform the data processing method in any other suitable manner (eg via firmware).

[0114] Various embodiments of the systems and techniques described herein may be implemented in digital electronic circuitry systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may be embodied in one or more computer programs that can be executed and / or interpreted by a programmable system that includes at least one programmable processor, which may be a special purpose or general purpose programmable processor, and that can receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0115] Program codes for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, so that when the program code is executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are performed. The program code may be executed entirely on a device, partially on a device, partially on a device as a separate software package, and partially on a remote device, or entirely on a remote device or server.

[0116] In the context of this disclosure, a machine-readable medium may be a tangible medium, and may contain or store a program for use in or in connection with an instruction execution system, apparatus, or electronic device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or electronic device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include an electrical connection of one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0117] To provide interaction with a user, a computer may implement the systems and techniques described herein and include a display device (e.g., a cathode ray tube (CRT) display or a liquid crystal display (LCD)) for displaying information to a user, and a keyboard and pointing device (e.g., a mouse or trackball) through which a user can provide input to the computer. Other types of devices may also provide interaction with a user; for example, the feedback provided to the user may be any form of sensing feedback (e.g., visual feedback, auditory feedback, or tactile feedback) and may receive input from the user in any form (including voice input, speech input, or tactile input).

[0118] It should be understood that various types of flows shown above may be used, and steps may be rearranged, added, or deleted. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present disclosure can be achieved, and the present specification is not limited thereto.

[0119] The specific embodiments described above do not limit the scope of protection of the present disclosure. Those skilled in the art should understand that various modifications, combinations, subcombinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present disclosure should be included within the scope of protection of the present disclosure.

Claims

1. 1. A data processor core, comprising: control means arranged to generate a preheat command in response to detecting a computation command to be processed; a computing means array including at least one computing means sub-array; The computing means sub-array comprises: receiving the preheat command instructing the computing means sub-array to perform read and computing operations but not write operations; According to the preheat command, read first data corresponding to the preheat command to enter a preheat state, and perform a calculation operation according to the first data; configured to, in response to receiving a target command corresponding to the calculation command to be processed, read second data corresponding to the target command and switch from the preheating state to a calculation state; The target commands direct the computation means sub-arrays to perform read operations, computation operations, and write operations. Processor core.

2. The computing means sub-array further comprises: reading the second data and switching from the preheating state to the calculation state; Performing a calculation operation based on the second data to obtain a target calculation result; and arranged to write the target calculation result to an address space corresponding to the target command. The processor core of claim 1 .

3. The computing means sub-array further comprises: and configured to overwrite a result obtained by performing a calculation operation based on said first data based on second data corresponding to said target command. The processor core of claim 1 .

4. The control means further and configured to output the target command to a target computing means subarray in at least one of the computing means subarrays in the preheat state in response to determining that the number of the computing means subarrays in the preheat state is equal to or greater than a predetermined number threshold. The processor core of claim 1 .

5. the computing means array includes M (M is an integer equal to or greater than 1) computing means groups, each of which includes at least one computing means subarray; The control means further outputting the preheat command to an m-th (m is an integer equal to or greater than 1 and less than M) calculation means group of the M calculation means; is configured to output the preheat command to an m+1-th calculation means group of M calculation means in response to the N calculation means subarrays in the m calculation means group determining to enter the preheat state. The processor core of claim 1 .

6. A power consumption difference between the first power consumption corresponding to the preheating state and the second power consumption corresponding to the calculation state is less than or equal to a predetermined power consumption difference threshold. The processor core of claim 1 .

7. The data type of the first data matches the data type of the second data; The magnitude difference between the first data and the second data is equal to or less than a predetermined magnitude difference threshold. The processor core of claim 1 .

8. The control means is plural, The computing means array is plural, and the control means corresponds to one of the computing means arrays. The processor core of claim 1 .

9. Comprising at least one data processor core according to any one of claims 1 to 8 Data processor.

10. 10. A data processor comprising: Data processing device.

11. A data processing device according to claim 10 electronic equipment.

12. A data processing method executed by at least one sub-array of computing means included in a computing means array of a data processor core, comprising: receiving a preheat command generated upon detecting a computation command to be processed, the preheat command instructing the computation means sub-array to perform read and computation operations but not write operations; According to the preheat command, read first data corresponding to the preheat command to enter a preheat state, and perform a calculation operation according to the first data; in response to receiving a target command corresponding to the calculation command to be processed, reading second data corresponding to the target command and switching from the preheating state to a calculation state; The target commands direct the computation means sub-arrays to perform read operations, computation operations, and write operations. Data processing methods.

13. Switching from the preheating state to the calculation state comprises: reading the second data and switching from the preheating state to the calculating state; performing a calculation operation based on the second data to obtain a target calculation result; and writing the target calculation result into an address space corresponding to the target command. The method of claim 12.

14. and overwriting a result obtained by performing a calculation operation based on the first data based on the second data. The method of claim 12.

15. The target command is output to a target computing means subarray in at least one of the computing means subarrays in the preheating state when it is determined that the number of the computing means subarrays in the preheating state is equal to or greater than a predetermined number threshold. The method of claim 12.

16. the computing means array includes M (M is an integer equal to or greater than 1) computing means groups, each of which includes at least one computing means subarray; The method comprises: outputting the preheat command to an m-th (m is an integer equal to or greater than 1 and less than M) group of calculation means of the M group of calculation means; outputting the preheat command to the (m+1)th computing means group of the M computing means group in response to the N computing means subarrays in the m computing means group determining to enter the preheat state; The method of claim 12.

17. A power consumption difference between the first power consumption corresponding to the preheating state and the second power consumption corresponding to the calculation state is less than or equal to a predetermined power consumption difference threshold. The method of claim 12.

18. the preheat command corresponds to first data, the target command corresponds to second data; the data type of the first data and the data type of the second data match; The magnitude difference between the first data and the second data is equal to or less than a predetermined magnitude difference threshold. The method of claim 12.

19. at least one processor; a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor such that the at least one processor can perform the method of any one of claims 12 to 18. electronic equipment.

20. A non-transitory computer-readable storage medium having computer instructions stored thereon, comprising: The computer instructions cause a computer to carry out the method of any one of claims 12 to 18. A non-transitory computer-readable storage medium having computer instructions stored thereon.

21. A computer program which, when executed by a processor, implements the method according to any one of claims 12 to 18.

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