Method for manufacturing ceramic circuit board and method for manufacturing semiconductor device

Abstract

To provide a ceramic circuit board having a good adhesion with a mold resin, and provide a manufacturing method for obtaining a semiconductor device.SOLUTION: A manufacturing method of a ceramic circuit board according to an embodiment, comprises: a first step of manufacturing a lamination body to which a plurality of metal parts is bonded to each of a plurality of first regions on a first surface of a ceramic substrate; and a second step of executing an etching step or a chemical polishing step to a second region positioned to between the adjacent first regions on the first surface. In the case where an average length RSm in the second region after the second step is measured under a measurement condition that λs filter is presence, λs cutoff ratio is 300, a cutoff type is Gaussian, and a cutoff wavelength (λc) is 0.8 mm, the average length RSm is 40 μm or larger.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments described below generally relate to a method for manufacturing a ceramic circuit board and a method for manufacturing a semiconductor device. [Background technology]

[0002] In recent years, as industrial equipment has become more sophisticated, the power output of the power modules mounted therein has been increasing. Accordingly, the output of semiconductor elements has also been increasing. The guaranteed operating temperature of semiconductor elements is 125°C to 150°C, but this may rise to 175°C or higher in the future. Ceramic circuit boards are used as circuit boards on which semiconductor elements are mounted. Ceramic circuit boards include a ceramic substrate and a metal plate bonded thereon. For example, Japanese Patent No. 6789955 (Patent Document 1) describes a metal plate having a protruding portion where the bonding layer protrudes from the edge of the metal plate. In Patent Document 1, the TCT characteristics (thermal cycle resistance characteristics) are improved by controlling the hardness and size of the protruding portion of the bonding layer.

[0003] In addition, a resin mold may be applied to protect the semiconductor element. The mold resin protects the semiconductor element and wiring from external stress. The mold resin also protects the semiconductor element from external air such as humidity.

[0004] As the guaranteed operating temperature of semiconductor elements rises, the adhesion between ceramic circuit boards and molding resins has become an issue. The difference in the thermal expansion coefficient between the ceramic circuit board and the molding resin has caused the molding resin to peel off from the ceramic circuit board. Peeling of the molding resin causes poor conductivity of semiconductor elements, etc.

[0005] For example, in International Publication No. 2018 / 173921 (Patent Document 2), a recess is provided in a copper plate of a ceramic circuit board, and in Japanese Patent Application Laid-Open No. 2021-68850 (Patent Document 3), a recess is provided in a ceramic substrate. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 6789955 [Patent Document 2] International Publication No. 2018 / 173921 [Patent Document 3] Patent Publication No. 2021-68850 [Patent Document 4] International Publication No. 2019 / 054294 Summary of the Invention [Problem to be solved by the invention]

[0007] In the ceramic circuit boards of Patent Documents 2 and 3, recesses are provided in the metal plate or ceramic substrate to improve adhesion with the mold resin. Meanwhile, in recent years, the mounting density of semiconductor elements on ceramic circuit boards has been increasing. One method for increasing the mounting density is to increase the mounting area of ​​semiconductor elements on the surface of the metal plate. Another method for increasing the mounting area on the surface of the metal plate is to increase the flat surface of the metal plate. Another method is to increase the mounting area of ​​the metal plate by narrowing the distance between the metal plates. The method of providing recesses in the metal plate, as in Patent Document 2, does not allow for an increase in the mounting area. It could not be said that conventional ceramic circuit boards were able to sufficiently achieve both sufficient mounting area and adhesion with the mold resin.

[0008] The embodiments address these issues and provide a method for manufacturing a ceramic circuit board and a method for manufacturing a semiconductor device that can ensure both a sufficient mounting area and good adhesion to the molding resin. [Means for solving the problem]

[0009] A method for manufacturing a ceramic circuit board according to an embodiment includes a first step of producing a laminate in which a plurality of metal portions are bonded to a plurality of first regions on a first surface of a ceramic substrate, and a second step of etching or chemically polishing a second region located between adjacent first regions on the first surface. When the average length RSm of the second region after the second step is measured under the following measurement conditions: λs filter: present, λs cutoff ratio: 300, cutoff type: Gaussian, and cutoff wavelength (λc): 0.8 mm, the average length RSm is 40 μm or more. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view showing an example of a ceramic circuit substrate according to an embodiment. [Figure 2] FIG. 1 is a side view showing an example of a ceramic circuit substrate according to an embodiment. [Figure 3] FIG. 1 is a plan view showing an example of a ceramic substrate. [Figure 4] FIG. 2 is a side view showing an example of a ceramic substrate. [Figure 5] FIG. 10 is a plan view showing another example of a ceramic substrate. [Figure 6] FIG. 10 is a plan view showing another example of a ceramic substrate. [Figure 7] FIG. 1 is a side view showing an example of a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] A method for manufacturing a ceramic circuit board according to an embodiment includes a first step of producing a laminate in which a plurality of metal portions are bonded to a plurality of first regions on a first surface of a ceramic substrate, and a second step of etching or chemically polishing a second region located between adjacent first regions on the first surface. When the average length RSm of the second region after the second step is measured under the following measurement conditions: λs filter: present, λs cutoff ratio: 300, cutoff type: Gaussian, and cutoff wavelength (λc): 0.8 mm, the average length RSm is 40 μm or more.

[0012] Fig. 1 is a plan view showing an example of a ceramic circuit board according to an embodiment. Fig. 2 is a side view showing an example of a ceramic circuit board according to an embodiment. In Figs. 1 and 2, reference numeral 1 indicates a ceramic circuit board. Reference numeral 2 indicates a ceramic substrate. Reference numeral 3 indicates a metal portion. In the ceramic circuit board 1, a plurality of metal portions 3 are provided on at least one surface of a ceramic substrate 2, with a plurality of bonding layers 4 interposed therebetween.

[0013] Fig. 3 is a plan view showing an example of a ceramic substrate. Fig. 4 is a side view showing an example of a ceramic substrate. In Figs. 3 and 4, reference numeral 2a denotes a first surface (front surface) of the ceramic substrate 2. Reference numeral 2b denotes a second surface (rear surface) of the ceramic substrate 2. The second surface 2b is located on the opposite side to the first surface 2a.

[0014] As shown in Figures 3 and 4, the first surface 2a includes two or more first regions r1 and one or more second regions r2. In Figure 3, the first region r1 is indicated by a two-dot chain line. The second region r2 is indicated by dots. Also in Figure 3, the metal portion 3 bonded to the first surface 2a is indicated by a dashed line. The metal portion 3 is bonded to the first region r1. The second region r2 is located between the first regions r1. No metal portion 3 is provided on the second region r2. The second region r2 is sometimes called an inter-pattern region. In the illustrated example, three metal portions 3 are arranged on the ceramic substrate 2. In this case, the first surface 2a of the ceramic substrate 2 includes three first regions r1 and two second regions r2.

[0015] More specifically, the second region r2 is a region located between adjacent first regions r1 in the direction in which the distance between adjacent metal portions 3 is shortest. Here, the direction parallel to the thickness direction of the ceramic substrate 2 is referred to as the "Z direction." Two directions perpendicular to the Z direction and orthogonal to each other are referred to as the "X direction" and "Y direction." For convenience, the X direction is the long side direction of the ceramic substrate 2, and the Y direction is the short side direction. In the example shown in FIG. 3, the multiple metal portions 3 include metal portions 3a, 3b, and 3c. The distance d1 between the metal portion 3a and the metal portion 3b is shortest in the X direction. Therefore, the region located between the first region r1 to which the metal portion 3a is bonded and the first region r1 to which the metal portion 3b is bonded in the X direction is the second region r2. Similarly, the distance d2 between the metal portion 3b and the metal portion 3c is shortest in the X direction. In the X direction, the region between the first region r1 to which the metal portion 3b is joined and the first region r1 to which the metal portion 3c is joined becomes the second region r2.

[0016] 5 and 6 are plan views showing another example of a ceramic substrate. In the example shown in FIGS. 5 and 6, the size and position of the metal portion 3 bonded to the ceramic substrate 2 differ from those in the examples shown in FIGS. 1 to 4. In the examples shown in FIGS. 1 to 4, the shape of each metal portion 3 is rectangular when viewed from the Z direction, and the longitudinal directions of each metal portion 3 are parallel to each other. In the example shown in FIG. 5, multiple metal portions 3 are arranged in the X direction and the Y direction. In the example shown in FIG. 6, multiple metal portions 3 are arranged so that the longitudinal directions of each metal portion 3 are oblique to each other.

[0017] 5 and 6, the second region r2 on the first surface 2a is identified in the same manner as in the example shown in FIG. 3. Specifically, in the example shown in FIG. 5, metal portions 3a to 3d are provided. The distance d1 between metal portion 3a and metal portion 3b and the distance d2 between metal portion 3c and metal portion 3d are shortest in the X direction. In the X direction, the region located between the first region r1 to which metal portion 3a is bonded and the first region r1 to which metal portion 3b is bonded, and the region located between the first region r1 to which metal portion 3c is bonded and the first region r1 to which metal portion 3d is bonded, respectively, are the second region r2. Furthermore, the distance d3 between metal portion 3a and metal portion 3c and the distance d4 between metal portion 3b and metal portion 3d are shortest in the Y direction. In the Y direction, the region located between the first region r1 to which metal portion 3a is joined and the first region r1 to which metal portion 3c is joined, and the region located between the first region r1 to which metal portion 3b is joined and the first region r1 to which metal portion 3d is joined, are each the second region r2.

[0018] Furthermore, the distance d5 between metal portion 3a and metal portion 3d and the distance d6 between metal portion 3b and metal portion 3c are shortest in the directions inclined relative to the X and Y directions. Therefore, in the inclined directions, the region located between the first region r1 to which metal portion 3a is bonded and the first region r1 to which metal portion 3d is bonded, and the region located between the first region r1 to which metal portion 3b is bonded and the first region r1 to which metal portion 3c is bonded, can also be considered as the second region r2. However, locations where the distance between adjacent metal portions 3 exceeds 3 mm are not considered as the second region r2. For example, even if the shortest distance between adjacent metal portions 3 is 3 mm or less, the region where the distance between adjacent metal portions 3 exceeds 3 mm is not included in the second region r2.

[0019] In the example shown in FIG. 6, the distance d1 between the metal portion 3a and the metal portion 3b and the distance d2 between the metal portion 3b and the metal portion 3c are shortest in the X direction. Therefore, in the X direction, the region located between the first region r1 to which the metal portion 3a is bonded and the first region r1 to which the metal portion 3b is bonded is the second region r2. In the X direction, the region located between the first region r1 to which the metal portion 3b is bonded and the first region r1 to which the metal portion 3c is bonded is the second region r2. However, the distance between a portion of the first region r1 to which the metal portion 3a is bonded and a portion of the first region r1 to which the metal portion 3b is bonded exceeds 3 mm. Therefore, the region between the portion of the first region r1 to which the metal portion 3a is bonded and the portion of the first region r1 to which the metal portion 3b is bonded is not included in the second region r2.

[0020] 1 and 2, reference numeral 4 denotes a bonding layer provided on the first surface 2a. Reference numeral 5 denotes a metal portion. The metal portion 5 is also called a back metal portion. Reference numeral 6 denotes a bonding layer provided on the second surface 2b. The metal portion 3 may be directly bonded to the first surface 2a, or may be bonded to the first surface 2a via a bonding layer 4 as shown in FIGS. 1 and 2. The metal portion 5 may be bonded to the second surface 2b as shown in FIG. 2. The metal portion 5 may be directly bonded to the second surface 2b, or may be bonded to the second surface 2b via a bonding layer 6 as shown in FIG. 2. The metal portion 5 is used as a heat sink. The metal portion 5 is used for bonding to a heat sink or a housing (not shown). In the ceramic circuit board 1 according to the embodiment, the metal portion 5 may be used as a circuit.

[0021] When the metal part 3 is bonded to the first surface 2a via a bonding layer 4, the bonding layer 4 preferably includes a protruding portion 4a. The protruding portion 4a is a portion of the bonding layer 4 that protrudes from the end of the metal part 3. When the bonding layer 4 includes the protruding portion 4a, the region of the first surface 2a that contacts the protruding portion 4a is also included in the first region r1. The second region r2 is located between the first regions r1 that contact the bonding layer 4 that includes the protruding portion 4a. In other words, the second region r2 is a region that does not overlap with either the metal part 3 or the bonding layer 4 (including the protruding portion 4a) when viewed from the Z direction.

[0022] The ceramic circuit substrate 1 according to the embodiment is characterized in that the average length RSm of the roughness curve elements in the second region r2 of the first surface 2a is 40 μm or more. The average length RSm of the roughness curve elements is the average value of the lengths Xs of the profile curve elements in the reference length. The average length RSm of the roughness curve elements is defined in JIS-B-0601 (2013). As defined in JIS-B-0601 (2013), measurement of the average length RSm of the roughness curve elements requires the identification of the minimum height and minimum length that are judged to represent peaks and valleys. The standard value of the minimum distinguishable height is 10% of the maximum height roughness Rz. The standard value of the minimum distinguishable length is 1% of the reference length. After determining the peaks and valleys so that both of these conditions are satisfied, the average length Xs of the profile curve elements is calculated. JIS-B-0601 corresponds to ISO 4287.

[0023] A mean length RSm of 40 μm or more of the roughness curve elements indicates that one cycle of peaks and valleys is 40 μm or more. A RSm of 40 μm or more in the second region r2 indicates that one cycle of peaks and valleys is large. This improves the adhesion between the ceramic substrate 2 and the mold resin when the ceramic circuit substrate 1 is molded with resin. Conventional ceramic substrates have a small RSm of less than 40 μm. A small cycle of peaks and valleys results in the formation of microscopic gaps between the ceramic substrate 2 and the mold resin. Generally, the thermal expansion coefficient of the mold resin is greater than that of the ceramic substrate 2. When the temperature of the ceramic substrate 2 and the mold resin changes due to the heat of the semiconductor element, stress is generated at the interface between the ceramic substrate 2 and the mold resin due to the difference in thermal conductivity. If microscopic gaps exist between the ceramic substrate 2 and the mold resin, the mold resin is more likely to peel off from the ceramic substrate 2 due to the stress generated by the heat of the semiconductor element.

[0024] Furthermore, the molded resin near the second region r2 is easily affected by the heat from the semiconductor element mounted on the metal portion. Generally, the thermal conductivity of the metal portion 3 is higher than that of the ceramic substrate 2. The heat from the semiconductor element is dissipated through the metal portion 3. The protruding portion 4a alleviates the stress generated at the end of the metal portion 3a. On the other hand, the heat transferred to the metal portion 3 is also transferred to the second region r2, where the metal portion 3 is not provided. Because the metal portion 3 is not provided in the second region r2, the heat transferred to the second region r2 is less likely to be dissipated. This makes it easier for the temperature to rise near the second region r2. Furthermore, the molded resin in contact with the second region r2 is also subjected to stress due to the thermal expansion of the metal portion 3. Therefore, peeling of the molded resin from the ceramic substrate 2 is more likely to occur between the second region r2 and the molded resin than in other areas.

[0025] According to the embodiment, by controlling RSm in the second region r2, it is possible to improve the adhesion between the ceramic substrate 2 and the mold resin. When the adhesion between the ceramic substrate 2 and the mold resin is improved, the peaks and valleys on the surface of the second region r2 are caught by the mold resin when stress is applied to the mold resin in a direction parallel to the XY plane. In other words, an anchor effect is generated for the mold resin. This makes it possible to prevent the mold resin from peeling off from the ceramic substrate 2. The embodiment is particularly effective for ceramic circuit substrates in which there are locations where the distance between metal portions 3 is 3 mm or less.

[0026] Although there is no particular upper limit for the average length RSm of the roughness profile elements, it is preferably 100 μm or less. If RSm exceeds 100 μm, it may be difficult to control RSm. For this reason, RSm in the second region r2 is preferably in the range of 40 μm to 100 μm, more preferably in the range of 50 μm to 80 μm.

[0027] Furthermore, the maximum peak height Rp of the roughness curve in the second region r2 is preferably 1.0 μm or more. The maximum valley depth Rv of the roughness curve in the second region r2 is preferably 1.0 μm or more. The maximum peak height Rp and maximum valley depth Rv of the roughness curve are also specified in JIS-B-0601(2013).

[0028] The maximum peak height Rp of the roughness curve is the height of the largest peak on the roughness curve. By setting Rp to 1.0 μm or more, the adhesion between the ceramic substrate 2 and the mold resin can be improved. If Rp is less than 1.0 μm, the adhesion between the ceramic substrate 2 and the mold resin may be reduced. The upper limit of Rp is not particularly limited, but is preferably 3.0 μm or less. If Rp is greater than 3.0 μm, there is a possibility that the mold resin will not penetrate into the gaps between the irregularities on the surface of the second region r2. For this reason, Rp is preferably in the range of 1.0 μm to 3.0 μm, and more preferably in the range of 1.2 μm to 2.0 μm.

[0029] The maximum valley depth Rv of the roughness curve is the depth of the largest valley in the roughness curve. By setting Rv to 1.0 μm or more, the adhesion between the ceramic substrate 2 and the mold resin can be improved. If Rv is less than 1.0 μm, the adhesion between the ceramic substrate 2 and the mold resin may be reduced. The upper limit of Rv is not particularly limited, but is preferably 3.0 μm or less. If Rv is greater than 3.0 μm, there is a possibility that the mold resin will not penetrate into the gaps between the irregularities on the surface of the second region r2. For this reason, Rv is preferably in the range of 1.0 μm to 3.0 μm, and more preferably in the range of 1.2 μm to 2.0 μm. The deeper the valley, the larger Rv.

[0030] By controlling one or both of Rp and Rv after controlling RSm, it is possible to further improve the adhesion between the ceramic substrate 2 and the molding resin. This makes it even more difficult for the molding resin to peel off from the ceramic substrate 2.

[0031] RSm, Rp, and Rv are measured according to JIS-B-0601 (2013). The measurement conditions are set as follows: measurement length: 4.0 mm, measurement speed: 0.6 mm / s, shape removal: least-squares linear, λs filter: enabled, λs cutoff ratio: 300, cutoff type: Gaussian, cutoff wavelength (λc): 0.8 mm. If a measurement length of 4.0 mm cannot be ensured in one measurement, the measurement may be performed multiple times. The measurement direction of the average length RSm of the roughness curve element in the second region r2 is arbitrary. The measurement length of 4.0 mm is the reference length.

[0032] In the ceramic circuit substrate 1 according to the embodiment, the average length RSm of the roughness curve elements in the second region r2 is controlled. For example, when the above measurement conditions are met, RSm is 40 μm or greater regardless of which part of the second region r2 is measured. Furthermore, Rp is preferably 1.0 μm or greater regardless of which part of the second region r2 is measured. Rv is preferably 1.0 μm or greater regardless of which part of the second region r2 is measured. Note that the first region r1 bonded to the metal part 3 may have a portion where RSm is less than 40 μm.

[0033] Furthermore, it is preferable that the total area of ​​each second region r2 relative to the surface area of ​​the first surface 2a is within the range of 5% to 50%. In other words, it is preferable that 5 (%)≦[total area of ​​second regions r2 / area of ​​first surface 2a]×100≦50 (%). For example, in the case of a ceramic substrate with long sides of 50 mm×short sides of 40 mm, the surface area of ​​the first surface 2a is 50×40=2000 mm. 2 When only one second region r2 exists on the first surface 2a, the area of ​​that second region r2 corresponds to the above-mentioned "total area of ​​the second regions r2." When multiple second regions r2 exist on the first surface 2a, the sum of the areas of the second regions r2 corresponds to the above-mentioned "total area of ​​the second regions r2." For example, in the example shown in FIGS. 1 to 4, there are two second regions r2. The sum of the areas of the two second regions r2 is the "total area of ​​the second regions r2."

[0034] By setting the total area of ​​the second regions r2 within the range of 5% to 50% of the surface area of ​​the first surface 2a, it is possible to achieve both good adhesion of the molding resin and a sufficient mounting area for semiconductor elements. If the total area of ​​the second regions r2 is less than 5%, the effect of improving adhesion between the ceramic substrate 2 and the molding resin may be insufficient. If the total area of ​​the second regions r2 is greater than 50%, the area for mounting semiconductor elements or the like may be insufficient. For this reason, the total area of ​​the second regions r2 is preferably within the range of 5% to 50% of the surface area of ​​the first surface 2a, and more preferably within the range of 10% to 40%.

[0035] Various substrates can be used for the ceramic substrate 2. Examples of ceramic substrates include silicon nitride substrates, aluminum nitride substrates, alumina substrates, zirconia substrates, and aluzirconia substrates. The aluzirconia substrate is a sintered ceramic body made of a mixture of alumina and zirconia. The thickness of the ceramic substrate is preferably 0.2 mm or more and 3 mm or less.

[0036] The three-point bending strength of the silicon nitride substrate is preferably 600 MPa or more. The thermal conductivity of the silicon nitride substrate is preferably 80 W / m·K or more. Increasing the strength of the silicon nitride substrate allows the substrate thickness to be reduced. Therefore, the three-point bending strength of the silicon nitride substrate is preferably 600 MPa or more, more preferably 700 MPa or more. By using a silicon nitride substrate, the substrate thickness can be reduced to 2 mm or less, or even 0.40 mm or less.

[0037] The three-point bending strength of an aluminum nitride substrate is approximately 300 to 450 MPa. On the other hand, the thermal conductivity of an aluminum nitride substrate is 160 W / m·K or more. Because the strength of an aluminum nitride substrate is low, a substrate thickness of 0.60 mm or more is preferable. The three-point bending strength of an aluminum oxide substrate is approximately 300 to 450 MPa, but aluminum oxide substrates are inexpensive. The three-point bending strength of an aluminium nitride substrate is high, at approximately 550 MPa, but the thermal conductivity is approximately 30 to 50 W / m·K.

[0038] A silicon nitride substrate is preferably used as the ceramic substrate 2. Silicon nitride substrates have high strength and can withstand the thermal contraction of molding resins. Furthermore, by using a silicon nitride substrate with a thermal conductivity of 80 W / m·K or more, heat dissipation can be improved. Furthermore, silicon nitride substrates are mainly composed of silicon nitride crystal grains with an aspect ratio of 1.5 or more. The entanglement of the elongated silicon nitride crystal grains increases the strength of the ceramic substrate 2. Furthermore, the random orientation of the elongated silicon nitride crystal grains makes it easier to control RSm.

[0039] Examples of the metal part 3 include a metal plate, a thin film, and a metallized film. A thin film refers to a conductive film formed by a sputtering method, a plating method, or the like. A metallized film refers to a conductive film formed by applying a metal powder paste and firing it.

[0040] The metal part 3 is preferably a member obtained by processing a metal plate. The thickness of the metal plate (metal part 3) is preferably 0.3 mm or more. Increasing the thickness of the metal plate can improve heat dissipation. It can also improve current-carrying capacity. For this reason, the thickness of the metal plate is preferably 0.3 mm or more, more preferably 0.6 mm or more. There is no particular upper limit to the thickness of the metal plate, but it is preferably 5 mm or less. If the thickness exceeds 5 mm, it may be difficult to control the inclined shape of the side surface of the metal part 3. Furthermore, from the viewpoint of heat dissipation, it is preferable to use a copper plate having a thickness of 0.3 mm or more for the metal part 3. Furthermore, it is preferable that the thicknesses of the metal part 3 and the metal part 5 are both 0.3 mm or more. By using a metal plate for the metal part 3, it is possible to improve the adhesion between the metal part 3 and the molded resin, and also improve the current-carrying capacity and heat dissipation of the metal part 3.

[0041] The metal plate may be one or more selected from copper plate, copper alloy plate, aluminum plate, and aluminum alloy plate. Copper plate is preferred as the metal plate. Oxygen-free copper plate is also preferred. Oxygen-free copper has a copper purity of 99.96 wt% or higher, as specified in JIS-H-3100. The thermal conductivity of copper is approximately 400 W / m·K, while the thermal conductivity of aluminum is approximately 240 W / m·K. Copper has a higher thermal conductivity than aluminum. Using a copper plate for the metal part 3 improves the heat dissipation of the metal part 3. The aluminum plate is preferably pure aluminum. Pure aluminum is specified in JIS-H-4000. JIS-H-4000 corresponds to ISO 6361. JIS-H-3100 corresponds to ISO 197, etc.

[0042] The ceramic substrate 2 and the metal part 3 are preferably bonded via a bonding layer 4. The bonding layer 4 is preferably a member formed using an active metal bonding method. The active metal bonding method is a bonding method using one or more active metals selected from Ti (titanium), Zr (zirconium), and Hf (hafnium). An active metal brazing filler metal containing copper (Cu) or silver (Ag) as the main component and an active metal is used. The main component here refers to the component that is contained in the largest amount among the metal components of the brazing filler metal.

[0043] The active metal brazing filler metal preferably contains 0% to 60% by mass of Ag (silver), 15% to 70% by mass of Cu (copper), and 1% to 15% by mass of Ti (titanium) or TiH2 (titanium hydride). When both Ti and TiH2 are used, their total content is within the range of 1% to 15% by mass. When both Ag and Cu are used, it is preferable that Ag be within the range of 20% to 60% by mass and Cu be within the range of 15% to 40% by mass. If necessary, one or both of Sn (tin) and In (indium) may be contained within the range of 1% to 50% by mass. If necessary, C (carbon) may be contained within the range of 0.1% to 2% by mass.

[0044] The composition ratio of the active metal brazing filler metal is calculated with the total of the mixed raw materials being 100% by mass. For example, if the active metal brazing filler metal is composed of three elements, Ag, Cu, and Ti, then Ag + Cu + Ti = 100% by mass. If the active metal brazing filler metal is composed of four elements, Ag, Cu, TiH2, and In, then Ag + Cu + TiH2 + In = 100% by mass. If the active metal brazing filler metal is composed of five elements, Ag, Cu, Ti, Sn, and C, then Ag + Cu + Ti + Sn + C = 100% by mass.

[0045] Ag or Cu is a component that serves as the base material of the brazing filler metal. Sn or In has the effect of lowering the melting point of the brazing filler metal. C (carbon) has the effect of controlling the fluidity of the brazing filler metal and controlling the structure of the joining layer by reacting with other components. For this reason, the components of the brazing filler metal include Ag-Cu-Ti, Ag-Cu-Sn-Ti, Ag-Cu-Ti-C, Ag-Cu-Ti, Ag-Sn-Ti, Cu-Sn-Ti, Ag-Ti-C, Cu-Ti-C, Ag-Sn-Ti-C, and Cu-Sn-Ti-C. In may be used instead of Sn. Both Sn and In may be used.

[0046] The active metal brazing material may contain at least one element selected from tungsten (W), molybdenum (Mo), and rhenium (Re) in an amount ranging from 0.1% by mass to 10% by mass. The addition of tungsten, molybdenum, or rhenium can control the fluidity of the active metal brazing material. Magnesium (Mg) may also be added to the active metal brazing material.

[0047] The active metal brazing material described above is effective for joining copper plates. The metal portion 3 is preferably a copper member, and the ceramic substrate and the copper member are preferably joined via a bonding layer that does not contain Ag. A bonding layer that does not contain Ag refers to a member formed using an active metal brazing material that does not contain Ag. Ag may be contained in an amount of 0.01 mass% or less (including zero, which is below the detection limit) as an unavoidable impurity. Using a bonding layer that does not contain Ag can suppress the occurrence of Ag ion migration. Ag ion migration is a phenomenon in which Ag in the bonding layer ionizes and migrates when voltage is applied in a humid environment. When Ag ions migrate, Ag precipitates in another location, which can cause insulation failure. Among active metal brazing materials, Ag is most susceptible to ion migration. By not using Ag in the bonding layer, Ag ion migration can be suppressed.

[0048] When the metal plate is an aluminum plate, it is preferable to use an Al-Si or AlMg brazing filler metal as the active metal brazing filler metal. The content of one or both of Si and Mg in the active metal brazing filler metal is preferably in the range of 0.1 mass % to 20 mass %.

[0049] The ceramic circuit board according to the embodiment can be used in a semiconductor device in which a semiconductor element is mounted on the metal part 3. The ceramic circuit board preferably includes a molding resin.

[0050] FIG. 7 is a side view showing an example of a semiconductor device according to an embodiment. In FIG. 7, reference numeral 1 indicates a ceramic circuit substrate. Reference numeral 6 indicates a semiconductor element. Reference numeral 7 indicates a molded resin. Reference numeral 10 indicates a semiconductor device. The semiconductor element 7 is mounted on a metal part 3. FIG. 7 shows an example of a semiconductor device 10 on which two semiconductor elements 7 are mounted. The semiconductor device 10 according to the embodiment is not limited to this form. The number of semiconductor elements 7 is arbitrary. The semiconductor device 10 may also include wire bonding or a lead frame, not shown.

[0051] 7, the first surface 2a on which the semiconductor element 7 is mounted is covered with mold resin 8. The mold resin 8 is not limited to this form, and the mold resin 8 may also cover the metal portion 5 of the semiconductor device 10.

[0052] The mold resin 8 serves to protect the semiconductor element 7, wiring, etc. from external stress. The mold resin also serves to protect the semiconductor element 7, etc. from external air, such as humidity. Thermosetting resin is mainly used as the mold resin. Examples of thermosetting resins include epoxy resin and silicone resin.

[0053] Molding methods include the transfer method and the compression method. The transfer method is a sealing method in which molten resin is injected into a mold and hardened. Molds formed by the transfer method are called transfer molding. The compression method is a sealing method in which resin is poured into a mold in advance, melted, and hardened. Molds formed by the compression method are called compression molding. Transfer molding is excellent for mass production because it involves injecting resin. Transfer molding involves resin flow, which can cause misalignment of semiconductor elements and wire bonding. With the compression method, resin is poured into the mold in advance and melted, so there is little impact on misalignment of semiconductor elements, etc. On the other hand, resin must be poured into the mold in advance. For this reason, the mass productivity of the compression method is lower than that of transfer molding.

[0054] In the ceramic circuit board according to the embodiment, the ceramic substrate surface in the gaps between the metal portions has an average roughness curve element length RSm of 40 μm or more. One cycle of peaks and valleys is increased, thereby improving adhesion with the molded resin. Adhesion can be improved with either transfer molding or compression molding. For example, transfer molding involves resin flow. Even if the resin flows, increasing one cycle of peaks and valleys allows the flowing resin to penetrate the surface irregularities. This improves adhesion. In other words, this is suitable for a semiconductor device 10 equipped with a molded resin 8.

[0055] In semiconductor devices with mold resin, when measuring the average length RSm of the roughness curve elements in the gap (region between metal parts), the average length RSm is measured after removing the mold resin. Methods for removing the mold resin include chemical treatment that dissolves only the resin.

[0056] Next, a method for manufacturing the ceramic circuit board 1 according to the embodiment will be described. The method for manufacturing the ceramic circuit board 1 according to the embodiment is not limited as long as it has the above-described configuration. Here, a method for manufacturing the ceramic circuit board 1 with a good yield will be described.

[0057] First, a bonded body of a ceramic substrate 2 and a metal plate is prepared. The metal plate is provided on one or both sides of the ceramic substrate 2. The ceramic substrate 2 is preferably one selected from a silicon nitride substrate, an aluminum nitride substrate, an alumina substrate, a zirconia substrate, and an aluminium alloy substrate. The metal plate is preferably one or more selected from a copper plate, a copper alloy plate, an aluminum plate, and an aluminum alloy plate. The ceramic substrate 2 and the metal plate are preferably bonded using an active metal bonding method.

[0058] When the metal plate is a copper plate (including a copper alloy plate), the active metal brazing material contains Cu or Ag as a main component and further contains one or more selected from Ti, Zr, and Hf. If necessary, one or more selected from Sn, In, and C (carbon) may be added. When the metal plate is an aluminum plate, it is preferable to use an Al-Si-based or Al-Mg-based brazing material as the active metal brazing material. The preferred composition range of the active metal brazing material is as described above.

[0059] The bonding step may involve heating a laminate of a ceramic substrate and a metal plate at 600 to 980°C in a vacuum or in an inert atmosphere. -2 The pressure is preferably 100 Pa or less. The inert atmosphere is preferably a nitrogen atmosphere. In the bonding step in a vacuum, a batch furnace is preferably used. In the bonding step in an inert atmosphere, a continuous furnace is preferably used. By the bonding step, a bonded body in which the ceramic substrate 2 and the metal plate are bonded via the bonding layer 4 is prepared.

[0060] Next, an etching step is performed. The etching step is performed to impart a circuit shape to the metal plate. By imparting a circuit shape to the metal plate, the above-mentioned metal portion 3 is obtained. Furthermore, by imparting a circuit shape to the metal plate, the ceramic circuit board 1 is produced. Note that a metal plate that has been processed into a circuit shape in advance may be bonded to the ceramic substrate 2. In this case, there is no need to perform the etching step, and the metal plate in the circuit shape corresponds to the above-mentioned metal portion 3.

[0061] Utilizing an etching process is effective for controlling RSm, Rp, and Rv. A bonding layer using an active metal brazing material is formed by forming a layer mainly composed of Ag or Cu and a layer mainly composed of an active metal. International Publication No. WO2019 / 054294 (Patent Document 4) discloses a method of using a brazing material etching process and a chemical polishing process as an etching process for a bonding layer using an active metal brazing material.

[0062] When a portion of the copper plate is etched, a portion of the bonding layer is exposed. In the brazing material etching process, the exposed portion of the bonding layer is removed. Furthermore, when a portion of the brazing material is exposed, the surface of the exposed brazing material may be oxidized. The copper plate etching process may also produce reaction products on the surface of the brazing material. The chemical polishing process is performed to remove oxides or reaction products that form on the surface of the brazing material. By performing the chemical polishing process, the bonding layer can be efficiently removed in the subsequent brazing material etching process.

[0063] Increasing the etching amount of the brazing filler metal etchant is effective for controlling RSm, etc. Effective methods for increasing the etching amount of the brazing filler metal etchant include at least one method selected from the group consisting of increasing the etching rate of the brazing filler metal etchant, suppressing a decrease in the etching rate of the brazing filler metal etchant, and lengthening the etching time.

[0064] The brazing material etchant may be a solution containing hydrogen peroxide and having a pH of 6 or less. Increasing the concentration of hydrogen peroxide water is effective for increasing the etching rate of the brazing material etchant. The etchant may contain, in addition to hydrogen peroxide, ammonium fluoride and a pH stabilizer. Examples of the pH stabilizer include HBF4, EDTA, NTA, CyDTA, DTPA, TTHA, GEDTA, glycine, dicarboxylic acids, tricarboxylic acids, oxycarboxylic acids, and salts thereof.

[0065] To prevent a decrease in the etching rate of the brazing material etchant, it is effective to add new etchant when the concentration of hydrogen peroxide solution changes by 5 mass %. This prevents a decrease in the etching rate of the brazing material etchant. Increasing the etching time of the brazing material etchant is also effective in controlling RSm. As a guideline, the time for one brazing material etching process should be set to 15 minutes or more.

[0066] In addition, in order to control RSm and the like, it is effective to increase the amount of the bonding layer removed by the chemical polishing process. Methods for increasing the amount removed by the chemical polishing process include increasing the concentration of hydrochloric acid or sulfuric acid, and extending the time for which the chemical polishing process is performed. For example, when a combination of hydrogen peroxide and sulfuric acid is used in the brazing material etchant, the sulfuric acid content can be increased to 5 mass% or more. When hydrochloric acid is used in the brazing material etchant, the hydrochloric acid content can be increased to 7 mass% or more. It is also effective to extend the time for the chemical polishing process to 5 minutes or more.

[0067] The brazing material etching process and the chemical polishing process may be performed in combination. That is, the above method may be applied to each of the chemical polishing process and the brazing material etching process. The chemical polishing process and the brazing material etching process may also be performed alternately. In this case, it is effective to apply the above method to the last chemical polishing process of a plurality of chemical polishing processes, and to apply the above method to the last brazing material etching process of a plurality of brazing material etching processes.

[0068] The final brazing material etching process is a process for completely removing the bonding layer. When the ceramic substrate 2 and a metal plate are bonded using the active metal bonding method, a layer primarily composed of active metal is formed. When Ti is used as the active metal and a silicon nitride substrate is used as the ceramic substrate, the layer primarily composed of active metal is a titanium nitride (TiN) layer. The formation of a layer primarily composed of active metal in the bonding layer improves the bonding strength. However, because the layer primarily composed of active metal is conductive, if it remains on the ceramic circuit substrate 1, it may cause poor conductivity between the metal parts 3. For this reason, it is necessary to remove the layer primarily composed of active metal. By increasing the amount removed in the etching process or chemical polishing process, it is possible to remove the layer primarily composed of active metal and part of the ceramic substrate surface underneath. This allows for control of RSm, etc.

[0069] If a metal plate having a circuit shape is bonded to the ceramic substrate 2 in advance and no etching process is performed, it is effective to perform a chemical polishing process on the gaps between the metal plates. In addition, if necessary, it is also effective to perform a blasting process or a polishing process on the second region to control RSm, etc.

[0070] The ceramic circuit board 1 according to the embodiment can be manufactured by the above steps. Furthermore, a semiconductor device 10 can be manufactured by mounting a semiconductor element 7 or the like on the ceramic circuit board 1. If necessary, a mold resin 8 is provided on the semiconductor device 10.

[0071] (Examples 1 to 7, Comparative Examples 1 and 2) A silicon nitride substrate was prepared as the ceramic substrate for Examples 1 to 6. The silicon nitride substrate had a thermal conductivity of 90 W / m K and a three-point bending strength of 700 MPa. The silicon nitride substrate had a length of 50 mm, a width of 40 mm, and a thickness of 0.32 mm. A copper plate with a thickness of 0.8 mm was prepared as the metal plate.

[0072] Next, a bonded silicon nitride substrate and copper plate (silicon nitride circuit board) was produced using the active metal bonding method. Copper plates with a thickness of 0.8 mm were bonded to both sides of the silicon nitride substrate. The composition of the active metal brazing material is shown in Table 1.

[0073] An aluminum nitride substrate was prepared as the ceramic substrate according to Example 7. The aluminum nitride substrate had a thermal conductivity of 170 W / m K and a three-point bending strength of 400 MPa. A 0.4 mm thick copper plate was prepared as the metal plate. A 0.4 mm thick copper plate was bonded to both sides of the aluminum nitride substrate using an active metal bonding method to produce a bonded body (aluminum nitride circuit board). A silicon nitride circuit board was also produced as Comparative Example 1. An aluminum nitride circuit board was also produced as Comparative Example 2.

[0074] [Table 1]

[0075] Next, a circuit shape was imparted to the copper plate by an etching process to form the metal part 3. For the ceramic circuit boards according to the examples, a method of increasing the etching amount of the brazing material etching solution or a method of increasing the amount removed by the chemical polishing process was used.

[0076] In the manufactured ceramic circuit board, the total area (%) of the second regions r2 is as shown in Table 2. The total area (%) of the second regions r2 was calculated by (total area of ​​each second region r2 / surface area of ​​the first surface 2a) × 100 (%). The surface area of ​​the first surface 2a is 50 mm long × 40 mm wide = 2000 mm 2 In addition, RSm, Rp, and Rv in the second region r2 were measured. The method for measuring RSm, Rp, and Rv was as described above.

[0077] [Table 2]

[0078] In the ceramic circuit boards according to the examples, RSm was set to 40 μm or more. Rp was set to 1.0 μm or more, and Rv was set to 1.0 μm or more. In the comparative examples 1 and 2, RSm was set to less than 40 μm.

[0079] Next, semiconductor elements were mounted on the ceramic circuit substrates according to the examples and comparative examples to manufacture semiconductor devices. A molding resin was provided on the semiconductor devices. The Ag migration characteristics and resin adhesion of the semiconductor devices provided with the molding resin were measured.

[0080] To evaluate the Ag migration characteristics, a voltage was applied to the semiconductor device in a high-temperature, high-humidity atmosphere, and the occurrence rate of Ag migration marks was measured. An electrochemical migration evaluation system from Espec Corporation was used as the measurement device. An applied voltage of AC 2000V (peak voltage 2820V) was applied to the semiconductor device for 40 consecutive hours in an environment with a temperature of 85°C and humidity of 85%. The presence or absence of Ag migration marks on the surface of the ceramic circuit board was examined.

[0081] In each example and comparative example, 100 semiconductor devices were evaluated. In each example, the number of semiconductor devices having at least one Ag migration mark was counted. An example in which the count was 0 was rated "best." An example in which the count was 1 to 10 was rated "good." An example in which the count was 11 or more was rated "poor."

[0082] Regarding resin adhesion, the presence or absence of peeling of the molded resin after a thermal cycle test (TCT) was measured. In the TCT test, one cycle consisted of -40°C x 30 minutes, room temperature (25°C) x 10 minutes, 175°C x 30 minutes, and room temperature (25°C) x 10 minutes. The presence or absence of peeling of the molded resin after 300 cycles was measured. The presence or absence of peeling of the resin on the surface of the second region r2 was measured using ultrasonic testing (SAT). The peeling rate (%) of the molded resin was calculated by (total peeled resin in the second region r2 / total area of ​​the second region r2) x 100. The results are shown in Table 3.

[0083] [Table 3]

[0084] As can be seen from Table 3, the semiconductor device according to the example had good adhesion between the ceramic substrate and the resin. The adhesion was improved even without providing a recess in the copper plate as in Patent Document 2. Therefore, according to the embodiment, it is possible to suppress a reduction in the area for mounting the semiconductor element.

[0085] As in Examples 6 and 7, when RSm was out of the range of 40 μm or more and 100 μm or less, resin peeling occurred. Therefore, it is clear that RSm is preferably in the range of 40 μm or more and 100 μm or less. Furthermore, in Examples 4 to 7, in which an Ag-less brazing filler metal was used, Ag ion migration did not occur. From this point of view, it is preferable to use an Ag-less brazing filler metal. In other words, by using an Ag-less brazing filler metal, it is possible to achieve both suppression of Ag ion migration and improvement of adhesion of the molded resin. In contrast, in Comparative Examples 1 and 2, RSm was small, and therefore adhesion of the molded resin decreased.

[0086] Embodiments of the present invention may include the following features. (Configuration 1) a ceramic substrate having a first surface; a plurality of metal portions provided in the plurality of first regions of the first surface, the first surface has a second region located between adjacent first regions, A ceramic circuit board, wherein the average length RSm of the roughness curve elements in the second region is 40 μm or more. (Configuration 2) 2. The ceramic circuit board according to claim 1, wherein the average length RSm in the second region is 100 μm or less. (Configuration 3) 3. The ceramic circuit board according to claim 1, wherein the maximum peak height Rp of the surface roughness curve in the second region is 1.0 μm or more. (Configuration 4) 4. The ceramic circuit board according to any one of configurations 1 to 3, wherein the maximum valley depth Rv of the surface roughness curve in the second region is 1.0 μm or more. (Configuration 5) 5. The ceramic circuit board according to any one of configurations 1 to 4, wherein the sum of the areas of the one or more second regions relative to the surface area of ​​the first surface is within a range of 5% to 50%. (Configuration 6) 6. The ceramic circuit board according to any one of configurations 1 to 5, wherein the ceramic substrate is a silicon nitride substrate. (Configuration 7) each of the plurality of metal portions is a copper member; 7. The ceramic circuit board according to claim 1, wherein the copper members are bonded to the first regions via bonding layers that do not contain Ag. (Configuration 8) 8. The ceramic circuit board according to claim 7, wherein the maximum peak height Rp of the roughness curve in the second region is 1.0 μm or more, and the maximum valley depth Rv of the roughness curve is 1.0 μm or more. (Configuration 9) 9. The ceramic circuit board according to claim 8, wherein the sum of the areas of the one or more second regions relative to the surface area of ​​the first surface is within a range of 5% to 50%. (Configuration 10) A ceramic circuit substrate according to any one of configurations 1 to 9; a semiconductor element mounted on any one of the plurality of metal parts; A semiconductor device comprising: (Configuration 11) 11. The semiconductor device according to claim 10, further comprising a molding resin covering the second region.

[0087] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0088] 1...Ceramic circuit board 2...Ceramic substrate 2a…First side (front) 2b…Second side (back side) 3,3a~3d…metal part 4...Joining layer 5...Metal part (back metal part) 6...Joining layer 7...Semiconductor element 8...Molding resin 10...Semiconductor device r1…first area r2…Second area

Claims

1. a first step of producing a laminate in which a plurality of metal portions are respectively bonded to a plurality of first regions on a first surface of a ceramic substrate; a second step of etching or chemically polishing a second region located between the adjacent first regions on the first surface, A method for manufacturing a ceramic circuit board, wherein when an average length RSm in the second region after the second step is measured under measurement conditions of: λs filter: present; λs cutoff ratio: 300; cutoff type: Gaussian; and cutoff wavelength (λc): 0.8 mm, the average length RSm is 40 μm or more.

2. the laminate includes a bonding layer formed on the plurality of first regions and on the second region; the plurality of metal portions are bonded to the plurality of first regions via the bonding layer, In the second step, the etching step is performed at least once on the bonding layer formed on the second region; The method for manufacturing a ceramic circuit board according to claim 1 , wherein the time for one etching step on the bonding layer is 15 minutes or more.

3. the laminate includes a bonding layer formed on the plurality of first regions and on the second region; the plurality of metal portions are bonded to the plurality of first regions via the bonding layer, In the second step, the chemical polishing step is performed on the bonding layer formed on the second region using a brazing material etching solution containing hydrogen peroxide and hydrochloric acid. The method for manufacturing a ceramic circuit board according to any one of claims 1 and 2.

4. 3. The method for manufacturing a ceramic circuit board according to claim 1, wherein the second step includes the chemical polishing step for 5 minutes or more.

5. The method for manufacturing a ceramic circuit board according to claim 3 , wherein the second step includes the chemical polishing step for 5 minutes or more.

6. the second step includes the etching step, 3. The method for manufacturing a ceramic circuit board according to claim 1, wherein hydrogen peroxide solution is used in the etching step, and new etching solution is added when the concentration of the hydrogen peroxide solution changes by 5 mass %.

7. the second step includes the etching step, 6. The method for manufacturing a ceramic circuit board according to claim 5, wherein hydrogen peroxide solution is used in the etching step, and new etching solution is added when the concentration of the hydrogen peroxide solution changes by 5 mass %.

8. 2. The method for manufacturing a ceramic circuit substrate according to claim 1, wherein in the second step, a portion of the ceramic substrate is removed in the second region while the plurality of metal portions are provided on the plurality of first regions, respectively.

9. 9. The method for manufacturing a ceramic circuit board according to claim 8, wherein the average length RSm in the second region after the second step is 153 μm or less.

10. 3. The method for manufacturing a ceramic circuit board according to claim 1, wherein a maximum peak height Rp of a surface roughness curve in the second region after the second step is 1.0 μm or more.

11. 3. The method for manufacturing a ceramic circuit board according to claim 1, wherein a maximum valley depth Rv of a surface roughness curve in the second region after the second step is 1.0 μm or more.

12. 3. The method for manufacturing a ceramic circuit substrate according to claim 1, wherein in the laminate, a sum of the areas of the one or more second regions with respect to a surface area of ​​the first surface is within a range of 5% to 50%.

13. 3. The method for manufacturing a ceramic circuit board according to claim 1, wherein the ceramic substrate is a silicon nitride substrate.

14. each of the plurality of metal portions is a copper member; 3. The method for manufacturing a ceramic circuit board according to claim 1, wherein the copper members are bonded to the first regions via a bonding layer that does not contain Ag.

15. 9. The method for manufacturing a ceramic circuit board according to claim 8, wherein the maximum peak height Rp of the roughness curve in the second region after the second step is 1.0 μm or more, and the maximum valley depth Rv of the roughness curve is 1.0 μm or more.

16. The method for manufacturing a ceramic circuit substrate according to claim 15 , wherein the sum of the areas of the one or more second regions relative to the surface area of ​​the first surface is within a range of 5% to 50%.

17. The method for manufacturing a ceramic circuit board according to claim 16, wherein the ceramic substrate is a silicon nitride substrate.

18. Implementing the method for manufacturing a ceramic circuit substrate according to any one of claims 1 and 2, A method for manufacturing a semiconductor device, comprising mounting a semiconductor element on any one of the plurality of metal portions of the ceramic circuit substrate.

19. 20. The method for manufacturing a semiconductor device according to claim 18, wherein the second region is covered with a molding resin after the semiconductor element is mounted.

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