Semiconductor devices for power electronics applications

Abstract

To provide a semiconductor element for integration in a semiconductor module and an operation method of a power module including the semiconductor element.SOLUTION: A semiconductor element 1 includes a semiconductor layer 10 having a plurality of recesses 11 on the first side, an insulating layer 12 (12a, 12b) that is placed on the first side of the semiconductor layer 10 and engages with a recess 11, a first conductive layer 14 (14a, 14b) that is placed on the insulating layers 12a and 12b for contact with the semiconductor element 1, and a second conductive layer 16 mounted on the second side located opposite to the first side of the semiconductor layer 10 due to the contact of the semiconductor element 1, and the first conductive layer 14 (14a, 14b) includes a plurality of notches 20 and a plurality of partial regions 24.SELECTED DRAWING: Figure 1B

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device for use in power electronics or for integration into a power module. [Background technology]

[0002] Power modules consist of (semiconductor) elements or power semiconductors that are configured and designed for power electronics for switching large currents (1 A to several thousand A) and / or high voltages (at least above 24 V, but typically higher than 100 V). Examples of power semiconductors are power diodes, thyristors, or power transistors such as power MOSFETs, GTOs, and IGBTs. So-called snubbers (Boucherot circuits) are used in electrical circuits to damp undesirable oscillations in the electrical circuit or to dissipate and thereby prevent current or voltage spikes. Undesirable oscillations or voltage spikes occur in particular when the current flow is suddenly interrupted and inductive loads are switched off.

[0003] The above elements are also understood to have a four-layer structure, and the snubber is primarily concerned with switching off or turning off the elements, and less with switching them on.

[0004] In electronic devices, snubbers are realized, for example, as RC snubber circuits. An RC snubber circuit is a series connection of a capacitor and a resistor. Functionally, this snubber circuit is a passive load reduction circuit in circuit technology, preventing the load from being applied to the power semiconductors that are switching (off). In fact, inductive components are always present in power switching circuits, even if they are parasitic, so anyone who knows and works with inductive loads can easily understand the importance of this passive circuit.

[0005] From the prior art, various semiconductor devices are known and have been realized which are integrated RC snubber circuits, i.e. in which a capacitor and a resistor are integrated in one device.

[0006] U.S. Patent No. 7,738,226 and U.S. Patent No. 8,563,388 each disclose an integrated RC snubber element. The element comprises a silicon substrate (resistive component) having a plurality of trenches on one side (front side). The side of the silicon substrate having the trenches is covered with an insulating layer (capacitive component). A conductive material is placed on the side of the silicon substrate having the trenches for contact, and the covered trenches are further filled. A conductive material is also placed on the side of the silicon substrate opposite the side having the trenches (back side) for contacting the element.

[0007] US Patent Application Publication No. 2019 / 007041 or US Pat. No. 8,705,257 show the use of the above element in a power module.

[0008] US Pat. No. 8,330,247, US Pat. No. 9,455,151 or US Pat. No. 9,917,146 show specific embodiments of a trench on the backside of the substrate and an insulating layer or additional trench. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] U.S. Patent No. 7,738,226 [Patent Document 2] U.S. Patent No. 8,563,388 [Patent Document 3] US Patent Application Publication No. 2019 / 007041 [Patent Document 4] U.S. Patent No. 8,705,257 [Patent Document 5] U.S. Patent No. 8,330,247 [Patent Document 6] U.S. Patent No. 9,455,151 [Patent Document 7] U.S. Patent No. 9,917,146 Summary of the Invention [Problem to be solved by the invention]

[0010] The object of the present invention is to provide a semiconductor element that ensures a high level of safety when used with power semiconductors and at the same time has a long service life. [Means for solving the problem]

[0011] The problem is solved by a semiconductor device according to claim 1, a semiconductor device according to claim 8 and a semiconductor device according to claim 12. A solution is also possible with a method according to claim 24.

[0012] In a first aspect of the present invention, a semiconductor element to be integrated into a power module includes a semiconductor layer, an insulating layer, a first conductive layer for contacting the semiconductor element, and a second conductive layer for contacting the semiconductor element. The semiconductor layer has a first side having a plurality of recesses. An insulating layer is placed on the first side of the semiconductor layer and engages with the recesses. The first conductive layer is placed on the insulating layer, and the second conductive layer is placed on a second side opposite the first side of the semiconductor layer.

[0013] The first conductive layer has a number of notches, each of which surrounds a partial region of the first conductive layer, leaving a region with a narrowed cross section.

[0014] The first conductive layer may also have a plurality of notches and a plurality of partial regions, each partial region being surrounded by at least one notch, leaving at least one region with a narrowed cross section.

[0015] The semiconductor element may be a microelectronic element, and the individual (thin) layers of the semiconductor element may accordingly each have a layer thickness in the nano- to micro-range.

[0016] The semiconductor layer may include, and preferably consist of, silicon.

[0017] Recesses (trenches) in the semiconductor layer can be produced, for example, by deep reactive ion etching (Deep Reactive Ion Etching - DRIE).

[0018] Preferably, the semiconductor layer may comprise several hundred equal recesses which may be arranged in a grid in the semiconductor layer.

[0019] The insulating layer may comprise a dielectric, preferably a dielectric, for example it may comprise a ceramic, a plastic or a plastic blend, an electrolyte (double) layer or an oxide layer.

[0020] The first and second conductive layers for contacting each may comprise or preferably consist of a metal, more preferably aluminum.

[0021] The semiconductor element can be contacted and connected to other (semiconductor) elements via the first and second conductive layers.

[0022] The number of notches in the first conductive layer may correspond to the number of recesses. Each notch may be assigned to one recess. The notches may be equal to one another and / or arranged in a grid in the first conductive layer.

[0023] Each region having a narrowed cross-section can be defined by a notch, and preferably, multiple notches can define the respective widths of the cross-sections. The height (in the z-direction) of the cross-sections can be determined by the layer thickness of the (flat) section of the first conductive layer. Instead of all regions having a narrowed cross-section, the width and length of the cross-sections having a narrowed region can be determined by each notch. In this case, narrowed can mean that the length (in the x-direction) of the region having a narrowed cross-section is many times smaller than the length of the first conductive layer, and that the width (in the y-direction) of the region having a narrowed cross-section is many times smaller than the width of the first conductive layer.

[0024] For example, the web width is narrowed relative to the length of the curve of the notch. To put the concept of "narrowed" more concretely, the web width is longer than the rest of the web.

[0025] However, the number of notches in the first conductive layer may be less than the number of recesses, for example, one notch may be assigned to two recesses.

[0026] One or more partial regions of the first conductive layer can be surrounded by corresponding recesses, leaving regions with narrowed cross sections, with each recess being assigned to one partial region, as are the regions with narrowed cross sections assigned to each partial region.

[0027] For example, the two cutouts can surround one partial region of the first conductive layer only to the extent that two regions with narrowed cross sections remain in the first conductive layer.

[0028] The regions in the first conductive layer having a narrowed cross section may each have a height of 100.0 nm to 1.0 μm and a width of 50.0 nm to 5.0 μm. Preferably, the height may be 400.0 nm to 800.0 nm and the width may be 1.0 μm to 2.0 μm.

[0029] The regions having narrowed cross sections may each have the same height and width.

[0030] The width and height (and length) of the region having the narrowed cross section can set or adjust the amount of current that can be passed through the region without impairing the proper operation of the semiconductor device.

[0031] Each recess in the first conductive layer can be considered a (trench) capacitor. Accordingly, a semiconductor component can have several (trench) capacitors connected in parallel with one another. The regions with narrowed cross sections can be considered as defined connecting conductive paths. If a certain (limiting) current density is exceeded, for example if a partial region of the insulating layer fails, the individual region with narrowed cross section or individual regions with narrowed cross sections can fuse, thereby electrically isolating the trench capacitor or individual trench capacitors, so that the semiconductor component integrated in the power module can continue to operate without damaging other electronic components of the power module.

[0032] All recesses in the first conductive layer can be made in one step, for example an etching step.

[0033] Each one of the partial regions of the first conductive layer can at least partially cover, preferably completely cover, each one of the openings of the recesses, and more preferably can each extend radially beyond the edge of the respective opening of the recesses.

[0034] Each partial region of the first conductive layer may at least partially cover, preferably completely cover, the openings of the associated recess and may further preferably extend radially beyond the edges of the openings.

[0035] The cutouts can have a circular (annular), part-circular, rectangular or polygonal basic shape, and correspondingly the (released) partial areas in the first conductive layer can have a circular, rectangular or polygonal basic shape.

[0036] If several notches are assigned to one sub-region, the entire notch can be seen for each sub-region.

[0037] Another aspect of the present invention relates to a semiconductor device for integration into a power module, comprising a semiconductor layer, an insulating layer, a first conductive semiconductor layer for contacting the semiconductor device, and a second conductive layer for contacting the semiconductor device. The semiconductor layer has a first side having a plurality of recesses as trenches. The insulating layer is disposed on the first side of the semiconductor layer and extends into the trenches. The first conductive layer for contacting the semiconductor device is disposed on the insulating layer and extends into but does not fill the trenches. The second conductive layer is disposed on a second side of the semiconductor layer opposite the first side.

[0038] The insulating layer has thickened portions in the opening regions of the trenches to define respective conductive regions having narrowed cross sections in the first conductive layer.

[0039] The recess or recesses as trenches in the first side of the semiconductor layer can be produced by an etching method, for example by deep reactive ion etching (DRIE).

[0040] Preferably, there can be multiple trenches in the semiconductor layer, which can be created in a single etching step.

[0041] The trenches may be arranged in a grid in the semiconductor layer.

[0042] Each thickened portion of the insulating layer may extend radially inward from the respective side wall of the recess in the form of a bulge, near the opening area (near the edge), which in this case may mean that each thickened portion is located in the upper third of the recess.

[0043] Preferably, the thickened portions are each arranged in the opening region of the trench such that a hollow space in the trench is formed below the thickened portion in the process of depositing the first conductive layer, the respective hollow space being considered as a confinement in the first conductive layer and which can be filled with, for example, a gas.

[0044] The narrowed cross-sectional regions in the first conductive layer may each have a first diameter of 100.0 nm to 2.0 μm, preferably in the range of 300.0 nm to 700.0 nm, in which case the first diameter may be the smallest diameter of each narrowed cross-sectional region.

[0045] Each trench can have a second diameter. The ratio of the first diameter to the second diameter can be between 1:2 and 1:20, preferably between 1:5 and 1:15. That is, the first diameter is at most 20 times smaller than the second diameter, which involves a narrowing of a drilled narrowing in the opening area of ​​the trench. The narrowing corresponds to the area (having a narrowed cross section) lying in the xy plane of the first invention.

[0046] The insulating layer (or the portion of the insulating layer that engages the trench) can have a first thickness in a piecewise fashion, and the thicker portion of the insulating layer can have a second thickness in a piecewise fashion. The ratio of the first thickness to the second thickness can be 100:105 to 100:150, and preferably 100:110 to 100:115.

[0047] Each narrowed cross-section region is preferably formed so that it can pass a certain threshold current. Currents above this threshold can (at least) partially melt the material of the narrowed cross-section region, thereby preventing current flow. The trench capacitor is isolated from the capacitor array, and damage to the power semiconductors to be protected cannot occur.

[0048] Another semiconductor element according to the present invention is intended to be integrated into a power module having at least one switchable power semiconductor. The semiconductor element comprises a semiconductor layer, a conductive layer, an insulating layer, and another conductive layer. The semiconductor layer has a first side with a plurality of recesses as trenches. The conductive layer is disposed on a second side of the semiconductor layer opposite the first side. The insulating layer is disposed on the first side of the semiconductor layer and extends into the trenches.

[0049] The other conductive layer is disposed on the insulating layer and has a plurality of narrowed portions, which determine the current carrying capacity of each trench capacitor. When a group of the trench capacitors is assigned to a partial region of the other conductive layer, the current carrying capacity of the group is set.

[0050] Each narrowing point conductively connects a small area section to a large area section, but can also be separated to electrically isolate the small areas.

[0051] Electrical separation can occur, for example, if a certain current density is exceeded in one of the narrowings during operation and this results in a power surge that melts one of the narrowings. Smaller sections can be separated from larger sections by corresponding narrowings.

[0052] Each narrow spot can transmit a maximum power of 80mW to 2000mW, preferably 200mW to 800mW.

[0053] At least some of the narrowed points may be located within the recesses.

[0054] The insulating layer may have a thickened portion in the opening region of the recess.

[0055] The thickened portion in the open region of the recess may correspond to a narrowed portion of another conductive layer.

[0056] A hollow space may be formed in the recess below each of the narrowed portions.

[0057] Dissolution of one of the narrow spots can dissolve the material, which enters the hollow space in the recess located below it.

[0058] Alternatively, the narrowed portion may be located on the first side of the semiconductor layer, outside or above the recess.

[0059] The narrowed points may be located above and outside the opening of the recess, respectively.

[0060] A narrowed area can be assigned to several recesses, thus forming an electrically coupled group of load-relief capacitors.

[0061] It is also possible to assign one narrow spot to only one recess.

[0062] The constrictions can preferably be formed in such a way that they are broken or cut by the flow of a current, in particular by the flow of a current whose height exceeds a threshold value that exceeds the current carrying capacity (as the melting current density of the selected metal). The melting current density is the current density (here at the constriction) at which the conductor temperature (the temperature at the constriction) rises to the melting temperature (of the selected metal) after 1 / 100 s (i.e. 10 ms) of load application (value according to Muller-Hildebrand, https: / / de.wikipedia.org / wiki / Elektrische_Stromdichte, version as of 19 July 2019, 17:04), expressed as a direct current and without skin effect.

[0063] Each of the smaller areas occupies an area that is less than 1 / 10 to 1 / 100 of the area of ​​the larger areas.

[0064] The proposed method of operating a power module comprising a multilayer semiconductor element, preferably one of the above-mentioned semiconductor elements, comprises that narrowed areas serving as electrical connection paths in the conductive layers of the multilayer semiconductor element dissolve and become non-conductive in the event of a current greater than a predetermined threshold, thereby isolating the defective element acting as a capacitor and isolating it from the parallel-connected elements acting as capacitors of the multilayer semiconductor element.

[0065] The semiconductor device can be one of the following:

[0066] A semiconductor element integrated into a power module having at least one switchable power semiconductor, (a) a semiconductor layer, wherein a first side of the semiconductor layer has a plurality of recesses as trenches; (b) a conductive layer disposed on a second side opposite the first side of the semiconductor layer; (c) an insulating layer disposed on the first side of the semiconductor layer and extending into the trench; (d) another conductive layer for contacting the semiconductor element, the another conductive layer being placed on the insulating layer, the another conductive layer having a plurality of narrowed portions.

[0067] A semiconductor element integrated into a power module, (a) a semiconductor layer, wherein a first side of the semiconductor layer has a plurality of recesses as trenches; (b) an insulating layer disposed on the first side of the semiconductor layer and extending into the trench; (c) a first conductive layer for contacting the semiconductor device, the first conductive layer being disposed on the insulating layer and extending into but not filling the trench; (d) a second conductive layer disposed on a second side opposite the first side of the semiconductor layer; A semiconductor device, wherein the insulating layer has thickened portions in trench opening regions, each thickened portion defining a conductive region having a narrowed cross section in the first conductive layer.

[0068] A semiconductor element integrated into a power module, (a) a semiconductor layer, wherein a first side of the semiconductor layer (10) has a plurality of recesses; (b) an insulating layer disposed on the first side of the semiconductor layer and engaging the recess; (c) a first conductive layer for contacting a semiconductor element, the first conductive layer being disposed on the insulating layer; (d) a second conductive layer for contacting a semiconductor element, the second conductive layer being disposed on a second side opposite the first side of the semiconductor layer; A semiconductor element, wherein the first conductive layer has a plurality of notches and a plurality of partial regions, each partial region being surrounded by at least one notch, leaving at least one region having a narrowed cross section.

[0069] The threshold value can be between 20.0 mA and 500.0 mA, and is preferably between 50.0 mA and 200.0 mA.

[0070] Dissolving one of the constrictions will dissolve the material of the constriction and the material can enter the hollow space located below the constriction.

[0071] Embodiments of the present invention will be described by way of example, but no limitations or specific embodiments of the figures should be read therein unless such limitations or more specific embodiments are included in the claims. Like reference numerals in the figures refer to like elements. [Brief explanation of the drawings]

[0072] [Figure 1A] 1 is a schematic partial top view of a semiconductor element 1 having a plurality of annular, unclosed notches 20 in a contact layer 14 of the semiconductor element 1. FIG. [Figure 1B] 1 is a first schematic cross-sectional view of a semiconductor element 1 taken along line AA. [Figure 1C]2 is a second schematic cross-sectional view of the semiconductor component 1 along the line BB in the region 22 between the two free ends of the notch 20, also called the narrowed portion 22. FIG. [Figure 2] 2 shows a schematic top view of a possible basic shape of at least one, preferably all, cutouts 20 in a contact layer 14 of a semiconductor component 1, with at least one narrowing point 22. FIG. [Figure 3A] 1 is a schematic partial top view of another semiconductor element 2 having multiple elliptical ring-shaped notches 20 in a contact layer 14 of the semiconductor element 2. FIG. [Figure 3B] 2 is a schematic cross-sectional view of the semiconductor element 2 taken along line CC. FIG. [Figure 4A] 10 is a schematic cross-sectional view of another semiconductor element 3 according to an embodiment in which the contact layer 14 of the semiconductor element 3 does not have a notch. [Figure 4B] 2 is a schematic cross-sectional view of a semiconductor element 3 taken along the line DD to clarify an area 32, also called a narrowed portion 22, having a narrowed cross-section. DETAILED DESCRIPTION OF THE INVENTION

[0073] 1A is a schematic partial (section) top view of a semiconductor device 1 having a plurality of annular cutouts 20 in a contact layer 14 of the semiconductor device 1. The cutouts 20 are not closed; sections 22 of the contact layer 14 remain.

[0074] An xyz coordinate system is plotted to represent the orientation, with the z axis being the elevation direction, and the xy axes defining the plane in which the trench capacitors are distributed and positioned.

[0075] 1A shows a total of nine notches 20 in the contact layer 14 of the semiconductor component 1. However, the semiconductor component may have more than nine notches 20, preferably several hundred notches 20, each having a section 22.

[0076] The cutouts 20 in the contact layer 14, which serves as the first conductive layer of the semiconductor component 1, define regions 22 with narrowed cross sections in the first conductive layer 14. (Connecting) webs 22 are shown here. Alternatively, smaller partial regions 24 in (or from) the first conductive layer 14 are free. "Free" in this context means that one (side) surface is "separated" or delimited parallel to the z-axis by the respective cutout in the first conductive layer, with the partial regions 24 being conductively connected to the rest of the first conductive layer only by the narrowed portions 22 (also called "webs"). Alternatively, the corresponding cutouts 20 delimit the partial regions 24, with the ends 20a and 20b of each cutout 20 approaching each other and thereby defining the lateral extent of the narrowed portions 22 (as webs).

[0077] Each partial region 24 refers to a flat region of the first conductive layer 14 that is released by the notch 20 and is connected to the flat region 14a of the first conductive layer 14 only by the narrowed conductive cross section. As will be explained in more detail below, the conductive connection is intended to become non-conductive when the release defined as the narrowed point 22 is removed, i.e., physically separated.

[0078] As will be explained later, the first conductive layer 14, which comprises flat regions 14a and finger-shaped regions 14b, should be considered functional.

[0079] A cross-sectional view taken along line AA is shown in FIG. 1B, and a cross-sectional view taken along line BB is shown in FIG. 1C.

[0080] 1B, it can be seen that the semiconductor component 1 is made up of several layers, with the bottom layer 16 in the z-direction being the second conductive layer of the semiconductor component 1 and serving for electrical contact of the semiconductor component 1.

[0081] Disposed on or above second conductive layer 16 is semiconductor layer 10. Semiconductor layer 10 has a plurality of recesses 11, three recesses are shown here, but semiconductor layer 10 can have many more than three recesses 11, and preferably semiconductor layer can have hundreds of recesses 11.

[0082] An insulating layer 12 is provided on the semiconductor layer 10. The insulating layer 12 has a region 12a that corresponds to the surface of the semiconductor layer 10 and is flat and parallel to the x, y plane, and a region 12b whose outer contour corresponds to the shape of the recess 11 or fits into the recess 11.

[0083] The number of recesses 11 may correspond to the number of notches 20 .

[0084] The number of recesses 11 can be greater than the number of notches 20 .

[0085] In cross section, the recess 11 in FIG. 1B has a U-shape (2D, x, z plane).

[0086] The recesses 11 can have a finger-like shape (3D view). Finger-like means that each recess 11 drilled as a trench in the semiconductor layer 10 can have a cylindrical section and a semicircular section. The upper edge contour of the opening of the recess 11, as seen in the z direction, is correspondingly defined by a cylindrical section (circular edge contour).

[0087] The recess 11 can also have other geometries, for example the recess 11 can be formed as a trench.

[0088] The recesses 11 may be evenly distributed in the semiconductor layer 10, ie equally spaced from one another (in the x, y plane).

[0089] The semiconductor layer 10 has the maximum thickness of the semiconductor device. The recess 11 can extend into the semiconductor layer 10 more than half the thickness of the semiconductor layer 10.

[0090] The semiconductor layers extend parallel to the x, y plane (the semiconductor layers are flat).

[0091] An insulating layer 12 is provided on the semiconductor layer 10. The insulating layer 12 has flat regions 12a (parallel to the x, y plane) corresponding to the surface structure of the semiconductor layer 10, and finger-like regions 12b that engage with the recesses 11 or cover the sidewalls of the recesses.

[0092] The insulating layer 12 may have a uniform thickness.

[0093] A first conductive layer 14 is placed on the insulating layer 12. In Figure 1B it can be seen that the first conductive layer 14 is divided into flat regions 14a (parallel to the x, y plane) and finger-shaped regions 14b that fit into the recesses 11 and fill them (as filling material), in accordance with the surface structure of the insulating layer 12.

[0094] The greyed-out area, partly bordered by a dashed line, indicates the location of the area 22, which here has a narrowed cross section as seen in the x, y plane.

[0095] The partial regions 24 refer to flat regions of the first conductive layer 14, which are released by the notches 20 and are connected to the flat regions 14a of the first conductive layer 14 only in the respective regions 22 having a narrowed cross section, without taking into account the filling material 14b in the recesses 11 corresponding to the notches 20.

[0096] In this example, each notch 20 or each partial area 24 is assigned to one recess 11. Each partial area 24 in the first conductive layer 14 extends radially in the x, y plane beyond the opening of the recess 11 it covers.

[0097] The notches 20 are arranged in the first conductive layer so as to define respective flat areas 12a and finger-shaped drilled sections 12b of the insulating layer 12 in sections.

[0098] That is, insulating layer 12 should be considered functional.

[0099] In FIG. 1C, instead of all regions 22 having respective narrowed cross sections in the first conductive layer, the regions 22 having narrowed cross sections are each formed with a width b A and height h A i.e., cross section h A *b A It can be seen that it has

[0100] width b A and height h A The notch 20 is formed so that the narrowed cross section of the region 22 can pass a current up to a certain height. The narrowed cross section region 22 can pass a current up to this current without damage. Currents above the certain height will cause the narrowed cross section region 22 to melt or sublimate, thereby preventing current from passing through that region.

[0101] The length of the region 22 with narrowed cross section can also influence the time point of interruption of electrical conduction and can be adjusted accordingly.

[0102] The height h of the region 22 having the narrowed cross section A is substantially determined by the layer thickness of the flat region 14a of the first conductive layer 14, and can preferably correspond to the layer thickness of the flat region 14a.

[0103] By melting or sublimating the region 22 with the narrowed cross section, the region of the semiconductor component 1 that acts as a (trench) capacitor within the semiconductor component 1 can be electrically isolated sufficiently from the rest of the semiconductor component 1. If the release of a small partial region leads to the disconnection or removal of the trench capacitor, it can be said that a current that destroys the narrowing point can cause malfunctions, in particular short-circuiting of the snubber network (RC circuit). The other parallel-connected trench capacitors continue to function unharmed.

[0104] 2 a schematic top view of a possible basic shape of a cutout 20 in a contact layer 14 of a semiconductor component is shown, in this case the basic shape replaces all cutouts 20 in the first conductive layer 14 of a semiconductor component, e.g. semiconductor component 1.

[0105] The circular notches 20 (first row, first shape) correspond to the shape already shown and described in FIG. 1A.

[0106] The notches 20 can also have other basic shapes. They can have a triangular (first row, second shape), a square or rectangular (first row, third shape), or a pentagonal or polygonal (first row, fourth shape) basic shape. The recesses 11 can also have a non-round shape, for example as a trench.

[0107] Up to now, we have considered an example in which one notch 20 is assigned to the recess 11. However, it is also possible for several notches 20 to be assigned to the recess 11, or for several recesses to define one open partial area 24.

[0108] This is shown exemplarily in the second column of Figure 2. The first shape in the second column of Figure 2 still has a circular basic shape, but is formed by two half-ring-shaped cutouts 20 that define two regions 22 of narrowed cross section in the first conductive layer. The current carrying capacity is doubled.

[0109] The same applies to other embodiments of the cutouts 20. The different basic shapes (triangle, rectangle, polygon, etc.) remain essentially the same, but are formed by two or more cutouts 20. Depending on the number of cutouts 20, from which partial regions 24 are formed or released, the number of regions 22 with narrowed cross sections, i.e. the number of narrowing points, is determined accordingly.

[0110] 3A shows a schematic partial top view of a semiconductor device 2 having six oval ring-shaped notches 20 in a contact layer 14 of the semiconductor device 2. The contact layer 14 is a first conductive layer of the semiconductor device 2.

[0111] The cutouts 20 in the first conductive layer 14 of the semiconductor component 2 surround respective partial regions 24 in the first conductive layer 14, leaving behind regions 22 with narrowed cross sections. The cutouts 20 leave the partial regions 24 open on one side.

[0112] A cross-sectional view (cross-section along line CC) of semiconductor element 2 is shown in FIG. 3B.

[0113] From the cross-sectional view of Figure 3B, it can be seen that the semiconductor element 2 has the same layer configuration as the semiconductor element 1 from Figures 1A, 1B, and 1C, but differs in that one notch 20 surrounds or is assigned to two recesses 11, respectively.

[0114] The notches 20 can also be assigned to more than two recesses 11 each, the function being the same as in Figure 1. In that case, the separation of the trench capacitors corresponds to the electrical separation of a group of trench capacitors, of which there are two in this example.

[0115] FIG. 4A shows a schematic cross-sectional view of a semiconductor element 3 according to an alternative embodiment in which the first contact layer 14 of the semiconductor element 3 does not have a notch.

[0116] The semiconductor component 3 has a layer structure or layer configuration. The lowest layer 16 in the z direction is a second conductive layer for contacting the semiconductor component 3. The second conductive layer 16 has a semiconductor layer 10 disposed thereon.

[0117] An insulating layer 12 is provided on the semiconductor layer 10. The insulating layer 12 has a region 12a that corresponds to the surface of the semiconductor layer 10 and is flat and parallel to the x, y plane, and a region 12b whose outer contour corresponds to the shape of the recess 11 or fits into the recess 11.

[0118] The semiconductor layer 10 has a plurality of recesses 11, three recesses 11 in total shown here.

[0119] The semiconductor element 3 may have more than three recesses 11 , and preferably the semiconductor element 3 may have several hundred recesses 11 .

[0120] The recesses 11 may be arranged in the semiconductor layer 10 at equal intervals from one another (in the x, y plane).

[0121] The recess 11 may extend on one side beyond half the layer thickness of the semiconductor layer 10 or may extend into the semiconductor layer 10 (negative z-direction).

[0122] The recesses 11 preferably have a finger-like shape, meaning that each recess 11 has a sectioned cylindrical region and a section that is formed hemispherically, and the opening of the recess 11 has a correspondingly circular edge contour.

[0123] The recesses 11 may have other shapes, for example the shape of a rectangular parallelepiped or a trench. The recesses 11 increase the surface area of ​​the semiconductor layer 10.

[0124] An insulating layer 12 is provided on the semiconductor layer 10. The insulating layer 12 has a region 12a that is flat and parallel to the x, y plane, corresponding to the surface of the semiconductor layer 10, and a region 12b whose outer contour corresponds to the shape of the recess 11 or engages with the recess 11. In addition, the insulating layer 12 in each opening region of each recess 11 has a thickened portion 30 that extends radially inward (in the direction of the axis of the recess 11) from the respective cylindrical region of the recess 11.

[0125] The insulating layer 12 has a uniform thickness t1 except for the thickened region 30. The thickened portion has a maximum thickness t2. The thickness t1 is smaller than the thickness t2 of the thickened portion.

[0126] Corresponding to the surface geometry of the insulating layer 12, a first contact layer 14 as a first conductive layer has regions 14b which engage in the coated recess 11 and regions 14a which are parallel to the x, y plane.

[0127] Due to the thickened portions 30 in the insulating layer 12, the first conductive layer 14 or the regions 14b engaging the covered recesses 11 each have a region 32 with a narrowed cross section per recess 11.

[0128] The first conductive layer 14 can be grown or deposited (thermal oxidation, oxide or nitride deposited from the vapor phase, vapor phase deposition, sputtering, etc.) on the insulating layer 12, for example.

[0129] Due to the method, the conductive material of the first conductive layer 14 reaches and deposits through the regions 32 with narrowed cross section, but only until the regions 32 with narrowed cross section are closed by the deposited material, thereby leaving a hollow space 34 below the regions 32 with narrowed cross section that is not filled with conductive material (gas-confined region). Correspondingly, the recesses 11 coated with the insulating layer 12 can only be partially filled with the material of the conductive layer 14.

[0130] Each region 32 having a narrowed cross section can be specifically formed so that only a current of a pre-specified intensity or magnitude can pass through it without damage. If a current above a current threshold flows through one of the regions 32 having a narrowed cross section, this will lead to melting of the region 32 having a narrowed cross section, thereby preventing the region 32 having a narrowed cross section from passing a current.

[0131] The molten material of region 32 can accumulate in hollow spaces 34 that are not filled with the material of first semiconductor layer 14, thereby preventing current from passing through region 32 with the narrowed cross section.

[0132] A (partial) cross-sectional view (cross-section along line DD) of the semiconductor device 3 is shown in FIG. 4B.

[0133] 4B shows cross sections of a total of nine recesses 11. As mentioned above, the semiconductor element 3 may have many more recesses 11 (not shown).

[0134] Each finger-like recess 11 has at least a segmental (in the segmental cylindrical section of the recess) insulating diameter d2. The region 32 having the narrowed cross section has a conductive diameter d1 therein.

[0135] The diameter d2 of the recess is greater than the diameter d1 of the region 32 with the narrowed cross section. The ratio of the two diameters can be specifically designed so that the region 32 with the narrowed cross section (the narrowed spot) of the first conductive layer 14 can pass a current of a certain intensity without damage. In other words, above this current threshold, the narrowed spot 32 unravels.

[0136] As mentioned above, if a limiting current is exceeded in one of the regions 32 having a narrowed cross section, the material at diameter d1 melts, thereby electrically isolating the region of the semiconductor element from the rest of the semiconductor element. [Explanation of symbols]

[0137] 1, 2, 3 Semiconductor elements 10 Semiconductor layer 11 Recess 12, 12a, 12b insulating layers 14, 14a, 14b First conductive layer 16 Second conductive layer 20 Notch 22 Areas with narrowed cross sections, constrictions 24 subregion 30 Thick wall part 32 Areas with narrowed cross sections, constrictions 34 Hollow space

Claims

1. A semiconductor element (1, 2) for integration into a power module, (a) a semiconductor layer (10), wherein a first side of the semiconductor layer (10) has a plurality of recesses (11); (b) an insulating layer (12; 12a, 12b) placed on the first side of the semiconductor layer (10) and engaging the recess (11); (c) a first conductive layer (14; 14a, 14b) for contacting the semiconductor element (1, 2), the first conductive layer (14; 14a, 14b) being placed on the insulating layer (12a, 12b); (d) a second conductive layer (16) for contacting the semiconductor elements (1, 2), the second conductive layer (16) being disposed on a second side of the semiconductor layer (10) opposite the first side, The semiconductor element (1, 2) has a first conductive layer (14; 14a, 14b) having a plurality of notches (20, 20) and a plurality of partial regions (24), each of which is surrounded by at least one notch (20), leaving at least one region (22, 22) having a narrowed cross section.

2. 2. The semiconductor device of claim 1, wherein at least some of the partial regions (24) of the first conductive layer (14; 14a, 14b) are surrounded by a plurality of notches (20, 20), leaving a plurality of regions (22, 22) with a narrowed cross section.

3. The narrowed cross-section regions (22) in the first conductive layer (14; 14a, 14b) each have a height (h) of 100.0 nm to 1.0 μm. Ａ ), and a width of 50.0 nm to 5.0 μm (b Ａ 3. The semiconductor device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

4. The narrowed cross-sectional areas (22) are each of the same height (h Ａ ), and the same width (b Ａ 4. The semiconductor device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

5. 5. The semiconductor element according to claim 1, wherein each of the partial regions (24) of the first conductive layer (14; 14a, 14b) at least partially covers or completely covers an opening of a recess (11) or extends radially beyond the edge of the respective opening of the recess (11).

6. 5. The semiconductor element according to claim 1, wherein each of the partial regions (24) of the first conductive layer (14; 14a, 14b) at least partially covers or completely covers a plurality of openings of the associated recess (11) or respectively extends radially beyond the edges of the openings.

7. The semiconductor component according to any one of claims 1 to 6, wherein the cutout (20) has a basic shape that is part-circular, circular, rectangular or polygonal.

8. A semiconductor element (3) for integration into a power module, (a) a semiconductor layer (10), wherein a first side of the semiconductor layer (10) has a plurality of recesses (11) as trenches; (b) an insulating layer (12; 12a, 12b) disposed on the first side of the semiconductor layer (10) and extending into the trench (11); (c) a first conductive layer (14; 14a, 14b) for contacting the semiconductor element (3), the first conductive layer (14; 14a, 14b) resting on the insulating layer (12; 12a, 12b) and extending into the trench (11) but not filling it (34); (d) a second conductive layer (16) disposed on a second side of the semiconductor layer (10) opposite the first side; The insulating layer (12) has thickened portions (30) in the opening regions of the trenches (11), each thickened portion (30) defining a conductive region (32) having a narrowed cross section in the first conductive layer (14; 14a, 14b).

9. The conductive regions (32) having the narrowed cross section in the first conductive layer (14) each have a first diameter (d １ 9. The semiconductor device of claim 8, wherein

10. Each trench (11) at least partially has a second diameter (d ２ ) and a first diameter (d １ ) and the second diameter (d ２ ) ratio (d １ :d ２ 10. The semiconductor device according to claim 8, wherein the ratio of the ratio of the weight of the semiconductor layer to the weight of the substrate is 1:2 to 1:

20.

11. The insulating layer (12; 12a, 12b) is piecewise formed to a first thickness (t １ ), and the thick portion (30) of the insulating layer has a second layer thickness (t ２ ), and the first layer thickness (t １ ) and the second layer thickness (t ２ ) ratio (t １ :t ２ 11. The semiconductor device according to claim 8, wherein the ratio of the molecular weight of the polymer to the molecular weight of the substrate is 100:105 to 100:

150.

12. A semiconductor element (1, 2, 3) for integration into a power module having at least one switchable power semiconductor, (a) a semiconductor layer (10), wherein a first side of the semiconductor layer (10) has a plurality of recesses (11) as trenches; (b) a conductive layer (16) disposed on a second side of the semiconductor layer (10) opposite the first side; (c) an insulating layer (12; 12a, 12b) disposed on the first side of the semiconductor layer (10) and extending into the trench (11); (d) another conductive layer (14; 14a, 14b) for contacting the semiconductor element (3), the another conductive layer (14; 14a, 14b) being placed on the insulating layer (12), the another conductive layer (14; 14a, 14b) having a plurality of narrowed portions (22, 32), (e) A semiconductor element (1, 2, 3) in which each of said narrowed portions (22, 32) electrically connects a small area section (24) with a large or larger area section, but can also be separated to electrically isolate it.

13. 13. The semiconductor device according to claim 12, wherein at least some of the narrowed portions (32) are located within the recesses (11).

14. 14. The semiconductor element according to claim 13, wherein the insulating layer (12) has a thickened portion (30) in the opening region of the recess (11).

15. 15. The semiconductor component according to claim 14, wherein the thickened portion (30) in the opening region of the recess (11) corresponds to the narrowed portion (32) of the further conductive layer (14; 14a, 14b).

16. 13. The semiconductor device according to claim 12, wherein the narrowed portion (22) is located on the first side of the semiconductor layer (10), outside or above the recess (11).

17. 17. The semiconductor component according to claim 12 or 16, wherein one narrow spot (22) is assigned to a plurality of recesses (11).

18. 17. The semiconductor component according to claim 12 or 16, wherein a plurality of narrowed portions (22) are assigned to one recess (11).

19. A semiconductor element as described in any one of claims 1 to 18, wherein the narrowed portion (22, 32) is formed so as to be divided or cut by the flow of current.

20. 13. The semiconductor device of claim 12, wherein each of the smaller area sections (24) occupies less than 1 / 10 or less than 1 / 100 of the conductive area of ​​the larger area section (14b).

21. 15. The semiconductor element according to claim 13 or 14, wherein a hollow space (34) is formed in the recess (11) below each of the narrowed portions (32).

22. 22. The semiconductor element according to claim 21, wherein the melting of one of the narrowed points (32) melts material which enters the hollow space (34) in the recess (11) located therebelow.

23. A method of operating a power module having a multi-layer semiconductor device including a plurality of parallel-connected capacitor-resistor elements, comprising: (a) the narrowed portions (22, 32) serving as electrical connection conductive paths in the conductive layers (14; 14a, 14b) of the multilayer semiconductor element dissolve or sublimate and become non-conductive when a current greater than a predetermined threshold is applied; (b) whereby a faulty capacitor-resistor element, functioning as a snubber, is individualized and isolated from the plurality of parallel-connected capacitor-resistor elements of said multi-layer semiconductor device.

24. 24. The method of claim 23, wherein the threshold is between 20.0 mA and 500.0 mA.

25. A method as described in claim 23 or claim 24, wherein dissolving one of the narrow areas (32) melts material, which enters a hollow space (34) located below the narrow area (32).

26. A method according to claim 23, comprising a semiconductor element (1, 2, 3) according to any one of claims 1 to 22.

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