nitride semiconductor devices

Abstract

This nitride semiconductor device 1 comprises: a substrate 2 which has a first main surface 2a and a second main surface 2b that is on the reverse side of the first main surface; and a nitride epitaxial layer 20 which is formed on the first main surface 2a. When viewed in plan, the nitride semiconductor device 1 has: an active region 101 in which a two-dimensional electron gas 19 is able to be formed within the nitride epitaxial layer 20; and an inert region 102 in which a two-dimensional electron gas 19 is not formed within the nitride epitaxial layer 20. At least in the inert region 102 among the active region 101 and the inert region 102, the nitride semiconductor device 1 has a trench 14 which is formed by digging the substrate 2 from the second main surface 2b toward the first main surface 2a, and a buried metal 15A which is formed within the trench 14.

Description

[Technical Field]

[0001] The present disclosure relates to a nitride semiconductor device made of a group III nitride semiconductor (hereinafter sometimes simply referred to as a "nitride semiconductor"). [Background technology]

[0002] Group III nitride semiconductors are semiconductors that use nitrogen as a group V element in the III-V group of semiconductors. Typical examples are aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN). Generally, Al x In y Ga 1-x-y It can be expressed as N(0≦x≦1, 0≦y≦1, 0≦x+y≦1).

[0003] Patent Document 1 discloses a HEMT (High Electron Mobility Transistor) using a nitride semiconductor. The HEMT in Patent Document 1 includes a p-type Si substrate, a buffer layer formed on the p-type Si substrate, an electron transit layer made of GaN formed on the buffer layer, and an electron supply layer made of AlGaN formed on the electron transit layer. A drain electrode and a gate electrode are formed in contact with this electron supply layer.

[0004] A source electrode is formed through the electron supply layer, the electron transit layer, and the buffer layer to contact the p-type Si substrate. A backside electrode is formed on the backside of the p-type Si substrate and is electrically connected to the source electrode via the p-type Si substrate.

[0005] Due to polarization caused by the lattice mismatch between GaN and AlGaN, two-dimensional electron gas is formed in the electron transit layer, a few angstroms inward from the interface between the electron transit layer and the electron supply layer. This two-dimensional electron gas acts as a channel to connect the source and drain. By applying a control voltage to the gate electrode, the two-dimensional electron gas is blocked, thereby blocking the connection between the source and drain. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-363563 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present disclosure is to provide a nitride semiconductor device with high heat dissipation properties. [Means for solving the problem]

[0008] One embodiment of the present disclosure provides a nitride semiconductor device including a substrate having a first main surface and a second main surface opposite to the first main surface, and a nitride epitaxial layer formed on the first main surface, wherein the nitride semiconductor device has, in a planar view, an active region in which two-dimensional electron gas can be formed in the nitride epitaxial layer, and an inactive region in which two-dimensional electron gas is not formed in the nitride epitaxial layer, and at least the inactive region of the active region and the inactive region includes a trench dug from the second main surface of the substrate toward the first main surface of the substrate, and a buried metal formed in the trench.

[0009] This configuration makes it possible to realize a nitride semiconductor device with high heat dissipation properties.

[0010] The above and other objects, features, and advantages of the present disclosure will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view illustrating the configuration of a nitride semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. [Figure 4A] FIG. 4A is a cross-sectional view showing an example of a manufacturing process of the nitride semiconductor device. [Figure 4B] FIG. 4B is a cross-sectional view showing the next step of FIG. 4A. [Figure 4C] FIG. 4C is a cross-sectional view showing the next step of FIG. 4B. [Figure 4D] FIG. 4D is a cross-sectional view showing the next step of FIG. 4C. [Figure 4E] FIG. 4E is a cross-sectional view showing the next step of FIG. 4D. [Figure 4F] FIG. 4F is a cross-sectional view showing the next step of FIG. 4E. [Figure 4G] FIG. 4G is a cross-sectional view showing the step subsequent to FIG. 4F. [Figure 4H] FIG. 4H is a cross-sectional view showing the step subsequent to FIG. 4G. [Figure 4I] FIG. 4I is a cross-sectional view showing the step subsequent to FIG. 4H. [Figure 5] FIG. 5 is a plan view illustrating the configuration of a nitride semiconductor device according to a second embodiment of the present disclosure. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8A] FIG. 8A is a cross-sectional view showing an example of a manufacturing process of the nitride semiconductor device. [Figure 8B] FIG. 8B is a cross-sectional view showing the next step of FIG. 8A. [Figure 8C] FIG. 8C is a cross-sectional view showing the step subsequent to FIG. 8B. [Figure 8D] FIG. 8D is a cross-sectional view showing the step subsequent to FIG. 8C. [Figure 9] FIG. 9 is a plan view illustrating the configuration of a nitride semiconductor device according to a third embodiment of the present disclosure. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12A] FIG. 12A is a cross-sectional view showing an example of a manufacturing process of the nitride semiconductor device. [Figure 12B] FIG. 12B is a cross-sectional view showing the next step of FIG. 12A. [Figure 12C] FIG. 12C is a cross-sectional view showing the next step of FIG. 12B. [Figure 12D] FIG. 12D is a cross-sectional view showing the step subsequent to that of FIG. 12C. [Figure 12E] FIG. 12E is a cross-sectional view showing the step subsequent to that of FIG. 12D. [Figure 12F] FIG. 12F is a cross-sectional view showing the step subsequent to that of FIG. 12E. [Figure 12G] FIG. 12G is a cross-sectional view showing the step subsequent to FIG. 12F. [Figure 12H] FIG. 12H is a cross-sectional view showing the step subsequent to FIG. 12G. [Figure 13] FIG. 13 is a cross-sectional view showing a modification of the nitride semiconductor device of FIG. [Figure 14] FIG. 14 is a cross-sectional view showing a modification of the nitride semiconductor device of FIG. [Figure 15] FIG. 15 is a cross-sectional view showing a modification of the nitride semiconductor device of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] [Description of the embodiments of the present disclosure] One embodiment of the present disclosure provides a nitride semiconductor device including a substrate having a first main surface and a second main surface opposite to the first main surface, and a nitride epitaxial layer formed on the first main surface, wherein the nitride semiconductor device has, in a planar view, an active region in which two-dimensional electron gas can be formed in the nitride epitaxial layer, and an inactive region in which two-dimensional electron gas is not formed in the nitride epitaxial layer, and at least the inactive region of the active region and the inactive region includes a trench dug from the second main surface of the substrate toward the first main surface of the substrate, and a buried metal formed in the trench.

[0013] In one embodiment of the present disclosure, the trench is formed only in the inactive region out of the active region and the inactive region.

[0014] In one embodiment of the present disclosure, the trenches are formed in both the active region and the inactive region.

[0015] In one embodiment of the present disclosure, the total volume of the trenches present in the inactive region is equal to or greater than one-third of the volume of the substrate in the inactive region.

[0016] In one embodiment of the present disclosure, the insulating film further includes an extraction metal formed on the second main surface and thermally connected to the buried metal.

[0017] In one embodiment of the present disclosure, the trench is dug from the second main surface toward the first main surface to a point partway through the substrate.

[0018] In one embodiment of the present disclosure, the trench extends through the substrate to the nitride epitaxial layer.

[0019] In one embodiment of the present disclosure, the semiconductor device includes a source electrode, a drain electrode, and a gate electrode disposed on the nitride epitaxial layer, and a contact metal that penetrates the nitride epitaxial layer and electrically connects the source electrode and the buried metal.

[0020] In one embodiment of the present disclosure, the nitride epitaxial layer includes a first nitride semiconductor layer constituting an electron transit layer, and a second nitride semiconductor layer formed on the first nitride semiconductor layer, constituting an electron supply layer, and having a band gap higher than that of the first nitride semiconductor layer.

[0021] In one embodiment of the present disclosure, the semiconductor device further includes a semi-insulating nitride layer disposed between the substrate and the first nitride semiconductor layer, the semi-insulating nitride layer having a higher acceptor concentration than a donor concentration.

[0022] In one embodiment of the present disclosure, a buffer layer made of a nitride semiconductor is disposed between the substrate and the semi-insulating nitride layer.

[0023] In one embodiment of the present disclosure, the first nitride semiconductor layer is made of a GaN layer, and the second nitride semiconductor layer is made of an AlGaN layer.

[0024] In one embodiment of the present disclosure, the first nitride semiconductor layer is made of a GaN layer, the second nitride semiconductor layer is made of an AlGaN layer, and the semi-insulating nitride layer is made of a GaN layer containing carbon.

[0025] In one embodiment of the present disclosure, the first nitride semiconductor layer is made of a GaN layer, the second nitride semiconductor layer is made of an AlGaN layer, the semi-insulating nitride layer is made of a GaN layer containing carbon, and the buffer layer is made of a stacked film of an AlN layer formed on the first main surface and an AlGaN layer stacked on the AlN layer.

[0026] In one embodiment of the present disclosure, the first nitride semiconductor layer is a GaN layer, the second nitride semiconductor layer is an AlGaN layer, the semi-insulating nitride layer is a GaN layer containing carbon, and the buffer layer is an AlN layer or an AlGaN layer.

[0027] Detailed Description of Embodiments of the Present Disclosure Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0028] Fig. 1 is a plan view illustrating the configuration of a nitride semiconductor device according to a first embodiment of the present disclosure, Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1, and Fig. 3 is a cross-sectional view taken along line III-III in Fig. 2.

[0029] In the following description, the left-right direction of the paper surface of FIG. 1 may be referred to as the horizontal direction, and the up-down direction of the paper surface of FIG. 1 may be referred to as the vertical direction.

[0030] As shown in FIG. 1, the nitride semiconductor device 1 has, for example, a rectangular parallelepiped shape that is long in the horizontal direction.

[0031] The nitride semiconductor device 1 includes a substrate 2 having a first main surface (front surface) 2a and a second main surface (back surface) 2b opposite to the first main surface 2a of the substrate 2, and a nitride epitaxial layer 20 formed on the first main surface 2a of the substrate 2. The nitride epitaxial layer 20 includes a buffer layer 3 formed on the first main surface 2a of the substrate 2, a semi-insulating nitride layer 4 formed on the buffer layer 3, a first nitride semiconductor layer 5 formed on the semi-insulating nitride layer 4, and a second nitride semiconductor layer 6 formed on the first nitride semiconductor layer 5.

[0032] The nitride semiconductor device 1 further includes an insulating film 7 formed on the second nitride semiconductor layer 6. The nitride semiconductor device 1 further includes a source electrode 10 and a drain electrode 11 that pass through a source contact hole 8 and a drain contact hole 9 formed in the insulating film 7 and make ohmic contact with the second nitride semiconductor layer 6. The source electrode 10 and the drain electrode 11 are arranged with a gap between them.

[0033] Furthermore, this nitride semiconductor device 1 includes a gate electrode 13 that penetrates a gate contact hole 12 formed in the insulating film 7 and contacts the second nitride semiconductor layer 6. The gate electrode 13 is disposed between the source electrode 10 and the drain electrode 11. Furthermore, this nitride semiconductor device 1 has a heat dissipation structure 15.

[0034] In this embodiment, the substrate 2 is made of a low-resistivity Si (silicon) substrate. The substrate 2 may contain, for example, p-type impurities. The p-type impurity concentration is, for example, 1×10 17 cm -3 ~1×10 20 cm -3 The thickness of the substrate 2 is, for example, about 100 μm to 700 μm. In this embodiment, the thickness of the substrate 2 is about 200 μm.

[0035] The buffer layer 3 is a buffer layer for alleviating strain caused by the difference between the lattice constant of the semi-insulating nitride layer 4 formed on the buffer layer 3 and the lattice constant of the substrate 2. In this embodiment, the buffer layer 3 is composed of a multilayer buffer layer in which a plurality of nitride semiconductor films are stacked. In this embodiment, the buffer layer 3 is composed of a stacked film of an AlN film in contact with the surface of the substrate 2 and an AlGaN film stacked on the surface of this AlN film (the surface opposite to the substrate 2). The buffer layer 3 may be composed of a single AlN film or a single AlGaN film. The thickness of the buffer layer 3 is, for example, about 0.1 μm to 5 μm. In this embodiment, the thickness of the buffer layer 3 is about 0.5 μm.

[0036] The semi-insulating nitride layer 4 is provided to suppress leakage current. The semi-insulating nitride layer 4 is made of a GaN layer doped with impurities, and has a thickness of about 1 μm to 10 μm. In this embodiment, the thickness of the semi-insulating nitride layer 4 is about 2 μm. The impurity is, for example, C (carbon), and the difference between the acceptor concentration Na and the donor concentration Nd (Na−Nd) is 1×10 17 cm -3 It is doped to such an extent that

[0037] The first nitride semiconductor layer 5 constitutes an electron transit layer. In this embodiment, the first nitride semiconductor layer 5 is made of an n-type GaN layer doped with donor-type impurities, and has a thickness of, for example, about 0.05 μm to 1 μm. In this embodiment, the first nitride semiconductor layer 5 has a thickness of about 0.2 μm. The first nitride semiconductor layer 5 may also be made of an undoped GaN layer.

[0038] Regarding the first nitride semiconductor layer 5, the lower surface on the side of the semi-insulating nitride layer 4 is referred to as the back surface, and the upper surface on the opposite side is referred to as the front surface. The central portion 5A in the shape of a horizontally long rectangle in plan view on the surface of the first nitride semiconductor layer 5 protrudes more than the peripheral portion 5B in the shape of a rectangular ring in plan view on the same surface. As a result, a step is formed between the central portion 5A and the peripheral portion 5B on the surface of the first nitride semiconductor layer 5. Therefore, the surface (upper surface) of the first nitride semiconductor layer 5 consists of the central portion 5A of the high step portion, the peripheral portion 5B of the low step portion, and the connecting portion 5C connecting them.

[0039] The second nitride semiconductor layer 6 is formed on the central portion 5A of the surface of the first nitride semiconductor layer 5. The second nitride semiconductor layer 6 constitutes an electron supply layer. The second nitride semiconductor layer 6 is made of a nitride semiconductor having a larger bandgap than the first nitride semiconductor layer 5. Specifically, the second nitride semiconductor layer 6 is made of a nitride semiconductor having a higher Al composition than the first nitride semiconductor layer 5. In a nitride semiconductor, the larger the Al composition, the larger the bandgap. In this embodiment, the second nitride semiconductor layer 6 is an Al x1 Ga 1-x1 N layer (0 < x1 ≦ 1), and its thickness is, for example, about 1 nm to 100 nm. In this embodiment, the thickness of the second nitride semiconductor layer 6 is about 20 nm, and x1 = 0.2.

[0040] As described above, the first nitride semiconductor layer 5 (electron traveling layer) and the second nitride semiconductor layer 6 (electron supply layer) are made of nitride semiconductors having different bandgaps (Al compositions), and a lattice mismatch occurs between them. Then, due to the spontaneous polarization of the first nitride semiconductor layer 5 and the second nitride semiconductor layer 6 and the piezo polarization caused by the lattice mismatch between them, the energy level of the conduction band of the first nitride semiconductor layer 5 at the interface between the first nitride semiconductor layer 5 and the second nitride semiconductor layer 6 becomes lower than the Fermi level. As a result, in the first nitride semiconductor layer 5, a two-dimensional electron gas (2DEG) 19 spreads at a position close to the interface with the second nitride semiconductor layer 6 (for example, at a distance of about several Å from the interface).

[0041] In a plan view, a region where two-dimensional electron gas 19 can be formed is referred to as active region 101, and a region where two-dimensional electron gas (2DEG) 19 is not formed is referred to as inactive region 102. In this embodiment, the region where central portion 5A of the surface of first nitride semiconductor layer 5 exists in a plan view is active region 101, and the region where peripheral portion 5B of the surface of first nitride semiconductor layer 5 exists in a plan view is inactive region 102.

[0042] The insulating film 7 is formed on almost the entire surface of the second nitride semiconductor layer 6. In this embodiment, the insulating film 7 is made of SiN. The thickness of the insulating film 7 is, for example, about 10 nm to 200 nm. In this embodiment, the thickness of the insulating film 7 is about 100 nm. In addition to SiN, the insulating film 7 may be made of SiO2, SiN, SiON, Al2O3, AlN, AlON, HfO, HfN, HfON, HfSiON, AlON, etc.

[0043] The source electrode 10 covers the source contact hole 8 and the periphery of the source contact hole 8 on the surface of the insulating film 7. A part of the source electrode 10 enters the source contact hole 8 and is in contact with the surface of the second nitride semiconductor layer 6 inside the source contact hole 8.

[0044] The drain electrode 11 covers the drain contact hole 9 and the peripheral portion of the drain contact hole 9 on the surface of the insulating film 7. A portion of the drain electrode 11 enters the drain contact hole 9 and is in contact with the surface of the second nitride semiconductor layer 6 within the drain contact hole 9.

[0045] The source electrode 10 and the drain electrode 11 are each made of a Ti / Al laminated film, in which a Ti film and an Al film are laminated in that order from the bottom up. The thickness of the lower Ti film is, for example, about 20 nm, and the thickness of the upper Al film is, for example, about 300 nm.

[0046] The source electrode 10 and the drain electrode 11 may be made of any material that can make ohmic contact with the second nitride semiconductor layer 6 (AlGaN layer). The source electrode 10 and the drain electrode 11 may be made of a Ti / Al / Ni / Au stacked film in which a Ti film, an Al film, a Ni film, and an Au film are stacked in that order from the bottom up.

[0047] The gate electrode 13 covers the gate contact hole 12 and the periphery of the gate contact hole 12 on the surface of the insulating film 7. A part of the gate electrode 13 enters the gate contact hole 12 and is in contact with the surface of the second nitride semiconductor layer 6 within the gate contact hole 12.

[0048] Gate electrode 13 is made of, for example, a Ni / Au laminated film in which a Ni film and an Au film are laminated in that order from the bottom up. The thickness of the lower Ni film is, for example, about 10 nm, and the thickness of the upper Au film is, for example, about 600 nm. Gate electrode 13 may be made of any material that can form a Schottky barrier with respect to second nitride semiconductor layer 6 (AlGaN layer).

[0049] The heat dissipation structure 15 will now be described. In this embodiment, a plurality of trenches 14 are formed in the substrate 2 in the inactive region 102, digging from the second main surface 2b toward the first main surface 2a. In this embodiment, the trenches 14 are dug from the second main surface 2b toward the first main surface 2a to partway through the thickness of the substrate 2. In this embodiment, the cross-sectional shape of the trenches 14 is elliptical. The plurality of trenches 14 are arranged in a lattice pattern in plan view. In this embodiment, the plurality of trenches 14 are arranged in a matrix pattern in plan view. The plurality of trenches 14 may also be arranged in a staggered pattern in plan view.

[0050] The cross-sectional shape of the trench 14 is arbitrary and may be circular or polygonal (triangular, rectangular, hexagonal, etc.). The size of the cross-section of the trench 14 (cross-sectional area) and the distance between two adjacent trenches 14 can be set arbitrarily. The depth of the trench 14 is preferably at least half the thickness of the substrate 2, more preferably at least two-thirds the thickness of the substrate 2, and even more preferably at least three-quarters the thickness of the substrate 2. The sum of the volumes (total volume) of the multiple trenches 14 present in the inactive region 102 is preferably at least one-third the volume of the substrate 2 within the inactive region 102.

[0051] A barrier metal film 16 is formed on the entire inner surface (side surface and bottom surface) of each trench 14 and on the entire second main surface 2b of the substrate 2. The barrier metal film 16 is made of, for example, TiN.

[0052] Furthermore, a heat dissipation metal 17 is buried in each trench 14 and surrounded by a barrier metal film 16. The heat dissipation metal 17 is made of a metal with high thermal conductivity, such as gold (Au) or copper (Cu). In this embodiment, the heat dissipation metal 17 is made of gold (Au). The heat dissipation metal 17 includes a buried portion 17A in the trench 14 and an extension portion 17B that is extended from the opening end of the trench 14 along the second main surface 2b of the substrate 2 outside the trench 14. The extension portion 17B is uniformly extended from each trench 14 and covers the entire second main surface 2b of the substrate 2. The back surface of the heat dissipation metal 17 (the back surface of the extension portion 22B) is formed flat over its entire surface.

[0053] The buried metal 15A in the present disclosure is composed of the barrier metal film 16 in the trench 14 and the buried portion 17A surrounded by the barrier metal film 16. The barrier metal film 16 formed on the second main surface 2b of the substrate 2 and the lead-out portion 17B constitute the lead-out metal 15B in the present disclosure. The buried metal 15A in all the trenches 14 and the lead-out metal 15B constitute the heat dissipation structure 15. In other words, the heat dissipation structure 15 is composed of the barrier metal film 16 and the heat dissipation metal 17.

[0054] The heat dissipation metal 17 does not have to be completely embedded in the trench 14. In that case, the back surface of the heat dissipation metal 17 does not have to be flat. Furthermore, the barrier metal film 16 and the heat dissipation metal 17 do not have to be formed on the second main surface 2b of the substrate 2.

[0055] In this nitride semiconductor device 1, a heterojunction is formed by forming a second nitride semiconductor layer 6 (electron supply layer) having a different band gap (Al composition) on a first nitride semiconductor layer 5 (electron transit layer). As a result, a two-dimensional electron gas 19 is formed in the first nitride semiconductor layer 5 near the interface between the first nitride semiconductor layer 5 and the second nitride semiconductor layer 6, and a HEMT is formed using this two-dimensional electron gas 19 as a channel.

[0056] When no control voltage is applied to the gate electrode 13, the two-dimensional electron gas 19 serves as a channel to connect the source electrode 10 and the drain electrode 11. Therefore, this HEMT is a normally-on type. When a control voltage is applied to the gate electrode 13 such that the potential of the gate electrode 13 becomes negative with respect to the source electrode 10, the two-dimensional electron gas 19 is cut off and the HEMT enters an off state.

[0057] In this embodiment, the embedded metal 15A is provided, which can improve the heat dissipation performance. Also, in this embodiment, the lead-out metal 15B is provided, which can further improve the heat dissipation performance.

[0058] 4A to 4I are cross-sectional views illustrating an example of a manufacturing process for the nitride semiconductor device 1 described above, showing cross-sectional structures at a number of stages in the manufacturing process.

[0059] 4A , a buffer layer 3 and a semi-insulating nitride layer 4 are epitaxially grown in this order on the first main surface 2a of the substrate 2, for example, by MOCVD (Metal Organic Chemical Vapor Deposition). Furthermore, a first nitride semiconductor layer (electron transit layer) 5 and a second nitride semiconductor layer (electron supply layer) 6 are epitaxially grown in this order on the semi-insulating nitride layer 4, also by MOCVD. Thus, a nitride epitaxial layer 20 consisting of the buffer layer 3, the semi-insulating nitride layer 4, the first nitride semiconductor layer 5, and the second nitride semiconductor layer 6 is formed on the first main surface 2a of the substrate 2.

[0060] Next, a resist film (not shown) is formed on the second nitride semiconductor layer 6, covering a region directly above a planned formation region of the central portion 5A of the surface of the first nitride semiconductor layer 5. By dry etching using this resist film as a mask, the peripheral portion of the second nitride semiconductor layer 6 is removed, and the peripheral portion of the first nitride semiconductor layer 5 is removed partway through its thickness, as shown in FIG. 4B. As a result, the surface of the first nitride semiconductor layer 5 is composed of a central portion 5A of the high step portion, a peripheral portion 5B of the low step portion, and a connecting portion 5C connecting them. As the etching gas, for example, a chlorine-based gas such as Cl2 or BCl3 is used.

[0061] This forms an inactive region 102 in which no two-dimensional electron gas 19 is generated. The region corresponding to central portion 5A of the surface of first nitride semiconductor layer 5 in plan view is active region 101, and the region corresponding to peripheral portion 5B of the surface of first nitride semiconductor layer 5 in plan view is inactive region 102.

[0062] This etching may be performed until the bottom of the etching reaches the top surface of the semi-insulating nitride layer 4, or until it reaches partway through the thickness of the semi-insulating nitride layer 4. This etching may be performed until the bottom of the etching reaches the top surface of the buffer layer 3, or until it reaches partway through the thickness of the buffer layer 3.

[0063] Next, as shown in FIG. 4C, an insulating material film 31, which is a material film of the insulating film 7, is formed by a plasma CVD method, an LPCVD (Low Pressure CVD) method, an MOCVD method, a sputtering method, or the like, so as to cover the peripheral portion 5B and the connecting portion 5C on the surface of the first nitride semiconductor layer 5 and the exposed surface of the second nitride semiconductor layer 6.

[0064] Next, a resist film (not shown) is formed on the insulating material film 31 in areas other than areas where the source contact holes 8 and the drain contact holes 9 are to be formed. The insulating material film 31 is, for example, dry-etched through this resist film, thereby forming the source contact holes 8 and the drain contact holes 9 in the insulating material film 31, as shown in FIG. 4D.

[0065] The source contact hole 8 and the drain contact hole 9 penetrate the insulating material film 31 and reach the second nitride semiconductor layer 6. The width of the source contact hole 8 and the drain contact hole 9 is about 3 to 5 μm. CF4 gas, for example, is used as the etching gas. Thereafter, the resist film is removed.

[0066] Next, an electrode film, which is a material film for the source electrode 10 and the drain electrode 11, is formed on the insulating material film 31 by, for example, vapor deposition, sputtering, or the like. After this, a resist film is formed to cover the areas on the surface of the electrode film where the source electrode and the drain electrode are to be formed. Then, using this resist film as a mask, the electrode film is selectively etched to obtain the source electrode 10 and the drain electrode 11, as shown in FIG. 4E. After this, the resist film is removed.

[0067] Next, as shown in FIG. 4F, a plurality of trenches 14 extending from the second main surface 2b toward the first main surface 2a to partway through the thickness of the substrate 2 are formed in the substrate 2 by photolithography and etching in the inactive region 102. The Bosch process may be used for this etching. In this embodiment, the plurality of trenches 14 are arranged in a matrix in a plan view.

[0068] Next, as shown in FIG. 4G, a barrier metal film 16 made of, for example, a TiN layer is formed on the inner surface (side surface and bottom surface) of the trench 14 and on the second main surface 2b of the substrate 2 by, for example, sputtering.

[0069] Next, as shown in FIG. 4H, a film of, for example, gold (Au) is formed on the barrier metal film 16 by, for example, plating. As a result, gold (Au), which is the material of the heat dissipation metal 17, is embedded in the trenches 14. As a result, the heat dissipation metal 17 consisting of the embedded portion 17A and the leading portion 17B is formed. As a result, the heat dissipation structure 15 consisting of the barrier metal film 16 and the heat dissipation metal 17 is formed. In other words, the heat dissipation structure 15 is formed, consisting of the embedded metal 15A embedded in each trench 14 and the leading metal 15B formed on the second main surface 2b.

[0070] Next, a resist film (not shown) is formed on the insulating material film 31, the source electrode 10, and the drain electrode 11 in areas excluding areas where the gate contact holes 12 are to be formed. The insulating material film 31 is etched through this resist film, thereby forming the gate contact holes 12 in the insulating material film 31, as shown in FIG. 4I. This results in patterning the insulating material film 31, and the insulating film 7 is obtained. The gate contact holes 12 penetrate the insulating film 7 and reach the second nitride semiconductor layer 6. As the etching gas, for example, CF4 gas is used.

[0071] Next, after the resist film is removed, the gate electrode 13 is formed, thereby obtaining the nitride semiconductor device 1 as shown in Figures 1 to 3. The gate electrode 13 is made of, for example, a Ni / Au laminated film in which a Ni film and an Au film are laminated in that order from the bottom up.

[0072] Fig. 5 is a plan view illustrating the configuration of a nitride semiconductor device according to a second embodiment of the present disclosure. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 2. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 6.

[0073] 5, 6 and 7, parts corresponding to those in the above-described FIGS. 1, 2 and 3 are denoted by the same reference numerals as in FIGS.

[0074] The nitride semiconductor device 1A according to the second embodiment differs from the nitride semiconductor device 1A according to the first embodiment in that trenches 14 are formed in the substrate 2 not only in the inactive region 102 but also in the active region 101.

[0075] A plurality of trenches 14 are formed in the active region 101 and the inactive region 102. The plurality of trenches 14 are arranged in a matrix in plan view. The plurality of trenches 14 may also be arranged in a staggered pattern in plan view. A barrier metal film 16 is formed on the inner surface of the plurality of trenches 14. A heat dissipation metal 17 is buried in these trenches 14 while being surrounded by the barrier metal film 16.

[0076] The buried metal 15A in the present disclosure is formed by the barrier metal film 16 in the trench 14 and the buried portion 17A surrounded by the barrier metal film 16. The barrier metal film 16 formed on the second main surface 2b of the substrate 2 and the lead-out portion 17B are formed by the lead-out metal 15B in the present disclosure. The buried metal 15A in all the trenches 14 and the lead-out metal 15B form the heat dissipation structure 15. In other words, the heat dissipation structure 15 is formed by the barrier metal film 51 and the heat dissipation metal 17 formed in the active region 101 and the inactive region 102.

[0077] In the second embodiment, the embedded metal 15A is also provided, thereby improving heat dissipation. Furthermore, the extension metal 15B is provided, thereby further improving heat dissipation. In the second embodiment, a plurality of trenches 14 are formed not only in the inactive region 102 but also in the active region 101, and the heat dissipation metal 17 is embedded in these trenches 14 via the barrier metal film 16, thereby improving heat dissipation compared to the first embodiment.

[0078] 8A to 8D are cross-sectional views for explaining an example of a manufacturing process for the nitride semiconductor device 1A described above, showing cross-sectional structures at a plurality of stages in the manufacturing process.

[0079] When manufacturing the nitride semiconductor device 1A shown in FIGS. 5 to 7, the steps shown in FIGS. 4A to 4E are carried out, similarly to when manufacturing the nitride semiconductor device 1 shown in FIGS.

[0080] 4E is completed, as shown in FIG. 8A, a plurality of trenches 14 extending from the second main surface 2b toward the first main surface 2a to partway through the thickness of the substrate 2 are formed in the substrate 2 by photolithography and etching in both the active region 101 and the inactive region 102. The etching may be performed using the Bosch process. In this embodiment, the plurality of trenches 14 are arranged in a matrix in a plan view.

[0081] Next, as shown in FIG. 8B, a barrier metal film 16 made of, for example, a TiN layer is formed on the inner surfaces (side surfaces and bottom surfaces) of trenches 14 and on second main surface 2b of substrate 2 by, for example, sputtering.

[0082] 8C, a film of, for example, gold (Au) is formed on the barrier metal film 16 by, for example, plating. As a result, gold (Au), which is the material of the heat dissipation metal 17, is embedded in the trenches 14. As a result, the heat dissipation metal 17 consisting of the embedded portion 17A and the leading portion 17B is formed. As a result, the heat dissipation structure 15 consisting of the barrier metal film 16 and the heat dissipation metal 17 is obtained. In other words, the heat dissipation structure 15 consisting of the embedded metal 15A embedded in each trench 14 and the leading metal 15B formed on the second main surface 2b is obtained.

[0083] Next, a resist film (not shown) is formed on the insulating material film 31, the source electrode 10, and the drain electrode 11 in areas excluding areas where the gate contact holes 12 are to be formed. The insulating material film 31 is dry-etched through this resist film, thereby forming the gate contact holes 12 in the insulating material film 31, as shown in FIG. 8D. This results in patterning the insulating material film 31, and the insulating film 7 is obtained. The gate contact holes 12 penetrate the insulating film 7 and reach the second nitride semiconductor layer 6. As the etching gas, for example, CF4 gas is used.

[0084] Next, after the resist film is removed, the gate electrode 13 is formed, thereby obtaining the nitride semiconductor device 1A as shown in Figures 5 to 7. The gate electrode 13 is made of, for example, a Ni / Au laminated film in which a Ni film and an Au film are laminated in that order from the bottom up.

[0085] Fig. 9 is a plan view illustrating the configuration of a nitride semiconductor device according to a third embodiment of the present disclosure. Fig. 10 is a cross-sectional view taken along line XX in Fig. 9. Fig. 11 is a cross-sectional view taken along line XI-XI in Fig. 10.

[0086] 9, 10 and 11, parts corresponding to those in the above-described FIGS. 1, 2 and 3 are denoted by the same reference numerals as in FIGS.

[0087] In the following description, the left-right direction on the plane of FIG. 9 may be referred to as the horizontal direction, and the up-down direction on the plane of FIG. 9 may be referred to as the vertical direction.

[0088] The nitride semiconductor device 1B of the third embodiment differs from the nitride semiconductor device 1 of the first embodiment in the configuration of the source electrode 10 and the drain electrode 11, and in that trenches 14 are formed in the substrate 2 not only in the inactive region 102 but also in the active region 101.

[0089] In the substrate 2, the nitride epitaxial layer 20 and the insulating film 7, a back contact hole 18 is formed on the opposite side of the source contact hole 8 from the gate contact hole 12, continuously penetrating the insulating film 7 and the nitride epitaxial layer 20 from the surface of the insulating film 7 and extending partway through the thickness of the substrate 2.

[0090] The source electrode 10 includes a main electrode portion 10A and an extension portion 10B. The main electrode portion 10A covers the source contact hole 8 and the peripheral portion of the source contact hole 8 on the surface of the insulating film 7. A portion of the main electrode portion 10A enters the source contact hole 8 and is in contact with the surface of the second nitride semiconductor layer 6 within the source contact hole 8.

[0091] The extension 10B covers the back contact hole 18 and the peripheral portion of the back contact hole 18 on the surface of the insulating film 7. The side edge of the extension 10B on the main electrode portion 10A side is connected to the side edge of the main electrode portion 10A on the extension 10B side. A portion of the extension 10B enters the back contact hole 18 and contacts the substrate 2 inside the back contact hole 18. The extension 10B is an example of a "conductive member that electrically connects the source electrode and the buried metal" in the present disclosure.

[0092] The source electrode 10 is made of a barrier metal film 41 and an electrode metal 42 formed on the barrier metal film 41. The barrier metal film 41 covers the inner surface (side surface and bottom surface) of the source contact hole 8, the peripheral portion of the source contact hole 8 on the surface of the insulating film 7, the inner surface of the back contact hole 18, and the peripheral portion of the back contact hole 18 on the surface of the insulating film 7. The barrier metal film 41 is made of, for example, a TiN film. The electrode metal 42 is made of, for example, Au. The electrode metal 42 may be made of Cu.

[0093] The drain electrode 11 covers the drain contact hole 9 and the peripheral portion of the drain contact hole 9 on the surface of the insulating film 7. A portion of the drain electrode 11 enters the drain contact hole 9 and is in contact with the surface of the second nitride semiconductor layer 6 within the drain contact hole 9.

[0094] The drain electrode 11 is made of a barrier metal film 43 that covers the drain contact hole 9 and the peripheral portion of the drain contact hole 9 on the surface of the insulating film 7, and an electrode metal 44 formed on the barrier metal film 43. The barrier metal film 41 is made of, for example, a TiN film. The electrode metal 44 is made of, for example, Au. The electrode metal 44 may also be made of Cu.

[0095] A plurality of trenches 14 are formed in the substrate 2 in the active region 101 and the inactive region 102. The plurality of trenches 14 includes a contact trench 14A that reaches the barrier metal film 41 formed on the bottom surface of the back contact hole 18. The plurality of trenches 14, excluding the contact trench 14A, are arranged in a matrix in plan view. The plurality of trenches 14 may also be arranged in a staggered pattern in plan view.

[0096] A barrier metal film 16 is formed on the inner surfaces of the plurality of trenches 14 including the contact trench 14A. A heat dissipation metal 17 is buried in these trenches 14 while being surrounded by the barrier metal film 16.

[0097] The heat dissipation metal 17 is made of a metal with high thermal conductivity and electrical conductivity, such as gold (Au) or copper (Cu). In this embodiment, the heat dissipation metal 17 is made of gold (Au). The heat dissipation metal 17 includes a buried portion 17A within the trench 14 and an extension portion 17B that is extended from the opening end of the trench 14 along the second main surface 2b of the substrate 2 outside the trench 14. The extension portion 17B is extended uniformly from each trench 14 and covers the entire second main surface 2b of the substrate 2. The back surface of the heat dissipation metal 17 (the back surface of the extension portion 22B) is formed flat all over.

[0098] The buried metal 15A in the present disclosure is constituted by the barrier metal film 16 in the trenches 14 (including the contact trenches 14A) and the buried portion 17A surrounded by the barrier metal film 16. The barrier metal film 16 formed on the second main surface 2b of the substrate 2 and the lead-out portion 17B constitute the lead-out metal 15B in the present disclosure. The buried metal 15A in all the trenches 14 and the lead-out metal 15B constitute the heat dissipation structure 15. In other words, the heat dissipation structure 15 is constituted by the barrier metal film 16 and the heat dissipation metal 17 formed in the active region 101 and the inactive region 102.

[0099] In the third embodiment, the embedded metal 15A is also provided, thereby improving heat dissipation. Furthermore, the extension metal 15B is provided, thereby further improving heat dissipation. In the third embodiment, a plurality of trenches 14 are formed not only in the inactive region 102 but also in the active region 101, and the heat dissipation metal 17 is embedded in these trenches 14 via the barrier metal film 16, thereby further improving heat dissipation compared to the first embodiment.

[0100] In the third embodiment, the main electrode portion 10A of the source electrode 10 is electrically connected to the lead metal 15B via the extension portion 10B and the buried metal 15A in the contact trench 14A. Therefore, the lead metal 15B can be used as a back electrode of the source electrode 10.

[0101] 12A to 12H are cross-sectional views illustrating an example of a manufacturing process for the nitride semiconductor device 1B described above, showing cross-sectional structures at a plurality of stages in the manufacturing process.

[0102] When manufacturing the nitride semiconductor device 1B shown in FIGS. 9 to 11, the steps shown in FIGS. 4A to 4C are carried out in the same manner as when manufacturing the nitride semiconductor device 1 shown in FIGS.

[0103] 4C is completed, a resist film (not shown) is formed in areas excluding areas where the back contact hole 18, the source contact hole 8, and the drain contact hole 9 are to be formed. The insulating material film 31 is dry-etched through this resist film, thereby forming a portion 18A of the back contact hole 18, the source contact hole 8, and the drain contact hole 9 in the insulating material film 31, as shown in FIG.

[0104] Portion 18A of back contact hole 18, source contact hole 8, and drain contact hole 9 penetrate insulating material film 31 and reach second nitride semiconductor layer 6. Portion 18A of back contact hole 18, source contact hole 8, and drain contact hole 9 have widths of approximately 3 to 5 μm. CF4 gas, for example, is used as the etching gas. Thereafter, the resist film is removed.

[0105] Next, a resist film (not shown) is formed on the insulating material film 31 in an area excluding an area where the back contact hole 18 is to be formed. The nitride epitaxial layer 20 and a portion of the substrate 2 are etched through this resist film. As a result, as shown in FIG. 12B, a hole 18B is formed that penetrates the nitride epitaxial layer 20 and reaches the inside of the substrate 2, i.e., the remaining portion 18B of the back contact hole 18. This results in the back contact hole 18 consisting of the portion 18A and the remaining portion 18B. The resist film is then removed.

[0106] Next, by, for example, sputtering, a barrier metal material film (for example, a TiN film) that is a material film for the barrier metal films 41 and 43 is formed on the surface of the insulating material film 31, the inner surfaces (side surfaces and bottom surfaces) of the back contact hole 18, the inner surfaces of the source contact hole 8, and the inner surfaces of the drain contact hole 9. Then, the barrier metal material film is patterned to form the barrier metal films 41 and 43, as shown in FIG.

[0107] 12D, an electrode metal 42 made of, for example, Au is formed on the barrier metal film 41, for example, by plating, and an electrode metal 44 made of, for example, Au is formed on the barrier metal film 43. This results in a source electrode 10 made of the barrier metal film 41 and the electrode metal 42, and a drain electrode 11 made of the barrier metal film 43 and the electrode metal 45. The source electrode 10 includes a main electrode portion 10A and an extension portion 10B.

[0108] 12E, photolithography and etching are used to form a plurality of trenches 14 in the substrate 2, extending from the second main surface 2b toward the first main surface 2a to partway through the thickness of the substrate 2 in both the active region 101 and the inactive region 102. The plurality of trenches 14 includes a contact trench 14A extending from the second main surface 2b of the substrate 2 to the underside of the barrier metal film 41 formed on the bottom surface of the back contact hole 18. A Bosch process may be used for etching. In this embodiment, the plurality of trenches 14, excluding the contact trench 14A, are arranged in a matrix in a plan view.

[0109] Next, as shown in FIG. 12F, a barrier metal film 16 made of, for example, a TiN layer is formed on the inner surface (side surface and bottom surface) of trench 14 and on second main surface 2b of substrate 2 by, for example, sputtering.

[0110] 12G, a film of, for example, gold (Au) is formed on the barrier metal film 16 by, for example, plating. As a result, gold (Au), which is the material of the heat dissipation metal 17, is buried in the trench 14. As a result, the heat dissipation metal 17 consisting of the buried portion 17A and the lead portion 17B is formed. As a result, the heat dissipation structure 15 consisting of the barrier metal film 16 and the heat dissipation metal 17 is obtained.

[0111] In other words, a heat dissipation structure 15 is obtained that is made up of buried metal 15A buried in each trench 14 and lead metal 15B formed on the second main surface 2b. The source electrode 10 is electrically connected to the lead metal 15B via the extension 10B and the buried metal 15A in the contact trench 14A.

[0112] Next, a resist film (not shown) is formed on the insulating material film 31, the source electrode 10, and the drain electrode 11 in areas excluding areas where the gate contact holes 12 are to be formed. The insulating material film 31 is dry-etched through this resist film, thereby forming the gate contact holes 12 in the insulating material film 31, as shown in FIG. 12H. This results in patterning the insulating material film 31, and the insulating film 7 is obtained. The gate contact holes 12 penetrate the insulating film 7 and reach the second nitride semiconductor layer 6. As the etching gas, for example, CF4 gas is used.

[0113] Next, after the resist film is removed, the gate electrode 13 is formed, thereby obtaining the nitride semiconductor device 1B as shown in Figures 9 to 11. The gate electrode 13 is made of, for example, a Ni / Au laminated film in which a Ni film and an Au film are laminated in that order from the bottom up.

[0114] Figures 13, 14 and 15 are cross-sectional views showing modifications of the first, second and third embodiments, respectively, and are cross-sectional views corresponding to the cut surfaces of Figures 2, 6 and 10. In Figures 13, 14 and 15, parts corresponding to parts in Figures 2, 6 and 10, respectively, are denoted by the same reference numerals as in Figures 2, 6 and 10.

[0115] In the first, second, and third embodiments described above, the trench 14 extends from the second main surface 2b toward the first main surface 2a to partway through the thickness of the substrate 2. However, as shown in Figures 13, 14, and 15, the trench 14 may be formed so as to penetrate the substrate 2 from the second main surface 2b toward the first main surface 2a and reach the buffer layer 3 (nitride epitaxial layer 20).

[0116] Furthermore, in the first to third embodiments described above, the semi-insulating nitride layer 4 is formed on the buffer layer 3, but the semi-insulating nitride layer 4 does not necessarily have to be formed.

[0117] Furthermore, in the first to third embodiments described above, examples have been described in which the first nitride semiconductor layer (electron transit layer) 5 is made of a GaN layer and the second nitride semiconductor layer (electron supply layer) 6 is made of an AlGaN layer, but other combinations are also possible as long as the first nitride semiconductor layer 5 and the second nitride semiconductor layer 6 have different bandgaps (e.g., Al composition). For example, examples of combinations of the first nitride semiconductor layer 5 / second nitride semiconductor layer 6 include GaN / AlN and AlGaN / AlN.

[0118] Although the embodiments of the present disclosure have been described in detail, these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be construed as being limited to these specific examples. The scope of the present disclosure is limited only by the appended claims, and various design modifications can be made within the scope of the matters described in the claims.

[0119] This application corresponds to Patent Application No. 2021-053735 filed with the Japan Patent Office on March 26, 2021, the entire disclosures of which are incorporated herein by reference. [Explanation of symbols]

[0120] 1,1A,1B Nitride semiconductor devices 2 boards 3. Buffer layer 4. Semi-insulating nitride layer 5. First nitride semiconductor layer 6. Second nitride semiconductor layer 7. Insulating film 8 Source Contact Hole 9 Drain contact hole 10 Source Power 10A main electrode section 10B Extension 11 Drain electrode 12 Gate contact hole 13 Gate electrode 14 Trench 14A Contact Trench 15 Heat dissipation structure 15A embedded metal 15B Drawer Metal 16 Barrier metal film 17 Heat dissipation metal 17A Embedded part 17B Drawer section 18 Back Contact Hole 19 Two-dimensional electron gas 20 Nitride epitaxial layer 31 Insulating material film 41,43 Barrier metal film 42,44 Electrode metal

Claims

1. A nitride semiconductor device including a substrate having a first main surface and a second main surface opposite to the first main surface, and a nitride epitaxial layer formed on the first main surface, the nitride semiconductor device has, in a plan view, an active region in which a two-dimensional electron gas can be formed within the nitride epitaxial layer, and an inactive region in which a two-dimensional electron gas is not formed within the nitride epitaxial layer; a trench extending from the second main surface of the substrate toward the first main surface of the substrate in at least the inactive region of the active region and the inactive region; a buried metal formed in the trench; The nitride semiconductor device, wherein the trench is formed only in the inactive region out of the active region and the inactive region.

2. A nitride semiconductor device including a substrate having a first main surface and a second main surface opposite the first main surface, and a nitride epitaxial layer formed on the first main surface, the nitride semiconductor device has, in a plan view, an active region in which a two-dimensional electron gas can be formed within the nitride epitaxial layer, and an inactive region in which a two-dimensional electron gas is not formed within the nitride epitaxial layer; a trench extending from the second main surface of the substrate toward the first main surface of the substrate in at least the inactive region of the active region and the inactive region; a buried metal formed in the trench; A nitride semiconductor device, wherein a total volume of the trenches present in the inactive region is equal to or greater than one-third of a volume of the substrate in the inactive region.

3. The nitride semiconductor device according to claim 2 , wherein said trench is formed only in said inactive region out of said active region and said inactive region.

4. The nitride semiconductor device according to claim 2 , wherein said trenches are formed in both said active region and said inactive region.

5. 5. The nitride semiconductor device according to claim 1, further comprising an extraction metal formed on said second main surface and thermally connected to said buried metal.

6. 6. The nitride semiconductor device according to claim 1, wherein said trench is dug from said second main surface toward said first main surface to a point partway through said substrate.

7. 6. The nitride semiconductor device according to claim 1, wherein the trench penetrates through the substrate and reaches the nitride epitaxial layer.

8. a source electrode, a drain electrode, and a gate electrode disposed on the nitride epitaxial layer; 8. The nitride semiconductor device according to claim 1, further comprising a contact metal that penetrates said nitride epitaxial layer and electrically connects said source electrode and said buried metal.

9. The nitride epitaxial layer is a first nitride semiconductor layer constituting an electron transit layer; 9. The nitride semiconductor device according to claim 1, further comprising: a second nitride semiconductor layer formed on the first nitride semiconductor layer, constituting an electron supply layer, and having a band gap higher than that of the first nitride semiconductor layer.

10. The nitride semiconductor device according to claim 9 , further comprising a semi-insulating nitride layer disposed between said substrate and said first nitride semiconductor layer, said semi-insulating nitride layer having an acceptor concentration higher than a donor concentration.

11. The nitride semiconductor device according to claim 10 , further comprising a buffer layer made of a nitride semiconductor, disposed between said substrate and said semi-insulating nitride layer.

12. 12. The nitride semiconductor device according to claim 9, wherein the first nitride semiconductor layer is made of a GaN layer, and the second nitride semiconductor layer is made of an AlGaN layer.

13. 11. The nitride semiconductor device according to claim 10, wherein the first nitride semiconductor layer is a GaN layer, the second nitride semiconductor layer is an AlGaN layer, and the semi-insulating nitride layer is a GaN layer containing carbon.

14. 12. The nitride semiconductor device according to claim 11, wherein the first nitride semiconductor layer is made of a GaN layer, the second nitride semiconductor layer is made of an AlGaN layer, the semi-insulating nitride layer is made of a GaN layer containing carbon, and the buffer layer is made of a stacked film of an AlN layer formed on the first main surface and an AlGaN layer stacked on the AlN layer.

15. 12. The nitride semiconductor device according to claim 11, wherein the first nitride semiconductor layer is a GaN layer, the second nitride semiconductor layer is an AlGaN layer, the semi-insulating nitride layer is a GaN layer containing carbon, and the buffer layer is an AlN layer or an AlGaN layer.

Images