Semiconductor Devices

Abstract

To provide a semiconductor device which can improve a dielectric voltage.SOLUTION: A semiconductor device A10 includes: a conductive support member 2 including a first die pad 3 and a second die pad 4; a first semiconductor element 11 mounted on the first die pad 3; a second semiconductor element 12 mounted on the second die pad 4; and a sealing resin 7. The first semiconductor element 11 includes a control part 111 constituting an input side circuit. The second semiconductor element 12 includes a high pressure driving part 121 constituting a high pressure output side circuit. The sealing resin 7 includes a first side face 73 positioned on an x1 side in an x direction, a second side face 74 positioned on an x2 side in the x direction, and a fourth side face 76 positioned on a y1 side in a y direction. The conductive support member 2 includes a plurality of input side terminals 51 that are conducted to the input side circuit and project from the first side face 73, and a plurality of high pressure output side terminals 52 that are conducted to the high pressure output side circuit and project from the second side face 74, and is not exposed from the fourth side face 76.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device that transmits signals between multiple semiconductor elements mounted in one package via an insulating portion. [Background technology]

[0002] Semiconductor devices are used in inverter devices used in electric vehicles, hybrid vehicles, home appliances, etc. The inverter device is made up of, for example, a semiconductor device and an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The inverter device includes a power semiconductor such as a semiconductor field effect transistor (ECU). The semiconductor device has a control element and a drive element. In the inverter device, a control signal output from an ECU (Engine Control Unit) is input to the control element of the semiconductor device. The control element converts the control signal into a PWM (Pulse Width Modulation) control signal and transmits it to the drive element. The drive element causes, for example, six power semiconductors to perform switching operations at desired timing based on the PWM control signal. The six power semiconductors perform switching operations at desired timing, generating three-phase AC power for driving a motor from DC power of an automotive battery. For example, Patent Document 1 discloses an example of a semiconductor device (drive circuit) used in a motor drive device.

[0003] However, the power supply voltage required for the control element may differ from the power supply voltage required for the drive element. In such a case, in a semiconductor device in which multiple semiconductor elements are mounted in a single package, there is a difference in the power supply voltage applied to the two conduction paths, the conduction path to the control element and the conduction path to the drive element, and therefore it is necessary to improve the dielectric strength voltage between these conduction paths. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-155412 Summary of the Invention [Problem to be solved by the invention]

[0005] In view of the above circumstances, an object of the present invention is to provide a semiconductor device that can improve the dielectric strength voltage. [Means for solving the problem]

[0006] A semiconductor device provided by the present disclosure comprises a conductive support member including a first die pad and a second die pad having a potential relatively different from that of the first die pad, a first semiconductor element mounted on the first die pad, a second semiconductor element mounted on the second die pad, and a sealing resin covering at least a part of the conductive support member, the first semiconductor element, and the second semiconductor element, wherein the first semiconductor element comprises a control unit which configures an input side circuit together with the first die pad, and a low-voltage drive unit which configures a low-voltage output side circuit which transmits and receives signals to and from the input side circuit, and the second ... low-voltage drive unit The element includes a high-voltage driving section that, together with the second die pad, constitutes a high-voltage output circuit that transmits and receives signals to and from the input circuit, and the conductive support member includes a plurality of input terminals that are arranged along a first direction perpendicular to the thickness direction and at least one of which is electrically connected to the input circuit, a plurality of high-voltage output terminals that are arranged along the first direction and at least one of which is electrically connected to the high-voltage output circuit, and a plurality of low-voltage output terminals that are arranged along the first direction on one side of the plurality of high-voltage output terminals in the first direction and at least one of which is electrically connected to the low-voltage output circuit. the sealing resin has a first side face located on one side of a second direction orthogonal to the thickness direction and the first direction and from which the plurality of input side terminals protrude, a second side face located on the other side of the second direction and from which the plurality of high-voltage output side terminals and the plurality of low-voltage output side terminals protrude, a third side face located on one side of the first direction and connected to the first side face and the second side face, and a fourth side face located on the other side of the first direction and connected to the first side face and the second side face, and the conductive support member is not exposed from the fourth side face. [Effects of the Invention]

[0007] According to the present disclosure, the conductive support member is not exposed from the fourth side surface of the sealing resin, which increases the insulation distance between the input terminals and the high-voltage output terminals, thereby improving the dielectric strength.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] 2 is a plan view showing the semiconductor device of FIG. 1, seen through a sealing resin. FIG. [Figure 3] FIG. 2 is a front view showing the semiconductor device of FIG. [Figure 4] FIG. 2 is a rear view showing the semiconductor device of FIG. [Figure 5] FIG. 2 is a left side view showing the semiconductor device of FIG. [Figure 6] FIG. 2 is a right side view showing the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2. [Figure 9] FIG. 2 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 2 is a cross-sectional view taken along line XX in FIG. [Figure 11] 2 is a plan view showing a process according to a method for manufacturing the semiconductor device of FIG. 1. [Figure 12] 2 is a plan view showing a process according to a method for manufacturing the semiconductor device of FIG. 1. [Figure 13] FIG. 10 is a plan view showing a semiconductor device according to a second embodiment of the present disclosure, seen through a sealing resin. [Figure 14] FIG. 10 is a plan view showing a semiconductor device according to a third embodiment of the present disclosure, seen through a sealing resin. [Figure 15] FIG. 10 is a plan view showing a semiconductor device according to a fourth embodiment of the present disclosure, seen through a sealing resin. [Figure 16] FIG. 10 is a plan view showing a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 17] FIG. 10 is a plan view showing a semiconductor device according to a sixth embodiment of the present disclosure. [Figure 18] FIG. 13 is a plan view showing a semiconductor device according to a seventh embodiment of the present disclosure, seen through a sealing resin. [Figure 19] FIG. 13 is a plan view showing a semiconductor device according to an eighth embodiment of the present disclosure, seen through a sealing resin. DETAILED DESCRIPTION OF THE INVENTION

[0010] Preferred embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0011] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, unless otherwise specified, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B." This includes "object A being placed directly on object B" and "object A being placed on object B with another object intervening between them." Similarly, "object A is located on object B," unless otherwise specified, includes "object A is in contact with object B and is located on object B" and "object A is located on object B with another object intervening between object A and object B." Furthermore, "object A overlaps object B when viewed in a certain direction," unless otherwise specified, includes "object A overlapping the entirety of object B" and "object A overlapping part of object B."

[0012] First Embodiment 1 to 10 show an example of a semiconductor device according to the present disclosure. The semiconductor device A10 of this embodiment includes a first semiconductor element 11, a second semiconductor element 12, a conductive support member 2, a plurality of wires 61, a plurality of wires 62, a plurality of wires 63, a plurality of wires 64, and a sealing resin 7. The conductive support member 2 includes a first die pad 3, a second die pad 4, a plurality of input terminals 51, a plurality of high-voltage output terminals 52, and a plurality of low-voltage output terminals 53. The semiconductor device A10 is surface-mounted on a wiring board of an inverter device of, for example, an electric vehicle or a hybrid vehicle. The use and function of the semiconductor device A10 are not limited. The package format of the semiconductor device A10 is an SOP (Small Outline Package). However, The package format of the semiconductor device A10 is not limited to SOP.

[0013] FIG. 1 is a plan view showing the semiconductor device A10. FIG. 2 is a plan view showing the semiconductor device A10. In FIG. 2, for ease of understanding, the outline of the sealing resin 7 is shown by an imaginary line (two-dot chain line) through the sealing resin 7. FIG. 3 is a front view showing the semiconductor device A10. FIG. 4 is a rear view showing the semiconductor device A10. FIG. 5 is a left side view showing the semiconductor device A10. FIG. 6 is a right side view showing the semiconductor device A10. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 2. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 1. FIG. 10 is a cross-sectional view taken along line XX in FIG. 1.

[0014] The semiconductor device A10 has a rectangular shape when viewed in the thickness direction (plan view). For ease of explanation, the thickness direction (plan view) of the semiconductor device A10 is referred to as the z direction, the direction along one side of the semiconductor device A10 perpendicular to the z direction (the left-right direction in FIGS. 1 and 2) is referred to as the x direction, and the direction perpendicular to the z direction and the x direction (the up-down direction in FIGS. 1 and 2) is referred to as the y direction. One side in the z direction (the upper side in FIGS. 3 to 8) is referred to as the z1 side, and the other side (the lower side in FIGS. 3 to 8) is referred to as the z2 side. One side in the x direction (the left side in FIGS. 1 and 2) is referred to as the x1 side, and the other side (the right side in FIGS. 1 and 2) is referred to as the x2 side. One side in the y direction (the upper side in FIGS. 1 and 2) is referred to as the y1 side, and the other side (the lower side in FIGS. 1 and 2) is referred to as the y2 side. The z direction corresponds to the "thickness direction" in this disclosure, the y direction corresponds to the "first direction" in this disclosure, and the x direction corresponds to the "second direction" in this disclosure. Note that the shape and dimensions of the semiconductor device A10 are not limited.

[0015] The first semiconductor element 11 and the second semiconductor element 12 are elements that are the core of the function of the semiconductor device A10.

[0016] 2, the first semiconductor element 11 is mounted on a part of the conductive support member 2 (first die pad 3 described below) and is disposed at the center in the y direction of the semiconductor device A10, closer to x1 than the center in the x direction. When viewed in the z direction, the first semiconductor element 11 has a rectangular shape that is long in the y direction. The first semiconductor element 11 has a substrate (not shown) made of Si, and a control unit 111 and a low-voltage drive unit 112 are formed on the substrate, as shown in FIG.

[0017] The control unit 111 has a circuit that converts a control signal input from an ECU or the like into a PWM control signal, and a transmission circuit that transmits the PWM control signal to the second semiconductor element 12 and the low-voltage drive unit 112. In this embodiment, the control unit 111 receives a high-side control signal and a low-side control signal, transmits the high-side PWM control signal to the second semiconductor element 12, and transmits the low-side PWM control signal to the low-voltage drive unit 112.

[0018] The low-voltage driving unit 112 is disposed closer to the x2 side in the x direction and closer to the y2 side in the y direction of the first semiconductor element 11, and is electrically connected to the control unit 111 inside the first semiconductor element 11. The low-voltage driving unit 112 has a circuit (gate driver) that receives a PWM control signal from the control unit 111 and performs a switching operation of a switching element (such as an IGBT or MOSFET) based on the received PWM control signal. The low-voltage driving unit 112 drives the low-side switching element.

[0019] 2, second semiconductor element 12 is mounted on a part of conductive support member 2 (second die pad 4 described below) and is disposed on the x2 side in the x direction with respect to first semiconductor element 11. When viewed in the z direction, second semiconductor element 12 has a rectangular shape that is long in the y direction. Second semiconductor element 12 has a substrate (not shown) made of Si, and as shown in FIG. 2, a high-voltage driver 121 and an insulating part 122 are formed on the substrate.

[0020] High voltage driver 121 receives a PWM control signal from control unit 111 via insulating unit 122, and has a circuit (gate driver) that performs a switching operation of a switching element (such as an IGBT or a MOSFET) based on the received PWM control signal. High voltage driver 121 drives a high-side switching element.

[0021] Insulator 122 is disposed closer to the x1 side of second semiconductor element 12 in the x direction and closer to the y2 side of second semiconductor element 12 in the y direction, and is electrically connected to high-voltage driver 121 inside second semiconductor element 12. Insulator 122 is a part for transmitting PWM control signals in an insulated state. Insulator 122 receives PWM control signals from control unit 111 of first semiconductor element 11 via wire 64 (described later), and transmits the received PWM control signals to high-voltage driver 121 in an insulated state. In other words, insulator 122 relays signal transmission and reception between control unit 111 of first semiconductor element 11 and high-voltage driver 121 of second semiconductor element 12, and also insulates control unit 111 of first semiconductor element 11 from high-voltage driver 121 of second semiconductor element 12 from each other. Insulator 122 is, for example, an inductive type. In this embodiment, the insulating section 122 is an insulating transformer that transmits electrical signals in an insulated state by inductively coupling a plurality of inductors (coils) made of, for example, Cu, formed on a substrate. The plurality of inductors include a transmitting inductor and a receiving inductor, and these inductors are stacked on top of each other in the thickness direction (z direction) of the second semiconductor element 12. Between the transmitting inductor and the receiving inductor, a layer made of SiO2 or the like is provided. A dielectric layer is interposed between the insulating section 122 and the receiving inductor. The transmitting inductor and the receiving inductor are electrically insulated by the dielectric layer. In this embodiment, the insulating section 122 is of an inductive type, but the insulating section 122 may also be of a capacitive type. An example of a capacitive insulating element is a capacitor.

[0022] The second semiconductor element 12 receives the PWM control signal transmitted from the first semiconductor element 11 via the insulating portion 122. The first semiconductor element 11 may transmit signals other than the PWM control signal to the second semiconductor element 12. The second semiconductor element 12 may also transmit signals such as a detection signal to the first semiconductor element 11.

[0023] In inverter devices for hybrid vehicles, etc., motor driver circuits generally use half-bridge circuits in which low-side switching elements and high-side switching elements are connected in a totem pole configuration. Only one of the low-side switching elements or the high-side switching elements functions as a switch. In the high-voltage region, the source of the low-side switching element and the reference potential of the isolated gate driver that drives the switching element are connected to ground, so the gate-source voltage operates with respect to ground. On the other hand, the source of the high-side switching element and the reference potential of the isolated gate driver that drives the switching element are connected to the output node of the half-bridge circuit. Depending on whether the low-side switching element or the high-side switching element is on, the potential of the output node of the half-bridge circuit changes, so the reference potential of the isolated gate driver that drives the high-side switching element also changes. When the high-side switching element is on, the reference potential becomes a voltage equivalent to the voltage applied to the drain of the high-side switching element (e.g., 600 V or higher). In the semiconductor device A10, the high-voltage driver 121 of the second semiconductor element 12 is used as an isolated gate driver that drives the high-side switching element. Because the high-voltage driving unit 121 of the second semiconductor element 12 and the control unit 111 of the first semiconductor element 11 are grounded separately to ensure insulation, a voltage of 600 V or more is transiently applied to the high-voltage driving unit 121 compared to the ground of the control unit 111. Because a significant potential difference occurs between the control unit 111 of the first semiconductor element 11 and the high-voltage driving unit 121 of the second semiconductor element 12, in the semiconductor device A10, the input side circuit including the control unit 111 of the first semiconductor element 11 and the high-voltage output side circuit including the high-voltage driving unit 121 of the second semiconductor element 12 are insulated by the insulating unit 122 of the second semiconductor element 12. In other words, the insulating unit 122 of the second semiconductor element 12 insulates the input side circuit, which has a relatively low potential, from the high-voltage output side circuit, which has a relatively high potential. In this embodiment, since the potential difference between the control unit 111 of the first semiconductor element 11 and the low-voltage driving unit 112 is small, there is no insulation between the input side circuit and the low-voltage output side circuit including the low-voltage driving unit 112 of the first semiconductor element 11.

[0024] A plurality of electrodes (not shown) are provided on the top surface (surface facing the z1 side) of the first semiconductor element 11. A back surface electrode (not shown) is provided on the bottom surface (surface facing the z2 side) of the first semiconductor element 11. These electrodes are electrically connected to the circuit configured in the first semiconductor element 11. Similarly, a plurality of electrodes (not shown) are provided on the top surface (surface facing the z1 side) of the second semiconductor element 12. A back surface electrode (not shown) is provided on the bottom surface (surface facing the z2 side) of the second semiconductor element 12. These electrodes are electrically connected to the circuit configured in the second semiconductor element 12.

[0025] In the semiconductor device A10, the conductive support member 2 is a member that forms a conductive path between the first semiconductor element 11 and the second semiconductor element 12 and the wiring board of the inverter device. The conductive support member 2 is made of an alloy containing Cu, for example. The conductive support member 2 is formed from a lead frame 81, which will be described later. The first semiconductor element 11 and the second semiconductor element 12 are mounted on the conductive support member 2. As shown in FIG. 2 , the conductive support member 2 includes a first die pad 3, a second die pad 4, a plurality of input side terminals 51, a high-voltage output side terminal 52, and a plurality of low-voltage output side terminals 53.

[0026] The first die pad 3 is disposed at the center in the y direction of the semiconductor device A10, closer to x1 than the center in the x direction. The second die pad 4 is disposed on the x2 side of the first die pad 3 in the x direction, spaced apart from the first die pad 3.

[0027] As shown in FIGS. 2, 7, and 8, the first die pad 3 has the first semiconductor element 11 mounted thereon. The first die pad 3 is electrically connected to the back electrode of the first semiconductor element 11 and is one element of the input circuit described above. The first die pad 3 has, for example, a substantially rectangular shape when viewed in the z direction. The first die pad 3 has a first main surface 31 and a first back surface 32. The first main surface 31 and the first back surface 32 are spaced apart in the z direction as shown in FIGS. 7 and 8. The first main surface 31 faces the z1 side, and the first back surface 32 faces the z2 side. The first main surface 31 and the first back surface 32 Each of the first semiconductor element 11 and the first main surface 32 is substantially flat. The first semiconductor element 11 is bonded to the first main surface 31 by a conductive bonding material (solder, metal paste, sintered metal, etc.) not shown.

[0028] As shown in FIGS. 2 and 7, the second die pad 4 has a second semiconductor element 12 mounted thereon. The second die pad 4 is electrically connected to the back electrode of the second semiconductor element 12 and is one element of the high-voltage output circuit described above. The second die pad 4 has, for example, a substantially rectangular shape when viewed in the z direction. The second die pad 4 has a second main surface 41 and a second back surface 42. The second main surface 41 and the second back surface 42 are spaced apart in the z direction as shown in FIG. 7. The second main surface 41 faces the z1 side, and the second back surface 42 faces the z2 side. The second main surface 41 and the second back surface 42 are each substantially flat. The second semiconductor element 12 is bonded to the second main surface 41 of the second die pad 4 by a conductive bonding material (not shown).

[0029] The input terminals 51 are bonded to a wiring board of an inverter device to form a conductive path between the semiconductor device A10 and the wiring board. Each input terminal 51 is electrically connected to the control unit 111 of the first semiconductor element 11 and is one element of the input circuit described above. As shown in FIGS. 1, 2, and 5, the input terminals 51 are spaced apart from one another and arranged along the y direction. Each of the input terminals 51 is located on the x1 side of the first die pad 3 in the x direction and protrudes from the sealing resin 7 (first side surface 73 described below) toward the x1 side in the x direction. The input terminals 51 include a power supply terminal to which a voltage is supplied, a ground terminal, input terminals to which two types of control input signals are respectively input, and input terminals to which other control signals are input. In this embodiment, the semiconductor device A10 includes ten input terminals 51. The number of input terminals 51 is not limited. Each input terminal 51 includes a lead portion 511 and a pad portion 512.

[0030] The lead portion 511 is a rectangular portion extending along the x-direction. The lead portion 511 includes a portion exposed from the sealing resin 7 and a portion covered by the sealing resin 7. As shown in FIG. 7 , the portion of the lead portion 511 exposed from the sealing resin 7 is bent into a gull-wing shape. The portion of the lead portion 511 exposed from the sealing resin 7 may be plated. The plating layer formed by the plating process is made of an alloy containing Sn, such as solder, and covers the portion exposed from the sealing resin 7. The plating layer improves solder adhesion to the exposed portion and prevents erosion of the exposed portion due to soldering when the semiconductor device A10 is surface-mounted on a wiring board of an inverter device by soldering. The lead portions 511 of the multiple input terminals 51 are spaced apart from each other and arranged at equal intervals along the y-direction.

[0031] The pad portion 512 is a portion connected to the x2 side of the lead portion 511 in the x direction. The shape of each pad portion 512 as viewed in the z direction is not limited, but is preferably such that each pad portion 512 is close to the first die pad 3 and is spaced apart from each other by a predetermined distance or more. The upper surfaces (surfaces facing the z1 side) of the pad portions 512 may be plated. A plating layer formed by this plating process is made of a metal containing Ag, for example, and covers the upper surfaces of the pad portions 512. The plating layer increases the bonding strength of the wires 61 described below and protects the lead frame 81 (described below) from impacts during wire bonding of the wires 61. The entire surface of the pad portion 512 is covered with the sealing resin 7. The pad portion 512 is substantially flat.

[0032] The multiple input terminals 51 include input terminal 51a and input terminal 51b. As shown in FIG. 2, input terminal 51a is arranged fourth from the y1 side in the y direction among the multiple input terminals 51. Input terminal 51a is connected by a pad portion 512 to a position closer to the y1 side in the y direction of the end portion on the x1 side of the x direction of the first die pad 3. In this way, input terminal 51a supports the first die pad 3. Pad portions 512 of input terminals 51 other than input terminal 51a are wider than lead portions 511 in the y direction, and wires 61 are connected to the pad portions 512. 2, the input terminal 51b is arranged closest to the y1 side in the y direction among the multiple input terminals 51. The shape of each input terminal 51 is not limited.

[0033] Like the input terminals 51, the high-voltage output terminals 52 are bonded to the wiring board of the inverter device to form a conductive path between the semiconductor device A10 and the wiring board. Each high-voltage output terminal 52 is electrically connected to the second semiconductor element 12 and is one element of the high-voltage output circuit described above. As shown in FIGS. 1, 2, and 6, the high-voltage output terminals 52 are spaced apart from one another and arranged along the y direction. Each of the high-voltage output terminals 52 is located on the x2 side of the second die pad 4 in the x direction and protrudes from the sealing resin 7 (the second side surface 74 described below) toward the x2 side in the x direction. The high-voltage output terminals 52 include a power supply terminal to which voltage is supplied, a ground terminal, a high-side output terminal, and the like. In this embodiment, the semiconductor device A10 has three high-voltage output terminals 52. The number of high-voltage output terminals 52 is not limited. Each high-voltage output terminal 52 has a lead portion 521 and a pad portion 522.

[0034] The lead portion 521 is a rectangular portion extending along the x direction. The lead portion 521 includes a portion exposed from the sealing resin 7 and a portion covered by the sealing resin 7. As shown in FIG. 7, the portion of the lead portion 521 exposed from the sealing resin 7 is bent into a gull-wing shape. Similar to the lead portion 511, a plating layer (for example, an alloy containing Sn, such as solder) may be formed on the portion of the lead portion 521 exposed from the sealing resin 7. The lead portions 521 of the multiple high-voltage output terminals 52 are spaced apart from each other and arranged at equal intervals along the y direction.

[0035] The pad portion 522 is connected to the x1 side of the lead portion 521 in the x direction and is wider than the lead portion 521 in the y direction. The shape of each pad portion 522 as viewed in the z direction is not limited, but each pad portion 522 is close to the second die pad 4 and is spaced apart from each other by a predetermined distance or more. The upper surface of the pad portion 522 (the surface facing the z1 side) may be covered with a plating layer (for example, a metal containing Ag), similar to the upper surface of the pad portion 512. The entire surface of the pad portion 522 is covered with the sealing resin 7. The pad portion 522 is approximately flat.

[0036] The multiple high-voltage output terminals 52 include a high-voltage output terminal 52a and a high-voltage output terminal 52b. As shown in FIG. 2, the high-voltage output terminal 52a is located closest to the y1 side in the y direction among the multiple high-voltage output terminals 52. The high-voltage output terminal 52a is connected by a pad portion 522 to a position closer to the x1 side of the end of the second die pad 4 on the y1 side in the y direction in order to support the second die pad 4. The high-voltage output terminal 52a corresponds to the "support terminal" in the present disclosure. A wire 62 is joined to the pad portion 522 of the high-voltage output terminals 52 other than the high-voltage output terminal 52a. As shown in FIG. 2, the high-voltage output terminal 52b is located closest to the y2 side in the y direction among the multiple high-voltage output terminals 52. The high-voltage output terminal 52b corresponds to the "inner high-voltage output terminal" in the present disclosure. The shape of each high-voltage output terminal 52 is not limited.

[0037] The plurality of low-voltage output terminals 53, like the plurality of input terminals 51, are joined to the wiring board of the inverter device, thereby forming a conductive path between the semiconductor device A10 and the wiring board. Each low-voltage output terminal 53 is appropriately electrically connected to the low-voltage drive unit 112 of the first semiconductor element 11, and is one element of the low-voltage output circuit described above. As shown in FIGS. 1, 2, and 6, the plurality of low-voltage output terminals 53 are spaced apart from one another and arranged along the y direction. Each of the plurality of low-voltage output terminals 53 is located on the x2 side of the first die pad 3 in the x direction, and protrudes from the sealing resin 7 (a second side surface 74 described later) on the x2 side in the x direction. The plurality of low-voltage output terminals 53 are also located on the y2 side of the plurality of high-voltage output terminals 52 in the y direction. The plurality of low-voltage output terminals 53 are used as power supply terminals, ground terminals, low-voltage terminals, and so on to which voltage is supplied. The semiconductor device A10 includes a side output terminal and the like. In this embodiment, the semiconductor device A10 has three low-voltage output terminals 53. The number of low-voltage output terminals 53 is not limited. Each low-voltage output terminal 53 has a lead portion 531 and a pad portion 532.

[0038] The lead portion 531 is a rectangular portion extending along the x direction. The lead portion 531 includes a portion exposed from the sealing resin 7 and a portion covered by the sealing resin 7. As shown in FIG. 3, the portion of the lead portion 531 exposed from the sealing resin 7 is bent into a gull-wing shape. Similar to the lead portion 511, a plating layer (for example, an alloy containing Sn, such as solder) may be formed on the portion of the lead portion 531 exposed from the sealing resin 7. The lead portions 531 of the multiple low-voltage output terminals 53 are spaced apart from each other and arranged at equal intervals along the y direction.

[0039] The pad portion 532 is connected to the x1 side of the lead portion 531 in the x direction and is wider than the lead portion 531 in the y direction. The shape of each pad portion 532 as viewed in the z direction is not limited, but each pad portion 532 is close to the first die pad 3 and is spaced apart from each other by a predetermined distance or more. A wire 63 is bonded to each pad portion 522. The upper surface of the pad portion 532 (the surface facing the z1 side) may be covered with a plating layer (for example, a metal containing Ag), similar to the upper surface of the pad portion 512. The pad portion 532 is entirely covered with the sealing resin 7. The pad portion 532 is substantially flat.

[0040] The plurality of low-voltage output terminals 53 includes a low-voltage output terminal 53a. As shown in Fig. 2, the low-voltage output terminal 53a is arranged furthest to the y1 side in the y direction among the plurality of low-voltage output terminals 53. The low-voltage output terminal 53a corresponds to the "inner low-voltage output terminal" in the present disclosure. The shape of each low-voltage output terminal 53 is not limited.

[0041] In this embodiment, the lead portions 521 of the plurality of high-voltage output terminals 52 and the lead portions 531 of the plurality of low-voltage output terminals 53 are separated by a large distance in the y direction. Specifically, the first inter-terminal distance L1, which is the distance between the lead portion 521 of the high-voltage output terminal 52b and the lead portion 531 of the low-voltage output terminal 53a, is large and is approximately seven times the second inter-terminal distance L2, which is the distance between the lead portions 521 of two adjacent high-voltage output terminals 52. Note that the first inter-terminal distance L1 is not limited, but is preferably five times or more the second inter-terminal distance L2.

[0042] In semiconductor device A10, a voltage of 600 V or more is transiently applied to high-voltage driver 121 of second semiconductor element 12, compared to the ground of control unit 111 of first semiconductor element 11. As a result, a significant potential difference may occur between high-voltage output terminal 52, which is connected to high-voltage driver 121, and input terminal 51, which is connected to control unit 111. Furthermore, because the potential difference between low-voltage driver 112 of first semiconductor element 11 and control unit 111 is small, a significant potential difference may also occur between high-voltage output terminal 52, which is connected to high-voltage driver 121, and low-voltage output terminal 53, which is connected to low-voltage driver 112.

[0043] 2, the plurality of wires 61, the plurality of wires 62, the plurality of wires 63, and the plurality of wires 64, together with the conductive support member 2, form a conductive path for the first semiconductor element 11 and the second semiconductor element 12 to perform predetermined functions. The material of each of the plurality of wires 61, the plurality of wires 62, the plurality of wires 63, and the plurality of wires 64 is a metal containing, for example, Au, Cu, or Al.

[0044] As shown in FIGS. 2 and 7, the plurality of wires 61 constitute a conductive path between the control unit 111 of the first semiconductor element 11 and the plurality of input terminals 51. The plurality of wires 61 allow the control unit 111 of the first semiconductor element 11 to be electrically connected to at least one of the plurality of input terminals 51. The plurality of wires 61 are one element of the input circuit described above. Each of the plurality of wires 61 As shown in FIG. 2, the electrode 512 is bonded to one of the electrodes of the control section 111 of the first semiconductor element 11 and to the pad section 512 of one of the input terminals 51.

[0045] As shown in FIGS. 2 and 7, the plurality of wires 62 form a conductive path between the high-voltage driver 121 of the second semiconductor element 12 and the plurality of high-voltage output terminals 52. The plurality of wires 62 electrically connects the high-voltage driver 121 of the second semiconductor element 12 to at least one of the plurality of high-voltage output terminals 52. The plurality of wires 62 is one element of the high-voltage output circuit described above. As shown in FIG. 2, each of the plurality of wires 62 is joined to one of the electrodes of the high-voltage driver 121 of the second semiconductor element 12 and to a pad 522 of one of the high-voltage output terminals 52.

[0046] As shown in FIG. 2, the plurality of wires 63 form a conductive path between the low-voltage drive unit 112 of the first semiconductor element 11 and the plurality of low-voltage output terminals 53. The plurality of wires 63 electrically connect the low-voltage drive unit 112 of the first semiconductor element 11 to at least one of the plurality of low-voltage output terminals 53. The plurality of wires 63 are one element of the low-voltage output circuit described above. As shown in FIG. 2, each of the plurality of wires 63 is joined to one of the electrodes of the low-voltage drive unit 112 of the first semiconductor element 11 and to the pad portion 532 of one of the low-voltage output terminals 53.

[0047] As shown in FIGS. 2 and 7, the multiple wires 64 form a conductive path between the control unit 111 of the first semiconductor element 11 and the insulating portion 122 of the second semiconductor element 12. The multiple wires 64 allow the control unit 111 of the first semiconductor element 11 and the insulating portion 122 of the second semiconductor element 12 to be electrically connected to each other. The multiple wires 64 are one element of the input side circuit described above. As shown in FIG. 2, each of the multiple wires 64 is joined to one of the electrodes of the control unit 111 of the first semiconductor element 11 and one of the electrodes of the insulating portion 122 of the second semiconductor element 12.

[0048] As shown in FIG. 1 , the sealing resin 7 covers the first semiconductor element 11, the second semiconductor element 12, the first die pad 3, the second die pad 4, the plurality of wires 61 to 64, and a portion of each of the plurality of input terminals 51, high-voltage output terminals 52, and low-voltage output terminals 53. The sealing resin 7 has electrical insulation properties. The sealing resin 7 is made of a material containing, for example, black epoxy resin. When viewed in the z direction, the sealing resin 7 has a rectangular shape that is long in the y direction.

[0049] As shown in FIGS. 3 to 6, the sealing resin 7 has a top surface 71, a bottom surface 72, a first side surface 73, a second side surface 74, a third side surface 75, and a fourth side surface .

[0050] The top surface 71 and the bottom surface 72 are spaced apart from each other in the z direction. The top surface 71 and the bottom surface 72 face opposite each other in the z direction. The top surface 71 is located on the z1 side in the z direction and faces the z1 side, just like the first main surface 31 of the first die pad 3. The bottom surface 72 is located on the z2 side in the z direction. The top surface 71 and the bottom surface 72 are positioned on the first die pad 3 and face the z2 side, similar to the first back surface 32 of the first die pad 3. Each of the top surface 71 and the bottom surface 72 is substantially flat.

[0051] The first side surface 73, the second side surface 74, the third side surface 75, and the fourth side surface 76 are each connected to the top surface 71 and the bottom surface 72 and are sandwiched between the top surface 71 and the bottom surface 72 in the z direction. The first side surface 73 and the second side surface 74 are spaced apart from each other in the x direction. The first side surface 73 and the second side surface 74 face opposite each other in the x direction. The first side surface 73 is located on the x1 side in the x direction, and the second side surface 74 is located on the x2 side in the x direction. The third side surface 75 and the fourth side surface 76 are spaced apart from each other in the y direction and are connected to the first side surface 73 and the second side surface 74. The third side surface 75 and the fourth side surface 76 face opposite each other in the y direction. The third side surface 75 is located on the y2 side in the y direction, and the fourth side surface 76 is located on the y1 side in the y direction.

[0052] 1, a portion of each of the plurality of input terminals 51 protrudes from the first side surface 73. A portion of each of the plurality of high-voltage output terminals 52 and the plurality of low-voltage output terminals 53 protrudes from the second side surface 74. The conductive support member 2 is not exposed from the third side surface 75 and the fourth side surface 76. Furthermore, the conductive support member 2 is not exposed between the high-voltage output terminal 52b and the low-voltage output terminal 53a on the second side surface 74.

[0053] As shown in FIGS. 3 to 5 , the first side surface 73 includes a first region 731, a second region 732, and a third region 733. One end of the first region 731 in the z direction is connected to the top surface 71, and the other end in the z direction is connected to the third region 733. The first region 731 is inclined with respect to the top surface 71. One end of the second region 732 in the z direction is connected to the bottom surface 72, and the other end in the z direction is connected to the third region 733. The second region 732 is inclined with respect to the bottom surface 72. One end of the third region 733 in the z direction is connected to the first region 731, and the other end in the z direction is connected to the second region 732. The third region 733 extends in both the z direction and the y direction. When viewed in the z direction, the third region 733 is located outward from the top surface 71 and the bottom surface 72. From the third region 733, a portion of each of the input terminals 51 is exposed.

[0054] As shown in FIGS. 3, 4, and 6, the second side surface 74 includes a fourth region 741, a fifth region 742, and a sixth region 743. One end of the fourth region 741 in the z direction is connected to the top surface 71, and the other end in the z direction is connected to the sixth region 743. The fourth region 741 is inclined with respect to the top surface 71. One end of the fifth region 742 in the z direction is connected to the bottom surface 72, and the other end in the z direction is connected to the sixth region 743. The fifth region 742 is inclined with respect to the bottom surface 72. One end of the sixth region 743 in the z direction is connected to the fourth region 741, and the other end in the z direction is connected to the fifth region 742. The sixth region 743 extends in both the z direction and the y direction. When viewed in the z direction, the sixth region 743 is located outward from the top surface 71 and the bottom surface 72. From the sixth region 743, a portion of each of the plurality of high voltage output terminals 52 and low voltage output terminals 53 is exposed.

[0055] As shown in FIGS. 3, 5, and 6, the third side surface 75 includes a seventh region 751, an eighth region 752, and a ninth region 753. One end of the seventh region 751 in the z direction is connected to the top surface 71, and the other end in the z direction is connected to the ninth region 753. The seventh region 751 is inclined with respect to the top surface 71. One end of the eighth region 752 in the z direction is connected to the bottom surface 72, and the other end in the z direction is connected to the ninth region 753. The eighth region 752 is inclined with respect to the bottom surface 72. One end of the ninth region 753 in the z direction is connected to the seventh region 751, and the other end in the z direction is connected to the eighth region 752. The ninth region 753 extends along both the z direction and the y direction. When viewed in the z direction, the ninth region 753 is located outward from the top surface 71 and the bottom surface 72.

[0056] As shown in FIGS. 4 to 6 , the fourth side surface 76 includes a tenth region 761, an eleventh region 762, and a twelfth region 763. The tenth region 761 has one end in the z direction connected to the top surface 71 and the other end in the z direction connected to the twelfth region 763. The tenth region 761 is inclined with respect to the top surface 71. The eleventh region 762 has one end in the z direction connected to the bottom surface 72 and the other end in the z direction connected to the twelfth region 763. The eleventh region 762 is inclined with respect to the bottom surface 72. The twelfth region 763 has one end in the z direction connected to the tenth region 761 and the other end in the z direction connected to the eleventh region 762. The twelfth region 763 extends in both the z direction and the y direction. When viewed in the z direction, the twelfth region 763 is located outward from the top surface 71 and the bottom surface 72.

[0057] In this embodiment, as shown in FIGS. 9 and 10, the surface roughness of each of the top surface 71, the bottom surface 72, the first region 731 of the first side surface 73, and the second region 732 of the first side surface 73 of the sealing resin 7 is is greater than the surface roughness of a third region 733 of the first side surface 73. Furthermore, the surface roughness of each of the top surface 71, the bottom surface 72, the fourth region 741 of the second side surface 74, and the fifth region 742 of the second side surface 74 of the sealing resin 7 is greater than the surface roughness of a sixth region 743 of the second side surface 74. The surface roughness of each of the top surface 71 and the bottom surface 72 is preferably 5 μmRz or more and 20 μmRz or less.

[0058] In this embodiment, the sealing resin 7 has a first groove 76a as shown in FIGS. 1 and 4. The first groove 76a is recessed in the y direction from the fourth side surface 76 and extends in the z direction from the top surface 71 to the bottom surface 72. In this embodiment, the sealing resin 7 has three first grooves 76a arranged at equal intervals. The number of first grooves 76a is not limited. In this embodiment, as shown in FIG. 1, the shape of the first groove 76a as viewed in the z direction is rectangular. The shape of the first groove 76a as viewed in the z direction is not limited and may be, for example, semicircular.

[0059] In this embodiment, the sealing resin 7 includes second grooves 74a as shown in FIGS. 1 and 6. The second grooves 74a are recessed from the second side surface 74 in the x direction and extend from the top surface 71 to the bottom surface 72 in the z direction. The second grooves 74a are disposed on the second side surface 74 between the high-voltage output terminals 52 and the low-voltage output terminals 53. That is, the second grooves 74a are disposed on the second side surface 74 between the high-voltage output terminal 52b and the low-voltage output terminal 53a. In this embodiment, the sealing resin 7 includes three second grooves 74a disposed at equal intervals. The number of second grooves 74a is not limited. In this embodiment, the shape of the second grooves 74a as viewed in the z direction is rectangular as shown in FIG. 1. The shape of the second grooves 74a as viewed in the z direction is not limited and may be, for example, semicircular.

[0060] Next, an example of a method for manufacturing the semiconductor device A10 will be described below with reference to Figures 11 and 12. Figures 11 and 12 are plan views showing steps involved in the method for manufacturing the semiconductor device A10. Note that the x, y, and z directions shown in these figures are the same as those in Figures 1 to 10.

[0061] First, as shown in FIG. 11 , a lead frame 81 is prepared. The lead frame 81 is a plate-shaped material. In this embodiment, the base material of the lead frame 81 is Cu. The lead frame 81 may be formed by etching a metal plate or by punching a metal plate. The lead frame 81 has a main surface 81A and a back surface 81B spaced apart in the z-direction. The lead frame 81 also includes an outer frame 811, a first die pad 812A, a second die pad 812B, a plurality of first leads 813, a plurality of second leads 814, a plurality of third leads 815, and a dam bar 816. Of these, the outer frame 811 and the dam bar 816 do not constitute the semiconductor device A10. The first die pad 812A is a portion that will later become the first die pad 3. The second die pad 812B is a portion that will later become the second die pad 4. The plurality of first leads 813 are portions that will later become the plurality of input terminals 51. The plurality of second leads 814 are portions that will later become the plurality of high-voltage output terminals 52. The plurality of third leads 815 are portions that will later become the plurality of low-voltage output terminals 53.

[0062] 12, first semiconductor element 11 is bonded to first die pad 812A by die bonding, and second semiconductor element 12 is bonded to second die pad 812B by die bonding. After these steps, each of a plurality of wires 61 to 64 is formed by wire bonding.

[0063] In the process of forming the wire 61, first, the capillary is lowered toward the control unit 111 of the first semiconductor element 11, and the tip of the wire is pressed against a predetermined electrode. At this time, the weight of the capillary and the action of ultrasonic waves oscillated from the capillary cause the tip of the wire to press against the electrode. The wire is crimped onto the electrode, forming a first bond. Next, the capillary is raised while feeding out the wire, forming a ball bond on the electrode. Next, the capillary is moved to just above the portion of the first lead 813 that will become the pad portion 512 of one of the input terminals 51, and is then lowered so that the tip of the capillary is pressed against the bonding surface. As a result, the wire is sandwiched between the tip of the capillary and the bonding surface, and is crimped onto the bonding surface, forming a second bond. Next, the capillary is raised, and the wire is cut.

[0064] In the process of forming wire 62, first bonding is performed on the electrode of high-voltage drive unit 121 of second semiconductor element 12, and second bonding is performed on a portion of second lead 814 that will become pad portion 522 of high-voltage output terminal 52. In the process of forming wire 63, first bonding is performed on the electrode of low-voltage drive unit 112 of first semiconductor element 11, and second bonding is performed on a portion of third lead 815 that will become pad portion 522 of low-voltage output terminal 53. In the process of forming wire 64, first bonding is performed on the electrode of control unit 111 of first semiconductor element 11, and second bonding is performed on the electrode of insulating portion 122 of second semiconductor element 12.

[0065] Next, the sealing resin 7 is formed. The sealing resin 7 is formed by transfer molding. In this process, the lead frame 81 is placed in a mold having multiple cavities. At this time, the portion of the lead frame 81 that is the conductive support member 2 covered by the sealing resin 7 in the semiconductor device A10 is placed in one of the multiple cavities. Then, fluidized resin is poured from the pot via a runner into each of the multiple cavities. After the fluidized sealing resin 7 solidifies in the multiple cavities, resin burrs located outside each of the multiple cavities are removed using high-pressure water or the like. This completes the formation of the sealing resin 7.

[0066] Thereafter, dicing is performed to separate the first die pad 812A, the second die pad 812B, the plurality of first leads 813, the plurality of second leads 814, and the plurality of third leads 815, which were connected to each other by the outer frame 811 and the dam bar 816. By going through the steps described above, the semiconductor device A10 is manufactured.

[0067] Next, the effects of the semiconductor device A10 will be described.

[0068] According to this embodiment, second semiconductor element 12 includes insulating element 122 that relays transmission and reception of signals between control element 111 of first semiconductor element 11 and high-voltage driving element 121 of second semiconductor element 12, and that insulates control element 111 from high-voltage driving element 121. Therefore, when a significant potential difference occurs between control element 111 and high-voltage driving element 121, it is possible to improve the withstand voltage between the input-side circuit including control element 111 of first semiconductor element 11 and the high-voltage output-side circuit including high-voltage driving element 121 of second semiconductor element 12.

[0069] Furthermore, in this embodiment, the conductive support member 2 includes a first die pad 3, a second die pad 4, a plurality of input terminals 51, a plurality of high-voltage output terminals 52, and a plurality of low-voltage output terminals 53. The plurality of input terminals 51 are exposed from a first side surface 73, and the plurality of high-voltage output terminals 52 and the plurality of low-voltage output terminals 53 are exposed from a second side surface 74. On the other hand, the conductive support member 2 is not exposed from a fourth side surface 76. Therefore, no metal portion of the conductive support member 2 exposed from the sealing resin 7 exists between the plurality of input terminals 51 and the plurality of high-voltage output terminals 52, which generate a significant potential difference. This increases the insulation distance between the plurality of input terminals 51 and the plurality of high-voltage output terminals 52. This increases the withstand voltage of the semiconductor device A10 compared to when the conductive support member 2, such as a support lead, is exposed from the fourth side surface 76.

[0070] Furthermore, according to this embodiment, the sealing resin 7 has a first groove 76a recessed in the y direction from the fourth side surface 76. Therefore, the creepage distance from the input terminal 51b along the first side surface 73, the fourth side surface 76, and the second side surface 74 of the sealing resin 7 to the high-voltage output terminal 52a is longer than in a case where the first groove 76a is not provided. This allows the semiconductor device A10 to have a further improved dielectric strength.

[0071] Furthermore, according to this embodiment, the surface roughness of each of the top surface 71, the bottom surface 72, the first region 731 of the first side surface 73, and the second region 732 of the first side surface 73 is greater than the surface roughness of the third region 733 of the first side surface 73. Furthermore, the surface roughness of each of the top surface 71, the bottom surface 72, the fourth region 741 of the second side surface 74, and the fifth region 742 of the second side surface 74 is greater than the surface roughness of the sixth region 743 of the second side surface 74. Therefore, the creeping distance from the input terminal 51b to the high-voltage output terminal 52a along the first region 731 of the first side surface 73 of the sealing resin 7, the top surface 71, and the fourth region 741 of the second side surface 74, and the creeping distance from the input terminal 51b to the high-voltage output terminal 52a along the second region 732 of the first side surface 73 of the sealing resin 7, the bottom surface 72, and the fifth region 742 of the second side surface 74, can be increased. This allows the semiconductor device A10 to further improve its dielectric strength.

[0072] Furthermore, in this embodiment, the first inter-terminal distance L1 (the distance between the lead portion 521 of the high-voltage output terminal 52b and the lead portion 531 of the low-voltage output terminal 53a) is five or more times the second inter-terminal distance L2 (the distance between the lead portions 521 of two adjacent high-voltage output terminals 52). Therefore, the lead portions 521 of the multiple high-voltage output terminals 52 and the lead portions 531 of the multiple low-voltage output terminals 53 are sufficiently separated in the y direction. Since the multiple high-voltage output terminals 52 and the low-voltage output terminals 53, which generate a significant potential difference, are sufficiently separated, the semiconductor device A10 has a high dielectric strength voltage. Furthermore, on the second side surface 74, the conductive support member 2 is not exposed between the high-voltage output terminal 52b and the low-voltage output terminal 53a, and no metal portion is present. Therefore, the insulation distance between the multiple high-voltage output terminals 52 and the multiple low-voltage output terminals 53 is long. This increases the dielectric strength of the semiconductor device A10 compared to when the conductive support member 2, such as the support lead, is exposed from the second side surface 74.

[0073] Furthermore, according to this embodiment, the sealing resin 7 has a second groove 74a recessed in the x-direction from the second side surface 74. Therefore, the creepage distance from the high-voltage output terminal 52b along the second side surface 74 of the sealing resin 7 to the low-voltage output terminal 53a is longer than in a case where the second groove 74a is not provided. This allows the semiconductor device A10 to have a further improved dielectric strength.

[0074] In semiconductor device A10, a voltage of 600 V or more is transiently applied to high voltage drive unit 121 of second semiconductor element 12, compared to the ground of control unit 111 of first semiconductor element 11. In this way, when a significant potential difference occurs between control unit 111 and high voltage drive unit 121, it is preferable to provide insulating unit 122 and further improve the dielectric strength voltage in order to improve the reliability of semiconductor device A10.

[0075] In the present embodiment, the case where the first semiconductor element 11 including the control unit 111 and the low-voltage driving unit 112 is mounted on the first die pad 3 has been described, but this is not limiting. For example, the first semiconductor element 11 may include only the control unit 111, and another semiconductor element including the low-voltage driving unit 112 may be mounted on the first die pad 3. In addition, in the present embodiment, the case where the second semiconductor element 12 including the high-voltage driving unit 121 and the insulating unit 122 is mounted on the second die pad 4 has been described, but this is not limiting. For example, the second semiconductor element 12 may include only the high-voltage driving unit 121, and another semiconductor element including the insulating unit 122 may be mounted on the second die pad 4. In addition, the second semiconductor element 12 may include only the high-voltage driving unit 121, and another semiconductor element including the insulating unit 122 may be mounted on the second die pad 4. Another semiconductor element including the above may be mounted on the first die pad 3.

[0076] In addition, in the present embodiment, the sealing resin 7 includes the first groove portion 76a and the second groove portion 74a, but this is not limiting. The sealing resin 7 does not necessarily have to include the first groove portion 76a, and does not necessarily have to include the second groove portion 74a.

[0077] Furthermore, in the present embodiment, the case has been described in which the surface roughness of each of the top surface 71, bottom surface 72, first region 731 of first side surface 73, second region 732 of first side surface 73, fourth region 741 of second side surface 74, and fifth region 742 of second side surface 74 of sealing resin 7 is greater than the surface roughness of the third region 733 of first side surface 73 and the sixth region 743 of second side surface 74, but this is not limited to this. Each surface 71 to 76 of sealing resin 7 may have the same degree of surface roughness. In this case, the surface roughness of each surface 71 to 76 of sealing resin 7 may be relatively small or relatively large (for example, 5 μmRz or more and 20 μmRz or less).

[0078] In addition, in this embodiment, the case where the conductive support member 2 is not exposed from the third side surface 75 and the fourth side surface 76 has been described, but this is not limited to this. The support leads may be exposed from the third side surface 75 or the fourth side surface 76.

[0079] 13 to 19 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals as those in the above embodiment.

[0080] Second Embodiment Fig. 13 is a diagram illustrating a semiconductor device A20 according to a second embodiment of the present disclosure. Fig. 13 is a plan view showing the semiconductor device A20, and is a diagram corresponding to Fig. 2. In Fig. 13, for ease of understanding, the outline of the sealing resin 7 is shown by an imaginary line (two-dot chain line) through the sealing resin 7. The semiconductor device A20 of this embodiment differs from the first embodiment in that it further includes two input side terminals 51 that support the first die pad 3.

[0081] In this embodiment, the multiple input terminals 51 further include an input terminal 51c and an input terminal 51d. The input terminal 51c is added further to the y1 side of the input terminal 51b in the y direction. The input terminal 51c is connected by a pad portion 512 to a position closer to the x2 side of the end of the first die pad 3 on the y1 side in the y direction. This allows the input terminal 51c to support the first die pad 3. The input terminal 51d is added at the y2 side of the input terminal 51d in the y direction. The input terminal 51d is connected by a pad portion 512 to a position closer to the x2 side of the end of the first die pad 3 on the y2 side in the y direction. This allows the input terminal 51d to support the first die pad 3.

[0082] In this embodiment, the second semiconductor element 12 also includes the insulating portion 122, thereby improving the dielectric strength between the input circuit and the high-voltage output circuit. Also in this embodiment, the conductive support member 2 is not exposed from the fourth side surface 76, thereby increasing the insulation distance between the multiple input terminals 51 and the multiple high-voltage output terminals 52. Furthermore, the sealing resin 7 includes the first groove portion 76a, thereby increasing the creepage distance from the input terminal 51c to the high-voltage output terminal 52a via the fourth side surface 76. Furthermore, the surface roughness of each of the top surface 71, the bottom surface 72, the first region 731 of the first side surface 73, the second region 732 of the first side surface 73, the fourth region 741 of the second side surface 74, and the fifth region 742 of the second side surface 74 is greater than the surface roughness of the third region 733 of the first side surface 73 and the sixth region 743 of the second side surface 74. Therefore, the creeping distance from the input terminal 51c to the high-voltage output terminal 52a via the top surface 71 or the bottom surface 72 can be made longer. Also in this embodiment, the first inter-terminal distance L1 is five times or more the second inter-terminal distance L2, so the lead portions 521 of the plurality of high-voltage output terminals 52 and the lead portions 531 of the plurality of low-voltage output terminals 53 are sufficiently separated in the y direction. Because the conductive support member 2 is not exposed between the terminal 52b and the low-voltage output terminal 53a, the insulation distance between the multiple high-voltage output terminals 52 and the multiple low-voltage output terminals 53 is increased. Furthermore, because the sealing resin 7 has the second groove 74a, the creepage distance from the high-voltage output terminal 52b along the second side surface 74 of the sealing resin 7 to the low-voltage output terminal 53a is increased. These features further improve the dielectric strength of the semiconductor device A20. Furthermore, according to this embodiment, the first die pad 3 is also supported by the input terminals 51c and 51d. This allows the first die pad 3 to be more stable during the process of bonding the first semiconductor element 11 to the first die pad 3 and the process of forming the wires 61.

[0083] <Third embodiment> 14 is a diagram illustrating a semiconductor device A30 according to a third embodiment of the present disclosure. FIG. 14 is a plan view showing the semiconductor device A30, and corresponds to FIG. 2. In FIG. 14, for ease of understanding, the outline of the sealing resin 7 is shown by an imaginary line (two-dot chain line) through the sealing resin 7. The semiconductor device A30 of this embodiment differs from the first embodiment in that the first die pad 3 is also supported by support leads.

[0084] In this embodiment, the conductive support member 2 further includes support leads 55. The support leads 55 have an elongated rectangular shape when viewed in the z direction and extend in the y direction. The end of the support lead 55 on the y1 side in the y direction is connected to the end of the first die pad 3 on the y2 side in the y direction at a position closer to the x2 side in the x direction, thereby supporting the first die pad 3. The end face of the support lead 55 on the y2 side in the y direction is exposed from the third side face 75 of the sealing resin 7. The support leads 55 are connected to the first die pad 3 and the outer frame 811 in the lead frame 81, and are cut from the outer frame 811 in the dicing process. The cut surface at this time becomes the end face on the y2 side in the y direction, and this end face is exposed from the third side face 75 of the sealing resin 7.

[0085] In this embodiment, the second semiconductor element 12 also includes the insulating portion 122, thereby improving the dielectric strength between the input circuit and the high-voltage output circuit. Also in this embodiment, the conductive support member 2 is not exposed from the fourth side surface 76, thereby increasing the insulation distance between the multiple input terminals 51 and the multiple high-voltage output terminals 52. Furthermore, the sealing resin 7 includes the first groove portion 76a, thereby increasing the creepage distance from the input terminal 51b to the high-voltage output terminal 52a via the fourth side surface 76. Furthermore, the surface roughness of each of the top surface 71, the bottom surface 72, the first region 731 of the first side surface 73, the second region 732 of the first side surface 73, the fourth region 741 of the second side surface 74, and the fifth region 742 of the second side surface 74 is greater than the surface roughness of the third region 733 of the first side surface 73 and the sixth region 743 of the second side surface 74. Therefore, the creepage distance from the input terminal 51b to the high-voltage output terminal 52a via the top surface 71 or the bottom surface 72 can be further increased. Furthermore, in this embodiment, the first inter-terminal distance L1 is at least five times the second inter-terminal distance L2, so the lead portions 521 of the high-voltage output terminals 52 and the lead portions 531 of the low-voltage output terminals 53 are sufficiently separated in the y direction. Furthermore, the conductive support member 2 is not exposed between the high-voltage output terminal 52b and the low-voltage output terminal 53a on the second side surface 74, so the insulation distance between the high-voltage output terminals 52 and the low-voltage output terminals 53 is increased. Furthermore, the sealing resin 7 includes the second groove 74a, so the creepage distance from the high-voltage output terminal 52b to the low-voltage output terminal 53a along the second side surface 74 of the sealing resin 7 is increased. These factors further improve the dielectric strength of the semiconductor device A30. Furthermore, in this embodiment, the first die pad 3 is also supported by the support leads 55. This makes it possible to further stabilize the first die pad 3 in the step of bonding the first semiconductor element 11 to the first die pad 3 and in the step of forming the wires 61. Because the end faces of the support leads 55 are exposed from the third side surface 75, the insulation distance between the plurality of input terminals 51 and the plurality of low-voltage output terminals 53 is shortened, but this does not pose a problem because the potential difference between the input circuit including the control unit 111 of the first semiconductor element 11 and the low-voltage output circuit including the low-voltage drive unit 112 is small.

[0086] <Fourth embodiment> 15 is a diagram illustrating a semiconductor device A40 according to a fourth embodiment of the present disclosure. FIG. 15 is a plan view showing the semiconductor device A40, and corresponds to FIG. 2. In FIG. 15, for ease of understanding, the outline of the sealing resin 7 is shown by an imaginary line (two-dot chain line) through the sealing resin 7. The semiconductor device A40 of this embodiment differs from the first embodiment in that it further includes a high-voltage output terminal 52 that supports the second die pad 4.

[0087] In this embodiment, the high-voltage output terminals 52 further include a high-voltage output terminal 52c. The high-voltage output terminal 52c is added further to the y2 side of the high-voltage output terminal 52b in the y direction. The high-voltage output terminal 52c is connected by a pad portion 512 to the end of the second die pad 4 on the x2 side in the x direction, near the center in the y direction. This allows the high-voltage output terminal 52c to support the second die pad 4. The addition of the high-voltage output terminal 52c narrows the gap between the lead portions 521 of the high-voltage output terminals 52 and the lead portions 531 of the low-voltage output terminals 53. However, the first inter-terminal distance L1′, which is the distance between the lead portion 521 of the high-voltage output terminal 52c and the lead portion 531 of the low-voltage output terminal 53a, is five times or more the second inter-terminal distance L2 (the distance between the lead portions 521 of two adjacent high-voltage output terminals 52).

[0088] In this embodiment, the second semiconductor element 12 also includes the insulating portion 122, thereby improving the dielectric strength between the input circuit and the high-voltage output circuit. Also in this embodiment, the conductive support member 2 is not exposed from the fourth side surface 76, thereby increasing the insulation distance between the multiple input terminals 51 and the multiple high-voltage output terminals 52. Furthermore, the sealing resin 7 includes the first groove portion 76a, thereby increasing the creepage distance from the input terminal 51b to the high-voltage output terminal 52a via the fourth side surface 76. Furthermore, the surface roughness of each of the top surface 71, the bottom surface 72, the first region 731 of the first side surface 73, the second region 732 of the first side surface 73, the fourth region 741 of the second side surface 74, and the fifth region 742 of the second side surface 74 is greater than the surface roughness of the third region 733 of the first side surface 73 and the sixth region 743 of the second side surface 74. Therefore, the creeping distance from the input terminal 51b to the high-voltage output terminal 52a via the top surface 71 or the bottom surface 72 can be made longer. Furthermore, according to this embodiment, the first inter-terminal distance L1' is at least five times the second inter-terminal distance L2, so the lead portions 521 of the high-voltage output terminals 52 and the lead portions 531 of the low-voltage output terminals 53 are sufficiently separated in the y direction. Furthermore, the conductive support member 2 is not exposed between the high-voltage output terminal 52c and the low-voltage output terminal 53a on the second side surface 74, so the insulation distance between the high-voltage output terminals 52 and the low-voltage output terminals 53 is made longer. Furthermore, the sealing resin 7 has the second groove portion 74a, so the creeping distance from the high-voltage output terminal 52c along the second side surface 74 of the sealing resin 7 to the low-voltage output terminal 53a is made longer. These factors contribute to further improving the dielectric strength of the semiconductor device A40. Furthermore, in this embodiment, the second die pad 4 is also supported by the high-voltage output terminal 52c. This makes it possible to further stabilize the second die pad 4 in the step of bonding the second semiconductor element 12 to the second die pad 4 and in the step of forming the wires 62.

[0089] Fifth Embodiment Fig. 16 is a diagram illustrating a semiconductor device A50 according to a fifth embodiment of the present disclosure. Fig. 16 is a plan view showing the semiconductor device A50, and corresponds to Fig. 1. The semiconductor device A50 of this embodiment differs from the first embodiment in that the sealing resin 7 has protrusions instead of the first groove portion 76a and the second groove portion 74a.

[0090] In this embodiment, the sealing resin 7 does not include the first groove portion 76a, but instead includes a first protrusion portion 76b. The first protrusion portion 76b protrudes in the y direction from the fourth side surface 76, and extends from the top surface 71 to the bottom surface 72 in the z direction. In this embodiment, the sealing resin 7 includes three first protrusion portions 76b arranged at equal intervals. Note that the first protrusion portions 76 The number of b's is not limited. In this embodiment, the shape of the first protrusion 76b when viewed in the z direction is rectangular. Note that the shape of the first protrusion 76b when viewed in the z direction is not limited, and may be, for example, semicircular.

[0091] Furthermore, in this embodiment, the sealing resin 7 does not include the second groove portion 74a, but instead includes a second protrusion 74b. The second protrusion 74b protrudes from the second side surface 74 in the x direction and extends from the top surface 71 to the bottom surface 72 in the z direction. The second protrusion 74b is disposed on the second side surface 74 between the plurality of high-voltage output terminals 52 and the plurality of low-voltage output terminals 53. In other words, the second protrusion 74b is disposed on the second side surface 74 between the high-voltage output terminal 52b and the low-voltage output terminal 53a. In this embodiment, the sealing resin 7 includes three second protrusions 74b disposed at equal intervals. Note that the number of second protrusions 74b is not limited. In this embodiment, the shape of the second protrusion 74b when viewed in the z direction is rectangular. Note that the shape of the second protrusion 74b when viewed in the z direction is not limited and may be, for example, semicircular.

[0092] In this embodiment, the second semiconductor element 12 also includes the insulating portion 122, thereby improving the dielectric strength between the input circuit and the high-voltage output circuit. Also in this embodiment, the conductive support member 2 is not exposed from the fourth side surface 76, thereby increasing the insulation distance between the multiple input terminals 51 and the multiple high-voltage output terminals 52. Furthermore, in this embodiment, the sealing resin 7 includes the first protrusion 76b, thereby increasing the creepage distance from the input terminal 51b to the high-voltage output terminal 52a via the fourth side surface 76. Furthermore, the surface roughness of each of the top surface 71, the bottom surface 72, the first region 731 of the first side surface 73, the second region 732 of the first side surface 73, the fourth region 741 of the second side surface 74, and the fifth region 742 of the second side surface 74 is greater than the surface roughness of the third region 733 of the first side surface 73 and the sixth region 743 of the second side surface 74. Therefore, the creepage distance from the input terminal 51b to the high-voltage output terminal 52a via the top surface 71 or the bottom surface 72 can be further increased. Furthermore, in this embodiment, the first inter-terminal distance L1 is at least five times the second inter-terminal distance L2, so the lead portions 521 of the high-voltage output terminals 52 and the lead portions 531 of the low-voltage output terminals 53 are sufficiently separated in the y direction. Furthermore, the conductive support member 2 is not exposed between the high-voltage output terminal 52b and the low-voltage output terminal 53a on the second side surface 74, so the insulation distance between the high-voltage output terminals 52 and the low-voltage output terminals 53 is increased. Furthermore, in this embodiment, the sealing resin 7 has the second protrusion 74b, so the creepage distance from the high-voltage output terminal 52b along the second side surface 74 of the sealing resin 7 to the low-voltage output terminal 53a is increased. These factors further improve the withstand voltage of the semiconductor device A50.

[0093] Sixth Embodiment Fig. 17 is a diagram illustrating a semiconductor device A60 according to a sixth embodiment of the present disclosure. Fig. 17 is a plan view showing the semiconductor device A60, and corresponds to Fig. 1. The semiconductor device A60 of this embodiment differs from the first embodiment in that the sealing resin 7 further includes a protrusion in addition to the first groove portion 76a and the second groove portion 74a.

[0094] In this embodiment, the sealing resin 7 has a first protrusion 76b between adjacent first grooves 76a. The first protrusion 76b protrudes in the y direction from the fourth side surface 76 and extends from the top surface 71 to the bottom surface 72 in the z direction. In this embodiment, the sealing resin 7 has two first protrusions 76b. The number of first protrusions 76b is not limited. In this embodiment, the shape of the first protrusion 76b when viewed in the z direction is rectangular. The shape of the first protrusion 76b when viewed in the z direction is not limited and may be, for example, a semicircular shape.

[0095] In this embodiment, the sealing resin 7 has second protrusions 74b between adjacent second grooves 74a. The second protrusions 74b protrude from the second side surface 74 in the x direction and extend in the z direction. The second protrusions 74b extend from the top surface 71 to the bottom surface 72 in the z direction. In this embodiment, the sealing resin 7 has two second protrusions 74b. The number of second protrusions 74b is not limited. In this embodiment, the shape of the second protrusions 74b when viewed in the z direction is rectangular. The shape of the second protrusions 74b when viewed in the z direction is not limited, and may be, for example, semicircular.

[0096] In this embodiment, the second semiconductor element 12 also includes the insulating portion 122, thereby improving the dielectric strength between the input circuit and the high-voltage output circuit. Also in this embodiment, the conductive support member 2 is not exposed from the fourth side surface 76, thereby increasing the insulation distance between the multiple input terminals 51 and the multiple high-voltage output terminals 52. Furthermore, in this embodiment, the sealing resin 7 includes the first groove 76a and the first protrusion 76b, thereby increasing the creepage distance from the input terminal 51b to the high-voltage output terminal 52a via the fourth side surface 76. Furthermore, the surface roughness of the top surface 71, the bottom surface 72, the first region 731 of the first side surface 73, the second region 732 of the first side surface 73, the fourth region 741 of the second side surface 74, and the fifth region 742 of the second side surface 74 is greater than the surface roughness of the third region 733 of the first side surface 73 and the sixth region 743 of the second side surface 74. Therefore, the creepage distance from the input terminal 51b to the high-voltage output terminal 52a via the top surface 71 or the bottom surface 72 can be further increased. Also in this embodiment, the first inter-terminal distance L1 is at least five times the second inter-terminal distance L2, so the lead portions 521 of the high-voltage output terminals 52 and the lead portions 531 of the low-voltage output terminals 53 are sufficiently separated in the y direction. Furthermore, the conductive support member 2 is not exposed between the high-voltage output terminal 52b and the low-voltage output terminal 53a on the second side surface 74, so the insulation distance between the high-voltage output terminals 52 and the low-voltage output terminals 53 is increased. Furthermore, in this embodiment, the sealing resin 7 includes the second groove portion 74a and the second protrusion portion 74b, so the creepage distance from the high-voltage output terminal 52b to the low-voltage output terminal 53a along the second side surface 74 of the sealing resin 7 is increased. These factors further improve the withstand voltage of the semiconductor device A60.

[0097] Seventh Embodiment Fig. 18 is a diagram illustrating a semiconductor device A70 according to a seventh embodiment of the present disclosure. Fig. 18 is a plan view showing the semiconductor device A70, and is a diagram corresponding to Fig. 2. In Fig. 18, for ease of understanding, the outline of the sealing resin 7 is shown by an imaginary line (two-dot chain line) through the sealing resin 7. The semiconductor device A70 of this embodiment differs from the first embodiment in that the second semiconductor element 12 does not include an insulating portion 122, and instead the first semiconductor element 11 includes an insulating portion.

[0098] In this embodiment, the second semiconductor element 12 does not include an insulating portion 122. On the other hand, the first semiconductor element 11 further includes an insulating portion 113. The insulating portion 113 is disposed closer to the x2 side of the first semiconductor element 11 in the x direction and closer to the y1 side of the y direction, and is electrically connected to the control unit 111 inside the first semiconductor element 11. The insulating portion 113 is a portion for transmitting a PWM control signal in an insulated state and has a configuration similar to that of the insulating portion 122. The insulating portion 113 receives a PWM control signal from the control unit 111 and transmits the received PWM control signal in an insulated state to the high-voltage driving portion 121 of the second semiconductor element 12 via the wire 64. In other words, the insulating portion 113 relays the transmission and reception of signals between the control unit 111 of the first semiconductor element 11 and the high-voltage driving portion 121 of the second semiconductor element 12, and also insulates the control unit 111 of the first semiconductor element 11 from the high-voltage driving portion 121 of the second semiconductor element 12 from each other.

[0099] According to this embodiment, the first semiconductor element 11 has the insulating portion 113, which improves the dielectric strength between the input circuit and the high-voltage output circuit. Also in this embodiment, the conductive support member 2 is not exposed from the fourth side surface 76, which increases the insulation distance between the plurality of input terminals 51 and the plurality of high-voltage output terminals 52. Furthermore, the sealing resin 7 has the first groove portion 76a, which increases the creepage distance from the input terminal 51b to the high-voltage output terminal 52a via the fourth side surface 76. Furthermore, the top surface 71, the bottom surface 72, the first region 731 of the first side surface 73, The surface roughness of the second region 732 of the first side surface 73, the fourth region 741 of the second side surface 74, and the fifth region 742 of the second side surface 74 is greater than the surface roughness of the third region 733 of the first side surface 73 and the sixth region 743 of the second side surface 74. Therefore, the creepage distance from the input terminal 51b to the high-voltage output terminal 52a via the top surface 71 or the bottom surface 72 can be increased. Also in this embodiment, the first inter-terminal distance L1 is at least five times the second inter-terminal distance L2, so the lead portions 521 of the high-voltage output terminals 52 and the lead portions 531 of the low-voltage output terminals 53 are sufficiently separated in the y direction. Furthermore, the conductive support member 2 is not exposed between the high-voltage output terminal 52b and the low-voltage output terminal 53a on the second side surface 74, so the insulation distance between the high-voltage output terminals 52 and the low-voltage output terminals 53 is increased. Furthermore, since the sealing resin 7 is provided with the second groove portion 74a, the creeping distance from the high-voltage output terminal 52b to the low-voltage output terminal 53a along the second side surface 74 of the sealing resin 7 is increased. As a result, the semiconductor device A70 can further improve the dielectric strength voltage.

[0100] In the present embodiment, the case has been described in which the first semiconductor element 11 including the control unit 111, the low-voltage driving unit 112, and the insulating unit 113 is mounted on the first die pad 3, but this is not limiting. For example, the first semiconductor element 11 may include only the control unit 111 and the low-voltage driving unit 112, and another semiconductor element including the insulating unit 113 may be mounted on the first die pad 3. Alternatively, the first semiconductor element 11 may include only the control unit 111, and another semiconductor element including the low-voltage driving unit 112 and another semiconductor element including the insulating unit 113 may be mounted on the first die pad 3.

[0101] Eighth Embodiment 19 is a diagram illustrating a semiconductor device A80 according to an eighth embodiment of the present disclosure. FIG. 19 is a plan view showing the semiconductor device A80, and corresponds to FIG. 2. In FIG. 19, for ease of understanding, the outline of the sealing resin 7 is shown by an imaginary line (two-dot chain line) through the sealing resin 7. The semiconductor device A80 of this embodiment differs from the first embodiment in that the first semiconductor element 11 does not include a low-voltage driving unit 112, and instead a semiconductor element including a low-voltage driving unit is mounted on a die pad that constitutes a low-voltage output-side circuit.

[0102] In this embodiment, the first semiconductor element 11 does not include the low-voltage driving section 112. The semiconductor device A80 further includes a third semiconductor element 13, a third die pad 45, and wires 65.

[0103] The third semiconductor element 13 is mounted on a third die pad 45 and is disposed on the x2 side in the x direction relative to the first semiconductor element 11 and on the y2 side in the y direction relative to the second semiconductor element 12. When viewed in the z direction, the third semiconductor element 13 has a rectangular shape that is long in the y direction. The third semiconductor element 13 has a substrate (not shown) made of Si, and a low-voltage drive unit 131 is formed on the substrate. The low-voltage drive unit 131 has a configuration similar to the low-voltage drive unit 112 of the first semiconductor element 11 according to the first embodiment. The low-voltage drive unit 131 receives a PWM control signal from the control unit 111 of the first semiconductor element 11 via wire 65 to drive the low-side switching element. A plurality of electrodes (not shown) are provided on the top surface (surface facing the z1 side) of the third semiconductor element 13. Furthermore, a backside electrode (not shown) is provided on the bottom surface (surface facing the z2 side) of the third semiconductor element 13. These electrodes are electrically connected to a circuit configured in the third semiconductor element 13.

[0104] The third die pad 45 has the third semiconductor element 13 mounted thereon. The third die pad 45 is electrically connected to the back electrode of the third semiconductor element 13, and is one element of the low-voltage output circuit described above. The third die pad 45 has, for example, a substantially rectangular shape when viewed in the z direction. The third semiconductor element 13 is bonded to the third die pad 45 by a conductive bonding material (not shown). In this embodiment, the plurality of low-voltage output terminals 53 are appropriately electrically connected to the low-voltage drive unit 131 of the third semiconductor element 13. Of the plurality of low-voltage output terminals 53, the terminal that is located furthest to the y2 side in the y direction is The low-voltage output terminal 53b is connected by a pad portion 532 to a position closer to the x1 side in the x direction of the end portion of the third die pad 45 on the y2 side in the y direction, and supports the third die pad 45.

[0105] In this embodiment, the second semiconductor element 12 also includes the insulating portion 122, thereby improving the dielectric strength between the input circuit and the high-voltage output circuit. Also in this embodiment, the conductive support member 2 is not exposed from the fourth side surface 76, thereby increasing the insulation distance between the multiple input terminals 51 and the multiple high-voltage output terminals 52. Furthermore, the sealing resin 7 includes the first groove portion 76a, thereby increasing the creepage distance from the input terminal 51b to the high-voltage output terminal 52a via the fourth side surface 76. Furthermore, the surface roughness of each of the top surface 71, the bottom surface 72, the first region 731 of the first side surface 73, the second region 732 of the first side surface 73, the fourth region 741 of the second side surface 74, and the fifth region 742 of the second side surface 74 is greater than the surface roughness of the third region 733 of the first side surface 73 and the sixth region 743 of the second side surface 74. Therefore, the creepage distance from the input terminal 51b to the high-voltage output terminal 52a via the top surface 71 or the bottom surface 72 can be further increased. Also in this embodiment, since the first inter-terminal distance L1 is at least five times the second inter-terminal distance L2, the lead portions 521 of the high-voltage output terminals 52 and the lead portions 531 of the low-voltage output terminals 53 are sufficiently separated in the y direction. Furthermore, since the conductive support member 2 is not exposed between the high-voltage output terminal 52b and the low-voltage output terminal 53a on the second side surface 74, the insulation distance between the high-voltage output terminals 52 and the low-voltage output terminals 53 is increased. Furthermore, since the sealing resin 7 has the second groove portion 74a, the creepage distance from the high-voltage output terminal 52b along the second side surface 74 of the sealing resin 7 to the low-voltage output terminal 53a is increased. These factors contribute to further improving the dielectric strength of the semiconductor device A80.

[0106] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways.

[0107] [Appendix 1] a conductive support member including a first die pad and a second die pad having a potential relatively different from that of the first die pad; a first semiconductor element mounted on the first die pad; a second semiconductor element mounted on the second die pad; a sealing resin that covers at least a portion of the conductive support member, the first semiconductor element, and the second semiconductor element; Equipped with The first semiconductor element is a control unit that configures an input side circuit together with the first die pad; a low-voltage driving unit that constitutes a low-voltage output circuit that transmits and receives signals to and from the input circuit, the second semiconductor element includes a high-voltage driving unit that, together with the second die pad, constitutes a high-voltage output circuit that transmits and receives signals to and from the input circuit; The conductive support member is a plurality of input terminals arranged along a first direction perpendicular to the thickness direction, at least one of which is electrically connected to the input circuit; a plurality of high-voltage output terminals arranged along the first direction, at least one of which is electrically connected to the high-voltage output circuit; a plurality of low-voltage output terminals arranged along the first direction on one side of the plurality of high-voltage output terminals, at least one of which is electrically connected to the low-voltage output circuit; further comprising The sealing resin is located on one side in a second direction perpendicular to the thickness direction and the first direction. and has a first side surface from which the plurality of input side terminals protrude, a second side surface located on the other side in the second direction and from which the plurality of high voltage output side terminals and the plurality of low voltage output side terminals protrude, a third side surface located on one side in the first direction and connected to the first side surface and the second side surface, and a fourth side surface located on the other side in the first direction and connected to the first side surface and the second side surface, the conductive support member is not exposed from the fourth side surface; Semiconductor device. [Appendix 2] the second semiconductor element further includes an insulating section that relays transmission and reception of signals between the input side circuit and the high voltage output side circuit and insulates the input side circuit and the high voltage output side circuit from each other. 2. The semiconductor device according to claim 1. [Appendix 3] the first semiconductor element further includes an insulating section that relays transmission and reception of signals between the input side circuit and the high voltage output side circuit and insulates the input side circuit and the high voltage output side circuit from each other. 2. The semiconductor device according to claim 1. [Appendix 4] the conductive support member is not exposed from the third side surface; 4. The semiconductor device according to any one of claims 1 to 3. [Appendix 5] the plurality of high-voltage output terminals include an inner high-voltage output terminal arranged on the most one side in the first direction, the plurality of low-voltage output terminals include an inner low-voltage output terminal arranged on the other side furthest in the first direction, 5. The semiconductor device according to any one of claims 1 to 4. [Appendix 6] a first inter-terminal distance, which is the distance between a portion of the inner high-voltage output terminal exposed from the sealing resin and a portion of the inner low-voltage output terminal exposed from the sealing resin, is five times or more a second inter-terminal distance, which is the maximum value of the distance between portions of two adjacent high-voltage output terminals exposed from the sealing resin; 6. The semiconductor device according to claim 5. [Appendix 7] the conductive support member is not exposed between the inner high-voltage output terminal and the inner low-voltage output terminal on the second side surface; 7. The semiconductor device according to claim 5 or 6. [Appendix 8] the plurality of high-voltage output terminals include only one support terminal connected to the second die pad; The support terminal is different from the inner high voltage output terminal. 8. The semiconductor device according to any one of appendixes 5 to 7. [Appendix 9] The plurality of high voltage output terminals is three, The plurality of low voltage output terminals is three. 9. The semiconductor device according to any one of appendices 1 to 8. [Appendix 10] the sealing resin further includes a first groove recessed from the fourth side surface in the first direction and extending in the thickness direction. 10. The semiconductor device according to any one of appendices 1 to 9. [Appendix 11] the sealing resin further includes a first protruding portion protruding in the first direction from the fourth side surface and extending in the thickness direction. 11. The semiconductor device according to any one of claims 1 to 10. [Appendix 12] the sealing resin further includes a second groove portion recessed in the second direction from the second side surface and extending in the thickness direction; The second groove portion is disposed between the plurality of high-voltage output terminals and the plurality of low-voltage output terminals in the first direction. 12. The semiconductor device according to any one of claims 1 to 11. [Appendix 13] the sealing resin further includes a second protruding portion protruding in the second direction from the second side surface and extending in the thickness direction; the second protrusion is disposed between the plurality of high-voltage output terminals and the plurality of low-voltage output terminals in the first direction. 13. The semiconductor device according to any one of appendices 1 to 12. [Appendix 14] the sealing resin further has a top surface facing a side where the first semiconductor element is located with respect to the first die pad in the thickness direction, and a bottom surface facing an opposite side to the top surface in the thickness direction, the first side surface includes a first region connected to the top surface, a second region connected to the bottom surface, and a third region connected to the first region and the second region and from which the plurality of input terminals protrude; The surface roughness of each of the top surface, the bottom surface, the first region, and the second region is greater than the surface roughness of the third region. 14. The semiconductor device according to any one of claims 1 to 13. [Appendix 15] the second side surface includes a fourth region connected to the top surface, a fifth region connected to the bottom surface, and a sixth region connected to the fourth region and the fifth region and from which the plurality of high-voltage output terminals and the plurality of low-voltage output terminals protrude, The surface roughness of each of the top surface, the bottom surface, the fourth region, and the fifth region is greater than the surface roughness of the sixth region. 15. The semiconductor device according to claim 14. [Appendix 16] 16. The semiconductor device according to claim 14, wherein the surface roughness of each of the top surface and the bottom surface is 5 μmRz or more and 20 μmRz or less. [Explanation of symbols]

[0108] A10, A20, A30, A40, A50, A60, A70, A80: Semiconductor device 11: First semiconductor element 111: Control unit 112: Low voltage drive unit 113: Insulation part 12: Second semiconductor element 121: High voltage drive unit 122: Insulation part 13: Third semiconductor element 131: Low voltage drive unit 2: Conductive support member 3: First die pad 31: First main surface 32: First back side 4: Second die pad 41: Second main surface 42: Second back side 45: 3rd die pad 51, 51a, 51b, 51c, 51d: Input terminals 511: Lead section 512: Pad section 52, 52a, 52b, 52c: High voltage output terminals 521: Lead section 522: Pad section 53, 53a, 53b: Low voltage output terminals 531: Lead section 532: Pad section 55: Support Lead 61, 62, 63, 64, 65: Wire 7: Sealing resin 71:Top surface 72: Bottom 73:1st side 731:First area 732:Second area 733: Third area 74:Second side 741: 4th area 742: 5th area 743:6th area 74a: 2nd groove part 74b: Second protrusion 75:Third side 751:7th area 752:8th area 753:9th area 76:Fourth side 761: 10th area 762: 11th area 763: 12th area 76a: First groove 76b: 1st protrusion 81: Lead frame 81A: Main surface 81B: Back 811: Outer frame 812A: 1st die pad 812B: Second die pad 813: 1st lead 814: Second Lead 815: Third Lead 816:Dambar

Claims

1. a conductive support member including a first die pad and a second die pad having a potential relatively different from that of the first die pad; a first semiconductor element mounted on the first die pad; a second semiconductor element mounted on the second die pad; a sealing resin having a first side surface that is provided along a first direction perpendicular to the thickness direction and exposes a portion of the conductive support member, a second side surface that is provided on the opposite side of the first side surface along the first direction and exposes a portion of the conductive support member, a third side surface that is provided along a second direction perpendicular to the thickness direction and the first direction, and a fourth side surface that is provided on the opposite side of the third side surface along the second direction; Equipped with the third side surface and the fourth side surface are formed only by the sealing resin, the conductive support member exposed from the first side surface is an input terminal, The conductive support members exposed from the second side surface are high-voltage output terminals and low-voltage output terminals. Semiconductor device.

2. the first semiconductor element has a control unit that configures an input side circuit together with the first die pad, and a low-voltage drive unit that configures a low-voltage output side circuit that transmits and receives signals to and from the input side circuit, the second semiconductor element has a high-voltage driving section that, together with the second die pad, constitutes a high-voltage output circuit that transmits and receives signals to and from the input circuit; The semiconductor device according to claim 1 .

3. the second semiconductor element further includes an insulating section that relays transmission and reception of signals between the input side circuit and the high voltage output side circuit and insulates the input side circuit and the high voltage output side circuit from each other. The semiconductor device according to claim 2 .

4. the first semiconductor element further includes an insulating section that relays transmission and reception of signals between the input side circuit and the high-voltage output side circuit and insulates the input side circuit and the high-voltage output side circuit from each other. The semiconductor device according to claim 2 .

5. 5. The semiconductor device according to claim 1, wherein the fourth side surface of the sealing resin includes a first groove portion extending in the thickness direction.

6. the fourth side surface of the sealing resin includes a first protruding portion extending in the thickness direction; 5. The semiconductor device according to claim 1.

7. the second side surface of the sealing resin includes a second groove portion extending in the thickness direction, The second groove portion is disposed between the high-voltage output terminal and the low-voltage output terminal in the first direction.

7. The semiconductor device according to claim 1.

8. the second side surface of the sealing resin includes a second protruding portion extending in the thickness direction, the second protrusion is disposed between the high-voltage output terminal and the low-voltage output terminal in the first direction.

7. The semiconductor device according to claim 1.

9. the sealing resin further has a top surface facing a side where the first semiconductor element is located with respect to the first die pad in the thickness direction, and a bottom surface facing an opposite side to the top surface in the thickness direction, the first side surface includes a first region connected to the top surface, a second region connected to the bottom surface, and a third region connected to the first region and the second region and from which the input terminal protrudes, the surface roughness of each of the top surface, the bottom surface, the first region, and the second region is greater than the surface roughness of the third region; 9. The semiconductor device according to claim 1.

10. the second side surface includes a fourth region connected to the top surface, a fifth region connected to the bottom surface, and a sixth region connected to the fourth region and the fifth region and from which the high-voltage output terminal and the low-voltage output terminal protrude, the surface roughness of each of the top surface, the bottom surface, the fourth region, and the fifth region is greater than the surface roughness of the sixth region; The semiconductor device according to claim 9 .

11. 11. The semiconductor device according to claim 9, wherein the surface roughness of each of the top surface and the bottom surface is not less than 5 [mu]mRz and not more than 20 [mu]mRz.

12. the conductive support member is not exposed on the second side surface between the high-voltage output terminal and the low-voltage output terminal; 12. The semiconductor device according to claim 1.

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