TEG device and low-temperature intrinsic characteristic analysis method for quantitatively evaluating the influence of high-k based passivation layers on the electrical characteristics of 2D FET structures

Abstract

This disclosure provides a TEG device and a low-temperature intrinsic characteristic analysis method for evaluating the quantitative impact of high-k based passivation layers on the electrical characteristics of devices in 2D FET structures. [Solution] For analysis of FET devices including a channel made of a two-dimensional material and a passivation layer made of a high-k material, a first FET device in which the passivation layer is disposed in a first direction relative to the channel and a second FET device in which the passivation layer is disposed in a second direction different from the first direction relative to the channel can be prepared. The present disclosure can quantitatively evaluate the effect of the shape of the passivation layer on the FET device by comparing a first amount of charge trapped in the passivation layer of the first FET device with a second amount of charge trapped in the passivation layer of the second FET device. The present disclosure can quantitatively analyze mobility changes in the channel based on the rate of increase in resistance using an equivalent circuit based on the shape of the passivation layer for each of the first and second FET devices.

Description

[Technical Field]

[0001] This disclosure relates to a TEG (test element group) device and a method for analyzing intrinsic characteristics at low temperatures that can quantitatively evaluate the effect of the pattern shape of a high-k-based passivation layer on the electrical characteristics of a FET (field effect transistor) structure that uses a two-dimensional material as a channel. This patent was supported by the Ministry of Science and ICT and the Korea Research Foundation (RS-2023-00280841). [Background technology]

[0002] To overcome the physical scaling limitations of silicon-based devices, various materials have been studied as channel materials. Among them, two-dimensional materials have attracted much research because of their advantages of thickness close to two-dimensional and fewer interface traps. To improve the performance of devices using two-dimensional materials as channels, a passivation layer is essential. Therefore, it is necessary to quantitatively analyze how the electrical properties change depending on the shape of the passivation layer. Summary of the Invention [Problem to be solved by the invention]

[0003] This disclosure presents a method for quantitatively evaluating the characteristics of a TEG element by DC measurement at low temperatures, eliminating the influence of temperature.

[0004] This disclosure provides a TEG device and a low-temperature intrinsic characteristic analysis method for evaluating the quantitative impact of high-k based passivation layers on the electrical characteristics of devices in 2D FET structures. [Means for solving the problem]

[0005] In the present disclosure, a method of operating an electronic device for analyzing a FET element including a channel made of a two-dimensional material and a passivation layer made of a high-k material may include the steps of preparing a first FET element in which the passivation layer is disposed in a first direction relative to the channel, and a second FET element in which the passivation layer is disposed in a second direction relative to the channel that is different from the first direction, and comparing a first amount of charge trapped in the passivation layer of the first FET element with a second amount of charge trapped in the passivation layer of the second FET element to evaluate a quantitative effect of the shape of the passivation layer on the FET element.

[0006] In the present disclosure, a method for operating an electronic device further includes the steps of measuring a drain voltage and a drain current at low temperature for each of a first FET element and a second FET element; detecting a resistance value in the passivation layer from the drain voltage and the drain current using an equivalent circuit based on the shape of the passivation layer for each of the first FET element and the second FET element; and quantitatively analyzing a mobility change in the channel for each of the first FET element and the second FET element based on a rate of increase in resistance, where the rate of increase in resistance may indicate a ratio of the resistance value of a region of the channel covered by the passivation layer to the resistance value of a region of the channel exposed from the passivation layer.

[0007] In the present disclosure, an electronic device for analyzing a FET element including a channel made of a two-dimensional material and a passivation layer made of a high-k material includes a memory and a processor connected to the memory and configured to execute at least one instruction word stored in the memory, wherein the processor may be configured to prepare a first FET element in which the passivation layer is disposed in a first direction relative to the channel, and a second FET element in which the passivation layer is disposed in a second direction relative to the channel that is different from the first direction, and to compare a first amount of charge trapped in the passivation layer of the first FET element with a second amount of charge trapped in the passivation layer of the second FET element to evaluate a quantitative effect of the shape of the passivation layer on the FET element.

[0008] In the present disclosure, the processor is configured to measure the drain voltage and drain current at low temperatures for each of the first FET element and the second FET element, detect the resistance in the passivation layer for each of the first FET element and the second FET element from the drain voltage and drain current using an equivalent circuit based on the shape of the passivation layer, and quantitatively analyze the mobility change in the channel for each of the first FET element and the second FET element based on the rate of increase in resistance, where the rate of increase in resistance may indicate the ratio of the resistance of the region of the channel covered by the passivation layer to the resistance of the region of the channel exposed from the passivation layer. [Effects of the Invention]

[0009] According to the present disclosure, by quantitatively comparing and analyzing the influence of the shape of the passivation layer, which is essential for FET devices that use two-dimensional materials as channels, on the electrical properties of the FET device, it is possible to find the shape of the passivation layer that has the optimal electrical properties, which leads to the optimization of the FET device. [Brief explanation of the drawings]

[0010] [Figure 1]1A-1C are schematic diagrams illustrating a first FET device according to various embodiments. [Figure 2] 10A-10C are schematic diagrams illustrating a second FET device according to various embodiments. [Figure 3] 1A-1C are schematic diagrams illustrating various embodiments of an electronic device. [Figure 4] 1A-1C are diagrams that schematically illustrate methods of operation of electronic devices, according to various embodiments. [Figure 5] FIG. 5 is a diagram illustrating in detail the intrinsic characteristic analysis step of FIG. 4. [Figure 6] FIG. 5 is a detailed diagram of the quantitative impact assessment step of FIG. 4. DETAILED DESCRIPTION OF THE INVENTION

[0011] This disclosure presents a TEG device and a method for analyzing intrinsic characteristics at low temperatures that can quantitatively evaluate the effect of the pattern shape of a high-k-based passivation layer on the electrical characteristics of a FET structure using a two-dimensional material as a channel. To quantitatively analyze the effect of the pattern shape, this disclosure uses DC measurements at low temperatures and uses resistance and capacitance equivalent circuits that vary depending on the structure of the passivation layer.

[0012] Various embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0013] Figure 1 is a diagram illustrating a first FET element 100 according to various embodiments. Figure 2 is a diagram illustrating a second FET element 200 according to various embodiments. In Figures 1 and 2, (a) is a cross-sectional view, (b) is a plan view, and (c) is an equivalent circuit diagram.

[0014] 1 and 2, the first FET element 100 and the second FET element 200 may include source electrodes 110 and 210, drain electrodes 120 and 220, channels 130 and 230, gate electrodes 140 and 240, insulating layers 150 and 250, and passivation layers 160 and 260, respectively. The source electrodes 110 and 210 may supply charges. The drain electrodes 120 and 220 may receive charges. The channels 130 and 230 may serve as paths through which charges move and may be formed of two-dimensional materials. The gate electrodes 140 and 240 may apply a voltage to turn on the channels 130 and 230. The insulating layers 150 and 250 may function as gate insulating films, prevent leakage current to the gate electrodes 140 and 240, and provide capacitance. The passivation layers 160, 260 may be provided to improve device performance and protect the two-dimensional material of the channels 130, 230, and may be formed of a high-k material.

[0015] In various embodiments, the first FET element 100 and the second FET element 200 may be implemented in the same manner, except for the shape of the passivation layers 160, 260. As shown in FIG. 1 , in the first FET element 100, the passivation layer 160 may be disposed in a first direction relative to the channel 130. Meanwhile, as shown in FIG. 2 , in the second FET element 200, the passivation layer 260 may be disposed in a second direction different from the first direction relative to the channel 230. In some embodiments, the first direction may be defined as a vertical direction extending between and parallel to the source electrodes 110, 210 and the drain electrodes 120, 220, and the second direction may be defined as a horizontal direction extending between and parallel to the source electrodes 110, 210 and the drain electrodes 120, 220.

[0016] FIG. 3 is a schematic diagram of an electronic device 300 according to various embodiments.

[0017] Referring to FIG. 3 , electronic device 300 is for analyzing a FET device including a channel made of a two-dimensional material and a passivation layer made of a high-k material, and may include at least one of a camera module 310, a communication module 320, an input module 330, an output module 340, a measurement module 350, a memory 360, or a processor 370. In some embodiments, at least one of the components of electronic device 300 (e.g., camera module 310, communication module 320) may be omitted, or at least one other component may be added. In some embodiments, at least two of the components of electronic device 300 may be implemented as a single integrated circuit. In some embodiments, the components of electronic device 300 may be distributed across at least two devices, where these devices may be communicatively connected to each other.

[0018] The camera module 310 may capture an image in the electronic device 300. Here, the camera module 310 may be, but is not limited to, an RGB camera. For example, the camera module 310 may include at least one of a lens, an image sensor, an image signal processor, and a flash.

[0019] The communication module 320 may enable the electronic device 300 to communicate with an external device (not shown). The communication module 320 may establish a communication channel between the electronic device 300 and the external device and communicate with the external device via the communication channel. For example, the external device may include at least one of an electronic device, a base station, a server, or a satellite. The communication module 320 may include at least one of a wired communication module and a wireless communication module. For example, the wireless communication module may communicate with the external device via at least one of a telecommunications network and a short-range communication network.

[0020] The input module 330 may input commands to be used by at least one component of the electronic device 300. The input module 330 may include at least one of an input unit configured for a user to directly input commands or data to the electronic device 300, or a sensor unit configured to sense the surrounding environment and generate data. For example, the input unit may include at least one of a microphone, a mouse, or a keyboard. In some embodiments, the input unit may include at least one of touch circuitry configured to detect a touch or a sensor circuit configured to measure the intensity of a force generated by a touch.

[0021] The output module 340 may output information outside the electronic device 300. The output module 340 may include at least one of a display module that visually outputs information or an audio module that audibly outputs information. For example, the display module may include at least one of a display, a holographic device, or a projector. In one embodiment, the display module may be combined with at least one of the touch circuitry or sensor circuitry of the input module 330 and implemented as a touch screen. For example, the audio module may include at least one of a speaker or a receiver.

[0022] The measurement module 350 may perform measurements on the FET device, and to do so, the measurement module 350 may contact at least one point on the FET device.

[0023] Memory 360 may store various data used by at least one component of electronic device 300. For example, memory 360 may include volatile memory and / or non-volatile memory. The data may include input data or output data for programs or associated instructions. The programs may be stored in memory 360 as software and may include an operating system, middleware, or / and applications.

[0024] The processor 370 may execute a program in the memory 360 and control at least one component of the electronic device 300. This allows the processor 370 to process data or perform calculations. In this case, the processor 370 may execute instructions stored in the memory 360.

[0025] In various embodiments, the processor 370 may evaluate the quantitative effect of the shape of the passivation layer 160, 260 on the FET elements through the first FET element 100, the second FET element 200, and a third FET element (not shown) without a passivation layer. Here, the third FET element may be implemented in the same manner as the first FET element 100 and the second FET element 200, except that the third FET element does not have a passivation layer, i.e., it may include a channel formed of a two-dimensional material. Specifically, the processor 370 may compare the first amount of charge trapped in the passivation layer 160 of the first FET element 100 with the second amount of charge trapped in the passivation layer 260 of the second FET element 200 to evaluate the quantitative effect of the shape of the passivation layer on the FET elements.

[0026] In various embodiments, the processor 370 may analyze the intrinsic characteristics of the passivation layers 160, 260 for the first FET element 100 and the second FET element 200 by using low-temperature (e.g., 100 to 300 K) measurements and an equivalent circuit based on the shapes of the passivation layers 160, 260. Specifically, the processor 370 may detect the resistance values ​​in the passivation layers 160, 260 from the drain voltage and drain current measured at low temperatures using the equivalent circuit based on the shapes of the passivation layers 160, 260 for each of the first FET element 100 and the second FET element 200, and may quantitatively analyze the mobility change in the channels 130, 230 based on the rate of increase in the resistance values.

[0027] FIG. 4 is a diagram that schematically illustrates how electronic device 300 operates, according to various embodiments.

[0028] Referring to FIG. 4 , first, in step 410, a first FET element 100, a second FET element 200, and a third FET element may be prepared. As described above, the first FET element 100 and the second FET element 200 include channels 130, 230 formed of a two-dimensional material and passivation layers 160, 260 formed of a high-k material, and may be implemented in the same manner except for the shapes of the passivation layers 160, 260. In this case, as shown in FIG. 1 , in the first FET element 100, the passivation layer 160 may be disposed in a first direction relative to the channel 130. Meanwhile, as shown in FIG. 2 , in the second FET element 200, the passivation layer 260 may be disposed in a second direction different from the first direction relative to the channel 230. In some embodiments, the first direction may be defined as a vertical direction extending between and parallel to the source electrodes 110, 210 and the drain electrodes 120, 220, and the second direction may be defined as a horizontal direction extending between and parallel to the source electrodes 110, 210 and the drain electrodes 120, 220. Meanwhile, the third FET device may be implemented in the same manner as the first FET device 100 and the second FET device 200, except that it lacks a passivation layer, i.e., it may include a channel formed of a two-dimensional material.

[0029] Next, in step 420, the electronic device 300 may analyze the intrinsic characteristics of the passivation layers 160, 260 for the first FET element 100 and the second FET element 200 using low-temperature measurements and an equivalent circuit based on the shapes of the passivation layers 160, 260. Specifically, the processor 370 may detect the resistance values ​​in the passivation layers 160, 260 from the drain voltage and drain current measured at low temperatures using the equivalent circuit based on the shapes of the passivation layers 160, 260 for each of the first FET element 100 and the second FET element 200, and may quantitatively analyze the mobility change in the channels 130, 230 based on the rate of increase in the resistance values. This will be described in more detail with reference to FIG. 5.

[0030] FIG. 5 shows in detail the intrinsic characteristic analysis step (step 420) of FIG.

[0031] Referring to FIG. 5, in step 521, the processor 370 may measure the drain voltage and drain current for the first FET device 100 and the second FET device 200 at low temperature.

[0032] Next, in step 523, the processor 370 may detect the resistance values ​​(R1 and R2) in the passivation layers 160, 260 from the drain voltage and drain current for the first FET element 100 and the second FET element 200 using an equivalent circuit based on the shape of the passivation layers 160, 260. Here, the resistance values ​​may include the resistance value R1 of the region of the channels 130, 230 that is exposed from the passivation layers 160, 260, and the resistance value R2 of the region of the channels 130, 230 that is covered by the passivation layers 160, 260. In this case, the equivalent circuit of the first FET element 100 may be expressed as the following equation (1), and the equivalent circuit of the second FET element 200 may be expressed as the following equation (2). Therefore, the processor 370 can detect the resistance values ​​R1 and R2 based on the following equations (1) and (2).

[0033]

number

[0034]

number

[0035] where V D is the drain voltage, and I D is the drain current, and R tot may represent the total resistance, R1 the resistance of the region of the channel 130, 230 exposed from the passivation layer 160, 260, and R2 the resistance of the region of the channel 130, 230 covered by the passivation layer 160, 260.

[0036] Next, in step 522, the processor 370 may quantitatively analyze the mobility change in the channels 130, 230 based on the increase rates of the resistance values ​​R1 and R2. Here, the increase rates of the resistance values ​​R1 and R2 may indicate the ratio (i.e., R2 / R1) of the resistance value R2 of the region of the channels 130, 230 covered by the passivation layer 160, 260 to the resistance value R1 of the region of the channels 130, 230 exposed from the passivation layer 160, 260. R1 is 、 Since R1 / R2 represents the resistance of the region of the channel 130, 230 that is exposed through the passivation layer 160, 260, and R2 represents the resistance of the region of the channel 130, 230 that is covered by the passivation layer 160, 260, the passivation layer 160, 260 increases R2, increasing R2 / R1, which leads to an increase in overall resistance. Increased resistance means that electrons encounter more hindrance when moving from the source electrode 110, 210 to the drain electrode 120, 220, which may mean a decrease in mobility, which indicates how efficiently electrons move within the channel 130, 230. Ultimately, the decrease in mobility may result in a decrease in current (current is proportional to mobility) according to Ohm's Law, which may result in performance degradation at the product level. You may then return to FIG. 4 and proceed to step 430.

[0037] 4, in step 430, electronic device 300 may evaluate the quantitative effect of the shape of passivation layers 160, 260 on the FET elements through first FET element 100, second FET element 200, and a third FET element (not shown) that does not have a passivation layer. Specifically, processor 370 may compare a first amount of charge trapped in passivation layer 160 of first FET element 100 with a second amount of charge trapped in passivation layer 260 of second FET element 200 to evaluate the quantitative effect of the shape of passivation layers 160, 260 on the FET elements. This will be described in more detail with reference to FIG. 6.

[0038] FIG. 6 shows the quantitative impact assessment step (step 430) of FIG. 4 in more detail.

[0039] 6, in step 631, processor 370 may measure the capacitance-voltage characteristics of each of first FET element 100, second FET element 200, and third FET element. Next, in step 633, processor 370 may use the capacitance-voltage characteristics to detect the subthreshold swing (SS) of each of first FET element 100, second FET element 200, and third FET element. Specifically, processor 370 may detect the subthreshold swing of the third FET element as shown in the following equation (3). Meanwhile, processor 370 may detect the subthreshold swing of each of first FET element 100 and second FET element 200 as shown in the following equation (4).

[0040]

number

[0041]

number

[0042] Here, SS1 is the subthreshold swing of the third FET element, SS2 is the subthreshold swing of the first FET element 100 or the second FET element 200, kT is the Boltzmann constant, and C B is the capacitance of the depletion region in the channel 130, 230, and C OXmay represent the capacitance of the insulating layer 150, 250, i.e., the gate insulating film, C1 may represent the capacitance of the interface with the channel 130, 230 when the passivation layer 160, 260 is not present, and C2 may represent the capacitance of the interface with the channel 130, 230 when the passivation layer 160, 260 is present, i.e., the capacitance of the interface between the channel 130, 230 and the passivation layer 160, 260. More specifically, the depletion region refers to a region where no charge exists due to an electric field when a voltage is applied to the gate electrode 140, 240 and drain electrode 120, 220 of the first FET element 100, the second FET element 200, or the third FET element, and may be formed, for example, in the end and bottom regions of the channel 130, 230. In such cases, a source electrode 110, 210-depletion region-gate electrode 140, 240 structure is created and can be applied as a capacitance in the first FET element 100, the second FET element 200, or the third FET element.

[0043] Next, in step 635, processor 370 may compare the subthreshold swings of the first FET element 100 and the third FET element to detect a first amount of charge trapped in the passivation layer 160 of the first FET element 100. Specifically, processor 370 may detect the first amount of charge by the ratio of the subthreshold swing of the first FET element 100 to the subthreshold swing of the third FET element (i.e., SS2 / SS1). Meanwhile, in step 637, processor 370 may compare the subthreshold swings of the second FET element 200 and the third FET element to detect a second amount of charge trapped in the passivation layer 260 of the second FET element 200. Specifically, processor 370 may detect the second amount of charge by the ratio of the subthreshold swing of the second FET element 200 to the subthreshold swing of the third FET element (i.e., SS2 / SS1). In this case, the ratio of the subthreshold swing of the first FET element 100 or the second FET element 200 to the subthreshold swing of the third FET element (ie, SS2 / SS1) may be expressed as the following equation (5).

[0044]

number

[0045] Here, α represents the difference between C2 and C1 and may represent the additional capacitance generated by the passivation layers 160, 260. More specifically, the more traps there are at the interface between the passivation layers 160, 260 and the channels 130, 230, the more additional capacitance α is formed, and C2 may increase compared to C1. Therefore, as shown in Equation (5) above, SS2 increases compared to SS1, and this increase allows for quantitative comparison of the amount of charge trapped at the interface between the passivation layers 160, 260 and the channels 130, 230.

[0046] Next, in step 639, the processor 370 may compare the first charge amount with the second charge amount to evaluate a quantitative effect of the shape of the passivation layers 160, 260 on the FET element. At this time, the processor 370 may compare and analyze the first charge amount with the second charge amount according to the shape of the passivation layers 160, 260, and compare parameter values ​​according to the shape of the passivation layers 160, 260.

[0047] In summary, the present disclosure provides an electronic device 100 and method of operation for analysis of FET devices that include channels 130, 230 of two-dimensional materials and passivation layers 160, 260 of high-k materials.

[0048] In the present disclosure, a method for operating an electronic device 100 may include the steps of preparing a first FET element 100 in which a passivation layer 160 is disposed in a first direction relative to a channel 130, and a second FET element 200 in which a passivation layer 260 is disposed in a second direction relative to a channel 230 that is different from the first direction (step 410), and evaluating the quantitative effect of the shape of the passivation layers 160, 260 on the FET elements by comparing a first amount of charge trapped in the passivation layer 160 in the first FET element 100 with a second amount of charge trapped in the passivation layer 260 in the second FET element 200 (step 430).

[0049] In the present disclosure, the method for operating the electronic device 100 includes steps of measuring the drain voltage and drain current at low temperatures for each of the first FET element 100 and the second FET element 200 (steps 420 and 521); detecting the resistance in the passivation layers 160 and 260 from the drain voltage and drain current for each of the first FET element 100 and the second FET element 200 using an equivalent circuit based on the shape of the passivation layers 160 and 260 (steps 420 and 523); and quantitatively analyzing the mobility change in the channels 130 and 230 for each of the first FET element 100 and the second FET element 200 based on the rate of increase in resistance (steps 420 and 525). The rate of increase in resistance may indicate the ratio of the resistance of the region of the channels 130 and 230 covered by the passivation layers 160 and 260 to the resistance of the region of the channels 130 and 230 exposed from the passivation layers 160 and 260.

[0050] In the present disclosure, the equivalent circuit of the first FET element 100 may be expressed as in formula (1), and the equivalent circuit of the second FET element 200 may be expressed as in formula (2).

[0051] In the present disclosure, the method of operating the electronic device 100 may further include the step of providing a third FET element including a channel.

[0052] In the present disclosure, the step of evaluating the quantitative effect (step 430) may include the steps of measuring the capacitance-voltage characteristics of the first FET element 100, the second FET element 200, and the third FET element, respectively (step 631), and detecting the subthreshold swings of the first FET element 100, the second FET element 200, and the third FET element, respectively (step 633), comparing the subthreshold swings of the first FET element 100 and the third FET element to detect a first amount of charge of the first FET element 100 (step 635), comparing the subthreshold swings of the second FET element 200 and the third FET element to detect a second amount of charge of the second FET element 200 (step 637), and comparing the first amount of charge and the second amount of charge to evaluate the quantitative effect (step 639).

[0053] In the present disclosure, the subthreshold swing of the third FET element may be detected as in equation (3), and the subthreshold swing of each of the first FET element 100 and the second FET element 200 may be detected as in equation (4).

[0054] In the present disclosure, detecting the first amount of charge (Step 635) may include detecting the first amount of charge by a ratio of the sub-threshold swing of the first FET device 100 to the sub-threshold swing of the third FET device.

[0055] In the present disclosure, detecting the second amount of charge (Step 637) may include detecting the second amount of charge by a ratio of the sub-threshold swing of the second FET device 100 to the sub-threshold swing of the third FET device.

[0056] In the present disclosure, the first direction may be a vertical direction extending between the source electrodes 110, 210 and the drain electrodes 120, 220, and parallel to the source electrodes 110, 210 and the drain electrodes 120, 220, and the second direction may be a horizontal direction extending between the source electrodes 110, 210 and the drain electrodes 120, 220, and parallel to the source electrodes 110, 210 and the drain electrodes 120, 220.

[0057] In the present disclosure, the electronic device 100 includes a memory 360 and a processor 370 connected to the memory 360 and configured to execute at least one instruction stored in the memory 360, and the processor 370 may be configured to prepare a first FET element 100 in which the passivation layer 160 is arranged in a first direction relative to the channel 130, and a second FET element 200 in which the passivation layer 260 is arranged in a second direction relative to the channel 230 that is different from the first direction, and to compare a first amount of charge trapped in the passivation layer 160 in the first FET element 100 with a second amount of charge trapped in the passivation layer 260 in the second FET element 200 to evaluate a quantitative effect of the shape of the passivation layers 160, 260 on the FET elements.

[0058] In the present disclosure, the processor 370 is configured to measure the drain voltage and drain current at low temperatures for each of the first FET element 100 and the second FET element 200, detect the resistance in the passivation layers 160, 260 from the drain voltage and drain current for each of the first FET element 100 and the second FET element 200 using an equivalent circuit based on the shape of the passivation layers 160, 260, and quantitatively analyze the mobility change in the channel for each of the first FET element 100 and the second FET element 200 based on the rate of increase in resistance, which may indicate the ratio of the resistance of the region of the channel 130, 230 covered by the passivation layers 160, 260 to the resistance of the region of the channel 130, 230 exposed from the passivation layers 160, 260.

[0059] In the present disclosure, the processor 370 may be configured to prepare a third FET element including a channel, measure capacitance-voltage characteristics for the first FET element 100, the second FET element 200, and the third FET element, respectively, detect subthreshold swings of the first FET element 100, the second FET element 200, and the third FET element, respectively, compare the subthreshold swings of the first FET element 100 and the third FET element to detect a first amount of charge for the first FET element 100, compare the subthreshold swings of the second FET element 200 and the third FET element to detect a second amount of charge for the second FET element 200, and compare the first amount of charge and the second amount of charge to evaluate the quantitative effect.

[0060] According to the present disclosure, by quantitatively comparing and analyzing the influence of the shape of the passivation layer, which is essential for FET elements that use two-dimensional materials as channels, on the electrical properties of the FET elements, it is possible to find the shape of the passivation layer that has the optimal electrical properties, which leads to the optimization of the FET elements.

[0061] The above-described devices may be implemented using hardware components, software components, and / or a combination of hardware and software components. For example, the devices and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or various devices capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the OS. The processing device may also access, record, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, a single processing device may be described. However, those skilled in the art will understand that a processing device may include multiple processing elements and / or multiple types of processing elements. For example, a processing device may include multiple processors or one processor and one controller. Other processing configurations, such as parallel processors, are also possible.

[0062] Software may include computer programs, codes, instructions, or a combination of one or more of these, which may configure a processing device to operate as desired or may independently or collectively instruct the processing device. The software and / or data may be embodied in any type of machine, component, physical device, computer storage medium, or device to be interpreted by the processing device or to provide instructions or data to the processing device. The software may be distributed and stored and executed in a distributed manner on computer systems connected by a network. The software and data may be stored on one or more computer-readable storage media.

[0063] Methods according to embodiments may be implemented in the form of program instructions executable by various computer means and recorded on a computer-readable medium. In this case, the medium may continuously record a computer-executable program or may temporarily record the program for execution or download. The medium may be various recording or storage means in the form of a single piece of hardware or multiple pieces of hardware combined together. It may be a medium directly connected to a computer system or distributed over a network. Examples of media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and media configured to record program instructions, such as ROMs, RAMs, and flash memories. Other examples of media include recording media or storage media managed by app stores that distribute applications, or by websites or servers that provide or distribute various software.

[0064] The various embodiments described herein and the terminology used therein are not intended to limit the technology described herein to a particular embodiment, but should be understood to encompass various modifications, equivalents, and / or alternatives of the relevant embodiment. In connection with the description of the drawings, like reference numerals are used to refer to like elements. A singular expression may also include a plural expression unless the context clearly dictates otherwise. In this specification, expressions such as "A or B," "at least one of A and / or B," "A, B, or C," or "at least one of A, B, and / or C" may include all possible combinations of the listed items. Expressions such as "first," "second," "first," or "second" modify the corresponding element, regardless of order or importance, and are used merely to distinguish one element from other elements, not to limit the corresponding element. When a (e.g., first) component is described as being "(functionally or communicatively) coupled" or "connected" to another (e.g., second) component, such component may be directly coupled to such other component or may be coupled through another component (e.g., third component).

[0065] According to various embodiments, each of the components described above (e.g., modules or programs) may include one or more entities. According to various embodiments, one or more of the components or steps described above may be omitted, or one or more other components or steps may be added. Alternatively or additionally, multiple components (e.g., modules or programs) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in a manner that is the same as or similar to that performed by the corresponding component among the multiple components before integration. According to various embodiments, the steps performed by a module, program, or other component may be performed sequentially, in parallel, iteratively, or heuristically, and one or more of the steps may be performed in a different order, omitted, or one or more other steps may be added. [Explanation of symbols]

[0066] 300 Electronic equipment 310 Camera Module 320 Communication Module 330 Input Module 340 Output Module 350 Measurement Module 360 memory 370 processor

Claims

1. 1. A method of operating an electronic device for analysis of a FET device including a channel made of a two-dimensional material and a passivation layer made of a high-k material, comprising: providing a first FET element, the passivation layer being disposed in a first direction relative to the channel, and a second FET element, the passivation layer being disposed in a second direction relative to the channel, the second direction being different from the first direction; comparing a first amount of charge trapped in the passivation layer of the first FET element with a second amount of charge trapped in the passivation layer of the second FET element to evaluate a quantitative effect of the shape of the passivation layer on the FET element; Including, A method for operating an electronic device.

2. measuring a drain voltage and a drain current for each of the first and second FET devices at a low temperature; detecting a resistance value in the passivation layer from the drain voltage and the drain current using an equivalent circuit based on the shape of the passivation layer for each of the first FET element and the second FET element; quantitatively analyzing a mobility change in the channel based on the rate of increase in resistance value for each of the first FET element and the second FET element; further comprising the increase rate of the resistance value indicates a ratio of the resistance value of a region of the channel that is covered by the passivation layer to the resistance value of a region of the channel that is exposed from the passivation layer; A method for operating the electronic device of claim 1.

3. The equivalent circuit of the first FET element is expressed as the following equation (1): The equivalent circuit of the second FET element is expressed as the following equation (2): [Equation 1] [Equation 2] Here, V Ｄ is the drain voltage, I Ｄ is the drain current, R ｔｏｔ is the total resistance, R １ is the resistance value of the region of the channel exposed from the passivation layer, R ２ represents the resistance of the region of the channel covered by the passivation layer, A method for operating an electronic device according to claim 2.

4. Providing a third FET device including said channel. further comprising The step of assessing the quantitative effect comprises: measuring capacitance-voltage characteristics of the first FET element, the second FET element, and the third FET element, respectively, to detect subthreshold swings of the first FET element, the second FET element, and the third FET element, respectively; comparing the subthreshold swings of the first FET device and the third FET device to detect the first amount of charge on the first FET device; comparing the subthreshold swings of the second FET device and the third FET device to detect the second amount of charge on the second FET device; comparing the first charge amount to the second charge amount to assess the quantitative effect; Including, A method for operating the electronic device of claim 1.

5. The subthreshold swing of the third FET device is detected as follows: The subthreshold swings of the first and second FET devices are detected as follows: [Equation 3] [Equation 4] Here, SS １ is the subthreshold swing of the third FET device, SS ２ is the subthreshold swing of the first FET element or the second FET element, kT is the Boltzmann constant, C Ｂ is the capacitance of the depletion region, and C ＯＸ is the capacitance of the insulating layer, C １ is the interfacial capacitance when there is no passivation layer, and C ２ represents the interfacial capacitance when the passivation layer is present, A method for operating an electronic device according to claim 4.

6. The step of detecting the first amount of charge includes: detecting the first amount of charge based on a ratio of a subthreshold swing of the first FET device to a subthreshold swing of the third FET device; The step of detecting the second amount of charge includes: detecting the second amount of charge based on a ratio of a subthreshold swing of the second FET device to a subthreshold swing of the third FET device; A method for operating an electronic device according to claim 4.

7. the first direction is a vertical direction extending between the source electrode and the drain electrode and parallel to the source electrode and the drain electrode; the second direction is a direction extending from the source electrode across the drain electrode between the source electrode and the drain electrode; A method for operating the electronic device of claim 1.

8. An electronic device for analyzing a FET device including a channel made of a two-dimensional material and a passivation layer made of a high-k material, Memory and a processor coupled to the memory and configured to execute at least one instruction stored in the memory; Including, The processor: providing a first FET element, the passivation layer of which is disposed in a first direction relative to the channel, and a second FET element, the passivation layer of which is disposed in a second direction relative to the channel, the second direction being different from the first direction; and comparing a first amount of charge trapped in the passivation layer of the first FET element with a second amount of charge trapped in the passivation layer of the second FET element to evaluate a quantitative effect of the shape of the passivation layer on the FET element. electronic equipment.

9. The processor: measuring a drain voltage and a drain current at a low temperature for each of the first FET device and the second FET device; detecting a resistance value in the passivation layer from the drain voltage and the drain current using an equivalent circuit based on the shape of the passivation layer for each of the first FET element and the second FET element; a method for quantitatively analyzing a mobility change in the channel based on the rate of increase in the resistance value for each of the first FET element and the second FET element; the increase rate of the resistance value indicates a ratio of the resistance value of a region of the channel that is covered by the passivation layer to the resistance value of a region of the channel that is exposed from the passivation layer; 9. The electronic device of claim 8.

10. The processor: providing a third FET device including the channel; measuring capacitance-voltage characteristics of the first FET element, the second FET element, and the third FET element, respectively, to detect subthreshold swings of the first FET element, the second FET element, and the third FET element, respectively; comparing the subthreshold swings of the first FET device and the third FET device to detect the first amount of charge on the first FET device; comparing the subthreshold swings of the second FET device and the third FET device to detect the second amount of charge on the second FET device; and comparing the first charge amount to the second charge amount to assess the quantitative effect.

9. The electronic device of claim 8.

Images