Semiconductor device and semiconductor device manufacturing method

Abstract

This semiconductor device comprises: a semiconductor substrate; a wiring layer having an electrode pad and formed on a first surface of the semiconductor substrate; a rewiring layer that has wiring electrically connected to the electrode pad via vias and is formed on a second surface side opposite to the first surface; a protective film formed on the surface of the rewiring layer opposite to the semiconductor substrate; and partition portions formed of an insulating material and arranged between the wires in the rewiring layer, wherein the partition portions and voids are alternately formed between the wires in the direction in which the wiring extends.

Description

[Technical Field]

[0001] The present technology relates to a semiconductor device including a redistribution layer and a method for manufacturing the semiconductor device. [Background technology]

[0002] 2. Description of the Related Art There are semiconductor devices in which a redistribution layer (RDL) is formed to electrically connect electrode pads formed on a wiring layer to an external device. For high-speed operation of semiconductor devices, the wiring formed in the rewiring layer has been becoming finer.

[0003] When the distance between the wires is reduced, the capacitance between the wires increases, which hinders high-speed operation. In view of such problems, Patent Document 1 below discloses a technique for reducing capacitance by providing a gap between wirings. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 07-335747 Summary of the Invention [Problem to be solved by the invention]

[0005] In spin coating, a chemical solution is dropped onto the center of a semiconductor wafer, and the centrifugal force of the semiconductor wafer causes the chemical solution to be applied uniformly over the entire surface of the semiconductor wafer, so that the chemical solution spreads radially from the center of the semiconductor wafer.

[0006] In this case, voids are likely to be created when the direction in which the wiring extends and the direction in which the chemical solution flows are perpendicular, but it is difficult to say that voids will be created reliably when the direction in which the wiring extends and the direction in which the chemical solution flows are approximately parallel.

[0007] The present technology has been developed in view of such problems, and aims to reliably form gaps between wirings. [Means for solving the problem]

[0008] The semiconductor device according to the present technology comprises a semiconductor substrate, a wiring layer having electrode pads and formed on a first surface of the semiconductor substrate, a rewiring layer having wiring electrically connected to the electrode pads through vias and formed on a second surface of the semiconductor substrate opposite the first surface, a protective film formed on the surface of the rewiring layer opposite the semiconductor substrate, and partition portions formed of an insulating material and arranged between the wirings in the rewiring layer, wherein the partition portions and voids are alternately formed between the wirings in the direction in which the wirings extend. As a result, a gap is formed by the two wires and the two partitions.

[0009] The semiconductor device manufacturing method according to the present technology is a method for manufacturing a semiconductor substrate in which a wiring layer having electrode pads is formed on a first surface and a rewiring layer having wiring electrically connected to the electrode pads through vias is formed on a second surface opposite to the first surface, and partitions and voids are alternately formed between the wiring in the rewiring layer in the direction in which the wiring extends. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view showing an example of a semiconductor device. [Figure 2] 3. This figure shows an example of a rewiring layer together with FIG. 3, and is a plan view of the back surface side. [Figure 3] FIG. 10 is a cross-sectional view of an example of a redistribution layer. [Figure 4] FIG. 10 is a plan view of the rear surface side showing a state in which partition portions and gaps are formed between the parallel wirings. [Figure 5] FIG. 5 is a cross-sectional view taken along line BB in FIG. [Figure 6] FIG. 5 is a cross-sectional view taken along line CC in FIG. [Figure 7]FIG. 10 is an enlarged cross-sectional view showing the parallel wiring, the partition portion, and the gap. [Figure 8] FIG. 10 is a cross-sectional view showing a state in which a rewiring layer is formed. [Figure 9] FIG. 10 is a cross-sectional view showing a state in which a recessed groove is formed. [Figure 10] FIG. 2 is a cross-sectional view showing a state in which an insulating film has been formed. [Figure 11] FIG. 10 is a cross-sectional view showing a state in which parallel wiring is exposed by CMP processing. [Figure 12] FIG. 2 is a plan view of the back surface side showing a state in which a resist is applied. [Figure 13] FIG. 13 is a cross-sectional view taken along line DD in FIG. [Figure 14] FIG. 10 is a plan view of the back surface side showing a state in which the insulating film has been removed. [Figure 15] FIG. 15 is a cross-sectional view taken along line EE in FIG. [Figure 16] FIG. 15 is a cross-sectional view taken along the line FF in FIG. [Figure 17] FIG. 10 is a plan view of the back surface side showing a state in which the resist has been removed. [Figure 18] FIG. 18 is a cross-sectional view taken along line GG in FIG. [Figure 19] FIG. 18 is a cross-sectional view taken along line HH in FIG. [Figure 20] FIG. 10 is a plan view of the back surface side showing a state in which a resist is applied in the first modified example. [Figure 21] FIG. 21 is a cross-sectional view taken along line JJ in FIG. 20. [Figure 22] FIG. 10 is a plan view of the rear surface side showing a state in which the insulating film has been removed in the first modified example. [Figure 23] FIG. 23 is a cross-sectional view taken along line KK in FIG. 22. [Figure 24] FIG. 10 is a plan view of the rear surface side showing a state in which the resist has been removed in the first modified example. [Figure 25] FIG. 10 is a plan view of the back surface side showing a state in which a resist is applied in a second modified example. [Figure 26] FIG. 26 is a cross-sectional view taken along the line PP in FIG. 25. [Figure 27] FIG. 10 is a plan view of the rear surface side showing a state in which the insulating film has been removed in the second modified example. [Figure 28] FIG. 28 is a cross-sectional view taken along line RR in FIG. 27. [Figure 29] FIG. 10 is a plan view of the back surface side showing a state in which the resist has been removed in the second modified example. [Figure 30] FIG. 10 is a diagram for explaining a third modified example, and is a plan view of the rear surface side showing a state in which the arrangement intervals of the partitioning portions are changed according to the distance between the wirings. [Figure 31] FIG. 10 is a diagram for explaining a fourth modified example, and is a plan view of the rear surface side showing a state in which partition portions are formed between parallel wirings formed on a non-linear line. [Figure 32] 1 is a cross-sectional view showing a state in which the present technology is applied to a semiconductor device as an image sensor. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, with reference to the accompanying drawings, embodiments according to the present technology will be described in the following order. <1. Configuration of semiconductor device> <2. Inter-wiring capacitance> <3. Manufacturing method> <4. Modifications> <4-1. First modified example> <4-2. Second modified example> <4-3.Third modified example> <4-4. Fourth Variation> <4-5. Other variations> <5. Summary> <6. This technology>

[0012] <1. Configuration of semiconductor device> The semiconductor device 1 according to the present technology is manufactured by, for example, wafer level chip size package (WCSP) technology. A cross section of an example of the configuration of the semiconductor device 1 is shown in FIG. The semiconductor device 1 includes a semiconductor substrate 2, a wiring layer 3 stacked on the front surface 2a of the semiconductor substrate 2, an insulating resin film 4 stacked on the back surface 2b of the semiconductor substrate 2, a redistribution layer (RDL) 5, and a protective film 6.

[0013] In each cross-sectional view shown below, the lower side of the drawing is the front side and the upper side of the drawing is the back side when the reference numerals are viewed in the correct orientation.

[0014] The semiconductor substrate 2 is, for example, a silicon layer, and is formed to a certain thickness to improve the strength of the semiconductor wafer.

[0015] Various semiconductor elements EL such as transistors are formed on a surface 2a of the semiconductor substrate 2. Furthermore, the semiconductor substrate 2 has through holes 2c formed at predetermined positions.

[0016] The wiring layer 3 is formed of multiple layers that cover the surface 2a of the semiconductor substrate 2 on which the transistors are formed. The wiring layer 3 is made by alternately laminating first layers 3a formed of an insulating material and second layers 3b on which a wiring pattern is formed. The simplest structure of the wiring layer 3 is a three-layer structure consisting of two first layers 3a and a second layer 3b formed between them.

[0017] The wiring layer 3 in the example shown in FIG. 1 has a seven-layer structure consisting of four first layers 3a and three second layers 3b.

[0018] In the wiring layer 3, vias (not shown) are formed in the stacking direction to electrically connect the second layers 3b to each other.

[0019] Electrode pads 7 for electrical connection to an external device are formed on the second layer 3b of the wiring layer 3. In the example shown in Fig. 1, the electrode pads 7 are formed on the second layer 3b that is closest to the semiconductor substrate 2 among the three second layers 3b.

[0020] The wiring layer 3 has a recess 3c formed therein, which is continuous with the through hole 2c of the semiconductor substrate 2. The recess 3c is formed so that at least a part of the electrode pad 7 is exposed. The through-hole 2c and the recess 3c are holes 8 formed in the semiconductor substrate 2 and the wiring layer 3 in the stacking direction.

[0021] The electrode pad 7 and the hole 8 are provided at positions that coincide when viewed from the stacking direction of the layers. That is, the electrode pad 7 is in a state where a part of the electrode pad 7 is exposed at the bottom of the hole 8.

[0022] The insulating resin film 4 is a layer provided to prevent unnecessary electrical connection between the semiconductor substrate 2 and the rewiring layer 5, and is an organic film such as polyimide, silicon, acrylic, epoxy, or SOC (Spin-on Carbon). The insulating resin film 4 is formed not only on the rear surface 2 b of the semiconductor substrate 2 but also on the inner circumferential surface of the hole 8 .

[0023] The rewiring layer 5 is a layer electrically connected to the electrode pad 7 by being formed on the inner surface of the insulating resin film 4 formed over the inner surface of the hole 8 and at a predetermined position on the surface of the insulating resin film 4 formed on the surface 2a of the semiconductor substrate 2. In the rewiring layer 5, the portion formed on the inner circumferential surface of the insulating resin film 4 formed over the inner circumferential surface of the hole 8 is made into a through electrode TSV.

[0024] The rewiring layer 5 formed at a predetermined position on the surface of the insulating resin film 4 is made up of single wirings 5a, parallel wirings 5b, connection pads 5c, etc. In the example shown in Fig. 1, the connection pads 5c on which metal bumps 9 such as solder are formed are formed at predetermined positions.

[0025] The parallel wiring 5b is two or more wirings that extend in approximately the same direction with a distance between them that is less than a certain amount. For example, it may be two wirings that extend parallel to each other, or one wiring that extends in a straight line and the other wiring that is meandering. In order for the semiconductor device 1 to operate at high speed, the capacitance between the parallel wirings 5b becomes an issue.

[0026] A single wire is one that has no other wires arranged in parallel.

[0027] The rewiring layer 5 is formed of titanium (Ti), copper (Cu), tantalum (Ta), nickel (Ni), tungsten (W), or the like.

[0028] As will be described in detail later, partitions 10 and gaps 11 are alternately formed between the parallel wirings 5b.

[0029] The protective film 6 is a layer formed on the back surface side of the rewiring layer 5. The protective film 6 is made of an insulating resin material or the like, and is formed by a spin coating method.

[0030] 2 and 3 show an example of the redistribution layer 5. In Fig. 2, the redistribution layer 5 is indicated by a broken line, and is a view seen from the back surface side. Fig. 3 is a vertical cross-sectional view taken along line AA in Fig. 2.

[0031] As shown in FIG. 2, a part of the connection pad 5c is exposed on the back surface side, but the single wiring 5a and the parallel wiring 5b are covered with the protective film 6 and cannot be seen.

[0032] 3, gaps 11 are formed between the parallel wirings 5b. The gaps 11 are formed by preventing the protective film 6 from entering between the parallel wirings 5b. The gaps 11 are formed not only between the parallel wirings 5b but also by removing the insulating resin film 4 to the rear surface side.

[0033] In this way, the formation of the gap 11 between the parallel wirings 5b reduces the capacitance between the wirings.

[0034] The partitions 10 that form the gaps 11 are shown in Fig. 4. Note that Fig. 4 does not show the protective film 6 formed on the back surface of the rewiring layer 5. Between the parallel wirings 5b, partitions 10 and gaps 11 are alternately formed along the direction in which the parallel wirings 5b extend.

[0035] The material of the partition 10 may be organic or inorganic. Specifically, the partition 10 may be made of SiO2, SiON, or an organic resin material.

[0036] Fig. 5 is a cross-sectional view taken along line BB in Fig. 4, showing a portion where the partition portion 10 is formed. As shown in Fig. 5, the partition portion 10 has a substantially rectangular parallelepiped shape and is disposed on the bottom surface of the groove portion 12 between the parallel wirings 5b.

[0037] The partitions 10 are formed at regular intervals in the grooves 12 between the parallel wirings 5b, thereby forming voids 11. Fig. 6 shows a cross-sectional view of the portion where the voids 11 are formed, which is taken along line CC in Fig. 4.

[0038] As shown in the figure, the protective film 6 is prevented from entering the groove portion 12, thereby forming a gap 11.

[0039] <2. Inter-wiring capacitance> The inter-wire capacitance of the parallel wiring 5b will be described. The capacitance Q between wires can be expressed by the following equation (1) using capacitance C and voltage V.

[0040] Q=C V...Equation (1)

[0041] Here, the capacitance C can be expressed by the following formula (2) using the dielectric constant ε, the lateral area S, and the distance between the wirings d.

[0042] C=ε·S / d···Equation (2)

[0043] The lateral area S is the area of ​​the side surface 13 of the parallel wiring 5b. The inter-wiring distance d is the distance between opposing surfaces of the parallel wiring 5b (see FIG. 7).

[0044] The dielectric constant ε differs depending on the material, and can be expressed by the following equation (3):

[0045] ε=ε0·ε r ...Equation (3)

[0046] ε0 represents the dielectric constant of a vacuum, and ε r represents the relative permittivity, which is the ratio of the permittivity to that of a vacuum.

[0047] Here, for example, if the partitions 10 and the gaps 11 are not formed in the grooves 12, the protective film 6 will enter the grooves 12, and the side surfaces 13 will come into contact with the protective film 6 over the entire surface. The relative dielectric constant ε of the material forming the protective film 6 is higher than the relative dielectric constant of vacuum or air. r is higher. Therefore, the dielectric constant ε becomes higher than that of a vacuum or air, so the electrostatic capacitance C increases and the capacitance Q between the wirings also increases.

[0048] 7, by forming partitions 10 in grooves 12, gaps 11 are formed into which protective film 6 does not enter. Therefore, part of side surface 13 comes into contact with air. In this case, the relative permittivity of air, ε r is the relative dielectric constant ε of the protective film 6 r Since the capacitance of the side surface 13 is lower than the capacitance of the side surface 13, the capacitance Q between the wirings can be reduced.

[0049] The larger the contact area between the side surface 13 and the gap 11, that is, the smaller the contact area between the side surface 13 and the partition portion 10, the greater this effect.

[0050] <3. Manufacturing method> The method for manufacturing the semiconductor device 1 will now be described in detail with reference to the accompanying drawings. 8 shows a state in which an insulating resin film 4 is formed on the back surface 2b of a semiconductor substrate 2, and furthermore, parallel wiring 5b of a rewiring layer 5 is formed on the back surface side of the insulating resin film 4. That is, when the state shown in FIG. 8 is viewed from the back surface side, it appears that a wiring pattern as a rewiring layer 5 is formed on the surface of the insulating resin film 4. In this example, three parallel wirings 5b are taken as an example.

[0051] In addition, in each of the figures from FIG. 8 onwards, the wiring layer 3 formed on the surface 2a of the semiconductor substrate 2 is omitted from illustration.

[0052] 9, recessed grooves 4a that are open to the rear surface and sides are formed in the insulating resin film 4. The recessed grooves 4a are formed so as to be continuous with the side surfaces 13 of the parallel wirings 5b. The side surfaces 13 of the parallel wirings 5b and the recessed grooves 4a in the insulating resin film 4 form groove portions 12. This process is achieved by, for example, an etching process.

[0053] 10, a film formation step is performed to form an insulating film 14 made of SiO2, SiON, an organic resin material, etc. The insulating film 14 is formed so as to fill the grooves 12 between the side surfaces 13 of the parallel wirings 5b.

[0054] 11, the parallel wirings 5b are exposed by performing a CMP (Chemical Mechanical Polishing) process on the back surface of the insulating film 14. At this time, the height position of the back surface of the insulating film 14 relative to the semiconductor substrate 2 and the height position of the back surface of the parallel wirings 5b relative to the semiconductor substrate 2 are made to coincide.

[0055] Next, a lithography step is performed in which a resist 15 is applied to the portion of the insulating film 14 formed in the groove 12 that is to remain as the partition 10 . FIG. 12 shows a plan view from the rear surface side in a state where the resist 15 is applied, and FIG. 13 shows a cross section taken along line DD in FIG.

[0056] As shown in the figure, strip-shaped resist 15, the longitudinal direction of which is perpendicular to the parallel wiring 5b, is applied at regular intervals along the direction in which the parallel wiring 5b extends.

[0057] Next, the insulating film 14 that is not covered by the resist 15 is removed by etching. A plan view from the back surface side after the insulating film 14 has been removed is shown in Fig. 14. A cross-sectional view taken along line EE in Fig. 14 is shown in Fig. 15, and a cross-sectional view taken along line FF in Fig. 14 is shown in Fig. 16.

[0058] As shown in FIG. 15, the insulating film 14 protected by the resist 15 remains in the groove 12 as the partition 10. On the other hand, as shown in FIG. 16, the insulating film 14 that was not protected by the resist 15 is removed, and the gap 11 is formed.

[0059] Next, a process is performed to remove the resist 15. The state after the resist 15 has been removed is shown in Fig. 17, which is a plan view of the back surface side, Fig. 18, which is a cross-sectional view taken along line GG in Fig. 17, and Fig. 19, which is a cross-sectional view taken along line HH in Fig. 17.

[0060] As shown in FIGS. 17 and 18, the partitions 10 are formed in the grooves 12 at regular intervals in the direction in which the parallel wirings 5b extend. As shown in FIGS. 17 and 19, gaps 11 are formed between the partitions 10 in the grooves 12.

[0061] In a state where the partitions 10 and the voids 11 are alternately formed in the grooves 12 in the direction in which the parallel wirings 5b extend, a protective film 6 is formed on the rear surface side of the rewiring layer 5 by spin coating.

[0062] In a state where the partitions 10 are not formed in the grooves 12, if the flow direction of the chemical solution forming the protective film 6 coincides with the extension direction of the parallel wirings 5b, the chemical solution will enter the grooves 12. Therefore, there are cases where no gaps are formed between the parallel wirings 5b, and it becomes impossible to reduce the inter-wire capacitance Q of the parallel wirings 5b.

[0063] Meanwhile, both the partitions 10 and the gaps 11 are rectangular parallelepiped shaped. In particular, by making the gaps 11 rectangular rather than simply grooves, the chemical solution used in the spin coating method is less likely to enter the gaps 11 regardless of the direction of flow of the chemical solution, and the gaps 11 can be stably formed between the parallel wirings 5b as shown in Fig. 6. This allows the inter-wiring capacitance Q of the parallel wirings 5b to be reduced.

[0064] When forming the protective film 6 by spin coating, it is more advantageous to apply dynamic coating rather than static coating. By adopting dynamic coating, it becomes difficult for the agent to enter the voids 11, and it is possible to ensure that the voids 11 are formed, and it is also possible to increase the volume of the voids 11 that are formed. Therefore, it is possible to efficiently reduce the inter-wire capacitance Q of the parallel wirings 5b.

[0065] <4. Modifications> <4-1. First modified example> The first modification is an example in which cylindrical partition portions 10A whose axial direction is the thickness direction of the semiconductor substrate 2 are formed in the groove portions 12 formed between the parallel wirings 5b.

[0066] A specific description will be given with reference to the accompanying drawings. The steps are the same up to the formation of the resist 15. That is, the steps shown in Figures 8 to 11 are the same, and the description will be omitted.

[0067] After the back surface of the parallel wiring 5b is exposed by CMP processing, a lithography process is performed in which circular resists 15A are applied to the back surface of the insulating film 14 that has entered the trench 12, spaced apart at regular intervals in the direction in which the parallel wiring 5b extends.

[0068] FIG. 20 shows a plan view of the back surface side in a state where the resist 15A is applied, and FIG. 21 shows a cross section taken along line JJ in FIG.

[0069] Next, a plan view of the back surface side of the semiconductor device 1A after etching is shown in FIG. 22, and a cross-sectional view taken along line KK in FIG. 22 is shown in FIG.

[0070] As shown in the figure, cylindrical partitions 10A are formed in the grooves 12 at regular intervals in the direction in which the parallel wirings 5b extend.

[0071] Next, a process for removing the resist 15A is performed. A plan view of the back surface side after the resist 15A has been removed is shown in Fig. 24. The cross-sectional view taken along line LL in Fig. 24 is the same as that in Fig. 18, and the cross-sectional view taken along line MM in Fig. 24 is the same as that in Fig. 19.

[0072] As shown in FIGS. 24 and 19, gaps 11A are formed between the cylindrical partitions 10A arranged in the grooves 12.

[0073] The columnar partition 10A has a side surface that contacts the side surface 13 of the parallel wiring 5b. Therefore, most of the side surface 13 of the parallel wiring 5b is adjacent to the gap 11A, which further reduces the inter-wiring capacitance Q.

[0074] <4-2. Second modified example> The second modification is an example in which cylindrical holes formed in the groove portions 12 serve as the voids 11. The steps up to forming the resist 15 are the same. That is, the steps in FIGS. 8 to 11 are the same, and therefore the description thereof will be omitted.

[0075] After the back surface of the parallel wiring 5b is exposed by CMP, a lithography process is performed in which a resist 15B is applied to the back surface of the insulating film 14 that has entered the trench 12 so that cylindrical portions of the insulating film 14 are removed at regular intervals in the direction in which the parallel wiring 5b extends.

[0076] A plan view of the back surface side of the semiconductor device 1B in a state where the resist 15B is applied is shown in Fig. 25. The cross-sectional view taken along line NN in Fig. 25 is the same as that in Fig. 13. A cross-sectional view taken along line PP in Fig. 25 is shown in Fig. 26.

[0077] As shown in FIGS. 25 and 26, the insulating film 14 located in the trench 12 has circular portions at regular intervals in the direction in which the parallel wirings 5b extend, where the resist 15B is not applied.

[0078] Next, a plan view of the back surface side of the semiconductor device 1B after etching is shown in Fig. 27. The cross-sectional view taken along line QQ in Fig. 27 is the same as that in Fig. 15. Also, a cross-sectional view taken along line RR in Fig. 27 is shown in Fig. 28.

[0079] As shown in the figure, cylindrical holes 16 are formed in the groove 12 at regular intervals in the direction in which the parallel wirings 5b extend.

[0080] Next, a process for removing resist 15B is performed. A plan view of the back surface side after resist 15B has been removed is shown in Fig. 29. Note that the cross-sectional view taken along line SS in Fig. 29 is the same as that in Fig. 18, and the cross-sectional view taken along line TT in Fig. 29 is the same as that in Fig. 19.

[0081] As shown in FIGS. 29 and 19, cylindrical holes 16 are formed as gaps 11B at regular intervals in the groove 12, and the insulating film 14 remains in the gaps between them as partitions 10B.

[0082] If the viscosity of the chemical solution used in the spin coating method in the subsequent step is low, there is a risk that the chemical solution will enter voids 11A and cause voids 11A to disappear in the first modified example, etc. However, according to this modified example, even when protective film 6 is formed using a chemical solution with a low viscosity, the opening of voids 11B is made small, so voids 11B can be formed stably.

[0083] Therefore, the inter-wire capacitance of the parallel wiring 5b can be reliably reduced.

[0084] <4-3.Third modified example> The third modification is an example in which the distance between the partitions 10, that is, the length of the gap 11 in the direction in which the parallel wirings 5b extend, is changed by the length of the inter-wiring distance d of the parallel wirings 5b.

[0085] A specific description will be given with reference to Fig. 30, which is a plan view of the back surface side, in which the protective film 6 is not shown.

[0086] As shown in the figure, first parallel wirings 5b1 having an inter-wiring distance d1 and second parallel wirings 5b2 having an inter-wiring distance d2 are formed on the rear surface side of the insulating resin film 4. The distance d1 between the wires is shorter than the distance d2 between the wires. That is, the first parallel wiring 5b1 is formed as a wiring pattern that is finer than the second parallel wiring 5b2.

[0087] In this case, the variable d in the formula (2) above is smaller for the first parallel wiring 5b1 than for the second parallel wiring 5b2, and therefore the capacitance C is larger. Therefore, in order to reduce the capacitance C, the average relative dielectric constant ε r The relative permittivity ε r The contact area between the small gap 11 and the side surface 13 of the first parallel running wiring 5b1 is increased.

[0088] That is, as shown in FIG. 30, by increasing the spacing between the partitions 10, it is possible to reduce the inter-wire capacitance Q in the miniaturized first parallel wirings 5b1.

[0089] Furthermore, even when taking into consideration the ease with which the liquid agent penetrates into the gaps 11 when forming the protective film 6 by the spin coating method, it is preferable to arrange the partition portions 10 at wider intervals for the finer first parallel wiring 5b1 than for the second parallel wiring 5b2.

[0090] That is, miniaturization of the parallel wirings 5b is synonymous with shortening the distance d between the wirings, and therefore makes it difficult for the liquid agent to enter the gaps 11. Therefore, even if the spacing between the partitions 10 is widened to take this into consideration, the liquid agent does not enter the gaps 11, and the protective film 6 can be formed in a state where the gaps 11 are formed without any problems.

[0091] <4-4. Fourth Variation> The fourth modification is an example in which adjacent partitions 10 in the grooves 12 of the parallel wiring lines 5b are not parallel to each other. A specific description will be given with reference to FIG.

[0092] The illustrated parallel wiring 5b is formed into a non-linear shape as a whole by connecting straight lines extending in different directions.

[0093] In this way, for parallel wiring lines 5b formed by curves or parallel wiring lines 5b formed by two or more straight lines, the partitions 10 formed in the grooves 12 are non-parallel. That is, the partitions 10 are formed so that the longitudinal direction is perpendicular to the direction in which the adjacent parallel wirings 5b extend.

[0094] When the partitions 10 are arranged so as to be spaced apart at a predetermined interval, the partitions 10 may be formed so as to be adjacent to the parallel wiring 5b on the inner periphery at a predetermined interval, or the partitions 10 may be formed so as to be adjacent to the parallel wiring 5b on the outer periphery at a predetermined interval.

[0095] <4-5. Other variations> In other modifications, application modes of the semiconductor device 1 (1A, 1B) will be described. The semiconductor device 1 may be various types such as a logic circuit device, an image sensor device, a memory device, an interposer, or the like.

[0096] As an example, an image sensor device is shown in Fig. 32. Note that in Fig. 32, the wiring layer 3 formed on the surface 2a side of the semiconductor substrate 2 is not shown.

[0097] As shown in the figure, photoelectric conversion elements 17 are provided in a two-dimensional array in the center of a semiconductor substrate 2, and an insulating resin film 4 and a protective film 6 are formed on the back surface side thereof.

[0098] No photoelectric conversion elements 17 are formed on the outer periphery of the semiconductor substrate 2, and an insulating resin film 4, a redistribution layer 5, and a protective film 6 are formed on the back surface side of the semiconductor substrate 2. In addition, in the grooves 12 formed between the parallel wirings 5b in the redistribution layer 5, the partitions 10 and voids 11 as described above are formed alternately.

[0099] In this way, by forming the redistribution layer 5, the partition portion 10, and the void 11 in the portion of the semiconductor substrate 2 where the photoelectric conversion element 17 is not formed, the inter-wiring capacitance Q for the parallel wiring 5b can be reduced without preventing light from entering the photoelectric conversion element 17.

[0100] <5. Summary> As described in each of the above examples, the semiconductor device 1 (1A, 1B) comprises a semiconductor substrate 2, a wiring layer 3 having electrode pads 7 formed on a first surface (front surface 2a) of the semiconductor substrate 2, a redistribution layer 5 having wiring electrically connected to the electrode pads 7 through vias (through-hole electrodes TSVs) and formed on a second surface (back surface 2b) opposite the first surface of the semiconductor substrate 2, a protective film 6 formed on the surface (back surface side) of the redistribution layer 5 opposite the semiconductor substrate 2, and partition portions 10 (10A, 10B) formed of an insulating material and arranged between the wirings in the redistribution layer 5 (between the parallel wiring 5b, the first parallel wiring 5b1, and the second parallel wiring 5b2), and partition portions 10 and voids 11 (11A, 11B) are alternately formed between the wirings in the direction in which the wirings extend. As a result, before the protective film 6 is formed, a gap 11 surrounded by the two wirings (the two parallel wirings 5b) and the two partition portions 10 is formed. Therefore, the protective film 6 can be formed while maintaining the gap 11. Furthermore, the contact area between the two wires and the partition 10 is reduced, thereby reducing the capacitance Q between the two wires. This is particularly effective when the protective film 6 is formed using a spin coating method. That is, the gap 11 can be inevitably formed between the wires simply by forming the protective film 6 using a spin coating method as usual. Furthermore, by reducing the capacitance Q between the wirings, it becomes possible to manufacture a semiconductor device 1 that can operate at high speed.

[0101] As described above, the insulating material used to form the partitions 10 (10A, 10B) may be any of SiOx, SiOxNy, and insulating organic resin, where x and y are variables representing natural numbers. This ensures a certain level of insulation in the partition 10. Therefore, the dielectric constant of the partition 10 is reduced, and the capacitance between the two wires can be further reduced.

[0102] As described in the third variant with reference to Figure 29, in the semiconductor device 1 (1A, 1B), two wires (two first parallel wires 5b1) having a first wire-to-wire distance d1 and two wires (two second parallel wires 5b2) having a second wire-to-wire distance d2 are formed in the redistribution layer 5, and the first wire-to-wire distance d1 is made shorter than the second wire-to-wire distance d2, and the spacing between the partition portions 10 arranged between the two wires having the first wire-to-wire distance d1 and adjacent in the direction in which the wires extend may be larger than the spacing between the partition portions 10 arranged between the two wires having the second wire-to-wire distance d2 and adjacent in the direction in which the wires extend. Furthermore, in the semiconductor device 1 (1A, 1B), the shorter the distance d between two wires (two parallel wires 5b) wired in the rewiring layer 5, the larger the spacing between the partition portions 10 (10A, 10B) arranged between the two wires and adjacent in the direction in which the wires extend. This reduces the contact area between the two wires, which have a large inter-wire capacitance Q due to the short inter-wire distance d, and the partition portion 10. Therefore, the effect of reducing the capacitance Q between the wirings is not reduced.

[0103] As described in the first modified example with reference to each of Figures 20 to 24, in the semiconductor device 1A, the partition portion 10A may be cylindrical in shape with the axial direction being the stacking direction of the redistribution layer 5 on the semiconductor substrate 2. That is, the side surface of the cylindrical partition portion 10A contacts the side surface 13 of the parallel wiring 5b. This further reduces the contact area between the wiring and the partition portion 10A, allowing the capacitance Q between the wiring to be further reduced.

[0104] As described with reference to FIGS. 4 and 5, the partition section 10 in the semiconductor device 1 may have a rectangular parallelepiped shape. As a result, the gap 11 adjacent to the partition 10 also has a rectangular parallelepiped shape. Therefore, the area where the wiring (parallel wiring 5b) is adjacent to the gap 11 is increased, and the capacitance Q between the wirings can be reduced.

[0105] As described with reference to each of Figures 25 to 28, the void 11B of the semiconductor device 1B may be a hole 16 formed in an insulating material that penetrates between the wirings (between the parallel wirings 5b). As a result, hole-like gaps 11B are formed between the partitions 10B. Therefore, the capacitance Q between the two wires arranged on both sides of the gap 11B can be reduced.

[0106] As explained with reference to each figure such as Figure 9, in the semiconductor device 1 (1A, 1B), an insulating resin film 4 is formed between the semiconductor substrate 2 and the rewiring layer 5, and the void 11 (11A, 11B) may be formed as a space that reaches into the insulating resin film 4, that is, as a space that includes a recess (recess groove 4a) formed in the insulating resin film 4. As a result, a gap 11 deeper than the height of the wiring (parallel wiring 5b) is formed. Therefore, the side surfaces 13 of the two wirings can be reliably placed adjacent to the gap, which reliably reduces the capacitance between the wirings Q. Furthermore, by digging down to the insulating resin film 4 and forming the gap 11, it is possible to reduce ion migration.

[0107] As explained in other modifications with reference to FIG. 31 etc., in the semiconductor device 1, the photoelectric conversion elements 17 that perform photoelectric conversion may be formed in a two-dimensional array on the semiconductor substrate 2. As a result, gaps 11 are formed between the wirings of the rewiring layer 5 in the semiconductor device 1 such as an image sensor. Therefore, the capacitance Q between the wirings can be reduced, which is suitable for high-speed driving of the image sensor.

[0108] The semiconductor device manufacturing method of the present technology is for a semiconductor device 1 (1A, 1B) comprising a semiconductor substrate 2, a wiring layer 3 having electrode pads 7 formed on a first surface (front surface 2a) of the semiconductor substrate 2, a redistribution layer 5 having wiring electrically connected to the electrode pads 7 through vias (through-hole electrodes TSVs) and formed on a second surface (back surface 2b) opposite the first surface of the semiconductor substrate 2, a protective film 6 formed on the surface of the redistribution layer 5 opposite the semiconductor substrate 2, and partition portions 10 formed of an insulating material and arranged between the wirings (between parallel wirings 5b) in the redistribution layer 5, by alternately forming partition portions 10 and voids 11 between the wirings in the direction in which the wirings extend. In addition, this manufacturing method is a method of forming partitions 10 and voids 11 alternately between the wirings in the rewiring layer 5 in the direction in which the wirings extend in a semiconductor substrate 2 having a wiring layer 3 with electrode pads 7 formed on a first surface (front surface 2a) and a rewiring layer 5 with wiring electrically connected to the electrode pads 7 through vias (through electrodes TSVs) formed on a second surface (back surface 2b) opposite the first surface. By using such a manufacturing method, it is possible to manufacture the semiconductor device 1 (1A, 1B) having the above-mentioned various functions and effects.

[0109] In the method for manufacturing a semiconductor device, the gaps 11 (11A, 11B) may be formed by forming the protective film 6 by a spin coating method. The protective film 6 is formed by causing a chemical solution to flow on the back surface side of the rewiring layer 5 by spin coating, and the gap 11 can be easily formed.

[0110] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0111] Furthermore, the above-described examples may be combined in any manner, and even when various combinations are used, the above-described various operational effects can be obtained.

[0112] <6. This technology> This technology can also be configured as follows. (1) a semiconductor substrate; a wiring layer having an electrode pad and formed on a first surface of the semiconductor substrate; a rewiring layer formed on a second surface of the semiconductor substrate opposite to the first surface, the rewiring layer having wiring electrically connected to the electrode pad through a via; a protective film formed on a surface of the rewiring layer opposite to the semiconductor substrate; a partition portion formed of an insulating material and disposed between the wirings in the rewiring layer; The partitions and gaps are alternately formed between the wirings in the direction in which the wirings extend. Semiconductor device. (2) The insulating material is one of SiOx, SiOxNy, and insulating organic resin. The semiconductor device according to (1) above. (3) two wirings having a first wiring distance and two wirings having a second wiring distance are formed in the rewiring layer; the first inter-wiring distance is shorter than the second inter-wiring distance; The interval between the partition portions arranged between the two wirings having the first wiring distance and adjacent to each other in the direction in which the wirings extend is larger than the interval between the partition portions arranged between the two wirings having the second wiring distance and adjacent to each other in the direction in which the wirings extend. The semiconductor device according to any one of (1) and (2) above. (4) The shorter the distance between the two wirings wired in the rewiring layer, the larger the interval between the partition portions disposed between the two wirings and adjacent to each other in the direction in which the wirings extend. The semiconductor device according to (3) above. (5) The partition portion is cylindrical in shape with its axial direction being the stacking direction of the rewiring layer on the semiconductor substrate. The semiconductor device according to any one of (1) to (4) above. (6) The partition portion is formed in a rectangular parallelepiped shape. The semiconductor device according to any one of (1) to (4) above. (7) The voids are holes formed in an insulating material between the wirings. The semiconductor device according to any one of (1) to (6) above. (8) an insulating resin film is formed between the semiconductor substrate and the rewiring layer; The gap is formed as a space that reaches the inside of the insulating resin film. The semiconductor device according to any one of (1) to (7) above. (9) Photoelectric conversion elements that perform photoelectric conversion are formed in a two-dimensional array on the semiconductor substrate. The semiconductor device according to any one of (1) to (8) above. (10) In a semiconductor substrate in which a wiring layer having electrode pads is formed on a first surface and a rewiring layer having wiring electrically connected to the electrode pads through vias is formed on a second surface opposite to the first surface, partitions and voids are alternately formed between the wiring in the rewiring layer in the direction in which the wiring extends. A semiconductor device manufacturing method. (11) The voids are formed by forming a protective film by spin coating. The method for manufacturing a semiconductor device according to (10) above. [Explanation of symbols]

[0113] 1, 1A, 1B Semiconductor Device 2. Semiconductor substrate 2a Surface (first surface) 2b Back side (second side) 3 wiring layer 4. Insulating resin film 5 Redistribution layer 6 Protective film 7 Electrode pads 10, 10A, 10B Partition 11, 11A, 11B void 12 Groove 16 Hole 17 Photoelectric conversion element TSV through-electrode (via)

Claims

1. a semiconductor substrate; a wiring layer having an electrode pad and formed on a first surface of the semiconductor substrate; a rewiring layer formed on a second surface of the semiconductor substrate opposite to the first surface, the rewiring layer having wiring electrically connected to the electrode pad through a via; a protective film formed on a surface of the rewiring layer opposite to the semiconductor substrate; a partition portion formed of an insulating material and disposed between the wirings in the rewiring layer; the partitions and the gaps are alternately formed between the wirings in the direction in which the wirings extend, two wirings having a first wiring distance and two wirings having a second wiring distance are formed in the rewiring layer; the first inter-wiring distance is shorter than the second inter-wiring distance, The interval between the partition portions arranged between the two wirings having the first wiring distance and adjacent to each other in the direction in which the wirings extend is larger than the interval between the partition portions arranged between the two wirings having the second wiring distance and adjacent to each other in the direction in which the wirings extend. Semiconductor device.

2. The insulating material is one of SiOx, SiOxNy, and insulating organic resin. The semiconductor device according to claim 1 .

3. The shorter the distance between the two wirings wired in the rewiring layer, the larger the interval between the partition portions disposed between the two wirings and adjacent to each other in the direction in which the wirings extend. The semiconductor device according to claim 1 .

4. The partition portion is cylindrical in shape with its axial direction being the stacking direction of the rewiring layer on the semiconductor substrate. The semiconductor device according to claim 1 .

5. The partition portion is formed in a rectangular parallelepiped shape. The semiconductor device according to claim 1 .

6. The voids are holes formed in an insulating material between the wirings. The semiconductor device according to claim 1 .

7. an insulating resin film is formed between the semiconductor substrate and the rewiring layer; The gap is formed as a space that reaches the inside of the insulating resin film. The semiconductor device according to claim 1 .

8. Photoelectric conversion elements that perform photoelectric conversion are formed in a two-dimensional array on the semiconductor substrate. The semiconductor device according to claim 1 .

9. In a semiconductor substrate having a wiring layer having electrode pads formed on a first surface and a rewiring layer having wiring electrically connected to the electrode pads through vias formed on a second surface opposite to the first surface, partitions and voids are alternately formed between the wirings in the rewiring layer in a direction in which the wirings extend, forming two wirings having a first wiring distance and two wirings having a second wiring distance in the rewiring layer; The first wiring distance is shorter than the second wiring distance, The interval between the partition portions arranged between the two wirings having the first wiring distance and adjacent to each other in the direction in which the wirings extend is set to be larger than the interval between the partition portions arranged between the two wirings having the second wiring distance and adjacent to each other in the direction in which the wirings extend. A semiconductor device manufacturing method.

10. The voids are formed by forming a protective film by spin coating.

10. The method for manufacturing a semiconductor device according to claim 9.

11. A semiconductor substrate; a wiring layer having an electrode pad and formed on a first surface of the semiconductor substrate; a rewiring layer formed on a second surface of the semiconductor substrate opposite to the first surface, the rewiring layer having wiring electrically connected to the electrode pad through a via; a protective film formed on a surface of the rewiring layer opposite to the semiconductor substrate; a partition portion formed of an insulating material and disposed between the wirings in the rewiring layer; the partitions and the gaps are alternately formed between the wirings in the direction in which the wirings extend, The partition portion is cylindrical in shape with its axial direction being the stacking direction of the rewiring layer on the semiconductor substrate. Semiconductor device.

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