Semiconductor device and method for manufacturing the same

Abstract

The present invention suppresses a leak current. This semiconductor device comprises: a first anode electrode provided in a portion of an upper surface of a gallium oxide layer of a first conductor type; a semiconductor layer of a second conductor type provided so as to cover a portion of the gallium oxide layer and a portion of at least the first anode electrode; and a second anode electrode provided so as to cover the semiconductor layer, wherein a plurality of trenches are provided in an outer layer part of the gallium oxide layer, the first anode electrode is provided on the outer layer part of the gallium oxide layer so as not to overlap the trenches as seen in a plan view, and the semiconductor layer is provided so as to cover the gallium oxide layer inside the trenches.

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to semiconductor technology. [Background technology]

[0002] Power electronics (abbreviated as "pawa-ele") is a technology that quickly and efficiently converts electricity between direct current, alternating current, and frequency. Power electronics (technology) is a fusion of traditional power engineering and recent semiconductor-based electronics and control engineering. Today, power electronics is applied everywhere electricity is used, including for power generation, industry, transportation, and even home use.

[0003] In recent years, the proportion of electrical energy in total energy consumption, or the electrification rate, has been on the rise not only in Japan but also around the world. Behind this trend is the development of convenient and energy-efficient equipment in terms of electricity usage, which has led to an improvement in the utilization rate of electricity. The technology that underpins this is power electronics technology.

[0004] Power electronics technology can be said to be the technology that converts input electricity into an electrical state suitable for the device being used, regardless of the state of the electricity being converted (for example, frequency, current, or voltage). The basic elements of power electronics technology are rectifiers and inverters. The foundation of these are semiconductors, and in turn, semiconductor elements such as diodes and transistors that use semiconductors.

[0005] In the current power electronics field, diodes, which are semiconductor rectifying elements, are used in a variety of applications, including electrical equipment, and are applicable to a wide range of frequency bands.

[0006] In recent years, switching elements capable of operating at low loss and high frequency for high-voltage and large-capacity applications have been developed and put to practical use. Furthermore, the materials used in semiconductor elements have shifted to wide-gap materials, and efforts are being made to increase the breakdown voltage of elements. Typical elements for which high breakdown voltages are being sought include Schottky barrier diodes (SBDs) and pn diodes (PNDs), and these diodes are widely used in a variety of applications.

[0007] Trench MOS SBDs, such as those described in Patent Document 1, have been developed as devices that use gallium oxide in the semiconductor layer. Generally, when a reverse voltage is applied to an SBD that uses a semiconductor material with high dielectric breakdown strength, a large leakage current occurs between the anode electrode and the semiconductor material layer. In contrast, the trench MOS SBD described in Patent Document 1 distributes and mitigates the electric field applied to the anode electrode edge, improving the device's reverse breakdown voltage.

[0008] Next, in a trench-type junction barrier controlled Schottky diode (JBS) diode, as exemplified in Patent Document 2, for example, when a reverse voltage is applied, a depletion layer spreads from the p-type semiconductor layer to the n-type semiconductor layer of the convex portion, closing the channel, thereby suppressing leakage current. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2020-170787 [Patent Document 2] Japanese Patent Application Publication No. 2019-036593 Summary of the Invention [Problem to be solved by the invention]

[0010] The MOS-type SBD exemplified in Patent Document 1 is considered to have a lower leakage current suppression effect than the JBS structure using a p-type semiconductor exemplified in Patent Document 2. On the other hand, it is difficult to form a pn junction in the structure exemplified in Patent Document 2.

[0011] The technology disclosed in the present specification has been made in consideration of the problems described above, and is a technology for suppressing leakage current. [Means for solving the problem]

[0012] A semiconductor device that is a first aspect of the technology disclosed in the present specification includes a gallium oxide layer of a first conductivity type, a first anode electrode provided on a portion of an upper surface of the gallium oxide layer, a semiconductor layer of a second conductivity type provided so as to cover a portion of the gallium oxide layer and at least a portion of the first anode electrode, and a second anode electrode provided so as to cover the semiconductor layer, wherein a surface portion of the gallium oxide layer has a plurality of trenches, the first anode electrode is provided on the surface portion of the gallium oxide layer so as not to overlap with the trenches in a planar view, and the semiconductor layer is provided so as to cover the gallium oxide layer inside the trenches. [Effects of the Invention]

[0013] According to at least the first aspect of the technique disclosed in the present specification, leakage current can be suppressed.

[0014] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description and accompanying drawings set forth below. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a cross-sectional view schematically showing an example of the configuration of a semiconductor device according to an embodiment. [Figure 2] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 3]1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] 1 is a cross-sectional view schematically showing an example of the configuration of a semiconductor device according to an embodiment. [Figure 10] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] 1 is a cross-sectional view schematically illustrating a configuration of a semiconductor device according to an embodiment; [Figure 13] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 14] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features will be shown for the purpose of explaining the technology, but these are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0017] The drawings are schematic, and for the sake of convenience, components may be omitted or simplified as appropriate. The relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Hatching may also be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the embodiments.

[0018] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions of them may be omitted to avoid duplication.

[0019] Furthermore, in the description given in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0020] Furthermore, although ordinal numbers such as "first" or "second" may be used in the descriptions in this specification, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0021] Furthermore, in the description provided in this specification, terms that indicate specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," may be used, but these terms are used for convenience to facilitate understanding of the contents of the embodiments and have no relation to the positions or directions when the embodiments are actually implemented.

[0022] Furthermore, in the description of the present specification, when "the upper surface of ..." or "the lower surface of ..." is used, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component. For example, when it is described as "B provided on the upper surface of A," it does not preclude another component "C" from being interposed between A and B.

[0023] First Embodiment Hereinafter, an oxide semiconductor device as a semiconductor device according to the present embodiment and a method for manufacturing the oxide semiconductor device will be described. First, the configuration of the oxide semiconductor device according to the present embodiment will be described. In the following description, the oxide semiconductor device may be referred to simply as a "semiconductor device."

[0024] <Configuration of semiconductor device> In the following description of the semiconductor device according to this embodiment, the electrode provided on the upper surface of the substrate is the anode electrode and the electrode provided on the lower surface of the substrate is the cathode electrode. However, the semiconductor device according to this embodiment is not limited to SBDs and may be other power device elements such as switching elements.

[0025] Fig. 1 is a cross-sectional view schematically showing an example of the configuration of a semiconductor device according to the present embodiment. As shown in Fig. 1, the semiconductor device includes an n-type gallium oxide layer. Hereinafter, the n-type gallium oxide layer will be described as including an n-type single-crystalline gallium oxide substrate 7 and an n-type gallium oxide epitaxial layer 6, but the n-type gallium oxide layer is not limited to this example configuration.

[0026] The n-type single-crystalline gallium oxide substrate 7 is an n-type oxide semiconductor having an upper surface (first main surface) and a lower surface (second main surface) opposite to the upper surface. The n-type gallium oxide epitaxial layer 6 is an epitaxial layer provided on the upper surface of the n-type single-crystalline gallium oxide substrate 7.

[0027] 1 has a trench structure 100 in a surface layer of an n-type gallium oxide epitaxial layer 6 in an active region surrounded by a termination structure in a plan view. The semiconductor device also includes an anode electrode 2 that is electrically junctioned with the n-type gallium oxide epitaxial layer 6 via a Schottky junction.

[0028] The semiconductor device also has a p-type semiconductor layer 5 provided so as to cover the inside and outside of the trench structure 100. The p-type semiconductor layer 5 is made of a material containing an element other than gallium oxide as a main component, and forms a hetero pn junction with the n-type gallium oxide epitaxial layer 6.

[0029] 1 further includes a termination structure provided outside an active region where current flows in an element such as an SBD, and a field plate insulating material layer 3 provided between n-type gallium oxide epitaxial layer 6 and anode electrode 1. The portion where field plate insulating material layer 3 and anode electrode 1 are stacked forms a field plate structure, which improves the breakdown voltage of the semiconductor device when a reverse bias is applied to the semiconductor device.

[0030] Further, on the lower surface of the n-type single-crystalline gallium oxide substrate 7, a cathode electrode 8 which is an electrode electrically ohmic-contacted with the lower surface of the n-type single-crystalline gallium oxide substrate 7 is provided.

[0031] Next, the above components will be described in more detail.

[0032] The n-type single-crystal gallium oxide substrate 7 is an n-type oxide semiconductor made of a single crystal of Ga2O3, and more preferably an n-type oxide semiconductor made of a single crystal of β-Ga2O3. When the n-type single-crystal gallium oxide substrate 7 is made of a single crystal of β-Ga2O3, the crystal structure is stable, and an n-type single-crystal gallium oxide substrate 7 having stable physical properties can be obtained.

[0033] The n-type single-crystalline gallium oxide substrate 7 exhibits n-type conductivity due to oxygen vacancies in the crystal, and therefore does not need to contain n-type impurities, but may contain n-type impurities such as silicon (Si) or tin (Sn). That is, the n-type single-crystalline gallium oxide substrate 7 may be one that exhibits n-type conductivity due to oxygen vacancies alone, one that exhibits n-type conductivity due to n-type impurities alone, or one that exhibits n-type conductivity due to both oxygen vacancies and n-type impurities.

[0034] The n-type carrier concentration (electron carrier concentration) of the n-type single crystal gallium oxide substrate 7 containing n-type impurities is the total concentration of oxygen vacancies and n-type impurities. The n-type carrier concentration (electron carrier concentration) of the n-type single crystal gallium oxide substrate 7 is, for example, 1×10 17 cm -3 Above and 1×10 19 cm -3 In order to reduce the contact resistance between the n-type single-crystalline gallium oxide substrate 7 and the cathode electrode 8, the impurity concentration may be higher than the above-mentioned range.

[0035] The n-type gallium oxide epitaxial layer 6 is provided on the upper surface of the n-type single crystal gallium oxide substrate 7. The n-type gallium oxide epitaxial layer 6 is an n-type oxide semiconductor made of a single crystal of Ga2O3, and more preferably an n-type oxide semiconductor made of a single crystal of β-Ga2O3. When the n-type gallium oxide epitaxial layer 6 is made of a single crystal of β-Ga2O3, the crystal structure is stable, and an n-type gallium oxide epitaxial layer 6 with stable physical properties can be obtained.

[0036] The n-type carrier concentration (electron carrier concentration) of the n-type gallium oxide epitaxial layer 6 is preferably lower than the electron carrier concentration of the n-type single crystal gallium oxide substrate 7, and is, for example, 1×10 15 cm -3 Above and 1×10 17 cm -3 It may be the following:

[0037] A trench structure 100 is formed in a surface portion of the n-type gallium oxide epitaxial layer 6. The method for forming the trench structure 100 is not particularly limited, and it may be formed by dry etching using BCl3 gas, for example.

[0038] When forming the trench structure 100, the anode electrode 2, which forms a Schottky junction with the n-type gallium oxide epitaxial layer 6, can be used as an etching mask. Therefore, it is desirable that the surface of the anode electrode 2 is not deteriorated by etching. The Schottky electrode may be made of, for example, platinum (Pt), nickel (Ni), gold (Au), or palladium (Pd). However, in the case of a material that is significantly deteriorated by etching, the anode electrode 2 may have a stacked structure.

[0039] For example, it is desirable to configure the anode electrode 2 having a stacked structure by providing a first layer made of a metal material suitable for forming a Schottky junction with the n-type gallium oxide epitaxial layer 6 in contact with the n-type gallium oxide epitaxial layer 6, and providing a second layer made of another metal material having excellent etching resistance on the upper surface of the first layer.

[0040] The cathode electrode 8 is provided on the lower surface of the n-type single crystalline gallium oxide substrate 7. Since the cathode electrode 8 forms an ohmic junction with the n-type single crystalline gallium oxide substrate 7, it is preferably made of a metal material having a work function smaller than that of the n-type single crystalline gallium oxide substrate 7. Furthermore, it is preferable that the cathode electrode 8 be made of a metal material that reduces the contact resistance between the n-type single crystalline gallium oxide substrate 7 and the cathode electrode 8 by heat treatment after the cathode electrode 8 is formed on the lower surface of the n-type single crystalline gallium oxide substrate 7. An example of such a metal material may be titanium (Ti).

[0041] The cathode electrode 8 may also be configured by laminating multiple metal materials. For example, when a metal material that is easily oxidized is in contact with the lower surface of the n-type single-crystal gallium oxide substrate 7, a metal material that is less likely to oxidize may be further formed on the lower surface of the metal material to form a laminated cathode electrode 8. For example, the laminated cathode electrode 8 may be configured by providing a first layer made of Ti in contact with the n-type single-crystal gallium oxide substrate 7 and providing a second layer made of gold (Au) or silver (Ag) on ​​the lower surface of the first layer.

[0042] The cathode electrode 8 may be provided on the entire lower surface of the n-type single-crystalline gallium oxide substrate 7, or may be provided on a part of the lower surface of the n-type single-crystalline gallium oxide substrate 7.

[0043] The anode electrode 1 is provided above the n-type gallium oxide epitaxial layer 6. A p-type semiconductor layer 5 is provided between the anode electrode 1 and the n-type gallium oxide epitaxial layer 6, and it is desirable that the anode electrode 1 and the p-type semiconductor layer 5 form an ohmic junction. Therefore, the anode electrode 1 is preferably made of a metal material having a work function smaller than that of the p-type semiconductor layer 5. Such a metal material may be, for example, Au.

[0044] The anode electrode 1 may have a laminated structure, similar to the anode electrode 2 or the cathode electrode 8. For example, the anode electrode 1 may have a laminated structure in which a first layer made of a metal material suitable for ohmic junction with the p-type semiconductor layer 5 is provided in contact with the p-type semiconductor layer 5, and a second layer made of another metal material is provided on the top surface of the first layer.

[0045] The p-type semiconductor layer 5 is also provided inside the trench structure 100 formed in the surface layer portion of the n-type gallium oxide epitaxial layer 6. The p-type semiconductor layer 5 is also formed so as to cover the outside (specifically, the top) of the trench structure 100 via the anode electrode 2.

[0046] The material of the p-type semiconductor layer 5 is not particularly limited, but is preferably a p-type oxide semiconductor material, and is preferably composed of a p-type oxide semiconductor that exhibits p-type conductivity without the addition of p-type impurities, such as copper oxide (CuO), silver oxide (AgO), nickel oxide (NiO), or tin oxide (SnO). For example, in the metal oxide CuO, the Cu 3d orbital forms the upper edge of the valence band responsible for hole conduction, and holes are generated due to Cu vacancies, resulting in p-type conductivity. When CuO is oxidized to CuO, the Cu 3d orbital no longer forms the upper edge of the valence band, and the p-type conductivity is lost. The p-type semiconductor layer 5 is preferably composed of a p-type oxide semiconductor made of a metal oxide having such properties, and p-type oxide semiconductors such as CuO generally exhibit p-type conductivity without the addition of p-type impurities.

[0047] When the p-type semiconductor layer 5 is limited to a p-type oxide semiconductor, it is composed of a p-type oxide semiconductor that exhibits p-type conductivity without adding p-type impurities as described above, but even in such a case, p-type impurities may be added. For example, when the p-type semiconductor layer 5 is CuO, nitrogen (N) can be used as the p-type impurity.

[0048] The p-type carrier concentration (electron carrier concentration) of the p-type semiconductor layer 5 is the concentration of metal atom vacancies in the p-type oxide semiconductor when no p-type impurities are added, and is the total concentration of the metal atom vacancies in the p-type oxide semiconductor and the p-type impurities when p-type impurities are added. When p-type impurities are added to the p-type semiconductor layer 5, even if the metal oxide of the p-type oxide semiconductor is oxidized and loses its p-type conductivity, the p-type oxide semiconductor as a whole may still exhibit p-type conductivity due to the p-type impurities. However, if the metal oxide of the p-type oxide semiconductor is oxidized and loses its p-type conductivity, the p-type conductivity of the entire p-type oxide semiconductor will decrease, so it is preferable not to oxidize the metal oxide of the p-type oxide semiconductor.

[0049] Field plate insulating material layer 3 is made of, for example, silicon dioxide (SiO2) or aluminum oxide (Al2O3). These materials have a higher breakdown field strength than Ga2O3 that makes up n-type gallium oxide epitaxial layer 6. The thickness of field plate insulating material layer 3 varies depending on the device structure, but may be 1 μm or less, for example, 200 nm or more and 900 nm or less.

[0050] Furthermore, the field plate insulating material layer 3 shown in FIG. 1 does not have a simple single-step structure, but rather has a multi-step field plate structure formed in a stepped pattern. Specifically, the field plate insulating material layer 3 is provided across the upper surfaces of the p-type semiconductor layer 5 and the n-type gallium oxide epitaxial layer 6. However, since the field plate insulating material layer 3 is formed across the portion of the p-type semiconductor layer 5 provided at the top of the trench structure 100 (i.e., the portion provided on the upper surface of the n-type gallium oxide epitaxial layer 6 via the anode electrode 2), the portion of the p-type semiconductor layer 5 provided on the upper surface of the n-type gallium oxide epitaxial layer 6 outside the trench structure 100, and the interior of the trench structure 100, it has a multi-step structure. Therefore, the field plate insulating material layer 3 is desirably formed in a sloping or stepped pattern. When the field plate insulating material layer 3 is formed in a sloping or stepped pattern, the electric field intensity at the electric field concentration point of the device can be suppressed, and therefore, a high breakdown voltage of the device can be expected.

[0051] <About the manufacturing method of semiconductor devices> Next, a method for manufacturing an oxide semiconductor device as a semiconductor device according to the present embodiment will be described with reference to Fig. 1 to Fig. 8. Fig. 2 to Fig. 8 are cross-sectional views for explaining the method for manufacturing a semiconductor device according to the present embodiment.

[0052] First, an n-type single-crystal gallium oxide substrate 7 is prepared, as shown in Fig. 2. The n-type single-crystal gallium oxide substrate 7 can be a substrate cut out from a single-crystal bulk of β-Ga2O3 produced by melt growth.

[0053] 3, an n-type gallium oxide epitaxial layer 6 is deposited by epitaxial growth on the upper surface of the n-type single-crystalline gallium oxide substrate 7. The method for forming the n-type gallium oxide epitaxial layer 6 is not particularly limited, but it can be formed on the upper surface of the n-type single-crystalline gallium oxide substrate 7 by, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), halide vapor phase epitaxy (HVPE), or the like.

[0054] Next, as shown in FIG. 4, a metal material that will become the cathode electrode 8 is deposited on the lower surface of the n-type single-crystalline gallium oxide substrate 7 by evaporation or sputtering. For example, a Ti layer is deposited to a thickness of 50 nm on the lower surface of the n-type single-crystalline gallium oxide substrate 7 by electron beam evaporation (EB evaporation), and then a Au layer is deposited to a thickness of 300 nm on the Ti layer by electron beam evaporation, thereby forming a two-layer cathode electrode 8. This is then followed by heat treatment at 550°C for 5 minutes in a nitrogen or oxygen atmosphere. As a result, the cathode electrode 8 is formed on the lower surface of the n-type single-crystalline gallium oxide substrate 7 in ohmic contact with the n-type single-crystalline gallium oxide substrate 7. Note that in order to reduce the contact resistance between the n-type single-crystalline gallium oxide substrate 7 and the cathode electrode 8, the lower surface of the n-type single-crystalline gallium oxide substrate 7 may be subjected to RIE treatment using a gas such as BCl3 before the formation of the cathode electrode 8.

[0055] 5, an anode electrode 2 is formed on a portion of the upper surface of the n-type gallium oxide epitaxial layer 6 in an active region surrounded by the termination structure in a planar view. The anode electrode 2 is formed in a position that does not overlap, in a planar view, with the trench structure 100 that will be formed in a later step. The method for forming the anode electrode 2 is not particularly limited, but for example, the anode electrode 2 can be formed by forming a resist pattern mask by photolithography, forming a metal that forms a Schottky junction with the n-type gallium oxide epitaxial layer 6, and then performing a lift-off process.

[0056] Next, as shown in FIG. 6, a trench structure 100 is formed using the anode electrode 2 as an etching mask. For example, the trench structure 100 is formed in the surface portion of the n-type gallium oxide epitaxial layer 6 by dry etching using a dry etching gas such as boron trichloride (BCl3). The method for forming the trench structure 100 is not particularly limited, and existing methods such as dry etching or wet etching can be used. It is also desirable to remove a damaged layer formed in the n-type gallium oxide epitaxial layer 6 by etching in a post-processing step.

[0057] Next, as shown in FIG. 7 , a p-type semiconductor layer 5 is formed so as to cover the inside of the trench structure 100 and the outside of the trench structure 100 (specifically, a portion including the top of the trench structure 100 on which the anode electrode 2 is formed and a portion of the upper surface of the n-type gallium oxide epitaxial layer 6 that is exposed without the anode electrode 2). The method for forming the p-type semiconductor layer 5 is not particularly limited, and examples include methods such as sputtering or pulsed laser deposition (PLD) to form a p-type semiconductor layer 5 with desired physical properties. Furthermore, various techniques can be used to form the pattern, such as lift-off or etching.

[0058] 8, in the termination structure, a field plate insulating material layer 3 is formed on the exposed upper surface of the n-type gallium oxide epitaxial layer 6 and the upper surface of the p-type semiconductor layer 5. The method for forming the field plate insulating material layer 3 is not particularly limited, and it can be formed using, for example, a plasma CVD method, a sputtering method, or a spin-on glass (SOG) method.

[0059] Finally, an anode electrode 1 is formed on the upper surface of the p-type semiconductor layer 5 and the upper surface of the field plate insulating material layer 3, thereby completing the semiconductor device according to this embodiment, as shown in FIG.

[0060] <Second embodiment> A semiconductor device and a method for manufacturing the semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0061] <Configuration of semiconductor device> 9 is a cross-sectional view schematically showing an example of the configuration of a semiconductor device according to this embodiment. The method for manufacturing the semiconductor device according to this embodiment is the same as the method for manufacturing the semiconductor device according to the first embodiment.

[0062] 1, the p-type semiconductor layer 5 is formed so as to fill the inside of the trench structure 100. On the other hand, in the semiconductor device according to this embodiment shown in FIG. 9, the p-type semiconductor layer 5A is formed on the sidewalls and bottom of the trench structure 100, and the p-type semiconductor layer 5A is provided on the bottom and side surfaces of the trench structure 100 without filling the inside of the trench structure 100. Then, an anode electrode 1 is provided inside the trench structure 100, surrounded by the p-type semiconductor layer 5A.

[0063] Since a p-type semiconductor layer may act as a resistance component of a device, a low-resistance semiconductor device can be realized by providing a p-type semiconductor layer 5A as shown in FIG.

[0064] <About the manufacturing method of semiconductor devices> Next, a method for manufacturing an oxide semiconductor device as a semiconductor device according to this embodiment will be described with reference to Fig. 9 to Fig. 11. Fig. 10 and Fig. 11 are cross-sectional views for explaining the method for manufacturing a semiconductor device according to this embodiment.

[0065] 6, a p-type semiconductor layer 5A is formed so as to cover the inside of the trench structure 100 and the outside of the trench structure 100 (specifically, a portion including the top of the trench structure 100 on which the anode electrode 2 is formed and a portion of the upper surface of the n-type gallium oxide epitaxial layer 6 that is exposed without the anode electrode 2), as shown in an example in Fig. 10. The method for forming the p-type semiconductor layer 5A is not particularly limited, and for example, a method such as a sputtering method or a PLD method may be used to form a p-type semiconductor layer 5A with desired physical properties.

[0066] 11, in the termination structure, a field plate insulating material layer 3 is formed on the exposed upper surface of n-type gallium oxide epitaxial layer 6 and the upper surface of p-type semiconductor layer 5A. The method for forming field plate insulating material layer 3 is not particularly limited, and it can be formed using, for example, a plasma CVD method, a sputtering method, or an SOG method.

[0067] Finally, an anode electrode 1 is formed on the upper surface of the p-type semiconductor layer 5A and the upper surface of the field plate insulating material layer 3, thereby completing the semiconductor device according to this embodiment, as shown in FIG.

[0068] <Third embodiment> A semiconductor device and a method for manufacturing the semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0069] <Configuration of semiconductor device> 12 is a cross-sectional view schematically illustrating the configuration of a semiconductor device according to this embodiment. The method for manufacturing the semiconductor device according to this embodiment is substantially the same as the methods for manufacturing the semiconductor devices according to the first and second embodiments.

[0070] 9, the p-type semiconductor layer 5A is also formed on the top of the trench structure 100 in the active region. On the other hand, in the semiconductor device according to the present embodiment shown in FIG. 12, the p-type change layer 4 is formed on the top of the trench structure 100 in the active region so as to cover the upper surface of the anode electrode 2.

[0071] The p-type change layer 4 is a layer with lower electrical resistance than the p-type semiconductor layer 5A, and if the p-type semiconductor layer 5A is, for example, an oxide semiconductor, it is desirably reduced and metallized (to have low electrical resistance). Note that the p-type semiconductor layer 5B is formed in areas where the p-type change layer 4 is not formed (other than the top of the outside of the trench structure 100, the inside of the trench structure 100, and the side surface of the anode electrode 2). The electrical resistance of the p-type change layer 4 is lower than the electrical resistance of the p-type semiconductor layer 5A.

[0072] The method for forming the p-type change layer 4 is not particularly limited, but for example, the p-type semiconductor layer 5A can be changed into a low-resistance layer (i.e., the p-type change layer 4) by plasma treatment. Here, gases such as helium, argon, hydrogen, nitrogen, or oxygen can be used for the plasma treatment. Due to these gases, the p-type change layer 4 contains at least one of helium, argon, hydrogen, nitrogen, and oxygen.

[0073] When the p-type change layer 4 is formed on the upper surface outside the trench structure 100 in the active region, the resistance between the anode electrode 1 and the anode electrode 2 decreases. This reduces the resistance of the semiconductor device itself. Furthermore, because the p-type semiconductor layer 5 can be changed into the p-type change layer 4 by plasma treatment using argon gas, it is possible to reduce the resistance of even materials that are highly etch-resistant and difficult to process.

[0074] <About the manufacturing method of semiconductor devices> Next, a method for manufacturing an oxide semiconductor device as a semiconductor device according to this embodiment will be described with reference to Fig. 12 to Fig. 14. Fig. 13 and Fig. 14 are cross-sectional views for explaining the method for manufacturing a semiconductor device according to this embodiment.

[0075] First, for the structure shown in Fig. 10, plasma is irradiated onto the top of the trench structure 100 where the anode electrode 2 is formed, as shown in Fig. 13. By doing so, the p-type semiconductor layer 5A formed on the top surface of the anode electrode 2 is changed, and a p-type change layer 4 is formed.

[0076] 14, in the termination structure, a field plate insulating material layer 3 is formed on part of the top surface of the p-type change layer 4, the exposed top surface of the n-type gallium oxide epitaxial layer 6, and the top surface of the p-type semiconductor layer 5B. The method for forming the field plate insulating material layer 3 is not particularly limited, and it can be formed using, for example, a plasma CVD method, a sputtering method, or an SOG method.

[0077] Finally, an anode electrode 1 is formed on the upper surface of the p-type change layer 4, the upper surface of the p-type semiconductor layer 5A, and the upper surface of the field plate insulating material layer 3, thereby completing the semiconductor device according to this embodiment, as shown in FIG. 12.

[0078] <Effects Produced by the Multiple Embodiments Described Above> Next, examples of effects obtained by the above-described embodiments will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the above-described embodiments, but these may be replaced with other specific configurations exemplified in the present specification as long as the same effects are obtained. In other words, for convenience, only one of the associated specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another associated specific configuration.

[0079] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations illustrated in different embodiments may be combined to produce the same effect.

[0080] According to the above-described embodiment, the semiconductor device includes a first conductivity type gallium oxide layer, a first anode electrode, a second conductivity type semiconductor layer, and a second anode electrode. Here, the gallium oxide layer corresponds to, for example, the n-type gallium oxide epitaxial layer 6. The first anode electrode corresponds to, for example, the anode electrode 2. The semiconductor layer corresponds to, for example, the p-type semiconductor layer 5, the p-type semiconductor layer 5A, the p-type semiconductor layer 5B, and the like. The second anode electrode corresponds to, for example, the anode electrode 1. The anode electrode 2 is provided on a portion of the upper surface of the n-type gallium oxide epitaxial layer 6. The p-type semiconductor layer 5 is provided so as to cover a portion of the n-type gallium oxide epitaxial layer 6 and at least a portion of the anode electrode 2. The anode electrode 1 is provided so as to cover the p-type semiconductor layer 5. A plurality of trenches are provided in a surface portion of the n-type gallium oxide epitaxial layer 6. Here, the trenches correspond to, for example, trench structures 100. The anode electrode 2 is provided in a surface portion of the n-type gallium oxide epitaxial layer 6 that does not overlap with the trench structures 100 in plan view. The p-type semiconductor layer 5 is provided to cover the n-type gallium oxide epitaxial layer 6 inside the trench structures 100.

[0081] With this configuration, it is possible to suppress leakage current. Specifically, by forming the anode electrode 2 on the top of the trench structure 100, the Schottky junction formed between the lower surface of the anode electrode 2 and the top of the trench structure 100 is protected by the anode electrode 2. Therefore, the Schottky junction formed between the lower surface of the anode electrode 2 and the top of the trench structure 100 is not damaged in the manufacturing process after the structure is formed. This makes it possible to suppress an increase in leakage current due to damage to the Schottky junction.

[0082] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0083] Furthermore, according to the embodiment described above, the p-type semiconductor layer 5A (p-type semiconductor layer 5B) is provided on the bottom and side surfaces inside the trench structure 100. Then, the anode electrode 1 is provided inside the trench structure 100, surrounded by the p-type semiconductor layer 5A (p-type semiconductor layer 5B). With this configuration, the device resistance can be lowered compared to when the entire inside of the trench structure 100 is filled with a p-type semiconductor layer.

[0084] Furthermore, according to the embodiment described above, the p-type semiconductor layer 5 is made of a metal oxide material. With such a configuration, the p-type semiconductor layer 5 can exhibit p-type conductivity without adding p-type impurities. Furthermore, a hetero pn junction between the p-type semiconductor layer 5 and the n-type gallium oxide epitaxial layer 6 is formed between oxides, improving stability.

[0085] Furthermore, according to the above-described embodiment, the metal oxide material is copper oxide, silver oxide, nickel oxide, or tin oxide. With such a configuration, the p-type semiconductor layer 5 can exhibit p-type conductivity without adding p-type impurities. Furthermore, a hetero pn junction between the p-type semiconductor layer 5 and the n-type gallium oxide epitaxial layer 6 is formed between oxides, improving stability.

[0086] Furthermore, according to the embodiment described above, the semiconductor device includes a second conductivity type change layer provided to cover the upper surface of the anode electrode 2. Here, the change layer corresponds to, for example, the p-type change layer 4. The p-type semiconductor layer 5B is provided to cover the side surface of the anode electrode 2. The electrical resistance of the p-type change layer 4 is lower than the electrical resistance of the p-type semiconductor layer 5B. Note that the p-type semiconductor layer 5B and the p-type change layer 4 may be formed as an integral semiconductor layer, with part of the semiconductor layer being changed into the p-type change layer 4 by plasma irradiation, or they may be formed separately. With this configuration, the electrical resistance between the anode electrode 2 and the anode electrode 1 can be reduced, thereby lowering the on-resistance of the device.

[0087] Furthermore, according to the embodiment described above, at least one of helium, argon, hydrogen, nitrogen, and oxygen is contained in the p-type change layer 4. With this configuration, the p-type change layer 4 is formed from the p-type semiconductor layer by plasma irradiation using at least one of helium, argon, hydrogen, nitrogen, and oxygen, thereby making it possible to reduce the resistance of a material that is highly etch-resistant (and difficult to process).

[0088] According to the embodiment described above, in the method for manufacturing a semiconductor device, an anode electrode 2 is provided on a portion of the upper surface of a first conductivity type n-type gallium oxide epitaxial layer 6. Then, a surface portion of the n-type gallium oxide epitaxial layer 6 is etched using the anode electrode 2 as a mask to provide a plurality of trench structures 100. Then, a second conductivity type p-type semiconductor layer 5 is provided so as to cover a portion of the n-type gallium oxide epitaxial layer 6 including the inside of the trench structures 100 and at least a portion of the anode electrode 2. Then, an anode electrode 1 is provided so as to cover the p-type semiconductor layer 5.

[0089] With this configuration, leakage current can be suppressed. Furthermore, by forming the trench structure 100 using the anode electrode 2 as an etching mask and forming the p-type semiconductor layer 5 to cover the inside and outside of the trench structure 100 while leaving the anode electrode 2, a JBS element can be easily manufactured without removing the p-type semiconductor layer 5 (without processing such as planarization). Furthermore, since processing of the p-type semiconductor layer 5 is not required, damage to the p-type semiconductor layer 5 that occurs during this processing is also suppressed, and the stability of the Schottky interface can be improved.

[0090] Unless otherwise specified, the order in which the processes are performed can be changed.

[0091] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0092] Furthermore, according to the embodiment described above, in the method for manufacturing a semiconductor device, a p-type change layer 4 of the second conductivity type is provided so as to cover the upper surface of the anode electrode 2. Here, the p-type semiconductor layer 5B is provided so as to cover the side surface of the anode electrode 2. Furthermore, the electrical resistance of the p-type change layer 4 is lower than the electrical resistance of the p-type semiconductor layer 5B. With this configuration, the electrical resistance between the anode electrode 2 and the anode electrode 1 can be reduced, thereby lowering the resistance of the device.

[0093] Furthermore, according to the embodiment described above, the p-type change layer 4 is formed by irradiating plasma onto the p-type semiconductor layer 5A covering the upper surface of the anode electrode 2. With this configuration, the p-type change layer 4 is formed from the p-type semiconductor layer by irradiating it with plasma using at least one of helium, argon, hydrogen, nitrogen, and oxygen, thereby making it possible to reduce the resistance of a material that is highly etch-resistant (and difficult to process).

[0094] <Modifications of the above-described embodiments> In the multiple embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limiting.

[0095] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component in at least one embodiment and combining it with a component in another embodiment.

[0096] Furthermore, in at least one of the embodiments described above, when a material name or the like is stated without being specifically specified, unless a contradiction arises, it is assumed that the material in question includes other additives, such as alloys.

[0097] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that "one" component is provided, it is also understood that "one or more" of that component may be provided.

[0098] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, cases where one component corresponds to part of a structure, and even cases where multiple components are provided in one structure.

[0099] Furthermore, each of the components in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

[0100] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art. [Explanation of symbols]

[0101] 1 anode electrode, 2 anode electrode.

Claims

1. a gallium oxide layer of a first conductivity type; a first anode electrode provided on a portion of an upper surface of the gallium oxide layer; a second conductivity type semiconductor layer provided to cover a portion of the gallium oxide layer and at least a portion of the first anode electrode; a second anode electrode provided to cover the semiconductor layer; A surface portion of the gallium oxide layer is provided with a plurality of trenches, the first anode electrode is provided on the surface portion of the gallium oxide layer that does not overlap with the trench in a plan view; the semiconductor layer is provided over the gallium oxide layer within the trench; Semiconductor device.

2. 2. The semiconductor device according to claim 1, the semiconductor layer is provided on the bottom and side surfaces of the interior of the trench; the second anode electrode is provided in the interior of the trench and surrounded by the semiconductor layer; Semiconductor device.

3. 3. The semiconductor device according to claim 1, The semiconductor layer is made of a metal oxide material. Semiconductor device.

4. 4. The semiconductor device according to claim 3, the metal oxide material is copper oxide, silver oxide, nickel oxide or tin oxide; Semiconductor device.

5. 3. The semiconductor device according to claim 1, a second conductivity type change layer provided to cover an upper surface of the first anode electrode; the semiconductor layer is provided to cover a side surface of the first anode electrode, the electrical resistance of the change layer is lower than the electrical resistance of the semiconductor layer; Semiconductor device.

6. 6. The semiconductor device according to claim 5, the change layer contains at least one of helium, argon, hydrogen, nitrogen, and oxygen; Semiconductor device.

7. a first anode electrode is provided on a portion of an upper surface of the first conductivity type gallium oxide layer; etching a surface portion of the gallium oxide layer using the first anode electrode as a mask to form a plurality of trenches; a semiconductor layer of a second conductivity type is provided so as to cover a portion of the gallium oxide layer including the inside of the trench and at least a portion of the first anode electrode; providing a second anode electrode so as to cover the semiconductor layer; A method for manufacturing a semiconductor device.

8. 8. The method for manufacturing a semiconductor device according to claim 7, a second conductivity type change layer is further provided so as to cover an upper surface of the first anode electrode; the semiconductor layer is provided to cover a side surface of the first anode electrode, the electrical resistance of the change layer is lower than the electrical resistance of the semiconductor layer; A method for manufacturing a semiconductor device.

9. 9. The method for manufacturing a semiconductor device according to claim 8, the change layer is formed by irradiating the semiconductor layer covering the upper surface of the first anode electrode with plasma. A method for manufacturing a semiconductor device.

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