Semiconductor device, semiconductor device control method, and semiconductor device manufacturing method

Abstract

A semiconductor device according to the present disclosure comprises: a drift layer including a first pillar region of a first conduction type alternating with a second pillar region of a second conduction type; a base region of the second conduction type disposed on the first main surface side of the drift layer; a gate insulating film disposed so as to be in contact with the base region; a gate electrode disposed on the gate insulating film; a charge-holding region of the first conduction type disposed between the base region and the second pillar region; and an emitter region of the first conduction type disposed on the surface layer, on the first main surface side, of the base region. The lower end of the second pillar region, which is the end lying on the second main surface side, is located further toward the second main surface side than the lower end of the first pillar region, which is the end lying on the second main surface side. When the width of the upper end of the second pillar region, which is the end lying on the first main surface side, is expressed by wp1, the width of a portion of the second pillar region which lies in the same position as the lower end of the first pillar region is expressed by wp2, and the width of the lower end of the second pillar region is expressed by wp3, then wp3>wp2 and wp1>wp2.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, a method for controlling the semiconductor device, and a method for manufacturing the semiconductor device. [Background technology]

[0002] The superjunction structure, in which n-type pillar regions and p-type pillar regions are arranged alternately in a plan view, is a structure mainly used in the drift layer of power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and by narrowing the pitch at which the n-type and p-type pillar regions are arranged, the n-type pillar regions can be made highly concentrated (reduced resistance).Power MOSFETs that employ the superjunction structure can achieve a lower on-voltage at the same breakdown voltage compared to conventional power MOSFETs (power MOSFETs that do not employ the superjunction structure).

[0003] Superjunction IGBTs, which apply the superjunction structure to IGBTs (Insulated Gate Bipolar Transistors), are expected to achieve even lower on-state voltages by using holes injected from the p-type collector layer on the backside to exert the IE (Injection Enhanced) effect, just like conventional IGBTs (IGBTs that do not use the superjunction structure), and by strengthening conductivity modulation.

[0004] In conventional IGBTs, a technology has been disclosed in which an n-type charge retention region is provided between the n-type drift region and the p-type base region to restrict the movement of holes injected from the p-type collector layer on the back surface, thereby enabling low on-resistance (see, for example, Patent Document 1).

[0005] It has also been disclosed that in superjunction IGBTs, the trade-off relationship between the collector-emitter on-voltage Vce(sat) and the turn-off loss Eoff can be improved compared to conventional IGBTs (see, for example, Patent Document 2).

[0006] Furthermore, a superjunction structure has been disclosed in which n-type pillar regions and p-type pillar regions are formed perpendicularly in the depth direction (see, for example, Non-Patent Document 1). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 3288218 [Patent Document 2] Special Publication No. 2009-525610 [Non-patent literature]

[0008] [Non-Patent Document 1] T. Tamaki, "Vertical Charge Imbalance Effect on 600 V-class Trench-Filling Superjunction Power MOSFETs", the 23rd International Symposium on Power Semiconductor Devices & IC's, May 23-26, 2011, p.308-311 Summary of the Invention [Problem to be solved by the invention]

[0009] Patent Documents 1 and 2 and Non-Patent Document 1 do not disclose a superjunction structure that can achieve both reduced on-state voltage and robust breakdown voltage. For example, in Patent Document 2, the p-type pillar region and the p-type base region are electrically connected, and holes injected from the backside in the on-state are discharged to the emitter terminal via the p-type pillar region and the p-type base region. Therefore, to reduce the on-state voltage, it is necessary to increase the concentration of the n-type pillar region by narrowing the pitch at which the n-type pillar region and the p-type pillar region are arranged. However, there are limitations to narrowing the pitch. Furthermore, increasing the concentration of the n-type pillar region results in a conduction state in which electrons flow unevenly in the n-type pillar region and holes flow unevenly in the p-type pillar region, which limits the reduction in on-state voltage.

[0010] Furthermore, in a structure in which the n-type pillar region and the p-type pillar region are formed vertically in the depth direction as in Non-Patent Document 1, the sensitivity of the device's withstand voltage to the concentration of the pillar region becomes strong, which has the disadvantage of significantly reducing the robustness of the withstand voltage against manufacturing variations.

[0011] The present disclosure has been made to solve such problems, and aims to provide a semiconductor device having a superjunction structure that can achieve both a reduced on-state voltage and robust breakdown voltage, a method for controlling the semiconductor device, and a method for manufacturing the semiconductor device. [Means for solving the problem]

[0012] In order to solve the above problems, a semiconductor device according to the present disclosure has a first main surface and a second main surface opposite to the first main surface, and includes a drift layer including first pillar regions of a first conductivity type and second pillar regions of a second conductivity type that are alternately arranged in a direction parallel to the first and second main surfaces, a base region of a second conductivity type selectively arranged on the first main surface side of the drift layer, a gate insulating film arranged to be in contact with the base region, a gate electrode arranged to be opposite to the base region via the gate insulating film, and a gate insulating film arranged between the base region and the second pillar region. and an emitter region of the first conductivity type selectively disposed in a surface layer of the base region on the first main surface side, wherein the lower end, which is the end of the second pillar region on the second main surface side, is located closer to the second main surface than the lower end, which is the end of the first pillar region on the second main surface side, and where the width of the upper end, which is the end of the second pillar region on the first main surface side, is wp1, the width of the second pillar region at the same position as the lower end of the first pillar region is wp2, and the width of the lower end of the second pillar region is wp3, then wp3 > wp2 and wp1 > wp2. [Effects of the Invention]

[0013] According to the present disclosure, it is possible to achieve both a reduction in on-state voltage and robustness in withstand voltage.

[0014] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first embodiment. [Figure 2] 10 is a diagram for explaining the relationship between the ratio of the amount of impurities in the p-type pillar region to the amount of impurities in the n-type pillar region and the breakdown voltage of the semiconductor device. FIG. [Figure 3] 10 is a diagram for explaining the relationship between the ratio of the amount of impurities in the p-type pillar region to the amount of impurities in the n-type pillar region and the breakdown voltage of the semiconductor device. FIG. [Figure 4]10 is a diagram for explaining the relationship between the ratio of the amount of impurities in the p-type pillar region to the amount of impurities in the n-type pillar region and the four pressures of the semiconductor device. FIG. [Figure 5] 10 is a diagram for explaining the relationship between the ratio of the amount of impurities in the p-type pillar region to the amount of impurities in the n-type pillar region and the breakdown voltage of the semiconductor device. FIG. [Figure 6] 1 is a graph showing an example of electric field strength along a direction from a first main surface to a second main surface in a semiconductor device. [Figure 7] 2A to 2C are cross-sectional views showing an example of a manufacturing process for the semiconductor device according to the first embodiment. [Figure 8] 2A to 2C are cross-sectional views showing an example of a manufacturing process for the semiconductor device according to the first embodiment. [Figure 9] 2A to 2C are cross-sectional views showing an example of a manufacturing process for the semiconductor device according to the first embodiment. [Figure 10] 2A to 2C are cross-sectional views showing an example of a manufacturing process for the semiconductor device according to the first embodiment. [Figure 11] 2A to 2C are cross-sectional views showing an example of a manufacturing process for the semiconductor device according to the first embodiment. [Figure 12] 2A to 2C are cross-sectional views showing an example of a manufacturing process for the semiconductor device according to the first embodiment. [Figure 13] 2A to 2C are cross-sectional views showing an example of a manufacturing process for the semiconductor device according to the first embodiment. [Figure 14] 2A to 2C are cross-sectional views showing an example of a manufacturing process for the semiconductor device according to the first embodiment. [Figure 15] 2A to 2C are cross-sectional views showing an example of a manufacturing process for the semiconductor device according to the first embodiment. [Figure 16] 2A to 2C are cross-sectional views showing an example of a manufacturing process for the semiconductor device according to the first embodiment. [Figure 17] 2A to 2C are cross-sectional views showing an example of a manufacturing process for the semiconductor device according to the first embodiment. [Figure 18] FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a modification of the first embodiment. [Figure 19] FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a second embodiment. [Figure 20]10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first modification of the second embodiment. FIG. [Figure 21] FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to Modification 2 of Embodiment 2. [Figure 22] FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a third embodiment. [Figure 23] 10A to 10C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to a third embodiment. [Figure 24] 10A to 10C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to a third embodiment. [Figure 25] 10A to 10C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to a third embodiment. [Figure 26] 10A to 10C are cross-sectional views showing an example of a manufacturing process for a semiconductor device according to a third embodiment. [Figure 27] FIG. 11 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a modification of the third embodiment. [Figure 28] FIG. 10 is a plan view showing an example of an upper surface layout of a semiconductor device according to a fourth embodiment. [Figure 29] 29 is a cross-sectional view taken along A1-A2 in FIG. 28. [Figure 30] 10 is a graph showing an example of a timing chart of a first gate voltage and a second gate voltage for driving a semiconductor device according to a fourth embodiment. [Figure 31] 10 is a graph showing an example of the delay time dependency of the second gate voltage on the surge voltage and the turn-off loss in the semiconductor device according to the fourth embodiment. [Figure 32] FIG. 13 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a modification of the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type. The same parts in the drawings are assigned the same numbers. Furthermore, the termination structure in the peripheral region of the device (semiconductor device) is not shown, and only the cross-sectional structure of a unit cell is illustrated. The semiconductor substrate used in the device may be a wafer manufactured by the MCZ (Magnetic Field Applied Czochralski) method, a wafer manufactured by the FZ (Floating Zone) method, or an epitaxial substrate manufactured by the CZ (Czochralski) method, and may be manufactured using any substrate manufacturing technology required for device manufacturing, regardless of the substrate manufacturing method.

[0017] The device may also be a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that uses an n-type drain layer instead of a p-type collector layer on the back surface, or may have a partially patterned n-type collector layer in addition to the p-type collector layer. Alternatively, the device may be an RC (Reverse-Conducting) IGBT in which both a MOSFET region and a diode region are provided on the front surface, a p-type collector region is located on the back surface of the semiconductor substrate directly below the MOSFET region, and an n-type cathode region is located on the back surface of the semiconductor substrate directly below the diode region.

[0018] <First Embodiment> <Configuration of Semiconductor Device According to First Embodiment> 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first embodiment. The semiconductor device shown in FIG. 1 is a planar gate type superjunction IGBT element manufactured using a silicon-based semiconductor substrate. A semiconductor device having a withstand voltage between the emitter and collector of about 1200 volts will be specifically described below as an example, but the present invention is also applicable to superjunction IGBT elements having other withstand voltage values ​​or semiconductor devices having other superjunction structures.

[0019] The semiconductor device shown in Fig. 1 has a first main surface and a second main surface opposite to the first main surface. The first main surface is the surface on the upper side of the paper in Fig. 1 and corresponds to the front side of the semiconductor device. The second main surface is the surface on the lower side of the paper in Fig. 1 and corresponds to the back side of the semiconductor device.

[0020] The drift layer 10 includes n-type pillar regions 107 (first conductivity type first pillar regions) and p-type pillar regions 108 (second conductivity type second pillar regions) alternately arranged in a direction parallel to the first and second main surfaces. The p-type base region 105 is selectively arranged on the first main surface side of the drift layer 10. The n-type emitter regions 103 and the p-type body contact regions 104 are selectively arranged in a surface layer on the first main surface side of the p-type base region 105. The n-type charge retention region (carrier stored region: CS region) 106 is arranged between the p-type base region 105 and the p-type pillar region 108. The gate insulating film 101 is arranged so as to be in contact with the p-type base region 105. The gate electrode 102 is arranged facing the p-type base region 105 with the gate insulating film 101 interposed therebetween. The lower end, which is the end on the second main surface side of the p-type pillar region 108, is located closer to the second main surface than the lower end, which is the end on the second main surface side of the n-type pillar region 107. If the width of the upper end, which is the end on the first main surface side of the p-type pillar region 108, is wp1, the width of the p-type pillar region 108 at the same position (same depth position) as the lower end of the n-type pillar region 107 is wp2, and the width of the lower end of the p-type pillar region 108 is wp3, then wp3>wp2 and wp1>wp2.

[0021] The n-type bottom layer 109 is disposed on the second major surface side of the drift layer 10. The n-type buffer layer 110 is disposed on the second major surface side of the n-type bottom layer 109. The p-type collector layer 111 is disposed on the second major surface side of the n-type buffer layer 110. The collector electrode 112 is disposed on the second major surface side of the p-type collector layer 111.

[0022] A plurality of gate electrodes 102 are arranged in a stripe pattern above the n-type pillar regions 107, and similar to the p-type pillar regions 108, the gate electrodes 102 are also arranged in a stripe pattern in the depth direction of the paper in FIG. 1 (perpendicular to the paper), thereby forming a MOSFET with a planar gate structure.

[0023] FIG. 1 illustrates a structure in which one gate electrode 102 is provided above one n-type pillar region 107, and the widthwise pitch of the n-type pillar region 107 and the gate electrode 102 is the same, but the widthwise widths of the n-type pillar region 107 and the gate electrode 102 may be different.

[0024] <Operation of the Semiconductor Device According to the First Embodiment> Next, the operation of the semiconductor device according to the first embodiment will be described.

[0025] 2 to 5 are diagrams illustrating the relationship between the ratio of the impurity amount in the p-type pillar region to the impurity amount in the n-type pillar region and the breakdown voltage of the semiconductor device. In FIG. 5, the horizontal axis represents the ratio (Qp / Qn) of the impurity amount in the p-type pillar region (Qp) to the impurity amount in the n-type pillar region (Qn), and the vertical axis represents the breakdown voltage of the semiconductor device. Structures A to C shown in FIGS. 2 to 4 are superjunction structures. Structures A and B are superjunction structures possessed by a semiconductor device according to a comparative example, and structure C is the superjunction structure possessed by a semiconductor device according to embodiment 1. FIG. 5 shows the results of a simulation regarding the influence of the impurity ratio in structures A to C shown in FIGS. 2 to 4 on the breakdown voltage.

[0026] 6 is a graph showing an example of the electric field intensity in the direction from the first main surface to the second main surface (depth direction) of a semiconductor device. Structures A to C shown in FIG. 6 correspond to structures A to C shown in FIGS.

[0027] The operation of the semiconductor device according to the comparative example will be described. As shown in FIGS. 2 and 3, the semiconductor device according to the comparative example is a semiconductor device including a drift layer including an n-type pillar region and a p-type pillar region that form a superjunction structure (Structure A or Structure B).

[0028] With the collector electrode as the positive electrode and the emitter electrode as the negative electrode, by applying a voltage between the collector electrode and the emitter electrode, depletion layers expand from the pn junction interface between the p-type pillar region and the n-type pillar region to the p-type pillar region and the n-type pillar region, respectively. At this time, the breakdown voltage can be ensured by setting the pitch interval or impurity concentration of the p-type pillar region and the n-type pillar region so that the depletion layers expanding from adjacent pillar regions can punch through each other.

[0029] The breakdown voltage of the semiconductor device depends on the impurity amount ratio in the drift layer. When the impurity amount (Qn) in the n-type pillar region is equal to the impurity amount (Qp) in the p-type pillar region, that is, when "Qn = Qp", the expansion of the depletion layer according to the voltage becomes maximum and the breakdown voltage becomes maximum. On the other hand, if one of the impurity amounts increases due to, for example, variations in the manufacturing process, that is, when "Qn>Qp" or "Qn<Qp", the depletion layer does not expand sufficiently and the breakdown voltage decreases.

[0030] Also, depending on the shape of the pillar region, the sensitivity of the breakdown voltage of the semiconductor device to the impurity amount ratio in the drift layer changes. For example, when the upper end width and the lower end width (width of the bottom) of the p-type pillar region are equal and the p-type pillar region is formed in the vertical direction, the sensitivity of the influence on the breakdown voltage to the change in the impurity amount of the pillar region becomes high. When "Qn = Qp" where the breakdown voltage is maximum, the space charge density in the drift layer becomes almost zero, the electric field strength distribution in the depth direction becomes flat, and the breakdown voltage is maximized. In this way, the state where the impurity amount (Qn) in the n-type pillar region is equal to the impurity amount (Qp) in the p-type pillar region and the charge balance is maintained is called the charge balance state.

[0031] A charge imbalance state refers to a state of charge imbalance in which either the impurity amount (Qn) in the n-type pillar region or the impurity amount (Qp) in the p-type pillar region increases. When "Qn > Qp", a drift layer with a positive space charge density holds the applied voltage, and when "Qn < Qp", a drift layer with a negative space charge density holds the applied voltage. At this time, along the direction from the first main surface to the second main surface, the electric field strength distribution in the drift layer generates a slope corresponding to the excess charge amount ΔQ (ΔQ = Qp - Qn). Therefore, the breakdown voltage in the charge imbalance state is lower than that in the charge balance state.

[0032] Suppression of the decrease in breakdown voltage due to the excess charge amount in the drift layer can be achieved, for example, as disclosed in Non-Patent Document 1, by forming a p-type pillar region having a smaller lower end width than the upper end width and having a forward taper shape from the first main surface to the second main surface. According to this method, the excess charge amount does not become uniform in the drift layer, but by creating a non-uniformity in the excess charge amount such that the excess charge amount in the drift layer decreases along the direction from the first main surface to the second main surface, an electric field distribution showing an electric field peak at a depth near the center of the drift layer is obtained in the charge balance state (Qn = Qp). At this time, when Qn > Qp, the position of the electric field peak shifts to the shallower side (the side of the first main surface), and when Qn < Qp, the position of the electric field peak shifts to the deeper side (the side of the second main surface). Therefore, even when the charge imbalance state is reached, the shape of the electric field strength distribution does not change significantly compared to the charge balance state (it does not change significantly like a vertical p-type pillar region), so the sensitivity of the impurity amount ratio in the drift layer to the breakdown voltage can be reduced.

[0033] The above-described effects of reducing the sensitivity of the drift layer impurity ratio to the breakdown voltage of a semiconductor device and improving the breakdown voltage of the semiconductor device can also be applied to superjunction MOSFET devices. In the case of superjunction MOSFET devices, the charge retention region serves as a current spreading layer, thereby reducing the JFET resistance occurring between the p-type base regions. However, even in superjunction MOSFET devices, the resistance component of the bottom layer cannot be reduced, making it difficult to sufficiently reduce the on-resistance. Therefore, by providing an n-type buffer region and a p-type collector region on the second main surface side, bipolar operation can be achieved, and by providing a charge retention region, the on-resistance can be further reduced.

[0034] When a positive voltage equal to or greater than the MOS threshold voltage is applied to the gate electrode to turn it conductive, an inversion layer forms on the surface of the p-type base region directly below the gate electrode, and electrons are injected from the emitter electrode into the drift layer through the n-type emitter region and the inversion layer. The electrons injected into the drift layer are drifted toward the second main surface by the electric field, passing through the n-type buffer layer and p-type collector layer and then onto the collector electrode. The electrons moving from the first main surface lower the potential of the n-type buffer layer, lowering the built-in potential of the pn junction on the second main surface, and holes are injected from the p-type collector layer. If the concentration of holes injected from the p-type collector layer is higher than the impurity concentrations in the n-type bottom layer and drift layer, conductivity modulation occurs, reducing the on-resistance.

[0035] However, as shown in Fig. 5, the breakdown voltage of a semiconductor device using a tapered p-type pillar region (structure B in Fig. 3) is lower than that of a semiconductor device using a vertical p-type pillar region (structure A in Fig. 2), even in a charge balanced state (Qn = Qp). This is because, as shown in Fig. 6, the electric field strength distribution in the depth direction of a semiconductor device using a vertical p-type pillar region is almost flat, whereas the electric field strength distribution in the depth direction of a semiconductor device using a tapered p-type pillar region has one peak in the drift layer, and the electric field strength is lower near the top and bottom of the p-type pillar region.

[0036] Furthermore, when the upper ends of the p-type pillar regions are connected to the p-type base region, holes injected from the p-type collector layer into the n-type buffer layer and the n-type bottom layer in the conductive state are directly discharged to the emitter electrode via the p-type pillar region and the p-type base region. As a result, the effect of conductivity modulation is weakened on the first main surface side of the drift layer, resulting in an increase in on-state voltage.

[0037] Therefore, in the semiconductor device according to the first embodiment (structure C in FIG. 4 ), the upper end width (wp1) of the p-type pillar region 108 is made wider than the width (wp2) of the p-type pillar region 108 at the same depth as the lower end of the n-type pillar region 107 (wp1>wp2), thereby reducing the sensitivity of the impurity amount ratio in the drift layer 10 to the breakdown voltage. In addition, by arranging the n-type bottom layer 109 below the drift layer 10, arranging the lower end of the p-type pillar region 108 closer to the second main surface than the n-type pillar region 107, and making the maximum width (wp3) of the bottom of the p-type pillar region 108 in the n-type bottom layer 109 larger than wp2 (wp3>wp2), it is possible to increase the electric field strength near the bottom of the p-type pillar region 108 and improve the breakdown voltage. Furthermore, by providing the n-type charge retention region 106 between the upper end of the p-type pillar region 108 and the p-type base region 105, the n-type charge retention region 106 acts as a potential barrier for holes injected from the p-type collector layer 111, and the hole accumulation effect (or IE effect) comes into play, making it possible to reduce the on-resistance.

[0038] 1, in a semiconductor device employing a planar gate structure, n-type charge retention region 106 is separated directly below the center of gate electrode 102 (at a position corresponding to the center of gate electrode 102). By separating n-type charge retention region 106 directly below the center of gate electrode 102, an increase in the electric field at the junction interface between p-type base region 105 and n-type charge retention region 106 can be suppressed, and a desired breakdown voltage can be obtained. Furthermore, even if n-type charge retention region 106 is separated directly below the center of gate electrode 102, n-type charge retention region 106 is formed at a deeper position than p-type base region 105 so as to surround p-type base region 105, and the planar dimensions of n-type charge retention region 106 (the width of n-type charge retention region 106 in a direction parallel to the first and second main surfaces) are set larger than the planar dimensions of p-type base region 105 (the width of p-type base region 105 in a direction parallel to the first and second main surfaces). This makes it possible to maintain the breakdown voltage when non-conductive without impairing the charge retention function when conductive.

[0039] The n-type charge retention region 106 and the p-type base region 105 are formed by ion implantation and diffusion processing. The impurity concentration of the n-type charge retention region 106 is made higher than the impurity concentration of the p-type pillar region 108, thereby separating the p-type base region 105 and the p-type pillar region 108 by the n-type charge retention region 106. As shown in FIG. 1, the p-type pillar region 108, which is separated from the p-type base region 105 by the n-type charge retention region 106, is floating (electrically floating). This allows the n-type charge retention region 106 sandwiched between the p-type pillar region 108 and the p-type base region 105 to function as a charge storage layer. However, for example, outside the active region that is the main part of the device, it is not necessarily necessary to separate the p-type pillar region 108 and the p-type base region 105. For example, by connecting the p-type pillar region 108 to the p-type base region 105 in an area other than the essential part of the device, it becomes possible to discharge unnecessary carriers generated during device operation through the contact of the emitter electrode 100, thereby improving the long-term reliability and breakdown resistance of the device.

[0040] <Method of Manufacturing Semiconductor Device According to First Embodiment> Next, each wafer processing step in the manufacturing method of the semiconductor device according to the first embodiment will be described. First, the steps required for forming the first main surface side will be described with reference to FIGS. 7 to 15. Here, only the processing steps required for manufacturing the essential parts of the device shown in FIG. 1 will be described. The thicknesses of the n-type bottom epitaxial layer 409 (n-type bottom layer 109) and the n-type top epitaxial layer 407 (drift layer 10), which will be described later, are exemplified as thicknesses for a superjunction IGBT device with a breakdown voltage of about 1200 volts. Furthermore, steps not directly related to the present disclosure, such as a cleaning process before forming a gate oxide film, a sintering process for an interlayer film and metal wiring, or a passivation film formation process, as well as processing steps required for manufacturing a device termination structure, and an assembly process for singulating devices and assembling them into modules, may be added as appropriate.

[0041] First, as shown in FIG. 7, for example, 10 13 cm -3 An n-type bottom epitaxial layer 409 doped with phosphorus of the order of 1000 .mu.m is formed to a thickness of about 30 to 50 .mu.m. 15 cm -3An n-type top epitaxial layer 407 doped with phosphorus on the order of 1000 nm is formed to a thickness of approximately 50 to 70 μm. In this manner, a semiconductor wafer is prepared in which an n-type bottom epitaxial layer 409 and an n-type top epitaxial layer 407 are formed on an n-type silicon single crystal substrate 400. Here, an n-type substrate is exemplified as the silicon single crystal substrate. However, as will be described later, since the n-type silicon single crystal substrate 400 is ultimately removed by grinding, a p-type substrate may be used instead of an n-type substrate. Furthermore, although there are no restrictions on the impurity concentration of the semiconductor wafer, in order to obtain a desired breakdown voltage, it is preferable that the impurity concentration of the n-type bottom epitaxial layer 409 be lower than that of the n-type top epitaxial layer 407. The surface of the n-type top epitaxial layer 407 of the semiconductor wafer is referred to as a first main surface, and the surface opposite to the first main surface is referred to as a second main surface.

[0042] 8, a hard mask film 410 for forming trenches, made of, for example, P-TEOS (Plasma-Tetraethylorthosilicate), is patterned on the first main surface. Thereafter, using the hard mask film for forming trenches 401 for p-type pillar regions as a mask, the n-type top epitaxial layer 407 is dry-etched to an extent that it reaches the n-type bottom epitaxial layer 409, thereby forming trenches 401 for p-type pillar regions (trenches for second pillar regions). The mesa portion sandwiched between the trenches 401 for p-type pillar regions becomes the n-type pillar region 107. The n-type bottom epitaxial layer 409 corresponds to the n-type bottom layer 109. Here, it is desirable that the bottom of the trench groove 401 for the p-type pillar region reaches the n-type bottom epitaxial layer 409. However, as long as the impurities at the bottom of the p-type pillar region 108 reach the n-type bottom layer 109 by a thermal diffusion process described later, the bottom of the trench groove 401 for the p-type pillar region does not necessarily have to reach the n-type bottom epitaxial layer 409 at this point. Also, at this time, boron ions may be implanted into the bottom of the trench groove 401 for the p-type pillar region. Thereafter, the hard mask film 410, which is no longer needed, is removed.

[0043] 9, epitaxial growth of a material doped with boron, for example, is performed on the trench grooves 401 for the p-type pillar regions, thereby filling the trench grooves 401 for the p-type pillar regions with an epitaxial layer. At this time, an epitaxially grown overgrowth region 411 is also formed on the n-type pillar region 107 so that the trench grooves 401 for the p-type pillar regions are completely filled.

[0044] 10, a planarization process using, for example, CMP (Chemical Mechanical Polishing) is performed to remove the overgrowth region 411 other than the trench grooves 401 for the p-type pillar region, and to planarize the first main surface of the semiconductor wafer. Note that, although the method of forming the superjunction structure by the trench fill epitaxial filling method shown in FIG. 10 has been exemplified here, it may also be formed by a multi-epitaxial manufacturing method.

[0045] 11, a gate oxide film is formed on almost the entire first main surface of the semiconductor wafer by thermal oxidation, and a polysilicon film (corresponding to gate electrode 102) is formed thereon by, for example, low-pressure CVD (Chemical Vapor Deposition). Then, using a resist film as a mask, lithography is used to dry-etch the polysilicon film and gate oxide film to pattern the gate electrode 102 and gate insulating film 101. Here, an approximately 100 nm Si oxide film is exemplified as the gate insulating film 101, and a polysilicon film is exemplified as the material for the gate electrode 102, but amorphous silicon or a metal material such as molybdenum may also be used as the material for the gate electrode 102. Thereafter, the resist film, which is no longer needed, is removed.

[0046] Next, as shown in FIG. 14 cm -2 The n-type charge retention region 106 is formed by ion implantation of phosphorus with a dose of about 100 .mu.m.

[0047] Next, as shown in FIG. 13, a thermal diffusion process is performed, for example, at 1100° C. for approximately 140 minutes, to diffuse the n-type charge retention region 106 to just below the gate electrode 102, and to diffuse the boron at the bottom of the p-type pillar region 108 into the n-type bottom layer 109, thereby widening the width of the bottom of the p-type pillar region 108.

[0048] Next, as shown in FIG. 14 cm -2 The p-type base region 105 is formed by ion implanting boron at a dose of about 1100° C., and then a thermal diffusion process is performed, for example, at 1100° C. for about 30 minutes to diffuse the p-type base region 105. Needless to say, at this time, the n-type charge retention region 106 and the bottom of the p-type pillar region 108 in the n-type bottom layer 109 are also diffused.

[0049] Next, using the resist film for the n-type emitter region as a mask, antimony, arsenic, etc. are doped at 4×10 15 cm -2 The n-type emitter region 103 is formed by implanting ions at a dose of about 100 . Then, the resist film for the n-type emitter region, which is no longer needed, is removed. After that, lithography is performed using the resist film for the p-type body contact region as a mask, and boron, for example, is implanted at a dose of 4×10 15 cm -2 Ion implantation is performed with a dose of about 1000° C. to form the p-type body contact region 104. Thereafter, in order to activate the n-type emitter region 103 and the p-type body contact region 104, annealing is performed at, for example, about 1000° C. using lamp heating or a diffusion furnace.

[0050] Next, a PSG (Phospho-Silicate-Glass) film is formed over almost the entire first main surface of the semiconductor wafer by CVD, and a BPSG (Boro-Phospho-Silicate Glass) film or an SOG (Spin on Glass) film may be overlaid for planarization.

[0051] 15, a resist film for opening an emitter contact hole is formed, and the emitter contact hole is opened by dry etching using the resist film as a mask. The unnecessary resist film is then removed. After that, an aluminum-based metal layer is formed by sputtering or the like on a barrier metal film such as TiW, and patterned to form the emitter electrode 100.

[0052] Next, steps required for forming the second main surface side in each wafer processing step in the method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS.

[0053] As shown in Figure 16, the n-type silicon single crystal substrate 400 located on the second main surface of the semiconductor wafer is completely removed, and the second main surface is ground so that the n-type bottom epitaxial layer 109 is exposed on the surface layer of the second main surface. If grinding damage remains on the second main surface after grinding, the grinding damage layer may be removed by chemical etching. Furthermore, when grinding the second main surface, it is desirable to protect the device structure formed on the first main surface by, for example, applying a protective resist to the first main surface or attaching protective tape to the first main surface.

[0054] Next, as shown in FIG. 17, a 5×10 12 cm -2 The n-type buffer layer 110 is formed by ion implantation of phosphorus with a dose of about 1×10 13 cm -2 A dose of boron is implanted into the n-type buffer layer 110 to form the p-type collector layer 111 at a position shallower than the n-type buffer layer 110 (at a position closer to the second main surface). Thereafter, the n-type buffer layer 110 and the p-type collector layer 111 are activated using, for example, a laser annealing device.

[0055] <Modification of the First Embodiment> 18 is a cross-sectional view schematically showing the structure of a semiconductor device according to a modification of the first embodiment. In FIG. 18, the same parts as those in FIG. 1 are denoted by the same reference numerals, and their description will be omitted. The semiconductor device according to this modification differs from the semiconductor device according to the first embodiment in that n-type JFET regions 121 having a higher impurity concentration than n-type pillar regions 107 are newly disposed between striped n-type charge retention regions 106 extending in a direction perpendicular to the paper surface of FIG. 18.

[0056] In the semiconductor device of this modification, when electrons are injected from the inversion layer formed on the surface of the adjacent p-type base region 105 into the upper part of the n-type pillar region 107 to make it conductive, the n-type JFET region 121 can suppress the width of the depletion layer extending from the p-type base region 105.

[0057] In a conventional semiconductor device with a structure in which striped n-type charge retention regions 106 are separated by n-type pillar regions 107, shortening the cell pitch causes a depletion layer extending from p-type base region 105 to narrow the current path between adjacent n-type charge retention regions 106, resulting in an increase in the on-resistance of the semiconductor device. This modification solves this problem by providing n-type JFET region 121, making it possible to reduce the on-resistance.

[0058] <Embodiment 2> 19 is a cross-sectional view schematically showing the structure of a semiconductor device according to embodiment 2. In Fig. 19, the same parts as those in Fig. 1 are denoted by the same reference numerals, and their description will be omitted. The semiconductor device according to embodiment 2 differs from the semiconductor device according to embodiment 1 in that the p-type pillar bottom region 122, which is located at a position deeper than the bottom end of the n-type pillar region 107 (at a position closer to the second main surface), contains a higher concentration of impurities than the p-type pillar region 108, which is located closer to the first main surface than the p-type pillar bottom region 122.

[0059] 19 , the p-type pillar bottom region 122 is located deeper than the lower end of the n-type pillar region 107 and below the p-type pillar region 108. The impurity concentration of the p-type pillar bottom region 122 is higher than the impurity concentration of the p-type pillar region 108. By providing such a p-type pillar bottom region 122, it is possible to further increase the electric field of the n-type bottom layer 109. As a result, for example, in cases where the drift layer 10 cannot have a sufficient thickness to obtain a desired breakdown voltage, the impurity concentration of the p-type pillar bottom region 122 located deeper than the lower end of the n-type pillar region 107 can be made higher than the impurity concentration of the p-type pillar region 108 above the p-type pillar bottom region 122. This increases the voltage share borne by the n-type bottom layer 109, thereby improving the breakdown voltage.

[0060] <Modifications 1 and 2 of Embodiment 2> Fig. 20 is a cross-sectional view schematically showing the structure of a semiconductor device according to Modification 1 of Embodiment 2. Fig. 21 is a cross-sectional view schematically showing the structure of a semiconductor device according to Modification 2 of Embodiment 2. In Figs. 20 and 21, the same parts as in Fig. 19 are given the same reference numerals and descriptions thereof will be omitted.

[0061] The semiconductor device according to Modification 1 shown in Fig. 20 differs from the semiconductor device according to Embodiment 2 in that p-pillar bottom regions 122, 123 are composed of multiple regions with different widths and impurity concentrations in the depth direction. The p-pillar bottom regions 122 in the semiconductor device according to Modification 1 shown in Fig. 20 are simply formed as an extension of the p-pillar region 108, and this point is what makes it different from the semiconductor device according to Modification 1.

[0062] 21 differs from the semiconductor device of embodiment 2 in that an n-type JFET region 124 having a higher impurity concentration than the n-type pillar region 107 is provided between adjacent p-type pillar bottom regions 122. The n-type JFET region 124 is in contact with the lower end of the n-type pillar region 107. The semiconductor device of embodiment 2 is the same as embodiment 2 or modification 1 in that the impurity concentration of the p-type pillar bottom region 122 is different from the impurity concentration of the p-type pillar region 108.

[0063] 19, the semiconductor device according to the second embodiment has one p-type pillar bottom region 122 arranged therein, which has a higher impurity concentration than the p-type pillar region 108 located at a position shallower than the bottom end of the n-type pillar region 107. On the other hand, the semiconductor device according to the first modification shown in FIG. 20 has multiple p-type pillar bottom regions 123 arranged in the depth direction, which enables more precise control of the electric field distribution.

[0064] Furthermore, if the impurity concentration of the p-pillar bottom regions 122 is increased in an attempt to improve the breakdown voltage, a depletion layer will expand between adjacent p-pillar bottom regions 122, resulting in an increase in on-state voltage. To address this issue, in the semiconductor device according to Modification 2 shown in FIG. 21 , an n-type JFET region 124 having a higher impurity concentration than the n-type pillar region 107 is disposed between the p-pillar bottom regions 122. This makes it possible to achieve both an improvement in the breakdown voltage and a reduction in on-state resistance.

[0065] <Third Embodiment> <Configuration of Semiconductor Device According to Third Embodiment> 22 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment. The semiconductor device according to the third embodiment is a trench-gate superjunction IGBT element manufactured using a silicon-based semiconductor substrate. A semiconductor device having a withstand voltage between the emitter and collector of about 1200 volts will be specifically described below as an example, but the present invention is also applicable to superjunction IGBT elements having other withstand voltage values ​​or semiconductor devices having other superjunction structures.

[0066] The semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment in that the semiconductor device according to the first embodiment is a planar gate MOS semiconductor device, whereas the semiconductor device according to the third embodiment is a trench gate MOS semiconductor device.

[0067] 22, the upper ends of the p-type pillar regions 108 and p-type base regions 105 selectively provided on the first main surface side above the p-type pillar regions 108 are separated by n-type charge retention regions 106. Trench grooves 201 are selectively arranged above the n-type pillar regions 107, extending from low-resistance n-type emitter regions 103 provided in the surface layer of the p-type base region 105, through the p-type base region 105, and reaching part of the n-type charge retention region 106. A gate electrode 102 is disposed in the trench groove 201 with a gate insulating film 101 interposed therebetween.

[0068] The depth position of the bottom (lower end) of the trench 201 is shallower than the depth position of the upper end of the p-type pillar region 108. Therefore, it is possible to prevent a decrease in breakdown voltage due to an increase in the electric field between the upper part of the p-type pillar region 108 and the trench 201.

[0069] <Method of Manufacturing a Semiconductor Device According to Third Embodiment> Next, each wafer processing step in the method for manufacturing a semiconductor device according to the third embodiment will be described with reference to Figures 23 to 26. Here, we will mainly describe the processing steps required to manufacture the essential part of the device shown in Figure 22, but the steps up to manufacturing the superjunction structure on the first main surface side are common to the manufacturing method for the planar gate type superjunction IGBT element shown in Figures 7 to 10, so their description will be omitted. In addition, the steps on the second main surface side are basically the same as those from Figure 16 onwards, so only the differences will be described here.

[0070] After forming a superjunction structure on the first main surface side of the n-type silicon single crystal substrate 400, as shown in FIG. 14 cm -2The n-type charge retention region 106 is formed by ion implantation of phosphorus with a dose of about 100 .mu.m.

[0071] Next, as shown in FIG. 24, for example, 3×10 14 cm -2 The p-type base region 105 is formed by implanting boron ions at a dose of about 100 .mu.m.

[0072] Next, as shown in FIG. 25, a thermal diffusion process is performed, for example, at 1100° C. for approximately 140 minutes to diffuse the n-type charge retention region 106 and the p-type base region 105, and at the same time, the boron at the bottom of the p-type pillar region 108 is diffused into the n-type bottom layer 109, thereby widening the width of the bottom of the p-type pillar region 108.

[0073] Next, as shown in FIG. 26, a trench gate MOSFET is formed in which a gate electrode 102 is buried in a trench 201 (gate trench) via a gate insulating film 101.

[0074] In FIGS. 25 and 26, the trench gate structure is formed after the p-type base region 105 is formed, but conversely, the trench gate structure may be formed first and then the p-type base region 105 may be formed.

[0075] <Modification of the Third Embodiment> FIG. 27 is a cross-sectional view schematically illustrating the structure of a semiconductor device according to a modification of the third embodiment. The same components as those in FIG. 22 are denoted by the same reference numerals, and their descriptions are omitted. The semiconductor device according to this modification differs from the semiconductor device according to the third embodiment in that, while the semiconductor device according to the third embodiment has only the gate electrode 102 formed in the trench 201, some of the trenches in this modification do not have the n-type emitter region 103 on the first major surface side of the p-type base region 105 that contacts the sidewall of the trench 201. Thus, a dummy gate electrode 202 is formed via the gate insulating film 101 in the trench 201 that contacts the p-type base region 105 that does not have the n-type emitter region 103 on the first major surface side. The dummy gate electrode 202 embedded in the trench 201 of the trench dummy gate may be connected to the gate electrode 102 or the emitter electrode 100.

[0076] No n-type emitter region 103 is provided on the first main surface side of the p-type base region 105 that contacts the sidewall of the trench groove 201 of the trench dummy gate, and electrons are not injected through the sidewall of the trench groove 201 of the trench dummy gate, so it is called a "trench dummy gate" to distinguish it from an original gate (trench gate). In this modification, by arranging this trench dummy gate, for example, above the p-type pillar region 108, it is possible to enhance the hole accumulation effect and reduce the on-voltage.

[0077] Furthermore, as shown in Figure 22, in a semiconductor device configured only with trench gates, narrowing the spacing between trench grooves 201 to reduce on-resistance increases the channel density, resulting in a larger saturation current. If the saturation current is large, there is a risk that a large current will flow and destroy the device if a load such as a motor shorts out. Therefore, a structure using trench dummy gates is an effective means of narrowing the trench pitch without increasing the channel density.

[0078] Preferably, the trench groove 201 of the trench dummy gate is disposed above the p-type pillar region 108, and the trench groove 201 of the trench gate is disposed above the n-type pillar region 107. This allows electrons to be efficiently injected from the n-type emitter region 103 into the n-type charge retention region 106 and the n-type pillar region 107 below it via an inversion layer formed in the p-type base region 105 near the sidewall of the trench groove 201 of the trench gate.

[0079] Dynamic avalanches are generated by high charges generated during switching operations, and hot carriers generated by the avalanches can be trapped at the MOS interface of the trench dummy gate provided above the p-pillar region 108. If the p-pillar region 108 is floating, the charges trapped at the bottom of the trench groove 201 above the p-pillar region 108 accumulate over long-term operation, gradually disrupting the charge balance near the top end of the p-pillar region 108 and impairing long-term reliability. Therefore, by connecting the p-pillar region 108 to the p-base region 105 in, for example, the termination structure region or gate interconnect region outside the active region and isolating the p-pillar region 108 from the p-base region 105 in the active region, it is possible to achieve both reduced on-resistance and long-term reliability.

[0080] <Fourth Embodiment> FIG. 28 is a plan view schematically illustrating the top surface layout of a semiconductor device according to the fourth embodiment. As illustrated in FIG. 28, first gate electrodes 203 and second gate electrodes 204 are alternately arranged in the active region. The first gate electrodes 203 arranged in the active region are bundled together near the center of the top surface layout (connected to a first gate wiring 304) and electrically connected to a first gate electrode pad 302. The second gate electrodes 204 arranged in the active region are bundled together around the periphery of the active region (connected to a second gate wiring 305) and electrically connected to a second gate electrode pad 303. As will be described later, by arranging the first gate electrodes 203 above the n-type pillar regions 107 and the second gate electrodes 204 above the p-type pillar regions 108, it becomes possible to drive each gate individually, enabling fine-tuned control suitable for reducing switching loss, for example.

[0081] 29 is a cross-sectional view schematically showing the structure of a semiconductor device according to a fourth embodiment, taken along the line A1-A2 in FIG. 28. The semiconductor device according to the fourth embodiment is a trench-gate type superjunction IGBT element manufactured using a silicon-based semiconductor substrate. The semiconductor device according to the fourth embodiment differs from the semiconductor devices according to the first to third embodiments in that it includes two types of gates to which different voltages can be applied.

[0082] 29, the upper end of the p-type pillar region 108 is separated by a p-type base region 105 selectively provided on the first main surface side above the p-type pillar region 108 and an n-type charge retention region 106. Trench grooves 201 are selectively formed above the n-type pillar region 107, extending from a low-resistance n-type emitter region 103 provided in the surface layer of the p-type base region 105, penetrating the p-type base region 105 and reaching a portion of the n-type charge retention region 106. A first gate electrode 203 is disposed within this trench groove 201, facing the n-type pillar region 107 with the gate insulating film 101 interposed therebetween.

[0083] Further, trenches 201 are selectively formed above the p-type pillar regions 108, extending from the low-resistance n-type emitter regions 103 provided on the surface layer of the p-type base region 105 and penetrating the p-type base region 105 to reach a part of the n-type charge retention region 106. A second gate electrode 204 is disposed within the trenches 201, facing the p-type pillar regions 108 with the gate insulating film 101 interposed therebetween.

[0084] 28, the first gate electrode 203 is disposed so as to divide the active region of the semiconductor device, and the second gate electrode 204 is disposed inward from the periphery of the active region. The first gate electrode 203 is disposed across a first gate wiring 304, and the second gate electrode 204 is disposed across a second gate wiring 305. The first gate wiring 304 and the second gate wiring 305 are routed and disposed on the upper surface of the semiconductor device, with the first gate wiring 304 electrically connected to a first gate electrode pad 302 and the second gate wiring 305 electrically connected to a second gate electrode pad 303. The first gate wiring 304 and the second gate wiring 305 may be formed of polysilicon or amorphous silicon, but are preferably formed of a metal wiring material such as aluminum to further reduce gate signal delay.

[0085] 28 illustrates a layout in which the first gate electrode 203 is bridged over the first gate wiring 304 in the active region so as to divide the active region of the semiconductor device, and the second gate electrode 204 is bridged over the second gate wiring 305 in the periphery of the semiconductor device, but the first gate electrode 203 may be bridged over the first gate wiring 304 in the periphery of the semiconductor device, and the second gate electrode 204 may be bridged over the second gate wiring 305 in the active region. Needless to say, similar effects can be expected with a layout in which the first gate electrodes 203 and the second gate electrodes 204 are alternately connected from the left and right or from the top and bottom of the active region toward the inside of the active region, rather than a layout of gate wiring that divides the active region.

[0086] 30 is a graph illustrating a timing chart of the first gate voltage and the second gate voltage for driving the semiconductor device according to embodiment 4. The first gate voltage is applied to the first gate electrode pad 302, and the second gate voltage is applied to the second gate electrode pad 303.

[0087] <Operation of the Semiconductor Device According to the Fourth Embodiment> The operation of the semiconductor device according to the fourth embodiment will be described.

[0088] The semiconductor device according to the fourth embodiment includes a drift layer 10 including n-type pillar regions 107 and p-type pillar regions 108 that form a superjunction structure.

[0089] With the emitter electrode 100 grounded and the collector electrode 112 receiving a power supply voltage, if the first gate voltage is equal to or lower than the gate threshold voltage of the MOSFET formed on the first main surface, a reverse bias is applied between the p-type base region 105 and the drift layer 10, and the current is cut off between the collector electrode 112 and the emitter electrode 100, resulting in an off state.

[0090] Next, when voltages exceeding the gate threshold voltage of the MOSFET formed on the first main surface are applied as a first gate voltage and a second gate voltage to first gate electrode 203 and second gate electrode 204 simultaneously, an n-type inversion layer is formed in the portion of p-type base region 105 that contacts first gate electrode 203 and second gate electrode 204 via gate insulating film 101. Then, a current flows from collector electrode 112 to emitter electrode 100 via this inversion layer, turning the device from an off state to an on state.

[0091] 30 , to turn the current flowing through the on-state semiconductor device back to the off-state, first, a zero bias or a negative bias is applied to the second gate electrode 204 as a second gate voltage, and after a time Δt has elapsed since the application, a zero bias or a negative bias is applied to the first gate electrode 203 as a first gate voltage. When the n-type inversion layers generated at the MOS interfaces of the p-type base region 105, which are in contact with the first gate electrode 203 and the second gate electrode 204 via the gate insulating film 101, disappear, the supply of electrons from the n-type emitter region 103 to the drift layer 10 stops. The accumulated carriers in the drift layer 10 and the n-type bottom layer 109 decay, the depletion layer between the p-type pillar region 108 and the n-type pillar region 107 in the drift layer 10 is punched through, and the voltage between the collector electrode 112 and the emitter electrode 100 increases, turning the device into the off-state.

[0092] Here, Δt is preferably between 0.1 microseconds and 10 microseconds.

[0093] <Functions and Effects of the Semiconductor Device According to the Fourth Embodiment> The operation and effects of the semiconductor device according to the fourth embodiment will be described.

[0094] During the process of turning off the semiconductor device, an off signal is first applied as a second gate voltage to the second gate electrode 204 provided above the p-type pillar region 108. This causes the n-type inversion layer formed at the MOS interface of the p-type base region 105 in contact with the second gate electrode 204 to disappear, stopping the supply of electrons from the n-type emitter region 103 adjacent to the second gate electrode 204 via the gate insulating film 101. At this time, a p-type inversion layer is formed in the portion of the n-type charge retention region 106 in contact with the second gate electrode 204 via the gate insulating film 101. This results in a pnp bipolar transistor in which the p-type pillar region 108 serves as the p-type emitter, the n-type charge retention region 106 serves as the n-type base, and the p-type inversion layer serves as the p-type collector. By configuring such a pnp bipolar transistor, holes are discharged from the top of the p-type pillar region 108 to the p-type base region 105 via the n-type charge retention region 106 and the p-type inversion layer. This causes the carriers accumulated in the drift layer 10 to be discharged, and the depletion layer extends to the area between the pn junctions of the p-type pillar regions 108 and n-type pillar regions 107 in the drift layer 10 and to a part of the n-type bottom layer. However, at this point, the superjunction region is not completely depleted.

[0095] After a delay time Δt, when an off signal is applied to the second gate electrode 204 as the second gate voltage, a zero bias or negative bias is applied to the first gate electrode 203 as the first gate voltage. This also eliminates the n-type inversion layer generated at the MOS interface of the p-type base region 105, which contacts the first gate electrode 203 via the gate insulating film 101, and all electron supply from the n-type emitter region 103 is stopped. Because an off signal is first applied to the second gate electrode 204 as the second gate voltage, the time required to completely deplete the drift layer 10 shortens as Δt increases. This was confirmed by simulation, and as shown in Figure 31, the turn-off loss Eoff decreases and saturates at a certain point as Δt increases. Meanwhile, with carriers accumulated in the n-type bottom layer 109, a depletion layer penetrates into the n-type bottom layer 109 when either the first gate electrode 203 or the second gate electrode 204 is turned off, and the collector-emitter voltage reaches its peak. Therefore, the surge voltage Vcep has almost no effect on Δt. Therefore, by setting Δt>0, it is possible to reduce the turn-off loss Eoff without incurring an increase in the surge voltage Vcep at turn-off.

[0096] <Modification of the Fourth Embodiment> 32 is a cross-sectional view schematically showing the structure of a semiconductor device according to a modification of the fourth embodiment. The same parts as those in FIG. 29 etc. are given the same reference numerals and their explanations will be omitted. The semiconductor device according to this modification differs from the semiconductor device according to the fourth embodiment in that the semiconductor device according to this modification has a planar gate structure.

[0097] In the semiconductor device according to this modification, when an off signal is applied to the second gate electrode 204 as the second gate voltage Δt earlier than when an off signal is applied to the first gate electrode 203 as the first gate voltage, the n-type inversion layer generated at the MOS interface of the p-type base region 105 in contact with the second gate electrode 204 disappears, and the supply of electrons from the n-type emitter region 103 adjacent to the second gate electrode 204 via the gate insulating film 101 stops. At this time, a p-type inversion layer is formed in the portion of the n-type charge retention region 106 in contact with the second gate electrode 204 via the gate insulating film 101. Because the p-type inversion layer is connected to both the p-type base region 105 and the p-type pillar region 108, accumulated carriers in the drift layer 10 are discharged to the emitter electrode 100 connected to the p-type base region 105 via the p-type pillar region 108 and the p-type inversion layer. Therefore, the time required for the drift layer 10 to be completely depleted when an off signal is applied to the first gate electrode 203 as the first gate voltage is shortened. Therefore, it is possible to reduce the turn-off loss without incurring an increase in surge voltage.

[0098] Within the scope of the present disclosure, the embodiments can be freely combined, modified, or omitted as appropriate.

[0099] Although the present disclosure has been described in detail, the above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned. [Explanation of symbols]

[0100] 10 drift layer, 100 emitter electrode, 101 gate insulating film, 102 gate electrode, 103 n-type emitter region, 104 p-type body contact region, 105 p-type base region, 106 n-type charge retention region, 107 n-type pillar region, 108 p-type pillar region, 109 n-type bottom layer, 110 n-type buffer layer, 111 p-type collector layer, 112 collector electrode, 121 n-type JFET region, 122 p-type pillar bottom region, 123 p-type pillar bottom region, 124 n-type JFET region, 201 trench groove, 202 dummy gate electrode, 203 first gate electrode, 204 second gate electrode, 302 first gate electrode pad, 303 second gate electrode pad, 304 first gate wiring, 305 second gate wiring, 400 n-type silicon single crystal substrate, 401 trench groove for p-type pillar region, 407 n-type top epitaxial layer, 409 n-type bottom epitaxial layer, 410 hard mask film, 411 overgrowth region.

Claims

1. A semiconductor device having a first main surface and a second main surface opposite to the first main surface, a drift layer including first pillar regions of a first conductivity type and second pillar regions of a second conductivity type alternately arranged in a direction parallel to the first main surface and the second main surface; a second conductivity type base region selectively disposed on the first main surface side of the drift layer; a gate insulating film disposed in contact with the base region; a gate electrode disposed opposite to the base region via the gate insulating film; a charge retention region of a first conductivity type disposed between the base region and the second pillar region; an emitter region of a first conductivity type selectively disposed in a surface layer of the base region on the first main surface side; Equipped with a lower end of the second pillar region that is an end on the second main surface side is located closer to the second main surface than a lower end of the first pillar region that is an end on the second main surface side, A semiconductor device in which, when the width of an upper end of the second pillar region, which is the end on the first main surface side, is wp1, the width of the second pillar region at the same position as the lower end of the first pillar region is wp2, and the width of the lower end of the second pillar region is wp3, wp3 > wp2 and wp1 > wp2.

2. a bottom layer of a first conductivity type disposed on the second main surface side of the drift layer; a buffer layer of a first conductivity type disposed on the second main surface side of the bottom layer; a collector layer of the second conductivity type disposed on the second main surface side of the buffer layer; The semiconductor device according to claim 1 , further comprising:

3. 3. The semiconductor device according to claim 1, wherein said charge retention regions are separated at positions corresponding to centers of said gate electrodes in a direction parallel to said first and second main surfaces.

4. 4. The semiconductor device according to claim 3, wherein a width of said charge retention region is larger than a width of said base region in a direction parallel to said first main surface and said second main surface.

5. 3. The semiconductor device according to claim 1, wherein in the second pillar region, an impurity concentration contained in a region from a position equal to a lower end of the first pillar region to the lower end of the second pillar region is higher than an impurity concentration contained in a region from an upper end of the second pillar region to a position equal to the lower end of the first pillar region.

6. a first conductivity type JFET region disposed on the second main surface side of the first pillar region so as to be in contact with a lower end of the first pillar region, The semiconductor device according to claim 5 , wherein the impurity concentration of the JFET region is higher than the impurity concentration of the first pillar region.

7. 3. The semiconductor device according to claim 1, wherein said gate electrode penetrates said base region and reaches said charge retention region.

8. The semiconductor device according to claim 1 , wherein the second pillar region is connected to the base region.

9. The semiconductor device according to claim 1 , wherein the second pillar region is partially separated from the base region.

10. the gate electrode includes a first gate electrode and a second gate electrode; the first gate electrode is disposed opposite the first pillar region via the gate insulating film, The semiconductor device according to claim 7 , wherein the second gate electrode is disposed opposite the second pillar region with the gate insulating film interposed therebetween.

11. 11. A method for controlling a semiconductor device, comprising: applying an off signal to the second gate electrode before applying an off signal to the first gate electrode when switching the semiconductor device according to claim 10 from an on state in which current is conducted to an off state in which current is not conducted.

12. (a) preparing a semiconductor wafer in which a bottom epitaxial layer of a first conductivity type is formed on a semiconductor substrate and a top epitaxial layer of the first conductivity type is formed on a surface layer of the bottom epitaxial layer; (b) forming a trench groove for a second pillar region so as to penetrate the top epitaxial layer and reach the bottom epitaxial layer, and forming the top epitaxial layer other than the trench groove for the second pillar region as a first pillar region; (c) forming a second pillar region by epitaxially growing a material doped with a second conductivity type impurity in the second pillar region trench; (d) planarizing a first main surface, which is a surface of the semiconductor wafer on the top epitaxial layer side, so that the first pillar region and the second pillar region are exposed; (e) forming a gate insulating film covering the first pillar region and extending from the first pillar region to a portion of the second pillar region, and forming a gate electrode on the gate insulating film; (f) forming a first conductivity type charge retention region in a surface layer of the second pillar region by implanting ions from the first main surface side; (g) performing a thermal diffusion process to diffuse the charge retention region to directly below the gate electrode and to diffuse an end of the second pillar region on the second main surface side facing the first main surface to directly below the first pillar region; (h) forming a base region of a second conductivity type in a surface layer of the charge retention region by implanting ions from the first main surface side; Equipped with A method for manufacturing a semiconductor device, wherein wp3 > wp2 and wp1 > wp2 are satisfied, where wp1 is the width of an upper end of the second pillar region which is the end on the first main surface side, wp2 is the width of the second pillar region at the same position as the lower end of the first pillar region, and wp3 is the width of the lower end of the second pillar region.

13. (a) preparing a semiconductor wafer in which a bottom epitaxial layer of a first conductivity type is formed on a semiconductor substrate and a top epitaxial layer of the first conductivity type is formed on a surface layer of the bottom epitaxial layer; (b) forming a trench groove for a second pillar region so as to penetrate the top epitaxial layer and reach the bottom epitaxial layer, and forming the top epitaxial layer other than the trench groove for the second pillar region as a first pillar region; (c) forming a second pillar region by epitaxially growing a material doped with a second conductivity type impurity in the second pillar region trench; (d) planarizing a first main surface, which is a surface of the semiconductor wafer on the bottom epitaxial layer side, so that the first pillar region and the second pillar region are exposed; (e) forming a first conductivity type charge retention region in a surface layer of the first pillar region and the second pillar region by implanting ions from the first main surface side; (f) forming a base region of a second conductivity type in a surface layer of the charge retention region by implanting ions from the first main surface side; (g) performing a thermal diffusion process to diffuse the charge retention region and the base region, and to diffuse an end of the second pillar region on a second main surface side facing the first main surface to a position directly below the first pillar region; (h) forming a gate trench groove so as to penetrate the base region and reach the charge retention region, forming a gate insulating film on an inner wall of the gate trench groove, and forming a gate electrode so as to fill the gate trench groove; Equipped with A method for manufacturing a semiconductor device, wherein wp3 > wp2 and wp1 > wp2 are satisfied, where wp1 is the width of an upper end of the second pillar region which is the end on the first main surface side, wp2 is the width of the second pillar region at the same position as the lower end of the first pillar region, and wp3 is the width of the lower end of the second pillar region.

14. (i) removing the entire semiconductor substrate from the second main surface side to expose the bottom epitaxial layer; (j) forming a buffer layer of a first conductivity type on a surface layer of the bottom epitaxial layer by ion implantation from the second main surface side; (k) forming a collector layer of a second conductivity type on a surface layer of the buffer layer by ion implantation from the second main surface side; (l) activating the buffer layer and the collector layer; The method for manufacturing a semiconductor device according to claim 12 or 13, further comprising:

15. 14. The method for manufacturing a semiconductor device according to claim 12, wherein the semiconductor substrate is a substrate doped with impurities of the first conductivity type formed using a CZ (Czochralski) method, an MCZ (Magnetic field Czochralski) method, or an FZ (Floating Zone) method.

Images