Semiconductor device manufacturing method

Abstract

To suppress an insulation circuit board from warping upward convexly.SOLUTION: A heater comprising a flat heating surface is used to heat a semiconductor unit 2, which is heated with a reverse side of an insulation circuit board arranged on the heating surface. A cooler 8a comprising a cooling surface 8a1 including a pair of support parts 8a2 is used to cool the semiconductor unit 2, reverse sides of a pair of outside regions of the insulation circuit board which are opposed to the pair of support parts 8a2 are arranged on the pair of support parts 8a2 in contact, and the insulation circuit board is cooled in a downward convex state by pressing downward a top side of a center region of the insulation circuit board, which is sandwiched between the pair of outside regions.SELECTED DRAWING: Figure 15

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] The semiconductor device includes a power device and is used as a power conversion device. Examples of the power device include an IGBT (Insulated Gate Bipolar Transistor) and a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor device includes a semiconductor chip including the power device, an insulating circuit board, and a metal base plate. The insulating circuit board includes, for example, an insulating plate that is a ceramic plate, multiple wiring boards formed on the front surface of the insulating plate, and a metal layer formed on the back surface of the insulating plate. For example, a semiconductor chip and a lead frame are bonded to the wiring board via a bonding member. Furthermore, the insulating circuit board is bonded to the metal base plate by a bonding member.

[0003] For example, when the joining material is solder and a semiconductor chip is joined to a wiring board of an insulating circuit board via the solder, the solder is first melted by heating. The molten solder is then cooled, and the semiconductor chip is joined to the wiring board of the insulating circuit board by the solidified solder. Furthermore, the insulating circuit board to which the semiconductor chip is joined is joined to a metal base plate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2017-147327 Summary of the Invention [Problem to be solved by the invention]

[0005] In an insulated circuit board, the insulating plate, wiring plate, and metal plate have different linear expansion coefficients. During the heating and cooling process for bonding a semiconductor chip to the insulating circuit board using a bonding material, the metal plate on the back surface of the insulating plate shrinks significantly. This causes the insulating circuit board to warp upward with the wiring board facing up. This upward warping of the insulating circuit board can cause misalignment of the semiconductor chip. This reduces the assembly yield of semiconductor devices. Furthermore, when an insulating circuit board is bonded to a metal base plate in an upwardly warped state, the thickness of the bonding material between the back surface of the insulating circuit board and the front surface of the metal base plate increases. This increases thermal resistance and reduces heat dissipation.

[0006] The present invention has been made in view of the above points, and has as its object to provide a method for manufacturing a semiconductor device in which the occurrence of convex warpage on an insulating circuit board is suppressed. [Means for solving the problem]

[0007] According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: a preparation step of preparing an insulated circuit board including a semiconductor chip, a bonding member, an insulating plate, a wiring board formed on the front surface of the insulating plate, and a metal plate formed on the back surface of the insulating plate; an assembly step of assembling a semiconductor unit by placing the semiconductor chip on the wiring board via the bonding member; a heating step of heating the semiconductor unit; and a cooling step of cooling the semiconductor unit, wherein the heating step uses a heater having a heating surface including a flat surface to heat the insulated circuit board with a lower surface placed on the flat surface; and the cooling step uses a cooler having a cooling surface including a pair of support portions to place the lower surfaces of a pair of outer regions of the insulated circuit board facing the pair of support portions in contact with the pair of support portions, and presses downward the upper surface of a central region of the insulated circuit board sandwiched between the pair of outer regions, thereby cooling the insulated circuit board in a state where it forms a downward convex shape. [Effects of the Invention]

[0008] According to the disclosed technology, it is possible to suppress the occurrence of upwardly projecting warpage in an insulating circuit board, thereby suppressing a decrease in the reliability of a semiconductor device. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a side cross-sectional view of a semiconductor device; [Figure 2] FIG. 1 is a plan view of a semiconductor device. [Figure 3] FIG. 2 is a diagram illustrating a semiconductor unit included in the semiconductor device. [Figure 4] FIG. 1 is a diagram illustrating an equivalent circuit included in a semiconductor device. [Figure 5] 1 is a flowchart of a method for manufacturing a semiconductor device. [Figure 6] 10 is a flowchart of a chip bonding step according to the first embodiment included in the method for manufacturing a semiconductor device. [Figure 7] 4 is a graph showing temperature changes of a semiconductor unit in a chip bonding process according to the first embodiment. [Figure 8] 1A to 1C are diagrams (part 1) illustrating an assembly process included in the chip bonding process according to the first embodiment. [Figure 9] FIG. 10 is a diagram (part 2) showing an assembly process included in the chip bonding process according to the first embodiment. [Figure 10] 5A to 5C are diagrams illustrating a pre-sintering step included in the chip bonding step according to the first embodiment. [Figure 11] FIG. 4 is a diagram showing a sintering step included in the chip bonding step of the first embodiment. [Figure 12] FIG. 4 is a diagram showing a post-sintering step included in the chip bonding step of the first embodiment. [Figure 13] FIG. 10 is a diagram (part 1) showing a transfer step included in the chip bonding step according to the first embodiment. [Figure 14] FIG. 10 is a diagram (part 2) showing a transfer step included in the chip bonding step according to the first embodiment. [Figure 15] 10A and 10B are diagrams illustrating a cooling step (pressurizing) included in the chip bonding step according to the first embodiment. [Figure 16] 10A and 10B are diagrams illustrating a cooling step (pressure release) included in the chip bonding step according to the first embodiment. [Figure 17] 10 is a graph showing the amount of warpage of the insulating circuit board due to pressure application versus the temperature of the insulating circuit board in a cooling step included in the chip bonding step of the first embodiment. [Figure 18] 10A and 10B are diagrams illustrating a wiring and housing step included in a manufacturing method of a semiconductor device according to a reference example. [Figure 19] FIG. 10 is a diagram illustrating a cooling step (pressurizing) included in the chip bonding step of Modification 1-1 of the first embodiment. [Figure 20] FIG. 10 is a diagram showing a cooling device used in a cooling step included in a chip bonding step of Modification 1-2 of the first embodiment. [Figure 21] FIG. 10 is a diagram showing a cooling device used in a cooling step included in a chip bonding step of Modification 1-3 of the first embodiment. [Figure 22] 10 is a flowchart of a chip bonding step according to a second embodiment included in a method for manufacturing a semiconductor device. [Figure 23] 10 is a graph showing temperature changes of a semiconductor unit in a chip bonding process according to the second embodiment. [Figure 24] FIG. 10 is a diagram showing a soldering step included in the chip bonding step according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "upper surface" refer to the surface facing upward (+Z direction) in the semiconductor device 1 shown in the drawings. Similarly, "up" refers to the upward (+Z direction) direction in the semiconductor device 1 shown in the drawings. The terms "back surface" and "lower surface" refer to the surface facing downward (-Z direction) in the semiconductor device 1 shown in the drawings. Similarly, "lower" refers to the downward (-Z direction) direction in the semiconductor device 1 shown in the drawings. Similar orientations will be used in other drawings as necessary. The terms "front surface," "upper surface," "upper," "back surface," "lower surface," "lower," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "upper" and "lower" do not necessarily refer to the vertical direction relative to the ground. In other words, the "upper" and "lower" directions are not limited to the direction of gravity. In the following description, the term "main component" refers to a component containing 80 vol% or more of a component. In the following description, "substantially parallel" and "substantially horizontal" refer to an angle between two objects that is in the range of 170° to 190°, and "substantially perpendicular" and "substantially vertical" refer to an angle between two objects that is in the range of 85° to 95°.

[0011] [First embodiment] In the first embodiment, a case will be described in which sintered metal is used for bonding member 16 that bonds insulating circuit board 10 and semiconductor chips 14, 15, which will be described later. The semiconductor device will be described below with reference to FIGS. 1 to 4. FIG. 1 is a side cross-sectional view of the semiconductor device, and FIG. 2 is a plan view of the semiconductor device. Note that FIG. 1 is a cross-sectional view taken along dashed dotted line YY in FIG. 2. FIG. 2 omits the illustration of sealing member 5. FIG. 3 is a diagram showing a semiconductor unit included in the semiconductor device. Note that FIG. 3(A) is a plan view of semiconductor unit 2, and FIG. 3(B) is a side view of semiconductor unit 2 as viewed in the +Y direction. Also, FIG. 4 is a diagram showing an equivalent circuit included in the semiconductor device.

[0012] The semiconductor device 1 includes at least a semiconductor unit 2, a metal base plate 3, and a case 4 that houses the semiconductor unit 2. The semiconductor unit 2 is provided with external connection terminals 21 to 25, wires 26 and 27, and lead frames 28 and 29. The inside of the case 4 may be sealed with a sealing member 5.

[0013] The semiconductor unit 2 includes an insulating circuit board 10 and semiconductor chips 14 and 15. The insulating circuit board 10 is rectangular in plan view. The insulating circuit board 10 has an insulating plate 11, a plurality of wiring boards 12a to 12e formed on the front surface of the insulating plate 11, and a metal plate 13 formed on the back surface of the insulating plate 11. The outer shapes of the plurality of wiring boards 12a to 12e and the metal plate 13 are smaller than the outer shape of the insulating plate 11 in plan view, and are formed inside the insulating plate 11. Note that the shapes and number of the plurality of wiring boards 12a to 12e are merely examples.

[0014] The insulating plate 11 has a rectangular shape in a plan view. The corners of the insulating plate 11 may be chamfered. For example, the corners may be C-chamfered or R-chamfered. The insulating plate 11 is surrounded on all four sides by long sides 11a, short sides 11b, long sides 11c, and short sides 11d, which form the outer periphery. The insulating plate 11 also includes a corner 11e formed by the long sides 11a and short sides 11b, and a corner 11f formed by the short sides 11b and long sides 11c. The insulating plate 11 also includes a corner 11g formed by the long sides 11c and short sides 11d, and a corner 11h formed by the short sides 11d and long sides 11a.

[0015] The insulating plate 11 is made of ceramics with good thermal conductivity. The ceramics may be made of a material whose main component is, for example, aluminum oxide, aluminum nitride, or silicon nitride. The thickness of the insulating plate 11 is 0.2 mm or more and 2.0 mm or less.

[0016] The wiring boards 12a to 12e are made of a metal with excellent conductivity. Examples of the metal include copper and copper alloys. They may be plated to improve corrosion resistance and bonding strength. Examples of plating materials include nickel, nickel-phosphorus alloys, nickel-boron alloys, silver, and silver alloys. The thickness of the wiring boards 12a to 12e is, for example, 0.1 mm or more and 1.0 mm or less.

[0017] The wiring boards 12a to 12e each have a rectangular shape in a plan view. The wiring board 12a is parallel to the long sides 11a and short sides 11b of the insulating board 11 and is formed near the corner 11e. That is, among the multiple wiring boards 12a to 12e formed on the insulating board 11, the wiring board 12a is the outermost one on the short side 11b (-X direction) side of the insulating board 11. The wiring board 12b is parallel to the long sides 11a and short sides 11b of the insulating board 11 and is formed next to the short side 11d side of the wiring board 12a. The wiring board 12c is parallel to the long sides 11a and short sides 11d of the insulating board 11 and is formed near the corner 11h. That is, among the multiple wiring boards 12a to 12e formed on the insulating board 11, the wiring board 12c is the outermost one on the short side 11d (+X direction) side of the insulating board 11. Wiring boards 12a to 12c are arranged in a straight line with respect to insulating plate 11, parallel to long sides 11a and 11c.

[0018] Furthermore, wiring board 12d is formed along long side 11c adjacent to wiring board 12a (control electrodes 14a of semiconductor chip 14) on the long side 11c side. Wiring board 12e is formed along long side 11c adjacent to wiring board 12b (control electrodes 15a of semiconductor chip 15) on the long side 11c side. Wiring boards 12d and 12e are parallel to long sides 11a and 11c of insulating plate 11 and are arranged in a straight line.

[0019] The metal plate 13 is mainly composed of a metal with excellent thermal conductivity. Examples of such metals include aluminum, iron, silver, copper, and alloys containing at least one of these. To improve corrosion resistance and bondability, the metal plate 13 may be plated. Examples of plating materials include nickel, nickel-phosphorus alloy, nickel-boron alloy, silver, and silver alloy.

[0020] Examples of insulating circuit board 10 having such a configuration include a DCB (Direct Copper Bonding) board and an AMB (Active Metal Brazed) board. Insulating circuit board 10 is joined to metal base plate 3 via joining member 3a. Insulating circuit board 10 can conduct heat generated in semiconductor chips 14 and 15 to metal base plate 3 via wiring boards 12a and 12b, insulating plate 11, and metal plate 13.

[0021] The end portions of each component of the semiconductor unit 2 will now be described in more detail. As shown in Fig. 3, in the insulating circuit board 10, the long sides 11a and 11c are parallel to the ±X directions (longitudinal direction), and the short sides 11b and 11d are parallel to the ±Y directions (lateral direction). In Fig. 3, the position where the metal plate 13 is formed is indicated by a dashed line.

[0022] The side of semiconductor chip 14 on the side of short side 11b is defined as end L1, the side of wiring board 12a on the side of short side 11b is defined as end L2, the side of metal plate 13 on the side of short side 11b is defined as end L3, and the side of insulating plate 11 on the side of short side 11b is defined as end L4.

[0023] The side of semiconductor chip 15 closest to short side 11d is defined as end R1, the side of wiring board 12c closest to short side 11d is defined as end R2, the side of metal plate 13 closest to short side 11d is defined as end R3, and the side of insulating plate 11 closest to short side 11d is defined as end R4.

[0024] On the upper surface of such insulating circuit board 10 (semiconductor unit 2), the central region is defined as a range in the longitudinal direction that includes at least semiconductor chips 14 and 15. The central region is, at a minimum, the region between end L1 and end R1.

[0025] The outer region is defined as a longitudinal range on the top surface of insulating circuit board 10 (semiconductor unit 2) that includes at least end L4 of insulating plate 11 to end L3 of metal plate 13. Preferably, the outer region is defined as a longitudinal range that includes end L4 of insulating plate 11 to end L2 of wiring board 12a.

[0026] The outer region is defined as a longitudinal range on the top surface of insulating circuit board 10 (semiconductor unit 2) that includes at least end R4 of insulating plate 11 to end R3 of metal plate 13. Preferably, the outer region is defined as a longitudinal range that includes end R4 of insulating plate 11 to end R2 of wiring board 12c.

[0027] Therefore, the boundary between the central region and the outer region is between ends L3, R3 of metal plate 13 and ends L1, R1 of semiconductor chips 14, 15. It is preferable that the boundary is between ends L2, R2 of wiring boards 12a, 12c and ends L1, R1 of semiconductor chips 14, 15.

[0028] The external connection terminals 21 to 25 each have a plate-like, columnar, or cylindrical shape. Here, a flat-plate shape is illustrated. As shown in FIG. 1 , the upper ends of the external connection terminals 21 to 25 extend outward (in the +Z direction) from the sealing member 5. The upper ends of the external connection terminals 21 to 25 may extend outward from the upper surface of the sealing member 5 in a planar direction (for example, the +X direction). Furthermore, as will be described later, if a lid (not shown) is provided to cover the upper part of the sealing member 5, the upper ends of the external connection terminals 21 to 25 may extend outward (in the +Z direction) from the lid. The upper ends of the external connection terminals 21 to 25 may extend outward from the upper surface of the lid in a planar direction (for example, the +X direction). Furthermore, these upper ends may be connected to an external device (not shown). The external connection terminals 21 to 25 are made of a metal with excellent conductivity. The metal may be, for example, copper or a copper alloy. Furthermore, plating may be performed to improve corrosion resistance and bondability. Examples of plating materials include nickel, nickel-phosphorus alloy, nickel-boron alloy, silver, and silver alloy.

[0029] External connection terminals 21 are provided on wiring board 12a between the end of wiring board 12a on the -X direction side and semiconductor chip 14. The lower ends of external connection terminals 21 are joined to wiring board 12a with a joining member. External connection terminals 21 extend upward (in the +Z direction) from the joint portion with wiring board 12a toward the front surface of wiring board 12a.

[0030] External connection terminals 22 are provided on wiring board 12b between semiconductor chip 15 on wiring board 12b and lead frame 28 (described later). Lower ends of external connection terminals 22 are joined to wiring board 12b with a joining member. External connection terminals 22 extend upward (in the +Z direction) from the joint portion with wiring board 12b toward the front surface of wiring board 12b.

[0031] External connection terminals 23 are provided on wiring board 12c between the end of wiring board 12c in the +X direction and lead frame 29, which will be described later. The lower ends of external connection terminals 23 are joined to wiring board 12c with a joining member. External connection terminals 23 extend upward (in the +Z direction) from the joint portion with wiring board 12c toward the front surface of wiring board 12c.

[0032] External connection terminals 24 and 25 are provided on the +X direction sides of wiring boards 12d and 12e, respectively. Lower ends of external connection terminals 24 and 25 are joined to wiring boards 12d and 12e with joining members. External connection terminals 24 and 25 extend upward (in the +Z direction) from their respective joining portions to wiring boards 12d and 12e toward the front surfaces of wiring boards 12d and 12e.

[0033] Wires 26 and 27 directly connect wiring boards 12d and 12e to control electrodes 14a and 15a of semiconductor chips 14 and 15. Wires 26 and 27 are primarily made of a highly conductive material. Such materials include, for example, gold, copper, aluminum, or an alloy containing at least one of these. Preferably, wires 26 and 27 are an aluminum alloy containing a trace amount of silicon. Wires 26 and 27 have a diameter of, for example, 100 μm or more and 400 μm or less.

[0034] The lead frames 28 and 29 are made of a metal with excellent conductivity. Examples of the metal include copper and copper alloys. To improve corrosion resistance, the lead frames 28 and 29 may be plated. Examples of plating materials include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0035] Lead frame 28 directly connects output electrode 14b of semiconductor chip 14 to wiring board 12b. One end of lead frame 28 is joined to output electrode 14b of semiconductor chip 14, and the other end is joined adjacent to external connection terminal 22 of wiring board 12b in the -X direction. Lead frame 29 directly connects output electrode 15b of semiconductor chip 15 to wiring board 12c. One end of lead frame 29 is joined to output electrode 15b of semiconductor chip 15, and the other end is joined adjacent to external connection terminal 23 of wiring board 12c in the -X direction.

[0036] One end of lead frames 28, 29 may be joined by a joining material (solder or a sintered metal) to output electrodes 14b, 15b of semiconductor chips 14, 15. The other end of external connection terminals 21-25 and lead frames 28, 29 may be joined to wiring boards 12a-12c and wiring boards 12b, 12c by a similar joining material or by ultrasonic bonding.

[0037] The metal base plate 3 has a rectangular shape in a plan view. The back surface of the insulating circuit board 10 is joined to the front surface of the metal base plate 3 with a joining member 3a. The case 4 is joined to the metal base plate 3 on all four sides of its outer periphery with adhesive members 4a. The front surface of the metal base plate 3 has a sufficient area for mounting the insulating circuit board 10 and the case 4. The metal base plate 3 is primarily composed of a material with excellent thermal conductivity. Examples of such materials include aluminum, iron, silver, copper, or an alloy containing at least one of these. The metal base plate 3 may be plated to improve corrosion resistance. Examples of plating materials include nickel, nickel-phosphorus alloy, and nickel-boron alloy. A plurality of fins may be integrally formed on the back surface of the metal base plate 3. A water-cooled cooling device may be used instead of the metal base plate 3. That is, the insulating circuit board 10 and the case 4 may be joined to the front surface of the top plate of the cooling device, as described above.

[0038] The case 4 has a rectangular shape in a plan view and is shaped like a frame with an opening on the inside. The case 4 surrounds the semiconductor chips 14 and 15, the insulating circuit board 10, and the lower ends of the external connection terminals 21 to 25. The opening of the case 4 is then filled with a sealing member 5. The lower surface of the case 4 is adhered to the metal base plate 3 with an adhesive member 4a. The case 4 may further have a lid (not shown) that covers the upper part of the opening. The upper ends of the external connection terminals 21 to 25 may extend outward from the case 4. The case 4 is molded from, for example, a thermoplastic resin. Examples of thermoplastic resins include polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, and acrylonitrile butadiene styrene resin.

[0039] The joining member 3a is, for example, solder. The solder is made of lead-free solder containing a predetermined alloy as its main component. The predetermined alloy is, for example, at least one of an alloy made of tin-silver, an alloy made of tin-zinc, and an alloy made of tin-antimony. The solder may contain additives such as copper, bismuth, indium, nickel, germanium, cobalt, or silicon. The joining member 3a may also be a sintered metal. The sintered metal is made of a metal containing silver as its main component. In particular, the joining member 3a that joins the insulating circuit board 10 and the metal base plate 3 may be silver solder.

[0040] The adhesive member 4a is made of a thermoplastic resin adhesive that softens and hardens depending on the temperature, or a thermosetting resin adhesive that hardens through a chemical reaction when heated. Examples of thermoplastic resins include vinyl acetate resin, polyvinyl alcohol, and polyamide resin. Examples of thermosetting resins include epoxy resin, silicone resin, polyimide resin, urethane resin (polyurethane), and ester resin (polyester).

[0041] The semiconductor chips 14 and 15 may include switching elements made of power MOSFETs. The front surfaces of the semiconductor chips 14 and 15 each include a gate electrode as a control electrode 14a or 15a, and a source electrode as a main output electrode 14b or 15b. The control electrodes 14a or 15a are provided at the center of the side of the front surface, and the output electrodes 14b or 15b are provided at the center of the front surface. The semiconductor chips 14 and 15 also include a drain electrode as a main input electrode on the rear surface. The semiconductor chips 14 and 15 may preferably be made of silicon carbide.

[0042] The semiconductor chips 14 and 15 may include switching elements made of IGBTs. These semiconductor chips 14 and 15 also have gate electrodes as control electrodes 14a and 15a and emitter electrodes as output electrodes 14b and 15b, which are main electrodes, on their front surfaces, and collector electrodes as input electrodes of the main electrodes on their back surfaces. Alternatively, the semiconductor chips 14 and 15 may include RC (Reverse Conducting)-IGBT switching elements. An RC-IGBT is a chip that combines an IGBT and an FWD (Free Wheeling Diode). These semiconductor chips 14 and 15 may be made of silicon.

[0043] Semiconductor chip 14 is bonded to wiring board 12a, and semiconductor chip 15 is bonded to wiring board 12b via bonding members 16. Semiconductor chip 14 constitutes upper arm portion A, which will be described later, and semiconductor chip 15 constitutes lower arm portion B, which will be described later. Semiconductor chip 14 and semiconductor chip 15 are connected in series by lead frame 28. In the first embodiment, bonding member 16 is made of a sintered porous metal containing silver as a main component.

[0044] The sealing member 5 may seal the inside of the case 4. The sealing member 5 seals the insulating circuit board 10, the semiconductor chips 14 and 15, one ends of the external connection terminals 21 to 25, the wires 26 and 27, and the lead frames 28 and 29 on the front surface of the metal base plate 3. The sealing member 5 contains, for example, a thermosetting resin and a filler contained in the thermosetting resin. Examples of the thermosetting resin include epoxy resin, phenolic resin, and maleimide resin. An example of such a sealing member is an epoxy resin containing a filler. An inorganic material is used as the filler. Examples of inorganic materials include silicon oxide, aluminum oxide, boron nitride, and aluminum nitride. In addition to the materials already mentioned, the sealing member 5 may be silicone gel.

[0045] 4, such a semiconductor device 1 forms a half-bridge circuit including an upper arm portion A and a lower arm portion B. The connection point P is connected to the positive electrode of an external power supply (not shown). The connection point P and a connection point D1 of the input electrode (drain electrode) of the semiconductor chip 14 are connected by a wiring 61 (external connection terminal 21 and wiring board 12a).

[0046] Connection point M is connected to a load (not shown). Connection point M and connection point S1D2 of the output electrode (source electrode) of semiconductor chip 14 and the input electrode (drain electrode) of semiconductor chip 15 are connected by wiring 63 (lead frame 28, wiring board 12b, and external connection terminal 22, and wiring board 12b and external connection terminal 22).

[0047] The connection point N is connected to the negative electrode of an external power supply (not shown). The connection point N and a connection point S1D2 of the output electrode (source electrode) of the semiconductor chip 15 are connected by a wiring 62 (the lead frame 29, the wiring board 12c, and the external connection terminal 23).

[0048] When the semiconductor device 1 is in operation, the connection point P has a higher potential than the connection point M. Therefore, the wiring 61 has a higher potential than the wiring 63. Furthermore, the connection point M has a higher potential than the connection point N. Therefore, the wiring 63 has a higher potential than the wiring 62.

[0049] Connection points G1 and G2 are connected to a control power supply (not shown). Connection point G1 is connected to control electrode 14a of semiconductor chip 14 via wiring 64 (external connection terminal 24, wiring board 12d, and wire 26). Connection point G2 is connected to control electrode 15a of semiconductor chip 15 via wiring 65 (external connection terminal 25, wiring board 12e, and wire 27).

[0050] Upper arm portion A of semiconductor device 1 includes wiring boards 12a and 12d of insulating circuit board 10, semiconductor chip 14, external connection terminals 21 and 24, and wire 26. Lower arm portion B of semiconductor device 1 includes wiring boards 12c, 12b, and 12e of insulating circuit board 10, semiconductor chip 15, external connection terminals 23 and 25, and wire 27. Furthermore, wiring boards 12a and 12b are electrically connected by lead frame 28, thereby connecting upper arm portion A and lower arm portion B. This allows semiconductor device 1 to function as a half-bridge circuit including upper arm portion A and lower arm portion B.

[0051] In this embodiment, the upper arm portion A is configured with one semiconductor chip 14, and the lower arm portion B is configured with one semiconductor chip 15. However, the present invention is not limited to this, and there may be a plurality of semiconductor chips 14 and 15 that configure the upper arm portion A and the lower arm portion B. For example, the upper arm portion A and the lower arm portion B may each include a plurality of semiconductor chips 14 and a plurality of semiconductor chips 15 connected in parallel to each other. Furthermore, the semiconductor chips 14 and the semiconductor chips 15 may each include a semiconductor chip consisting of an FWD chip connected in anti-parallel to each other.

[0052] (Method of manufacturing semiconductor device 1) Next, a manufacturing method of the semiconductor device 1 will be described with reference to FIG. 5. FIG. 5 is a flowchart of the manufacturing method of the semiconductor device. First, a preparation step is performed to prepare the components of the semiconductor device 1 (step S1 in FIG. 5). Examples of the components include semiconductor chips 14 and 15, an insulating circuit board 10, a metal base plate 3, a case 4, a sealing member 5, external connection terminals 21 to 25, and lead frames 28 and 29. Note that components not listed here may also be prepared as needed. Various manufacturing devices used in manufacturing the semiconductor device 1 are also prepared. Examples of the manufacturing devices include a wire bonding device, a transfer device, a sintering device, and a cooling device. Note that manufacturing devices not listed here may also be prepared as needed.

[0053] Next, a chip bonding step is performed (step S2 in FIG. 5) in which semiconductor chips 14 and 15 are bonded to insulating circuit board 10. Semiconductor chips 14 and 15 are bonded to wiring boards 12a and 12b of insulating circuit board 10 with bonding members 16. Details of step S2 in FIG. 5 will be described later using the flowchart in FIG. 6.

[0054] Next, a wiring and storage process is performed in which wiring is performed on the semiconductor chips 14, 15 and the insulating circuit board 10 and they are stored in the case 4 (step S3 in FIG. 5). The lower ends of the external connection terminals 21-25 are bonded to the wiring boards 12a-12e of the insulating circuit board 10 using a bonding material such as solder or ultrasonic bonding. Furthermore, one end and the other end of the lead frame 28 are bonded to the output electrode 14b of the semiconductor chip 14 and the wiring board 12b, respectively. One end and the other end of the lead frame 29 are bonded to the output electrode 15b of the semiconductor chip 15 and the wiring board 12c, respectively. Furthermore, the wiring boards 12d, 12e are connected to the control electrodes 14a, 15a of the semiconductor chips 14, 15 by wires 26, 27, respectively. Note that the various bonding steps may be performed in any order.

[0055] Insulated circuit board 10 including semiconductor chips 14, 15 wired in this manner is bonded to the center of the front surface of metal base plate 3 via bonding member 3a. Case 4, which is continuous in a ring shape around the periphery of insulated circuit board 10, is bonded to the front surface of metal base plate 3 via adhesive member 4a. The periphery of insulated circuit board 10 is surrounded by case 4, and insulated circuit board 10 is housed in case 4.

[0056] Next, a sealing step is performed to seal the inside of the case 4 with sealing member 5 (step S4 in FIG. 5). The inside of the case 4 is filled with sealing member 5. The sealing member 5 is filled into the area surrounded by the front surface of the metal base plate 3 and the case 4. This seals the insulating circuit board 10, the semiconductor chips 14, 15, one ends of the external connection terminals 21 to 25, the wires 26, 27, and the lead frames 28, 29. In this way, the semiconductor device 1 shown in FIGS. 1 and 2 is obtained.

[0057] Next, the chip bonding process of step S2 included in the manufacturing method of the semiconductor device 1 of FIG. 5 will be described with reference to FIGS. 6 and 7. FIG. 6 is a flowchart of the chip bonding process of the first embodiment included in the manufacturing method of the semiconductor device. FIG. 7 is a graph showing temperature changes of the semiconductor unit in the chip bonding process of the first embodiment. In FIG. 7, the horizontal axis represents time and the vertical axis represents the temperature of the semiconductor unit 2. FIG. 7 also shows temperature changes from the sintering process to the cooling process.

[0058] First, an assembly process is performed in which semiconductor chips 14, 15 are arranged in predetermined regions of wiring boards 12a, 12c of insulating circuit board 10 to assemble semiconductor assembly 6 (step S10 in FIG. 6). The assembly process will now be described with reference to FIGS. 8 and 9. FIGS. 8 and 9 are diagrams illustrating assembly steps included in the chip bonding process of the first embodiment. FIG. 8(A) shows the pressing of semiconductor chip 14 against sintered sheet 32. FIG. 8(B) shows the lifting of semiconductor chip 14 from sintered sheet 32. In the assembly process, first, bonding member 16 is attached to the backsides of semiconductor chips 14, 15 by transfer. This transfer is performed using transfer device 30 shown in FIG. 8. FIG. 8 merely illustrates the case of semiconductor chip 14, and similar transfer is performed for semiconductor chip 15.

[0059] 8, the transfer device 30 includes a transfer table 31 and a transfer tool 33. A sintered sheet 32 ​​is placed on the transfer table 31. The transfer tool 33 has a vacuum suction hole 33a in the center, and adsorbs the front surface (output electrode side) of the semiconductor chip 14. Then, the semiconductor chip 14 is transported directly above the transfer table 31.

[0060] In this transfer device 30, a sintered sheet 32 ​​is placed on a transfer table 31. The sintered sheet 32 ​​includes a release film 32a and a sintered material film 32b provided on one main surface of the release film 32a. The sintered material film 32b contains a metal that will form the joining member 16 after sintering. Such a sintered material film 32b contains, for example, silver particles of 1 nm or more and 100 nm or less and a resin. The sintered sheet 32 ​​is placed on the transfer table 31 with the sintered material film 32b facing upward. The sintered sheet 32 ​​is fixed to the transfer table 31 by the release film 32a.

[0061] Next, the transfer tool 33 picks up the semiconductor chip 14 by suction. At this time, the semiconductor chip 14 is picked with its back surface (input electrode side) facing downward. Specifically, first, the transfer tool 33 carrying the semiconductor chip 14 moves to a position directly above the transfer table 31. Next, it moves downward toward the transfer table 31 and presses the semiconductor chip 14 against the sintered sheet 32 ​​on the transfer table 31 (FIG. 8(A)). As a result, the back surface (input electrode side) of the semiconductor chip 14 is pressed against the sintered material film 32b of the sintered sheet 32. Thereafter, the transfer tool 33 moves upward and returns to a position directly above the transfer table 31. At this time, the bonding member 16 made of sintered metal is transferred from the sintered material film 32b of the sintered sheet 32 ​​to the back surface of the semiconductor chip 14.

[0062] As shown in FIG. 9 , the insulating circuit board 10 is placed on a positioning jig 40. The positioning jig 40 includes a main body 41 and a positioning region 42 formed in the main body 41. The main body 41 is mainly composed of a material with a low linear expansion coefficient. Examples of such materials include carbon and ceramics. The main body 41 is flat. The positioning region 42 is rectangular in plan view on the front surface of the main body 41, and has a concave depression formed therein. The bottom surface of the positioning region 42 is approximately parallel to the front surface of the main body 41. The outer shape of the positioning region 42 corresponds to the outer shape of the insulating circuit board 10. The depth of the positioning region 42 may be the same as or slightly greater than the thickness of the insulating circuit board 10.

[0063] The semiconductor chips 14, 15 with the bonding members 16 transferred thereto are placed with the bonding members 16 side down on the wiring boards 12a, 12b of the insulating circuit board 10, which are placed in the positioning area 42 of the positioning jig 40. Furthermore, as shown in FIG. 9, a buffer material 43 is placed on the semiconductor chips 14, 15. The buffer material 43 may be made of a material with a modulus of elasticity lower than that of the semiconductor chips 14, 15 and the pressure vessel 7b. An example of such a material is a carbon sheet. In this manner, the semiconductor assembly 6 is obtained. That is, the semiconductor assembly 6 includes the positioning jig 40, the insulating circuit board 10, and the semiconductor chips 14, 15 placed on the wiring boards 12a, 12b of the insulating circuit board 10 via the bonding members 16.

[0064] Next, the semiconductor assembly 6 provided with the buffer material 43 is set in the sintering device 7, and a pre-sintering step is performed in which heating is started (step S11 in FIG. 6). The pre-sintering step will now be described with reference to FIG. 10. FIG. 10 is a diagram showing the pre-sintering step included in the chip bonding step of the first embodiment. The semiconductor assembly 6 obtained in step S10 is carried into the sintering device 7.

[0065] The sintering apparatus 7 includes a chamber (not shown) containing a heater 7a and a pressurizer 7b positioned opposite the heater 7a. The heater 7a includes a heating surface 7a1 on which the semiconductor assembly 6 is placed. The heater 7a heats and cools the heating surface 7a1 at a predetermined heating rate. The heating surface 7a1 need only be substantially flat, and may include warping or undulations due to heating, pressure, or external impact. The flatness of the heating surface 7a1 is 0.05 mm or less, preferably 0.02 mm or less. The pressurizer 7b is located directly above the heating surface 7a1. The pressurizer 7b approaches the heating surface 7a1 to apply a predetermined pressure to the object to be pressed, and then moves away from the heating surface 7a1 to release the pressure. The heating and pressure, as well as the filling and discharging of nitrogen into the chamber (described later), are controlled by a control device (not shown) included in the sintering apparatus 7.

[0066] The semiconductor assembly 6 obtained in step S10 is placed on the heating surface 7a1 of the heater 7a of the sintering device 7. The pressurizer 7b is set on the cushioning material 43 of the semiconductor assembly 6 via a protective sheet 7c. The protective sheet 7c is intended to protect the cushioning material 43 from direct contact with the pressurizer 7b, and is made primarily of, for example, polyimide resin. After setting in this way, the temperature inside the chamber is room temperature, which can be considered to be the air atmosphere. Then, filling of the chamber with nitrogen begins, and heating by the heater 7a begins.

[0067] Next, a sintering step is performed in which pressure is applied to the semiconductor assembly 6 while increasing the heating temperature by the heater 7a (step S12 in FIG. 6). The sintering step will now be described with reference to FIG. 11. FIG. 11 is a diagram showing the sintering step included in the chip bonding step of the first embodiment.

[0068] As shown in the sintering step in FIG. 7, heating by heater 7a raises the temperature of semiconductor assembly 6 (semiconductor unit 2). Then, pressurizer 7b approaches heater 7a and applies a constant pressure in the −Z direction to semiconductor assembly 6 via buffer material 43. This pressure application begins before time tb, at which temperature T2, the sintering start temperature of bonding members 16, is reached. This pressure application is maintained throughout the sintering step. Accordingly, as shown in FIG. 11, buffer material 43 deforms and fits over the entire front surfaces of wiring boards 12a-12e and semiconductor chips 14 and 15 of insulating circuit board 10. This allows semiconductor chips 14 and 15 to be uniformly pressed in the −Z direction. The pressure applied during this process is, for example, between 0.1 tons and 2 tons.

[0069] When a predetermined time tb has elapsed since the start of heating, the temperature of the semiconductor assembly 6 reaches a temperature T2, which is the sintering start temperature of the bonding members 16, and sintering of the pressed bonding members 16 begins. The temperature T2 at this time is, for example, 100°C or higher and 300°C or lower when the bonding members 16 are mainly composed of silver or a silver alloy.

[0070] Heating by heater 7a is further continued. After a predetermined time tc (>tb) has elapsed since the start of heating, the temperature of semiconductor assembly 6 reaches a predetermined temperature T3. This temperature T3 is maintained for a predetermined time. At this time, temperature T3 is higher than temperature T2. For example, when bonding member 16 is composed primarily of silver or a silver alloy, temperature T3 is 200°C or higher and 400°C or lower. During this time, sintering of bonding member 16, which is being pressurized, continues, and semiconductor chips 14 and 15 are bonded to wiring boards 12a and 12b of insulating circuit board 10, respectively.

[0071] Next, a post-sintering step is performed in which the heating of the semiconductor assembly 6 is maintained and the pressure is released (step S13 in FIG. 6). The post-sintering step will now be described with reference to FIG. 12. FIG. 12 is a diagram showing the post-sintering step included in the chip bonding step of the first embodiment.

[0072] Heating by heater 7a is continued to maintain the temperature inside the chamber in the nitrogen atmosphere at temperature T3. Then, pressurizer 7b is moved away from heater 7a directly above it, releasing the pressure on semiconductor assembly 6. Cushioning material 43 and protective sheet 7c may be placed on semiconductor assembly 6. Preferably, cushioning material 43 is placed on semiconductor assembly 6. By placing cushioning material 43 on semiconductor assembly 6, a temperature drop in semiconductor assembly 6 can be suppressed during the subsequent transfer process. Furthermore, by placing protective sheet 7c, adhesion of dirt and dust to semiconductor assembly 6 and cushioning material 43 can be suppressed during the subsequent transfer process. At this time, as shown in FIG. 12 , semiconductor assembly 6 generates heat and is at temperature T3. That is, positioning jig 40, insulating circuit board 10, and semiconductor chips 14 and 15 are at temperature T3.

[0073] Next, a transport step is performed in which the semiconductor unit 2 including the semiconductor assembly 6 is transported from the sintering device 7 to the cooling device 8 (step S14 in FIG. 6). The transport step will now be described with reference to FIGS. 13 and 14. FIGS. 13 and 14 are diagrams showing the transport step included in the chip bonding step of the first embodiment. Note that FIG. 14 shows a top view of the cooling device 8 in which the semiconductor unit 2 of FIG. 13 has been set. However, a pressurizer 8b, which will be described later, is not shown.

[0074] In the sintering device 7, after the pressure applied to the semiconductor assembly 6 is released, the semiconductor unit 2 that is generating heat is transported to a cooling device 8. The cooling device 8 includes a cooler 8a and a pressurizer 8b disposed opposite the cooler 8a within a chamber (not shown).

[0075] The cooler 8a includes a cooling surface 8a1 and a support portion 8a2 provided on the cooling surface 8a1. The semiconductor unit 2 is placed on the cooling surface 8a1. The cooling surface 8a1 is cooled at a predetermined cooling rate by the cooler 8a. The cooling surface 8a1 only needs to be substantially flat, and may include warping or undulations due to cooling, pressure, etc. The flatness of the cooling surface 8a1 is only required to be 0.2 mm or less, and preferably 0.1 mm or less.

[0076] The support portion 8a2 has a columnar shape extending in a continuous straight line in a plan view. The support portion 8a2 is formed on the cooling surface 8a1. The cross section of the support portion 8a2 may be convex with respect to the cooling surface 8a1. The columnar shape of the support portion 8a2 may be, for example, triangular, rectangular, or a rod-like mountain shape with a semicircular cross section. Figures 13 and 14 show the case where the support portion 8a2 has a triangular columnar shape. The cross section of the support portion 8a2 may be an equilateral triangle or an isosceles triangle.

[0077] Furthermore, the support portions 8a2 are formed at positions that support a pair of outer regions of the insulating circuit board 10 when the insulating circuit board 10 is placed on the cooling surface 8a1. In the case of FIGS. 13 and 14, the support portions 8a2 are parallel to each other and are longer than a pair of short sides of the insulating circuit board 10. The height of the support portions 8a2 from the cooling surface 8a1 to the sides that support the insulating circuit board 10 only needs to be such that the pressed insulating circuit board 10 can be sufficiently warped, as will be described later. If this height is too low, the insulating circuit board 10 will not be able to be sufficiently warped. The positions of the sides of the pair of support portions 8a2 are designated as positions A1 and A2 (see FIGS. 13 and 14).

[0078] The pressurizer 8b is located directly above the cooling surface 8a1. The pressurizer 8b approaches the cooling surface 8a1 to apply a predetermined pressure to the object to be pressed, and moves away from the cooling surface 8a1 to release the pressure on the object to be heated. In the first embodiment, the pressurizer 8b has a pressurizing surface corresponding to the central region of the insulating circuit board 10. The pressurizer 8b is not limited to this case as long as it can impart a warp to the insulating circuit board 10 as shown in FIG. 15 (described later). The pressurizer 8b may be, for example, columnar. In this case, the columnar pressurizer 8b may pressurize the center of the top surface of the semiconductor unit 2. In this case, if semiconductor chips 14 and 15 are present at the pressurized area, the pressurized insulating circuit board 10 may be pressed while avoiding the semiconductor chips 14 and 15. However, by applying pressure to the central region of the insulating circuit board 10 as shown in FIGS. 13 and 14, stable pressure can be applied to the semiconductor unit 2. The cooling, pressurization, and filling and discharging of nitrogen into the chamber are controlled by a control device (not shown) included in the cooling device 8.

[0079] The semiconductor assembly 6 is removed from the sintering device 7 and transported to the cooling device 8. For example, a positioning jig 40 is used as a tray to transport the semiconductor unit 2 to the cooling device 8. At this time, the positioning jig 40 is heated to a predetermined temperature T3. By transporting the semiconductor unit 2 using the positioning jig 40, the semiconductor unit 2 that has such heat is kept warm until the next cooling step (see <Transportation Step> in FIG. 7). Note that in the transport step, the temperature of the semiconductor unit 2 may be lowered as long as it is higher than the plastic deformation start temperature (yield temperature) T1.

[0080] The semiconductor unit 2 removed from the positioning jig 40 is carried into the chamber of the cooling device 8 and placed on the cooling surface 8a1 of the cooler 8a. At this time, the cooling surface 8a1 of the cooler 8a may be preheated to a temperature higher than the plastic deformation starting temperature T1. A pair of outer regions (see FIG. 3) of the insulating circuit board 10 placed on the cooling surface 8a1 are supported by a pair of supports 8a2. The pressurizer 8b is moved to the cooling surface 8a1, and as shown in FIGS. 13 and 14, the pressurizer 8b presses the semiconductor chips 14 and 15 of the semiconductor unit 2 via the protective sheet 7c and the buffer material 43. At this time, the pressurizer 8b faces the central region (see FIG. 3) of the insulating circuit board 10 including the semiconductor chips 14 and 15. The positions of both longitudinal ends of the pressurizer 8b are designated as positions B1 and B2. When the pressurizer 8b faces the central region of the insulating circuit board 10, positions B1 and B2 are both located inside positions A1 and A2.

[0081] Next, a cooling step is performed in which the semiconductor unit 2 is pressurized under cooling (step S15 in FIG. 6). The cooling step will now be described with reference to FIGS. 15 and 16. FIG. 15 is a diagram illustrating the cooling step (pressurization) included in the chip bonding step of the first embodiment. FIG. 16 is a diagram illustrating the cooling step (pressurization release) included in the chip bonding step of the first embodiment.

[0082] Cooler 8a starts cooling cooling surface 8a1 on which semiconductor unit 2 is arranged. In insulating circuit board 10, metal plate 13 shrinks significantly due to differences in the linear expansion coefficients of insulating plate 11, wiring boards 12a to 12e, and metal plate 13. If this continues, insulating circuit board 10 will warp upward, with wiring boards 12a to 12e facing upward.

[0083] Meanwhile, as cooling begins, pressurizer 8b is moved downward and brought into contact with protective sheet 72c covering semiconductor chips 14 and 15 via buffer material 43. Then, pressurizer 8b presses semiconductor unit 2 in the −Z direction with a predetermined pressure. Note that the predetermined pressure is 0.1 tons or more and 2 tons or less. The pressure applied during the cooling process in step S15 of FIG. 6 is lower than the pressure applied during the sintering process in step S12 of FIG. 6. The back surfaces of a pair of outer regions of insulating circuit board 10 are supported by a pair of support portions 8a2, and the front surface of the central region of insulating circuit board 10 is pressed in the −Z direction by pressurizer 8b. Therefore, as shown in FIG. 15, semiconductor unit 2 (insulating circuit board 10) warps downward. At this time, the back surface of insulating circuit board 10 comes into contact with cooling surface 8a1. The amount of warping at this time is, for example, warping amount Wa. The amount of warping is the vertical distance from the bottom surface (cooling surface 8a1) where the convex portion of the insulating circuit board 10 contacts to the edge of the lower surface (back surface) of the insulating circuit board 10 when viewed from the side, for example, when the insulating circuit board 10 is warped convexly downward.

[0084] Furthermore, since the semiconductor unit 2 is pressurized while being maintained at a temperature higher than the yield temperature T1, which is the temperature at which plastic deformation begins, plastic deformation occurs. After pressurization, the pressure applied to the semiconductor unit 2 by the pressurizer 8b is released. As shown in FIG. 16, the downward convex warpage of the semiconductor unit 2 (insulated circuit board 10) is maintained. However, when the pressure is released, the downward convex warpage of the insulating circuit board 10 is somewhat alleviated. Therefore, the warpage of the insulating circuit board 10 after the pressure is released becomes a warpage amount Wb, which is smaller than the warpage amount Wa.

[0085] Here, the amount of warpage due to pressure application versus temperature of the semiconductor unit 2 (insulated circuit board 10) will be described with reference to Figure 17. Figure 17 is a graph showing the amount of warpage due to pressure application of the insulating circuit board versus the temperature of the insulating circuit board in the cooling step included in the chip bonding step of the first embodiment. In Figure 17, the horizontal axis represents the temperature T (°C) of the insulating circuit board 10 when pressure is applied, and the vertical axis represents the amount of downward warpage W (mm) of the insulating circuit board 10 due to pressure.

[0086] As shown in FIG. 17, insulating circuit board 10 is divided into an elastic deformation region where elastic deformation occurs and a plastic deformation region where plastic deformation occurs depending on the temperature at the time of pressure application and the amount of downward convex warping due to pressure.

[0087] If the warpage of the pressurized insulating circuit board 10 exceeds the warpage amount Wmax, the insulating circuit board 10 may be damaged. For this reason, the warpage of the insulating circuit board 10 must be kept within a range that does not exceed the warpage amount Wmax. The warpage amount Wmax (curvature) is, for example, 0.1 mm or more and 1.0 mm or less. It is preferable that the warpage amount W1 (curvature) within the range that does not exceed the warpage amount Wmax is, for example, 0.05 mm or more and 0.5 mm or less.

[0088] When the insulating circuit board 10 is at about room temperature Tr, even if the insulating circuit board 10 warps by about warpage W1, it only undergoes elastic deformation and returns to its original shape. For example, in the cooling process of step S15 in Fig. 6, if the insulating circuit board 10 is cooled to about room temperature Tr and warps upward in a convex manner, even if pressure is applied to the insulating circuit board 10 to cause it to warp downward in a convex manner, when the pressure is released the insulating circuit board 10 will warp upward in a convex manner as before.

[0089] For this reason, if the temperature of the insulating circuit board 10 is higher than the yield temperature T1, which is the temperature at which plastic deformation begins, plastic deformation will occur when pressure is applied to the insulating circuit board 10 to achieve the amount of warpage W1. Therefore, it is considered necessary to apply pressure to the insulating circuit board 10 at a temperature higher than the yield temperature T1. The yield temperature T1 of the insulating circuit board 10 is, for example, 100°C or higher and 200°C or lower. However, when the insulating circuit board 10 is near the yield temperature T1, the range of the amount of warpage at which the insulating circuit board 10 undergoes plastic deformation is narrow. Therefore, it is necessary to apply pressure to the insulating circuit board 10 at a temperature higher than the yield temperature T1 to achieve the amount of warpage W1.

[0090] For example, when the insulating circuit board 10 is at a temperature Ta higher than the yield temperature T1, pressure is applied to the insulating circuit board 10 so that the warpage becomes W1. After the pressure is released, the amount of warpage W1a, which is the amount of plastic deformation of the insulating circuit board 10, can be reduced. However, even at the temperature Ta, if the pressure is small (i.e., the amount of warpage W1 is small), and the amount of warpage of the insulating circuit board 10 that has warped upward convexly is greater than the amount of warpage W1a, the insulating circuit board 10 will return to its upward convex warpage after the pressure is released.

[0091] Furthermore, when the insulating circuit board 10 is at a temperature Tb that is even higher than the temperature Ta, pressure is applied to the insulating circuit board 10 so that the warpage becomes W1. After the pressure is released, the amount of warpage W2a (>W1a) of the plastic deformation of the insulating circuit board 10 can be reduced, and the downward convex warpage of the insulating circuit board 10 is maintained.

[0092] In this way, by applying pressure to insulating circuit board 10 at a temperature higher than yield temperature T1 and causing warpage, a larger amount of warpage can be alleviated. Note that if the pressure applied to insulating circuit board 10 at a temperature higher than yield temperature T1 is small and the downward convex warpage amount W1 is small, the amount of plastic deformation is small even at the same temperature, and the effect of alleviating the warpage is reduced.

[0093] In light of the above, the temperature of insulating circuit board 10 when pressure is applied to it is preferably higher than yield temperature T1, 100°C or higher and 200°C or lower, with warpage W1 being 0.05mm or higher and 0.5mm or lower, and more preferably 150°C or higher and 200°C or lower, with warpage W1 being 0.05mm or higher and 0.3mm or lower. However, the above numerical values ​​apply to an insulating circuit board 10 that includes general copper wiring boards 12a-12e, ceramic insulating plate 11, and copper metal plate 13. The above numerical values ​​may vary depending on the material, thickness, shape, etc., of insulating circuit board 10.

[0094] Next, an unloading step is performed in which the semiconductor unit 2 is unloaded from the cooling device 8 (step S16 in FIG. 6). The semiconductor unit 2 cooled in step S15 is unloaded from the cooling device 8. The unloaded semiconductor unit 2 maintains its downward convex warp. Thereafter, using such a semiconductor unit 2, the semiconductor device 1 shown in FIGS. 1 and 2 is obtained through the steps S3 and S4 of the flowchart shown in FIG. 5.

[0095] Here, a case where a semiconductor unit 2 manufactured without applying pressure to the semiconductor unit 2 in the cooling process of step S15 in Fig. 6 is bonded to a metal base plate 3 (step S3 in Fig. 5) will be described with reference to Fig. 18. Fig. 18 is a diagram showing a wiring and housing process included in a manufacturing method of a semiconductor device according to a reference example. Fig. 18 also shows a case where a semiconductor unit 2 manufactured without applying pressure to the semiconductor unit 2 in the cooling process of step S15 in Fig. 6 is bonded to a metal base plate 3 (step S3 in Fig. 5).

[0096] The semiconductor unit 2 of the semiconductor assembly 6 manufactured in step S13 of Fig. 6 is cooled through step S14 of Fig. 6. As a result, as described above, metal plate 13 contracts significantly due to the difference in the linear expansion coefficients of insulating plate 11, wiring boards 12a to 12e, and metal plate 13 of insulating circuit board 10. As a result, insulating circuit board 10 warps upward, with wiring boards 12a to 12e facing upward.

[0097] Such a semiconductor unit 2 is bonded to the front surface of a metal base plate 3 via a bonding member 3a, as shown in FIG. 18. The semiconductor unit 2 is warped upward. For this reason, the thickness of the bonding member 3a between the semiconductor unit 2 and the metal base plate 3 is not uniform overall. In particular, the bonding member 3a directly below the central portion of the semiconductor unit 2 that is warped upward is thick. Such bonding member 3a with varying thickness may cause a decrease in the cooling performance of the semiconductor unit 2.

[0098] In the manufacturing method of the semiconductor device 1 described above, first, an insulating circuit board 10 is prepared, which includes semiconductor chips 14, 15, bonding member 16, insulating plate 11, wiring boards 12a to 12e formed on the front surface of insulating plate 11, and metal plate 13 formed on the back surface of insulating plate 11. Semiconductor chips 14, 15 are placed on wiring boards 12a, 12b via bonding member 16 to assemble semiconductor unit 2, which is then heated and cooled.

[0099] In this case, when heating the semiconductor unit 2, a heater 7a having a flat heating surface 7a1 is used to heat the insulating circuit board 10 with the lower surface thereof placed on the heating surface 7a1. When cooling the semiconductor unit 2, a cooler 8a having a cooling surface 8a1 including a pair of support portions 8a2 is used to place the lower surfaces of a pair of outer regions of the insulating circuit board 10 facing the pair of support portions 8a2 in contact with the pair of support portions 8a2, and the upper surface of the central region of the insulating circuit board 10 sandwiched between the pair of outer regions is pressed downward, so that the insulating circuit board 10 is cooled in a state where it forms a downward convex shape.

[0100] The semiconductor unit 2 obtained in this manner is prevented from warping upward. That is, the semiconductor unit 2 is warped downward. Therefore, even when the semiconductor unit 2 is joined to the metal base plate 3, no large gap is formed between the semiconductor unit 2 and the metal base plate 3. This makes it possible to prevent a decrease in the heat dissipation performance of the semiconductor unit 2. Therefore, a decrease in the reliability of the semiconductor device 1 including such a semiconductor unit 2 is prevented.

[0101] [Variation 1-1] In Modification 1-1, a different form of cooling device 8 used in the cooling step of step S15 in Fig. 6 will be described with reference to Fig. 19. Fig. 19 is a diagram showing the cooling step (pressurization) included in the chip bonding step of Modification 1-1 of the first embodiment.

[0102] As described above, in the cooling process of step S15 in FIG. 6, pressure must be applied to the semiconductor unit 2 at or above the yield temperature T1. Therefore, when applying pressure to the semiconductor unit 2, for example, if the temperature of the cooler 8a is low (the cooling rate is fast) or the heat capacity of the semiconductor unit 2 is small, the temperature of the semiconductor unit 2 may drop suddenly, and pressure may not be applied in time. Therefore, as shown in FIG. 19, a preheated cooling jig 50 may be used to keep the semiconductor unit 2 at or above the yield temperature T1. However, in this case, the cooling surface 8a1 of the cooler 8a of the cooling device 8 does not have a support portion 8a2. The cooling jig 50 containing the semiconductor unit 2 is placed on the cooling surface 8a1.

[0103] The cooling jig 50 includes a main body 51 and a cooling region 52 formed in the main body 51. The main body 51 is mainly made of a material with high heat retention. An example of such a material is ceramics. The main body 51 has a flat plate shape.

[0104] The cooling region 52 is a rectangular, concave depression on the front surface of the main body 51 in plan view. The cooling surface 52a, which is the bottom surface of the cooling region 52, is approximately parallel to the front surface of the main body 51. In plan view, the outer shape of the cooling region 52 corresponds to the outer shape of the insulating circuit board 10. The depth of the cooling region 52 is equal to or slightly deeper than the thickness of the insulating circuit board 10, including the height of the support portion 52b described below. The cooling surface 52a of the cooling region 52 may be substantially flat and may include warping or undulations due to cooling, pressure, etc. The flatness of the cooling surface 52a of the cooling region 52 may be 0.2 mm or less, preferably 0.1 mm or less. A pair of support portions 52b is formed on the cooling surface 52a of the cooling region 52. The support portions 52b may have a shape similar to that of the support portion 8a2 in FIGS. 13 and 14 and provide the same effect. The support portion 52b may be formed integrally with the cooling region 52 of the main body portion 51.

[0105] The chip bonding step of Fig. 6 will be described using cooling jig 50. As described in the flowchart of Fig. 6, semiconductor assembly 6 is heated through steps S11 to S13 (semiconductor chips 14, 15 and insulating circuit board 10 are bonded).

[0106] Next, a transport step is performed in which the semiconductor unit 2 included in the semiconductor assembly 6 is transported from the sintering apparatus 7 to the cooling apparatus 8 (step S14 in FIG. 6). The semiconductor assembly 6 is removed from the sintering apparatus 7 and transported to the cooling apparatus 8. The semiconductor unit 2 removed from the positioning jig 40 is stored in the cooling area 52 of the cooling jig 50. At this time, the semiconductor unit 2 may be stored in the cooling area 52 with its upper surface covered with the buffer material 43 and the protective sheet 7c. The semiconductor unit 2 is then stored in the cooling area 52 so that the semiconductor chips 14, 15 face up. That is, the back surfaces of the pair of outer areas of the insulating circuit board 10 are supported by the pair of support portions 52b. The cooling jig 50 in which the semiconductor unit 2 is thus stored is carried into the chamber of the cooling apparatus 8 and placed on the cooling surface 8a1 of the cooler 8a. The semiconductor unit 2 is stored in the cooling area 52 so that the semiconductor chips 14, 15 face up. Compressor 8b is moved to cooling surface 8a1 and presses semiconductor chips 14, 15 of semiconductor unit 2 downward (in the -Z direction) via protective sheet 7c and buffer material 43. At this time, compressor 8b applies pressure to the central region (see FIG. 3) of insulating circuit board 10 including semiconductor chips 14, 15, in the same manner as in FIGS. 13 and 14 .

[0107] Next, a cooling step is performed in which the semiconductor unit 2 is pressurized under cooling (step S15 in FIG. 6). As in the first embodiment, the cooler 8a on which the semiconductor unit 2 is placed starts cooling the cooling surface 8a1, and the pressurizer 8b presses the semiconductor unit 2 in the −Z direction with a predetermined pressure.

[0108] At this time, the semiconductor unit 2 is kept at a temperature equal to or higher than the yield temperature T1 by the cooling jig 50, and the cooling rate is slowed. This allows the semiconductor unit 2 to be pressurized at an appropriate temperature. Therefore, the semiconductor unit 2 is pressurized while retaining sufficient heat, causing plastic deformation. The pressure applied to the semiconductor unit 2 by the pressurizer 8b is released. As shown in FIG. 19, the semiconductor unit 2 (insulated circuit board 10) maintains its downward convex warp.

[0109] In the case of Modification 1-1, similarly to the first embodiment, the semiconductor unit 2 remains warped downwards even after being cooled after heating. Therefore, even when the semiconductor unit 2 is joined to the metal base plate 3, no large gap is formed between the semiconductor unit 2 and the metal base plate 3. This makes it possible to suppress a decrease in the heat dissipation performance of the semiconductor unit 2. Therefore, a decrease in the reliability of the semiconductor device 1 including such a semiconductor unit 2 is suppressed.

[0110] [Variation 1-2] In Modification 1-2, a different form of the support portion 8a2 included in the cooling device 8 will be described with reference to FIG. 20. FIG. 20 is a diagram showing a cooling device used in a cooling step included in the chip bonding step of Modification 1-2 of the first embodiment. Note that the pressurizer 8b of the cooling device 8 in FIG. 20 is omitted. FIG. 20(A) shows a side view of the cooling device 8, and FIG. 20(B) shows a plan view of the cooling device 8. In FIG. 20(B), the position of the semiconductor unit 2 is represented by wiring.

[0111] In Modification 1-2, the support portions 8a2 are formed on the cooling surface 8a1 of the cooler 8a so as to face the four corners of each of the pair of outer regions of the insulating circuit board 10. The support portions 8a2 are convex. The convex shape may be, for example, a cube, a cylinder, a hemisphere, a truncated pyramid, or a truncated cone. The surface of the support portion 8a2 that supports the insulating circuit board 10 may have an area large enough to properly support the insulating circuit board 10.

[0112] Even with the cooling device 8 holding such a support portion 8a2, the back surface of the insulating circuit board 10 can be reliably supported when pressure is applied to the semiconductor unit 2 in step S15 of FIG. 6, which contributes to warping of the insulating circuit board 10.

[0113] [Variation 1-3] In Modification 1-3, a different support by the cooler 8a of the cooling device 8 relative to the back surface of the insulating circuit board 10 will be described with reference to FIG. 21. FIG. 21 is a diagram showing the cooling device used in the cooling process included in the chip bonding process of Modification 1-3 of the first embodiment. Note that the pressurizer 8b of the cooling device 8 in FIG. 21 is omitted. FIG. 21(A) shows a cross-sectional view taken along the dashed dotted line YY in FIG. 21(B), and FIG. 21(B) shows a plan view of the cooling device 8. In FIG. 21(B), the position of the semiconductor unit 2 is represented by wiring.

[0114] In Modification 1-3, no support portion 8a2 is formed on the cooling surface 8a1 of the cooler 8a. An opening 8a3 is formed on the cooling surface 8a1 of the cooler 8a. The opening 8a3 has a rectangular shape in a plan view. The pair of long sides of the opening 8a3 may be shorter than the long sides of the insulating circuit board 10 to be used. The pair of short sides of the opening 8a3 are longer than the pair of short sides of the insulating circuit board 10. In addition, a pair of support portions 8a4, which are opening edges, are set on each of the pair of short sides of the opening 8a3. As will be described later, when the insulating circuit board 10 is placed in the opening 8a3, the pair of support portions 8a4 are located in a pair of outer regions of the insulating circuit board 10. In addition, the depth of the opening 8a3 corresponds to the height of the support portions 8a2 in the first embodiment described above.

[0115] 6, the semiconductor unit 2 is transported to the cooling device 8 and placed on the cooling surface 8a1 of the cooler 8a in the chamber of the cooling device 8. At this time, the pair of outer regions of the insulating circuit board 10 of the semiconductor unit 2 are placed on the pair of support portions 8a4 of the opening 8a3 of the cooling surface 8a1, as shown in FIG.

[0116] 6, the semiconductor unit 2 on the cooler 8a is pressed in the -Z direction by the pressurizer 8b, as in the first embodiment. The back surfaces of the pair of outer regions of the insulating circuit board 10 are supported by the pair of support portions 8a4, and the front surface of the central region of the insulating circuit board 10 is pressed in the -Z direction by the pressurizer 8b. As a result, the back surface of the insulating circuit board 10 enters the opening 8a3, and the downward convex warp of the semiconductor unit 2 (insulating circuit board 10) is maintained.

[0117] In the case of Modification 1-3, the semiconductor unit 2 maintains its downwardly convex warped state, as in the first embodiment. Therefore, even when the semiconductor unit 2 is joined to the metal base plate 3, no large gap is formed between the semiconductor unit 2 and the metal base plate 3. This makes it possible to suppress a decrease in the heat dissipation performance of the semiconductor unit 2. Therefore, a decrease in the reliability of the semiconductor device 1 including such a semiconductor unit 2 is suppressed.

[0118] [Second embodiment] In the second embodiment, a case where the bonding member 16 of the first embodiment is solder will be described as an example. The semiconductor device 1 of the second embodiment is similar to that of the first embodiment except that the bonding member 16 is solder. In the second embodiment, differences from the first embodiment will be mainly described.

[0119] The semiconductor device 1 of the second embodiment is manufactured through the steps of the flowchart in Fig. 5. Step S1 in Fig. 5 is the same as that of the first embodiment except that a joining member 16, which is solder, is prepared. Steps S3 and S4 in Fig. 5 are also the same as those of the first embodiment. Step S2 in Fig. 5 will be described with reference to Figs. 22 and 23.

[0120] Fig. 22 is a flowchart of a chip bonding process according to a second embodiment included in a method for manufacturing a semiconductor device. Fig. 23 is a graph showing temperature changes in a semiconductor unit during the chip bonding process according to the second embodiment. In Fig. 23, the horizontal axis represents time, and the vertical axis represents the temperature of the semiconductor unit 2. Fig. 23 also shows temperature changes from the soldering process to the cooling process of the semiconductor unit 2. In Fig. 23, the temperature at which the bonding member 16, which is solder, melts is the melting temperature T2a.

[0121] The chip bonding process in step S2 of Fig. 5 is performed according to the flowchart of Fig. 22. First, an assembly process is performed in which semiconductor chips 14, 15 are placed in predetermined areas of wiring boards 12a, 12c of insulating circuit board 10 to assemble semiconductor assembly 6 (step S20 of Fig. 22). Insulated circuit board 10 is placed in positioning jig 40. Semiconductor chips 14, 15 are placed via bonding members 16 on wiring boards 12a, 12b of insulating circuit board 10 that are placed in positioning area 42 of positioning jig 40. In this manner, semiconductor assembly 6 is obtained.

[0122] Next, a pre-soldering process is performed in which the semiconductor assembly 6 is placed in the soldering apparatus 9 (step S21 in FIG. 22). The soldering apparatus 9 includes a heater 9a having a heating surface 9a1 within a chamber. The soldering apparatus 9 described in FIG. 24 includes a heater 9a within a chamber (not shown). The heater 9a includes a heating surface 9a1 on which the semiconductor assembly 6 is placed. The heating surface 9a1 is heated and cooled at a predetermined heating rate by the heater 9a. The heating surface 9a1 may be substantially flat, but may include warping or undulations due to heating, pressure, or external impact. The flatness of the heating surface 9a1 may be 0.2 mm or less, preferably 0.1 mm or less. The heating and the filling and exhaust of nitrogen within the chamber, which will be described later, are controlled by a control device (not shown) included in the soldering apparatus 9.

[0123] Next, the heating temperature by the heater 9a is increased to perform the soldering process (step S22 in FIG. 22). The soldering process will now be described with reference to FIG. 24. FIG. 24 is a diagram showing the soldering process included in the chip bonding process of the second embodiment.

[0124] Heating by the heater 9a increases the temperature of the semiconductor assembly 6 (semiconductor unit 2) as shown in the soldering process in Fig. 23. When a predetermined time tb has elapsed since the start of heating, the temperature of the semiconductor assembly 6 (semiconductor unit 2) reaches the melting temperature T2a of the joining members 16, and the joining members 16, which are solder, begin to melt. The melting temperature T2a at this time is, for example, 180°C or higher and 240°C or lower when the joining members 16 are mainly composed of solder.

[0125] Heating by the heater 9a is continued. After a predetermined time tc (> tb) has elapsed since the start of heating, the temperature of the semiconductor assembly 6 reaches a predetermined temperature T3 (> temperature T2). This temperature T3 is maintained for a predetermined time. During this time, the joining members 16 remain in a molten state.

[0126] Next, a transport step is performed in which the semiconductor unit 2 including the semiconductor assembly 6 is transported from the soldering apparatus 9 to the cooling apparatus 8 (step S24 in FIG. 22). The semiconductor assembly 6 is removed from the soldering apparatus 9 and transported to the cooling apparatus 8 in the same manner as in the first embodiment (step S14 in FIG. 6). That is, the positioning jig 40 may be used as a tray to transport the semiconductor unit 2 to the cooling apparatus 8. By using the positioning jig 40 to transport the semiconductor unit 2, the temperature T3 of the semiconductor unit 2 is maintained until the next cooling step (see <Transport step> in FIG. 23).

[0127] The semiconductor unit 2 removed from the positioning jig 40 is carried into the chamber of the cooling device 8 and placed on the cooling surface 8a1 of the cooler 8a. In this case, as in the first embodiment, a pair of outer regions (see FIG. 3) of the insulating circuit board 10 placed on the cooling surface 8a1 are supported by a pair of supports 8a2, respectively. The pressurizer 8b is moved to the cooling surface 8a1, and presses the semiconductor chips 14, 15 of the semiconductor unit 2 via the protective sheet 7c and the buffer material 43 (see FIGS. 13 and 14).

[0128] Next, a cooling step is performed in which the semiconductor units 2 are pressurized while being cooled (step S25 in FIG. 22). The semiconductor units 2 transported to the cooling device 8 are cooled by the cooler 8a and pressurized by the pressurizer 8b, similar to the first embodiment. In the second embodiment, pressurization by the pressurizer 8b begins in a range where the temperature of the insulating circuit board 10 (bonding members 16) is lower than the melting temperature T2a and higher than the yield temperature T1 (pressurization section in FIG. 23).

[0129] As described above, when the temperature is higher than the yield temperature T1, the insulating circuit board 10 undergoes plastic deformation. Furthermore, in the second embodiment, when the temperature drops below the melting temperature T2a, the joining member 16, which is solder, solidifies and the semiconductor chips 14, 15 are joined to the insulating circuit board 10. This prevents the semiconductor chips 14, 15 from shifting in position when the insulating circuit board 10 is pressurized. After the start of pressurization of the insulating circuit board 10 by the pressurizer 8b, the pressure is maintained at a predetermined level. This pressurization is continued until the temperature drops below the yield temperature T1.

[0130] When the temperature drops below the yield temperature T1, the pressure applied by the pressure device 8b to the semiconductor unit 2 is released, thereby maintaining the downward convex warp of the semiconductor unit 2 (insulating circuit board 10).

[0131] Next, an unloading step is performed in which the semiconductor unit 2 is unloaded from the cooling device 8 (step S26 in FIG. 22). The semiconductor unit 2 cooled in step S25 is unloaded from the cooling device 8. The unloaded semiconductor unit 2 maintains its downward convex warp. Thereafter, using such a semiconductor unit 2, the semiconductor device 1 shown in FIGS. 1 and 2 is obtained through the steps S3 and S4 of the flowchart shown in FIG. 5.

[0132] In the second embodiment, as in the first embodiment, the semiconductor unit 2 is prevented from warping upward. That is, the semiconductor unit 2 is warped downward. Therefore, even when the semiconductor unit 2 is joined to the metal base plate 3, no large gap is formed between the semiconductor unit 2 and the metal base plate 3. This makes it possible to prevent a decrease in the heat dissipation performance of the semiconductor unit 2. Therefore, a decrease in the reliability of the semiconductor device 1 including such a semiconductor unit 2 is prevented.

[0133] In the second embodiment, the cooling jig 50 of the modified example 1-1 may also be used. In addition, in the second embodiment, the support portion 8a2 of the modified example 1-2 and the opening 8a3 of the modified example 1-3 may also be applied to the cooler 8a of the cooling device 8. [Explanation of symbols]

[0134] 1. Semiconductor device 2 Semiconductor Unit 3 Metal base plate 3a Joint material 4 cases 4a Adhesive material 5 Sealing member 6 Semiconductor Assembly 7. Sintering equipment 7a Heater 7a1 Heating surface 7b Pressurizer 7c Protective Sheet 8 Cooling device 8a cooler 8a1 Cooling surface 8a2,8a4 Support part 8a3 opening 8b Pressurizer 9 Soldering equipment 9a heater 9a1 Heating surface 10. Insulated circuit board 11 Insulating plate 11a, 11c long side 11b, 11d short side 11e~11h corner 12a~12e wiring board 13 Metal plate 14,15 Semiconductor chips 14a, 15a control electrodes 14b, 15b Output electrodes 16 Joint materials 21~25 External connection terminals 26,27 Wire 28,29 Lead frame 30 Transcription device 31 Transfer table 32 Sintered sheet 32a Release film 32b Sintered film 33 Transcription Tool 33a Vacuum suction hole 40 Positioning jig 41 Main body 42 Positioning Area 43 Cushioning material 50 Cooling jig 51 Main body 52 Cooling area 52a Cooling surface 52b Support part 61~65 Wiring

Claims

1. a preparation step of preparing an insulating circuit board including a semiconductor chip, a bonding member, an insulating plate, a wiring board formed on the front surface of the insulating plate, and a metal plate formed on the back surface of the insulating plate; an assembly step of assembling a semiconductor unit by placing the semiconductor chip on the wiring board via the bonding member; a heating step of heating the semiconductor unit; a cooling step of cooling the semiconductor unit; Including, In the heating step, Using a heater having a heating surface including a flat surface, Heating the insulating circuit board with the lower surface thereof placed on the flat surface; In the cooling step, Using a cooler having a cooling surface including a pair of support portions, a lower surface of a pair of outer regions of the insulating circuit board that face the pair of support portions is placed in contact with the pair of support portions, and an upper surface of a central region of the insulating circuit board that is sandwiched between the pair of outer regions is pressed downward, and the insulating circuit board is cooled in a state in which it forms a downward convex shape; A method for manufacturing a semiconductor device.

2. a transport step of transporting the semiconductor unit from the heater to the cooler after the heating step and before the cooling step, The method for manufacturing a semiconductor device according to claim 1 .

3. In the transporting step, the semiconductor unit is placed on a cooling jig heated to a predetermined temperature or higher and transported to the cooler. The method for manufacturing a semiconductor device according to claim 2 .

4. the central region of the insulating circuit board is a region that includes at least all of the semiconductor chips arranged on the insulating circuit board; The method for manufacturing a semiconductor device according to any one of claims 1 to 3.

5. the pair of outer regions of the insulating circuit board are, in a plan view, regions from a pair of opposing ends of the metal plate parallel to the short-side direction to a pair of ends of the insulating plate parallel to the short-side direction, The method for manufacturing a semiconductor device according to claim 4 .

6. The pair of outer regions are further regions extending from a pair of ends of the wiring board on the pair of opposing short sides of the insulating circuit board to the pair of ends of the insulating plate in a plan view. The method for manufacturing a semiconductor device according to claim 5 .

7. In the cooling step, The insulating circuit board is pressed at a temperature higher than a plastic deformation starting temperature at which plastic deformation of the insulating circuit board occurs. The method for manufacturing a semiconductor device according to any one of claims 1 to 6.

8. In the cooling step, the insulating circuit board is pressurized via a buffer member, including the central region of the upper surface; The method for manufacturing a semiconductor device according to any one of claims 1 to 7.

9. The insulating circuit board has a rectangular shape in a plan view, the support portion is linear in plan view and convex in cross section, and is formed on the cooler along a pair of opposing short sides of the insulating circuit board. The method for manufacturing a semiconductor device according to any one of claims 1 to 8.

10. The cross section of the support portion is triangular, rectangular, or semicircular. The method for manufacturing a semiconductor device according to claim 9 .

11. The insulating circuit board has a rectangular shape in a plan view, the support portions are formed in ranges corresponding to the pair of outer regions and corresponding to the four corners of the insulating circuit board. The method for manufacturing a semiconductor device according to any one of claims 1 to 8.

12. The support portion is cubic, cylindrical, semispherical, truncated pyramid, or truncated cone. The method for manufacturing a semiconductor device according to claim 11 .

13. an opening is formed in the cooling surface, the opening including a pair of opening long sides that are shorter than a pair of long sides of the insulating circuit board and a pair of opening short sides that are longer than a pair of opposing short sides of the insulating circuit board; the pair of support portions are located along the pair of short sides of the opening, the insulating circuit board covers the opening and is supported by the pair of support portions; The method for manufacturing a semiconductor device according to any one of claims 1 to 8.

14. The joining member is a sintered material containing porous metal. The method for manufacturing a semiconductor device according to any one of claims 1 to 13.

15. In the heating step, pressing the semiconductor chip toward the lower surface; The method for manufacturing a semiconductor device according to claim 14.

16. The pressure in the heating step is greater than the pressure in the cooling step. The method for manufacturing a semiconductor device according to claim 15.

17. The joining member is solder. The method for manufacturing a semiconductor device according to any one of claims 1 to 13.

18. In the cooling step, when the temperature of the semiconductor unit has decreased to a temperature between the melting point of the bonding member and the yield temperature at which plastic deformation of the insulating circuit board begins, the insulating circuit board is pressurized to correct the warpage. The method for manufacturing a semiconductor device according to claim 17.

19. The steps from the heating step to the cooling step are carried out in a nitrogen atmosphere. The method for manufacturing a semiconductor device according to any one of claims 1 to 18.

20. the metal plate is formed on the entire rear surface of the insulating plate with a gap from the outer edge thereof, a plurality of the wiring boards are formed on the entire front surface of the insulating plate with gaps from the outer edge and with gaps between each other; The method for manufacturing a semiconductor device according to any one of claims 1 to 19.

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