Multilayer ceramic capacitors

Abstract

The present invention addresses the problem of providing an LW reversal type multilayer ceramic capacitor which is capable of suppressing deterioration of a self-alignment effect and achieving a stable mounting.　The present invention provides a multilayer ceramic capacitor 1 wherein if l is the length in the longitudinal direction connecting a first end surface LS1 and a second end surface LS2 of a multilayer body 10, w is the length in the width direction connecting a first lateral surface WS1 and a second lateral surface WS2 of the multilayer body 10, and t is the length in the height direction connecting a first main surface TS1 and a second main surface TS2 of the multilayer body 10, the dimensional relationship w > l > t is satisfied. With respect to this multilayer ceramic capacitor 1, a fourth surface part 40A4 and a fifth surface part 40A5 of a first external electrode 40A and a ninth surface part 40B4 and a tenth surface part 40B5 of a second external electrode 40B have openings H through which the surface of the multilayer body 10 is exposed; and the fourth surface part 40A4 and the ninth surface part 40B4, and the fifth surface part 40A5 and the tenth surface part 40B5 have projections K that protrude from the center side of the longitudinal direction, in which the surface parts face each other, in the longitudinal direction.

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] Conventionally, multilayer ceramic capacitors have been known. A typical multilayer ceramic capacitor has a laminate in the shape of a substantially rectangular parallelepiped, with the length direction L being longer than the width direction W, and external electrodes are provided on both ends of the laminate in the length direction L. Meanwhile, so-called LW-reversed multilayer ceramic capacitors are also known, in which the magnitude relationship between the length direction L and the width direction W of the laminate is reversed in order to reduce ESL (see Patent Documents 1 and 2).

[0003] Furthermore, in recent years, as the mounting density of circuit boards has increased, the mounting area for multilayer ceramic capacitors has decreased. Therefore, the PoP (Package on Package) mounting format has been adopted, and there has been an increase in demand for multilayer ceramic capacitors mounted on the bottom edge of a circuit board as an LSC (Land Side Capacitor) type. Multilayer ceramic capacitors mounted as such an LSC (Land Side Capacitor) type require low-profile multilayer ceramic capacitors with a thin height. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-57753 [Patent Document 2] Japanese Patent Publication No. 2020-61524 Summary of the Invention [Problem to be solved by the invention]

[0005] Patent Document 2 discloses an LW-reversed type multilayer ceramic electronic component in which a recess is provided on the edge of at least one of the fourth and fifth surface portions of the external electrode, recessed from the edge toward the first surface portion, and both side portions of the recess in the third direction form covering portions that cover the ridges of the two surfaces of the component body in the second direction.

[0006] However, in the multilayer ceramic electronic component disclosed in Patent Document 2, variations in the area and shape of the coating covering the ridges of the two surfaces of the component body in the second direction may occur due to variations in the formation position and thickness of the underlying conductor layer and the coated conductor layer formed thereon. When mounting an LW-reversed multilayer ceramic electronic component to a mounting substrate using solder, differences in the area and shape of the coating may cause differences in the way the solder wets the coating, resulting in differences in the way the tensile stress of the solder is applied. This may result in a deterioration of the self-alignment effect. As a result, the multilayer ceramic electronic component may be prone to rotation or tilt, reducing mountability. Furthermore, because the distance between the lands on the substrate on which an LW-reversed multilayer ceramic electronic component is mounted is short, the self-alignment effect is reduced. If the multilayer ceramic electronic component rotates significantly, one external electrode may be mounted across lands of opposite polarity, potentially resulting in a short circuit.

[0007] An object of the present invention is to provide an LW-reversed type multilayer ceramic capacitor that can suppress deterioration of the self-alignment effect and enable stable mounting. [Means for solving the problem]

[0008] The multilayer ceramic capacitor according to the present invention includes a laminate including a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in a height direction, and having first and second main surfaces opposing each other in the height direction, a first end face and a second end face opposing each other in a length direction perpendicular to the height direction, and a first side face and a second side face opposing each other in a width direction perpendicular to the height direction and the length direction; a first external electrode having a first surface portion located on the first end face, at least one of a second surface portion located on a portion of the first main surface and a third surface portion located on a portion of the second main surface, a fourth surface portion located on a portion of the first side face, and a fifth surface portion located on a portion of the second side face; a sixth surface portion located on the second end face, a seventh surface portion located on a portion of the first main surface, and a fifth surface portion located on a portion of the second main surface; a second external electrode having at least one of an eighth side surface portion located on a first end surface and an eighth side surface portion located on a part of the first side surface, a ninth side surface portion located on a part of the second side surface, and a tenth side surface portion located on a part of the second side surface, wherein, when the length in the longitudinal direction connecting the first end surface and the second end surface of the laminate is l, the length in the width direction connecting the first side surface and the second side surface is w, and the length in the height direction connecting the first main surface and the second main surface is t, a dimensional relationship of w>l>t is satisfied, and the fourth side surface portion and the fifth side surface portion and the ninth side surface portion and the tenth side surface portion have openings through which the surfaces of the laminate are exposed, and the fourth side surface portion and the ninth side surface portion and the fifth side surface portion and the tenth side surface portion each have a convex portion that protrudes in the longitudinal direction from a center side in the longitudinal direction that faces each other. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide an LW-reversed type multilayer ceramic capacitor that can suppress deterioration of the self-alignment effect and enable stable mounting. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is an external perspective view of a multilayer ceramic capacitor according to an embodiment; [Figure 2]2 is a view of the multilayer ceramic capacitor shown in FIG. 1, looking at a first side surface along the direction of arrow II. [Figure 3] 3 is a view of the multilayer ceramic capacitor shown in FIG. 1, looking at a second side surface along the direction of arrow III. [Figure 4] 4 is a view of the multilayer ceramic capacitor shown in FIG. 2, looking at the first main surface side along the direction of arrow IV. [Figure 5] 3 is a view of the multilayer ceramic capacitor shown in FIG. 2, looking at the second main surface side along the direction of arrow V. FIG. [Figure 6] 6 is a cross-sectional view taken along line VI-VI of the multilayer ceramic capacitor shown in FIG. [Figure 7] 7 is a cross-sectional view of the multilayer ceramic capacitor taken along line VII-VII of FIG. 6. [Figure 8A] 7 is a cross-sectional view taken along line VIIIA-VIIIA of the multilayer ceramic capacitor shown in FIG. 6, showing a first internal electrode layer. FIG. [Figure 8B] 8 is a cross-sectional view taken along line VIIIB-VIIIB of the multilayer ceramic capacitor shown in FIG. 6, showing a second internal electrode layer. FIG. [Figure 9A] 9 is a cross-sectional view taken along line IXA-IXA of the multilayer ceramic capacitor shown in FIG. 4, showing a first side surface of the laminate. [Figure 9B] 9 is a cross-sectional view taken along line IXB-IXB of the multilayer ceramic capacitor shown in FIG. 4, showing a second side surface of the laminate. [Figure 10A] 7 is an enlarged view of the XA portion in FIG. 6, showing a cross section of the first external electrode. FIG. [Figure 10B] 7 is an enlarged view of the XB portion in FIG. 6, showing a cross section of the second external electrode. FIG. [Figure 11A] 10B is a cross-sectional view showing a modified example of the layer structure of the external electrodes of the multilayer ceramic capacitor according to the embodiment, and corresponds to FIG. 10A. FIG. [Figure 11B]10B is a cross-sectional view showing a modified example of the layer structure of the external electrodes of the multilayer ceramic capacitor according to the embodiment, and corresponds to FIG. 10B. [Figure 12] 3A to 3C are diagrams illustrating intermediate states in the manufacturing process of the multilayer ceramic capacitor according to the embodiment. [Figure 13] 3A to 3C are diagrams illustrating intermediate states in the manufacturing process of the multilayer ceramic capacitor according to the embodiment. [Figure 14] 3A to 3C are diagrams illustrating intermediate states in the manufacturing process of the multilayer ceramic capacitor according to the embodiment. [Figure 15] 1. FIG. 4 is a cross-sectional view showing a modification of the arrangement position of the external electrodes of the multilayer ceramic capacitor according to the embodiment, and corresponds to FIG. [Figure 16A] FIG. 2 is an external perspective view of the multilayer ceramic capacitor of Comparative Example 1, and corresponds to FIG. [Figure 16B] 8B is a diagram showing a first internal electrode layer of the multilayer ceramic capacitor of the comparative example, and corresponds to FIG. 8A. FIG. [Figure 16C] 8B is a diagram showing a second internal electrode layer of the multilayer ceramic capacitor of the comparative example, and corresponds to FIG. 8B. [Figure 17A] FIG. 2 is an external perspective view of the multilayer ceramic capacitor of Comparative Example 2, corresponding to FIG. [Figure 17B] 8B is a diagram showing a first internal electrode layer of the multilayer ceramic capacitor of the comparative example, and corresponds to FIG. 8A. FIG. [Figure 17C] 8B is a diagram showing a second internal electrode layer of the multilayer ceramic capacitor of the comparative example, and corresponds to FIG. 8B. [Figure 18A] 10A and 10B are diagrams for explaining a method for evaluating mountability in an experimental example. [Figure 18B] 10A and 10B are diagrams for explaining a method for evaluating mountability in an experimental example. [Figure 18C] 10A and 10B are diagrams for explaining a method for evaluating mountability in an experimental example. [Figure 18D] 10A and 10B are diagrams for explaining a method for evaluating mountability in an experimental example. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, a multilayer ceramic capacitor 1 according to an embodiment of the present disclosure will be described. FIG. 1 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 1 , taken along the direction of arrow II, from the first side surface WS1. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 1 , taken along the direction of arrow III, from the second side surface WS2. FIG. 4 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 2 , taken along the direction of arrow IV, from the first main surface TS1. FIG. 5 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 2 , taken along the direction of arrow V, from the second main surface TS2. FIG. 6 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 4 , taken along line VI-VI. FIG. 7 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 6 , taken along line VII-VII. FIG. 8A is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 6 , taken along line VIIIA-VIIIA. FIG. 8B is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 6 , taken along line VIIIB-VIIIB. Fig. 9A is a cross-sectional view of the multilayer ceramic capacitor 1 shown in Fig. 4 taken along line IXA-IXA, illustrating a first side surface WS1 of the laminate 10. Fig. 9B is a cross-sectional view of the multilayer ceramic capacitor 1 shown in Fig. 4 taken along line IXB-IXB, illustrating a second side surface WS2 of the laminate 10. Fig. 10A is an enlarged view of portion XA in Fig. 6, illustrating a cross section of the first external electrode 40A. Fig. 10B is an enlarged view of portion XB in Fig. 6, illustrating a cross section of the second external electrode 40B.

[0012] The multilayer ceramic capacitor 1 includes a laminate 10 and external electrodes 40.

[0013] 1 to 9B show an XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The height direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 6 is also referred to as the LT cross section. The cross section shown in FIG. 7 is also referred to as the WT cross section. The cross sections shown in FIGS. 8A and 8B are also referred to as the LW cross sections.

[0014] As shown in Figures 1 to 5, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that face each other in a height direction T, a first end surface LS1 and a second end surface LS2 that face each other in a length direction L that is perpendicular to the height direction T, and a first side surface WS1 and a second side surface WS2 that face each other in a width direction W that is perpendicular to the height direction T and the length direction L.

[0015] The laminate 10 has a substantially rectangular parallelepiped shape. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Note that unevenness may be formed on part or all of the surfaces constituting the laminate 10.

[0016] As shown in Figures 6 and 7, the laminate 10 has an inner layer portion 11, and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged to sandwich the inner layer portion 11 in the height direction T.

[0017] The internal layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. In the height direction T, the internal layer portion 11 includes the internal electrode layer 30 located closest to the first main surface TS1 to the internal electrode layer 30 located closest to the second main surface TS2. In the internal layer portion 11, the multiple internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The internal layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor. The internal layer portion 11 is also referred to as an effective layer portion.

[0018] The plurality of dielectric layers 20 are made of a dielectric material. The dielectric material is, for example, a ceramic material. The dielectric material may be, for example, a dielectric ceramic containing a component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When these components are the main component, a minor component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound may be added in a smaller amount than the main component depending on the desired properties of the laminate.

[0019] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 10 μm or less. The number of laminated dielectric layers 20 is preferably 15 to 700. Note that this number of dielectric layers 20 is the total number of the dielectric layers in the inner layer portion 11 and the dielectric layers in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0020] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The first internal electrode layers 31 are disposed on the multiple dielectric layers 20 and extend to the first end face LS1. The second internal electrode layers 32 are disposed on the multiple dielectric layers 20 and extend to the second end face LS2. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are alternately disposed in the height direction T of the laminate 10, with the dielectric layers 20 interposed between them. The first internal electrode layers 31 and the second internal electrode layers 32 are disposed so as to sandwich the dielectric layers 20 therebetween.

[0021] As shown in Figure 8A, the first internal electrode layer 31 has a first opposing electrode portion 31A facing the second internal electrode layer 32, a first lead portion 31B extending from the first opposing electrode portion 31A to the first end face LS1, a portion of the first side surface WS1, and a portion of the second side surface WS2, a second lead portion 31C extending from the first opposing electrode portion 31A to a portion of the first side surface WS1, and a third lead portion 31D extending from the first opposing electrode portion 31A to a portion of the second side surface WS2.

[0022] The first counter electrode portion 31A is located inside the laminate 10. The first lead portion 31B is connected to the first counter electrode portion 31A and is exposed at the first end face LS1, a portion of the first side face WS1, and a portion of the second side face WS2. The second lead portion 31C is connected to the first counter electrode portion 31A and is exposed at a portion of the first side face WS1. The third lead portion 31D is connected to the first counter electrode portion 31A and is exposed at a portion of the second side face WS2.

[0023] The second lead portion 31C is disposed at a distance in the longitudinal direction L from the portion of the first lead portion 31B that is extended to the first side surface WS1. The third lead portion 31D is disposed at a distance in the longitudinal direction L from the portion of the first lead portion 31B that is extended to the second side surface WS2.

[0024] As shown in Figure 8B, the second internal electrode layer 32 has a second opposing electrode portion 32A facing the first internal electrode layer 31, a fourth lead portion 32B extending from the second opposing electrode portion 32A to the second end face LS2, a portion of the first side surface WS1, and a portion of the second side surface WS2, a fifth lead portion 32C extending from the second opposing electrode portion 32A to a portion of the first side surface WS1, and a sixth lead portion 32D extending from the second opposing electrode portion 32A to a portion of the second side surface WS2.

[0025] The second counter electrode portion 32A is located inside the laminate 10. The fourth lead portion 32B is connected to the second counter electrode portion 32A and is exposed at the second end face LS2, a portion of the first side face WS1, and a portion of the second side face WS2. The fifth lead portion 32C is connected to the second counter electrode portion 32A and is exposed at a portion of the first side face WS1. The sixth lead portion 32D is connected to the second counter electrode portion 32A and is exposed at a portion of the second side face WS2.

[0026] The fifth lead portion 32C is disposed at a distance in the longitudinal direction L from the portion of the fourth lead portion 32B that is extended to the first side surface WS1. The sixth lead portion 32D is disposed at a distance in the longitudinal direction L from the portion of the fourth lead portion 32B that is extended to the second side surface WS2.

[0027] Fig. 9A is a cross-sectional view taken along line IXA-IXA of the multilayer ceramic capacitor 1 shown in Fig. 4, illustrating a first side surface WS1 of the laminate 10. Fig. 9B is a cross-sectional view taken along line IXB-IXB of the multilayer ceramic capacitor 1 shown in Fig. 4, illustrating a second side surface WS2 of the laminate 10. Note that Figs. 8A and 8B also show line IXA-IXA indicating the position of the cross-sectional view in Fig. 9A, and line IXB-IXB indicating the position of the cross-sectional view in Fig. 9B.

[0028] 9A, the first lead portions 31B and second lead portions 31C of each of the plurality of first internal electrode layers 31 and the fourth lead portions 32B and fifth lead portions 32C of each of the plurality of second internal electrode layers 32 are exposed on the first side surface WS1 of the laminate 10. The plurality of first lead portions 31B and the plurality of second lead portions 31C are exposed on the surface of the laminate 10 while being spaced apart. The plurality of fourth lead portions 32B and the plurality of fifth lead portions 32C are exposed on the surface of the laminate 10 while being spaced apart.

[0029] 9A , on the first side surface WS1, of the multiple second lead portions 31C lined up in the height direction T of the laminate 10, the dimension in the length direction L of the multiple second lead portions 31C located in the center of the height direction T is longer than the dimension in the length direction L of the second lead portions 31C located outside the center of the height direction T, i.e., located closer to the first main surface TS1 and the second main surface TS2 than the center of the height direction T. The positions of the outer ends of all the second lead portions 31C in the length direction L, i.e., the ends on the first end face LS1 side, are aligned in the length direction L. Therefore, the center side in the length direction L of the multiple second lead portions 31C located in the center of the height direction T protrudes closer to the center in the length direction L than the multiple second lead portions 31C located outside the center of the height direction T. In other words, each of the multiple second drawer sections 31C located in the center of the height direction T has a protrusion 31C1 that protrudes toward the center in the length direction from the end portion of the multiple second drawer sections 31C other than the center in the height direction T on the center side in the length direction.

[0030] The longitudinal center-side tips of the protrusions 31C1 are located closer to the longitudinal center than the longitudinal center-side ends 40A9 of the second and third surfaces 40A2 and 40A3. That is, the longitudinal center sides of the plurality of second lead-out portions 31C located in the central portion in the height direction T protrude closer to the longitudinal center than the longitudinal center-side ends 40A9 of the second and third surfaces 40A2 and 40A3.

[0031] Furthermore, among the plurality of fifth lead portions 32C arranged in the height direction T of the laminate 10, the dimension in the length direction L of the plurality of fifth lead portions 32C located in the center of the height direction T is longer than the dimension in the length direction L of the fifth lead portions 32C located other than the center of the height direction T, i.e., located closer to the first main surface TS1 and the second main surface TS2 than the center of the height direction T. The positions of the outer ends in the length direction L of all the fifth lead portions 32C, i.e., the ends on the second end face LS2 side, are aligned in the length direction L. Therefore, the center side in the length direction L of the plurality of fifth lead portions 32C located in the center of the height direction T protrudes closer to the center in the length direction L than the plurality of fifth lead portions 32C other than the center of the height direction T. In other words, each of the multiple fifth drawer sections 32C located in the center of the height direction T has a protrusion 32C1 that protrudes toward the center of the length from the end of the multiple fifth drawer sections 32C other than the center of the height direction T.

[0032] The longitudinal center-side tips of the protrusions 32C1 are located closer to the longitudinal center than the longitudinal center-side ends 40B9 of the seventh and eighth surface portions 40B2, 40B3. That is, the longitudinal center sides of the plurality of fifth lead portions 32C located at the center in the height direction T protrude closer to the longitudinal center than the longitudinal center-side ends 40B9 of the seventh and eighth surface portions 40B2, 40B3.

[0033] As shown in FIG. 9B , on the second side surface WS2 side, among the multiple third lead portions 31D lined up in the height direction T of the laminate 10, the dimension in the length direction L of the multiple third lead portions 31D located in the center of the height direction T is longer than the dimension in the length direction L of the third lead portions 31D located other than the center of the height direction T, i.e., located closer to the first main surface TS1 and the second main surface TS2 than the center of the height direction T. The positions of the outer ends of all the third lead portions 31D in the length direction L, i.e., the ends on the first end face LS1 side, are aligned in the length direction L. Therefore, the center side in the length direction L of the multiple third lead portions 31D located in the center of the height direction T protrudes closer to the center in the length direction L than the multiple third lead portions 31D located other than the center of the height direction T. In other words, each of the multiple third drawer sections 31D located in the center of the height direction T has a protrusion 31D1 that protrudes toward the center of the length from the end of the multiple third drawer sections 31D other than the center of the height direction T on the center side of the length.

[0034] The longitudinal center-side tips of the protrusions 31D1 are located closer to the longitudinal center than the longitudinal center-side ends 40A9 of the second and third surfaces 40A2 and 40A3. That is, the longitudinal center sides of the plurality of third drawer portions 31D located in the central portion in the height direction T protrude closer to the longitudinal center than the longitudinal center-side ends 40A9 of the second and third surfaces 40A2 and 40A3.

[0035] Furthermore, among the multiple sixth lead portions 32D lined up in the height direction T of the laminate 10, the dimension in the length direction L of the multiple sixth lead portions 32D located in the center of the height direction T is longer than the dimension in the length direction L of the multiple sixth lead portions 32D located other than the center of the height direction T, i.e., located closer to the first main surface TS1 and the second main surface TS2 than the center of the height direction T. The positions of the outer ends of all the sixth lead portions 32D in the length direction L, i.e., the ends on the second end face LS2 side, are aligned in the length direction T. Therefore, the center side in the length direction L of the multiple sixth lead portions 32D located in the center of the height direction T protrudes closer to the center in the length direction L than the multiple sixth lead portions 32D other than the center of the height direction T. In other words, each of the multiple sixth drawer sections 32D located in the center of the height direction T has a protrusion 32D1 that protrudes toward the center of the length from the end of the multiple sixth drawer sections 32D other than the center of the height direction T.

[0036] The longitudinal center-side tips of the protrusions 32D1 are located closer to the longitudinal center than the longitudinal center-side ends 40B9 of the seventh and eighth surface portions 40B2, 40B3. That is, the longitudinal center sides of the plurality of sixth lead portions 32D located at the center in the height direction T protrude closer to the longitudinal center than the longitudinal center-side ends 40B9 of the seventh and eighth surface portions 40B2, 40B3.

[0037] The length direction L of the portions of the first lead portion 31B and the fourth lead portion 32B that are partially exposed on the first side surface WS1 is preferably 30 μm or more and 230 μm or less. The length direction L of the portions of the first lead portion 31B and the fourth lead portion 32B that are partially exposed on the second side surface WS2 is preferably 30 μm or more and 230 μm or less. The length direction L of the portions of the second lead portion 31C and the fifth lead portion 32C that are partially exposed on the first side surface WS1 is preferably 30 μm or more and 230 μm or less. The length direction L of the portions of the third lead portion 31D and the sixth lead portion 32D that are partially exposed on the second side surface WS2 is preferably 30 μm or more and 230 μm or less.

[0038] The dimensions of each of the lead portions exposed on the side surfaces of the laminate 10 are not particularly limited. However, the dimension in the length direction L of the portions of the second lead portion 31C and the fifth lead portion 32C exposed on the first side surface WS1 may be longer than the dimension in the length direction L of the portions of the first lead portion 31B and the fourth lead portion 32B exposed on the first side surface WS1. The dimension in the length direction L of the portions of the third lead portion 31D and the sixth lead portion 32D exposed on the second side surface WS2 may be longer than the dimension in the length direction L of the portions of the first lead portion 31B and the fourth lead portion 32B exposed on the second side surface WS2.

[0039] This makes it possible to realize the shape of the external electrode 40 of this embodiment, which has openings H and protrusions K, which will be described later. Furthermore, since the distance between the second lead portion 31C of the first internal electrode layer 31 and the fifth lead portion 32C of the second internal electrode layer 32 can be shortened, and the distance between the third lead portion 31D of the first internal electrode layer 31 and the sixth lead portion 32D of the second internal electrode layer 32 can be shortened, it becomes possible to shorten the path through which current flows. Therefore, the ESL can be reduced.

[0040] In this embodiment, the first opposing electrode portion 31A and the second opposing electrode portion 32A face each other via the dielectric layer 20, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0041] The shapes of the first opposing electrode portion 31A and the second opposing electrode portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or may be oblique.

[0042] The shapes of the first drawer section 31B and the fourth drawer section 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangle may be rounded or angled. In this embodiment, the first drawer section 31B and the fourth drawer section 32B are substantially T-shaped with some of the corners of the rectangle removed.

[0043] The shapes of second drawer section 31C, third drawer section 31D, fifth drawer section 32C, and sixth drawer section 32D are not particularly limited, but are preferably rectangular, although the corners of the rectangle may be rounded or angled.

[0044] The dimension in the width direction W of the portion of the first lead portion 31B exposed at the first end face LS1 is larger than the dimension in the width direction of the first counter electrode portion 31A. The dimension in the width direction W of the portion of the fourth lead portion 32B exposed at the second end face LS2 is larger than the dimension in the width direction of the second counter electrode portion 32A.

[0045] The first internal electrode layer 31 and the second internal electrode layer 32 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0046] The thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably, for example, about 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 15 or more and 200 or less.

[0047] The first main surface side outer layer portion 12 is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. That is, the first main surface side outer layer portion 12 is formed from multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 located closest to the first main surface TS1 among the multiple internal electrode layers 30. The dielectric layers 20 used in the first main surface side outer layer portion 12 may be the same as the dielectric layers 20 used in the internal layer portion 11.

[0048] The second main surface side outer layer portion 13 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 13 is an aggregate of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. That is, the second main surface side outer layer portion 13 is formed from multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 located closest to the second main surface TS2 among the multiple internal electrode layers 30. The dielectric layer 20 used in the second main surface side outer layer portion 13 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0049] As described above, the laminate 10 has a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20. In other words, the multilayer ceramic capacitor 1 has the laminate 10 in which the dielectric layers 20 and the internal electrode layers 30 are alternately laminated.

[0050] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is a portion where the first counter electrode portion 31A of the first internal electrode layer 31 and the second counter electrode portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as a part of the inner layer portion 11. FIGS. 8A and 8B show the ranges of the counter electrode portion 11E in the width direction W and length direction L. The counter electrode portion 11E is also referred to as the effective portion of the capacitor.

[0051] The laminate 10 has an end surface side outer layer portion. The end surface side outer layer portion includes a first end surface side outer layer portion LG1 located on the first end surface LS1 side and a second end surface side outer layer portion LG2 located on the second end surface LS2 side. The first end surface side outer layer portion LG1 is a portion including the dielectric layer 20 and the first lead portion 31B located between the counter electrode portion 11E and the first end surface LS1. In other words, the first end surface side outer layer portion LG1 is an aggregate of the portions of the multiple dielectric layers 20 on the first end surface LS1 side and the multiple first lead portions 31B. The second end surface side outer layer portion LG2 is a portion including the dielectric layer 20 and the fourth lead portion 32B located between the counter electrode portion 11E and the second end surface LS2. That is, the second end face side outer layer portion LG2 is an aggregate of the portions of the plurality of dielectric layers 20 on the second end face LS2 side and the plurality of fourth lead portions 32B. Figures 6, 8A, and 8B show the ranges in the length direction L of the first end face side outer layer portion LG1 and the second end face side outer layer portion LG2. The first end face side outer layer portion LG1 and the second end face side outer layer portion LG2 are also referred to as L gaps or end gaps.

[0052] The laminate 10 has side surface-side outer layer portions. The side surface-side outer layer portions include a first side surface-side outer layer portion WG1 located on the first side surface WS1 side and a second side surface-side outer layer portion WG2 located on the second side surface WS2 side. The first side surface-side outer layer portion WG1 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the first side surface WS1. That is, the first side surface-side outer layer portion WG1 is a collection of portions of the multiple dielectric layers 20 located on the first side surface WS1 side. The second side surface-side outer layer portion WG2 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the second side surface WS2. That is, the second side surface-side outer layer portion WG2 is a collection of portions of the multiple dielectric layers 20 located on the second side surface WS2 side. Figures 7, 8A, and 8B show the ranges of the first side surface-side outer layer portion WG1 and the second side surface-side outer layer portion WG2 in the width direction W. The first side surface outer layer portion WG1 and the second side surface outer layer portion WG2 are also called W gaps or side gaps.

[0053] 6 to 8B, when the length in the longitudinal direction L connecting the first end face LS1 and the second end face LS2 of the laminate 10 is l, the length in the width direction W connecting the first side face WS1 and the second side face WS2 is w, and the length in the height direction T connecting the first main face TS1 and the second main face TS2 is t, the dimensional relationship between these is w>l>t. This makes it possible to increase the width of the lead-out portion at the end face of the internal electrode layer 30. Furthermore, since the distance between the first external electrode 40A and the second external electrode 40B can be shortened, the ESL of the multilayer ceramic capacitor 1 can be reduced.

[0054] The length l in the longitudinal direction L connecting the first end surface LS1 and the second end surface LS2 of the laminate 10 is preferably 0.05 mm or more and 0.7 mm or less. The length w in the width direction W connecting the first side surface WS1 and the second side surface WS2 of the laminate 10 is preferably 0.15 mm or more and 1.5 mm or less. The length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 is preferably 150 μm or less. This allows for high-density packaging. The length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 is preferably 100 μm or less, and more preferably 50 μm or less. This allows for higher-density packaging.

[0055] The dimensions l, w, and t of the laminate 10 are measured by the following method.

[0056] First, the w dimension of the laminate 10 is measured. Specifically, the w dimension of the laminate 10 is measured with a micrometer at the center position in the length direction L of the laminate ceramic capacitor 1, that is, at a position L / 2 of the laminate ceramic capacitor 1.

[0057] Next, the l and t dimensions of the laminate 10 are measured. First, a multilayer ceramic capacitor 1 identical to the multilayer ceramic capacitor 1 whose w dimension was measured is polished to the center position in the width direction W of the multilayer ceramic capacitor 1, i.e., to a position W / 2 of the multilayer ceramic capacitor 1, so that it is parallel to the LT plane. Then, the LT cross section exposed by polishing is observed using a microscope. The l dimension of the laminate 10 is measured using a microscope at the center position in the height direction T of the laminate 10, i.e., at a position t / 2 of the laminate 10. The t dimension of the laminate 10 is measured using a microscope at the center position in the length direction L of the laminate 10, i.e., at a position l / 2 of the laminate 10.

[0058] The external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side and a second external electrode 40B arranged on the second end face LS2 side.

[0059] The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A of this embodiment has a first surface portion 40A1 located on the first end face LS1, a second surface portion 40A2 located on a portion of the first main surface TS1, a third surface portion 40A3 located on a portion of the second main surface TS2, a fourth surface portion 40A4 located on a portion of the first side surface WS1, and a fifth surface portion 40A5 located on a portion of the second side surface WS2. Note that the first external electrode 40A preferably has at least one of the second surface portion 40A2 located on a portion of the first main surface TS1 and the third surface portion 40A3 located on a portion of the second main surface TS2, the first surface portion 40A1 located on the first end face LS1, the fourth surface portion 40A4 located on a portion of the first side surface WS1, and the fifth surface portion 40A5 located on a portion of the second side surface WS2.

[0060] The first surface portion 40A1 covers the entire first end face LS1 and is the portion connected to the first internal electrode layer 31. Either the second surface portion 40A2 or the third surface portion 40A3 is the portion connected to a land of the mounting board.

[0061] The fourth surface 40A4 is connected to the first lead portion 31B and the second lead portion 31C exposed on the first side surface WS1. The fifth surface 40A5 is connected to the first lead portion 31B and the third lead portion 31D exposed on the second side surface WS2. In this way, the first lead portion 31B, the second lead portion 31C, and the third lead portion 31D are all connected to the same external electrode, the first external electrode 40A.

[0062] The fourth surface portion 40A4 and the fifth surface portion 40A5 have openings H through which the laminate 10 is exposed. The openings H are surrounded by the material that constitutes the external electrode 40. The openings H are recesses formed so as to be recessed from the surfaces of the fourth surface portion 40A4 and the fifth surface portion 40A5, and the surface of the laminate 10 is exposed at the bottom.

[0063] By forming such an opening H, connecting surfaces that connect the second surface portion 40A2 and the third surface portion 40A3 in the height direction are formed on both sides of the opening H in the longitudinal direction L of the laminate 10 on the fourth surface portion 40A4 and the fifth surface portion 40A5 as solder wetting-up portions.

[0064] 2, the fourth surface portion 40A4 has a first connecting surface F1 connecting the second surface portion 40A2 and the third surface portion 40A3 in the height direction on the center side of the opening H in the longitudinal direction L of the laminate 10. The fourth surface portion 40A4 also has a second connecting surface F2 connecting the second surface portion 40A2 and the third surface portion 40A3 in the height direction on the first end surface LS1 side of the opening H. The second connecting surface F2 is connected to the first surface portion 40A1.

[0065] 3, the fifth surface portion 40A5 has a third connecting surface F3 connecting the second surface portion 40A2 and the third surface portion 40A3 in the height direction, on the center side of the opening H in the longitudinal direction L of the laminate 10. The fifth surface portion 40A5 also has a fourth connecting surface F4 connecting the second surface portion 40A2 and the third surface portion 40A3 in the height direction, on the first end surface LS1 side of the opening H. The fourth connecting surface F4 is connected to the first surface portion 40A1.

[0066] The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B of this embodiment has a sixth surface portion 40B1 located on the second end face LS2, a seventh surface portion 40B2 located on a portion of the first main surface TS1, an eighth surface portion 40B3 located on a portion of the second main surface TS2, a ninth surface portion 40B4 located on a portion of the first side surface WS1, and a tenth surface portion 40B5 located on a portion of the second side surface WS2. It is preferable that the second external electrode 40B has at least one of a seventh surface portion 40B2 located on a portion of the first main surface TS1 and an eighth surface portion 40B3 located on a portion of the second main surface TS2, the first external electrode 40A, a sixth surface portion 40B1 located on the second end face LS2, a ninth surface portion 40B4 located on a portion of the first side surface WS1, and a tenth surface portion 40B5 located on a portion of the second side surface WS2.

[0067] The sixth surface portion 40B1 covers the entire second end face LS2 and is the portion connected to the second internal electrode layer 32. Either the seventh surface portion 40B2 or the eighth surface portion 40B3 is the portion connected to a land of the mounting board.

[0068] The ninth surface 40B4 is a portion connected to the fourth lead portion 32B and the fifth lead portion 32C exposed on the first side surface WS1. The tenth surface 40B5 is a portion connected to the fourth lead portion 32B and the sixth lead portion 32D exposed on the second side surface WS2. In this way, the fourth lead portion 32B, the fifth lead portion 32C, and the sixth lead portion 32D are all connected to the same external electrode, the second external electrode 40B.

[0069] The ninth and tenth surfaces 40B4, 40B5 have openings H through which the laminate 10 is exposed. The openings H are surrounded by the material that constitutes the external electrode 40. The openings H are recesses formed so as to be recessed from the surfaces of the ninth and tenth surfaces 40B4, 40B5, and the surface of the laminate 10 is exposed at the bottom.

[0070] By forming such an opening H, connecting surfaces that connect the seventh surface portion 40B2 and the eighth surface portion 40B3 in the height direction are formed on both sides of the opening H in the longitudinal direction L of the laminate 10 in the ninth surface portion 40B4 and the tenth surface portion 40B5, as solder wetting-up portions.

[0071] 2, the ninth surface portion 40B4 has a fifth connecting surface F5 connecting the seventh surface portion 40B2 and the eighth surface portion 40B3 in the height direction on the center side of the opening H in the longitudinal direction L of the laminate 10. The ninth surface portion 40B4 also has a sixth connecting surface F6 connecting the seventh surface portion 40B2 and the eighth surface portion 40B3 in the height direction on the second end surface LS2 side of the opening H. The sixth connecting surface F6 is connected to the sixth surface portion 40B1.

[0072] 3, the tenth surface 40B5 has a seventh connecting surface F7 connecting the seventh surface 40B2 and the eighth surface 40B3 in the height direction, on the center side of the opening H in the length direction L of the laminate 10. The tenth surface 40B5 also has an eighth connecting surface F8 connecting the seventh surface 40B2 and the eighth surface 40B3 in the height direction, on the second end surface LS2 side of the opening H. The eighth connecting surface F8 is connected to the sixth surface 40B1.

[0073] This allows the amount of solder to wet and rise appropriately on the first side surface WS1 and the second side surface WS2 of the laminate 10. Furthermore, because the solder wets and rises so as to surround the opening H, the solder can be divided into two parts that wet and rise, with the opening H as the boundary. Therefore, the points on the mounting surface of the multilayer ceramic capacitor 1 where stress is applied by the solder can be distributed to two points. This improves the self-alignment effect, stabilizing the mountability of the multilayer ceramic capacitor 1. As a result, tilting of the multilayer ceramic capacitor 1 can be prevented. Furthermore, rotation of the multilayer ceramic capacitor 1, which can lead to short-circuit defects, can be suppressed.

[0074] Preferably, the openings H provided in the fourth, fifth, ninth, and tenth surfaces 40A4, 40A5, 40B4, and 40B5 are formed to have approximately the same size. The shape of the openings H is not particularly limited, and is preferably rectangular, polygonal, circular, or elliptical.

[0075] The openings H formed in the fourth and fifth surfaces 40A4 and 40A5 are preferably positioned at the center of the fourth and fifth surfaces 40A4 and 40A5 in the height direction T. The openings H formed in the fourth and fifth surfaces 40A4 and 40A5 are preferably positioned at the center of the fourth and fifth surfaces 40A4 and 40A5 in the length direction L, or biased toward the first end face LS1 from the center of the fourth and fifth surfaces 40A4 and 40A5 in the length direction L. By positioning the openings H formed in the fourth and fifth surfaces 40A4 and 40A5 biased toward the first end face LS1, the areas of the first and third joining surfaces F1 and F3 as solder wetting portions can be secured.

[0076] The openings H formed in the ninth and tenth surfaces 40B4 and 40B5 are preferably positioned at the center of the ninth and tenth surfaces 40B4 and 40B5 in the height direction T. The openings H formed in the ninth and tenth surfaces 40B4 and 40B5 are preferably positioned at the center of the ninth and tenth surfaces 40B4 and 40B5 in the length direction L, or biased toward the second end face LS2 from the center of the ninth and tenth surfaces 40B4 and 40B5 in the length direction L. By positioning the openings H formed in the ninth and tenth surfaces 40B4 and 40B5 biased toward the second end face LS2, the areas of the fifth and seventh connecting surfaces F5 and F7 as solder wetting portions can be secured.

[0077] This allows the solder to separate into two at the opening H, making it easier to wet and rise. As a result, the points on the mounting surface of the multilayer ceramic capacitor 1 where stress is applied by the solder can be distributed to two points. This improves the self-alignment effect, stabilizing the mountability of the multilayer ceramic capacitor 1. As a result, tilting of the multilayer ceramic capacitor can be prevented. Furthermore, rotation of the multilayer ceramic capacitor 1, which can lead to short-circuit defects, can be suppressed.

[0078] The area of ​​the openings H formed in the fourth and fifth face portions 40A4, 40A5, and the ninth and tenth face portions 40B4, 40B5 is preferably 1% to 50% of the area of ​​the fourth and fifth face portions 40A4, 40A5, and the ninth and tenth face portions 40B4, 40B5, respectively. More preferably, the area ratio of the openings H is 3% to 20%. This provides a self-alignment effect, and more significantly prevents the multilayer ceramic capacitor 1 from tilting or rotating, which can lead to short-circuit defects.

[0079] The area ratio of the openings H described above is measured using an optical microscope. A method for measuring the area ratio of the openings H in the fourth surface portion 40A4 will be described below with reference to Fig. 2. Note that the following describes a measurement method when the region of the fourth surface portion 40A4 and the openings H are both substantially rectangular.

[0080] First, the field of view of the microscope is set to a magnification such that the first external electrode 40A located on the first side surface WS1 of the multilayer ceramic capacitor 1 is included within the field of view. Next, the contour of the opening H is identified, and the dimension d1 of the opening H in the length direction L and the dimension d2 of the opening H in the height direction T are measured. Then, the area A1 of the opening H is calculated using the formula A1 = d1 × d2. Next, the contour of the first external electrode 40A is identified, and the dimension D1 of the fourth surface portion 40A4 in the length direction L and the dimension D2 of the fourth surface portion 40A4 in the height direction T are measured. Then, the area A2 of the fourth surface portion 40A4 is calculated using the formula A2 = D1 × D2. Furthermore, the area ratio of the opening H located on the fourth surface portion 40A4 to the area of ​​the fourth surface portion 40A4 is calculated using the formula A1 ÷ A2.

[0081] The method for measuring the area ratio of the openings H located on the fourth surface 40A4 has been described above as a representative method for measuring the area ratio of the openings H, but the area ratios of the openings H located on the fifth surface 40A5, the ninth surface 40B4, and the tenth surface 40B5 can also be calculated using a similar measurement method. The area ratios of the openings H located on the fourth surface 40A4, the fifth surface 40A5, the ninth surface 40B4, and the tenth surface 40B5 are each calculated, and then the average value of the area ratios of the four openings H is calculated as the area ratio of the openings H in the multilayer ceramic capacitor 1.

[0082] In the multilayer ceramic capacitor 1 of this embodiment, the fourth surface portion 40A4 of the first external electrode 40A and the ninth surface portion 40B4 of the second external electrode 40B arranged in the longitudinal direction L, and the fifth surface portion 40A5 of the first external electrode 40A and the tenth surface portion 40B5 of the second external electrode 40B arranged in the longitudinal direction L, each have a convex portion K that protrudes in the longitudinal direction L from the center side of the longitudinal direction L that faces each other.

[0083] 2, the fourth surface portion 40A4 and the ninth surface portion 40B4 arranged on the first side surface WS1 of the laminate 10 each have a rectangular protrusion K. The protrusion K of the fourth surface portion 40A4 protrudes in the length direction L from a side K4 on the longitudinal center side that faces the ninth surface portion 40B4 toward the ninth surface portion 40B4. The protrusion K of the ninth surface portion 40B4 protrudes in the length direction L from a side K9 on the longitudinal center side that faces the fourth surface portion 40A4 toward the fourth surface portion 40A4.

[0084] 9A, the convex portion K of the fourth surface portion 40A4 covers each of the protruding portions 31C1 of the second lead portions 31C located in the center in the height direction T among the second lead portions 31C exposed on the first side surface WS1 of the laminate 10. The convex portion K of the fourth surface portion 40A4 is connected to the protruding portions 31C1. The convex portion K of the ninth surface portion 40B4 covers each of the protruding portions 32C1 of the fifth lead portions 32C located in the center in the height direction T among the fifth lead portions 32C exposed on the first side surface WS1 of the laminate 10. The convex portion K of the ninth surface portion 40B4 is connected to the protruding portions 32C1.

[0085] 3, the fifth and tenth surface portions 40A5, 40B5 arranged on the second side surface WS2 of the laminate 10 each have a rectangular protrusion K. The protrusion K of the fifth surface portion 40A5 protrudes in the length direction L from a side K5 on the longitudinal center side facing the tenth surface portion 40B5 toward the tenth surface portion 40B5. The protrusion K of the tenth surface portion 40B5 protrudes in the length direction L from a side K10 on the longitudinal center side facing the fifth surface portion 40A5 toward the fifth surface portion 40A5.

[0086] As shown in FIG. 9B , the convex portion K of the fifth surface portion 40A5 covers each of the protruding portions 31D1 of the second lead portions 31D located in the center in the height direction T among the third lead portions 31D exposed on the second side surface WS2 of the laminate 10. The convex portion K of the fifth surface portion 40A5 is connected to the protruding portions 31D1. The convex portion K of the tenth surface portion 40B5 covers each of the protruding portions 32D1 of the sixth lead portions 32D located in the center in the height direction T among the sixth lead portions 32D exposed on the second side surface WS2 of the laminate 10. The convex portion K of the tenth surface portion 40B5 is connected to the protruding portions 32D1.

[0087] As described above, in the multilayer ceramic capacitor 1 of this embodiment, the fourth surface portion 40A4 and the ninth surface portion 40B4 arranged on the first side surface WS1 and the fifth surface portion 40A5 and the tenth surface portion 40B5 arranged on the second side surface WS2 of each external electrode each have a protrusion K. As a result, if the amount of solder used is greater than necessary when soldering each external electrode to a substrate, the excess solder can be made to flow to the protrusion K, thereby adjusting the amount of solder between the external electrode and the substrate to an appropriate amount for mounting. In other words, the protrusion K serves as a sort of escape route for the solder, trapping the excess solder. As a result, the mountability of the multilayer ceramic capacitor 1 can be stabilized.

[0088] The convex portion K of the fourth surface portion 40A4 is preferably disposed in the center of the height direction T of the fourth surface portion 40A4. The convex portion K of the fifth surface portion 40A5 is preferably disposed in the center of the height direction T of the fifth surface portion 40A5. The convex portion K of the ninth surface portion 40B4 is preferably disposed in the center of the height direction T of the ninth surface portion 40B4. The convex portion K of the tenth surface portion 40B5 is preferably disposed in the center of the height direction T of the tenth surface portion 40B5. This makes it possible to make the above-mentioned effects more pronounced.

[0089] The dimension of each protrusion K in the height direction T is preferably 10% or more and 90% or less of the dimension in the height direction T. This makes it possible to make the above-mentioned effects more pronounced.

[0090] The dimension of each protrusion K in the length direction L is preferably 2% to 18% of the dimension in the length direction L. This makes it possible to make the above-mentioned effects more pronounced.

[0091] The dimension in the height direction T of each of the protrusions K arranged on the fourth surface 40A4 and the fifth surface 40A5 is measured with a microscope at a position halfway along the length direction L of each of the protrusions K arranged on the fourth surface 40A4 and the fifth surface 40A5 when observed from the first side surface WS1 of the laminate 10. Similarly, the dimension in the height direction T of each of the protrusions K arranged on the ninth surface 40B4 and the tenth surface 40B5 is measured with a microscope at a position halfway along the length direction L of each of the protrusions K arranged on the ninth surface 40B4 and the tenth surface 40B5 when observed from the second side surface WS2 of the laminate 10.

[0092] The dimension in the length direction L of each of the protrusions K arranged on the fourth surface 40A4 and the fifth surface 40A5 is measured with a microscope at a position halfway in the height direction T of each of the protrusions K arranged on the fourth surface 40A4 and the fifth surface 40A5 when observed from the first side surface WS1 of the laminate 10. Similarly, the dimension in the length direction L of each of the protrusions K arranged on the ninth surface 40B4 and the tenth surface 40B5 is measured with a microscope at a position halfway in the height direction T of each of the protrusions K arranged on the ninth surface 40B4 and the tenth surface 40B5 when observed from the second side surface WS2 of the laminate 10.

[0093] The shape of each protrusion K is not limited to a rectangular shape, but may be, for example, a polygonal shape, a semicircular arc shape, a semi-elliptical shape, or the like.

[0094] 10A, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The first base electrode layer 50A is disposed on the surface of the laminate 10. The first plating layer 60A is disposed so as to cover the first base electrode layer 50A.

[0095] 10B, the second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B. The second base electrode layer 50B is disposed on the surface of the laminate 10. The second plating layer 60B is disposed so as to cover the second base electrode layer 50B.

[0096] The first base electrode layer 50A and the second base electrode layer 50B include at least one selected from a baked layer, a thin film layer, and the like.

[0097] In this embodiment, the first base electrode layer 50A and the second base electrode layer 50B are thin film layers, which are layers on which metal particles are deposited.

[0098] When the first base electrode layer 50A and the second base electrode layer 50B are formed as thin film layers, they are preferably formed by a thin film formation method such as sputtering or vapor deposition. Here, a sputtered electrode formed by sputtering will be described.

[0099] In this embodiment, the first base electrode layer 50A is composed of a first thin film layer 51A formed by a sputtered electrode. The second base electrode layer 50B is composed of a second thin film layer 51B formed by a sputtered electrode. When forming the base electrode layer using a sputtered electrode, it is preferable to form the sputtered electrode directly on the first main surface TS1 and the second main surface TS2 of the laminate 10.

[0100] 6 and 10A, the first thin film layer 51A formed of a sputtered electrode is disposed on a portion of the first main surface TS1 on the first end face LS1 side and on a portion of the second main surface TS2 on the first end face LS1 side. Specifically, the first thin film layer 51A is preferably disposed on the first main surface TS1 in a portion covered by the first external electrode 40A shown in FIG. 4. The first thin film layer 51A is preferably disposed on the second main surface TS2 in a portion covered by the first external electrode 40A shown in FIG. 5.

[0101] 9A, the first thin film layer 51A is preferably disposed on a portion of the first main surface TS1 and continuing from that portion to slightly wrap around a portion of the first side surface WS1. The first thin film layer 51A is preferably disposed on a portion of the second main surface TS2 and continuing from that portion to slightly wrap around a portion of the first side surface WS1.

[0102] 9B, similarly to the first side surface WS1 side, also on the second side surface WS2 side, the first thin film layer 51A is preferably disposed on a part of the first main surface TS1 and continuously from a part of the first main surface TS1 to slightly wrap around a part of the second side surface WS2. The first thin film layer 51A is preferably disposed on a part of the second main surface TS2 and continuously from a part of the second main surface TS2 to slightly wrap around a part of the second side surface WS2.

[0103] For example, when the ridges of the laminate 10 are chamfered, such as rounded, the first thin film layer 51A is preferably disposed on a portion of the first main surface TS1 on the first end face LS1 side, and on the chamfered portions adjacent to the first side face WS1 and the second side face WS2. The first thin film layer 51A is preferably disposed on a portion of the second main surface TS2 on the first end face LS1 side, and on the chamfered portions adjacent to the first side face WS1 and the second side face WS2. This facilitates the formation of the thin film layer by a method such as sputtering.

[0104] By the above method, when forming a plating layer, it is possible to control the distance between the first thin film layer 51A arranged on a part of the first side surface WS1 and a part of the second side surface WS2 and the internal electrode layer 30 exposed on the first side surface WS1 and the second side surface WS2. Therefore, it becomes easy to deposit a plating layer also on the surface of the laminate 10 between the first thin film layer 51A arranged on a part of the first side surface WS1 and a part of the second side surface WS2 and the internal electrode layer 30 exposed on the first side surface WS1 and the second side surface WS2.

[0105] 6 and 10B, the second thin film layer 51B formed of a sputtered electrode is disposed on a portion of the first main surface TS1 facing the second end face LS2 and on a portion of the second main surface TS2 facing the second end face LS2. Specifically, the second thin film layer 51B is preferably disposed on the first main surface TS1 in a portion covered by the second external electrode 40B shown in FIG. 4. The second thin film layer 51B is preferably disposed on the second main surface TS2 in a portion covered by the second external electrode 40B shown in FIG. 5.

[0106] 9A, the second thin film layer 51B is preferably disposed on a portion of the first main surface TS1 and a portion of the first main surface TS1 that continues from the portion of the first main surface TS1 and slightly wraps around a portion of the first side surface WS1. The second thin film layer 51B is preferably disposed on a portion of the second main surface TS2 and a portion of the second main surface TS2 that continues from the portion of the second main surface TS2 and slightly wraps around a portion of the first side surface WS1.

[0107] 9B, similarly to the first side surface WS1 side, also on the second side surface WS2 side, second thin film layer 51B is preferably disposed on a part of first main surface TS1 and continuously from a part of first main surface TS1 to slightly wrap around a part of second side surface WS2. Also, second thin film layer 51B is preferably disposed on a part of second main surface TS2 and continuously from a part of second main surface TS2 to slightly wrap around a part of second side surface WS2.

[0108] For example, when the ridges of the laminate 10 are chamfered, such as rounded, the second thin film layer 51B is preferably disposed on a portion of the first main surface TS1 on the second end face LS2 side, and on the chamfered portions on the first side face WS1 side and the second side face WS2 side that are continuous with that portion. The second thin film layer 51B is preferably disposed on a portion of the second main surface TS2 on the second end face LS2 side, and on the chamfered portions on the first side face WS1 side and the second side face WS2 side that are continuous with that portion. This facilitates the formation of the thin film layer by a method such as sputtering.

[0109] The longitudinal center sides of the second and third lead portions 31C and 31D located at the center in the height direction T protrude more toward the center in the length direction than the longitudinal center-side end of the first thin film layer 51A located on the first main surface TS1 and the longitudinal center-side end of the first thin film layer 51A located on the second main surface TS2. Similarly, the longitudinal center sides of the fifth and sixth lead portions 32C and 32D located at the center in the height direction T protrude more toward the center in the length direction than the longitudinal center-side end of the second thin film layer 51B located on the first main surface TS1 and the longitudinal center-side end of the second thin film layer 51B located on the second main surface TS2.

[0110] By the above method, when forming a plating layer, it is possible to control the distance between the second thin film layer 51B arranged on a part of the first side surface WS1 and a part of the second side surface WS2 and the internal electrode layer 30 exposed on the first side surface WS1 and the second side surface WS2. Therefore, it becomes easy to deposit a plating layer also on the surface of the laminate 10 between the second thin film layer 51B arranged on a part of the first side surface WS1 and a part of the second side surface WS2 and the internal electrode layer 30 exposed on the first side surface WS1 and the second side surface WS2.

[0111] The thin film layer formed by the sputtered electrode preferably contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. This increases the adhesive strength of the external electrode 40 to the laminate 10. The thin film layer may be a single layer or may be formed of multiple layers. For example, it may be formed of a two-layer structure consisting of a layer of Ni-Cr alloy and a layer of Ni-Cu alloy.

[0112] The thickness of the sputtered electrode in the stacking direction connecting the first main surface TS1 and the second main surface TS2 is preferably 50 nm or more and 400 nm or less, and more preferably 50 nm or more and 130 nm or less.

[0113] When forming a base electrode layer by forming sputtered electrodes directly on the first main surface TS1 and the second main surface TS2 of the laminate 10, it is preferable to form a baked base electrode layer on the first end face LS1 and the second end face LS2, or to form a plating layer (described later) directly without forming a base electrode layer. In this embodiment, a plating layer (described later) is formed directly on the first end face LS1 and the second end face LS2 without forming a base electrode layer.

[0114] As will be described later in a modified example, the first base electrode layer 50A and the second base electrode layer 50B may be baked layers. The baked layer preferably contains a metal component and either a glass component or a ceramic component, or both. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, an Ag-Pd alloy, and Au. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, and Li. The ceramic component may be the same ceramic material as that of the dielectric layer 20, or a different ceramic material. The ceramic component may include at least one selected from, for example, BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, and CaZrO3.

[0115] The baked layer is formed by, for example, applying a conductive paste containing glass and metal to the laminate 10 and baking it. The baked layer may be formed by simultaneously firing a laminated chip having internal electrode layers and a dielectric layer with a conductive paste applied to the laminated chip, or by simultaneously firing a laminated chip having internal electrode layers and a dielectric layer to obtain the laminate 10 and then applying a conductive paste to the laminate 10 and baking it. When simultaneously firing a laminated chip having internal electrode layers and a dielectric layer with a conductive paste applied to the laminated chip, the baked layer is preferably formed by baking a layer containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may be formed in multiple layers.

[0116] Alternatively, a configuration may be adopted in which a first plating layer 60A and a second plating layer 60B, which will be described later, are disposed directly on the laminate 10 without providing the first base electrode layer 50A and the second base electrode layer 50B.

[0117] The first plating layer 60A is disposed so as to cover the first base electrode layer 50A.

[0118] The second plating layer 60B is disposed so as to cover the second base electrode layer 50B.

[0119] The first plating layer 60A and the second plating layer 60B may contain, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed of multiple layers.

[0120] When the base electrode layer is formed as a thin film layer, the plating layer preferably has a three-layer structure consisting of a Cu plating layer as a lower plating layer, a Ni plating layer as a middle plating layer, and a Sn plating layer as a upper plating layer. That is, the first plating layer 60A preferably has a first Cu plating layer 61A, a first Ni plating layer 62A, and a first Sn plating layer 63A. The second plating layer 60B preferably has a second Cu plating layer 61B, a second Ni plating layer 62B, and a second Sn plating layer 63B. However, the first plating layer 60A and the second plating layer 60B are not limited to a three-layer structure and may have other layer configurations.

[0121] The first Cu plating layer 61A is disposed so as to cover the first end face LS1 of the laminate 10 and the first thin film layer 51A serving as the first base electrode layer 50A disposed on the first main surface TS1 and the second main surface TS2 of the laminate 10. In this embodiment, the first Cu plating layer 61A is also disposed so as to cover the exposed portions of the internal electrode layer 30 on the first side surface WS1 and the second side surface WS2 of the laminate 10. Since the gaps between the first thin film layer 51A and the internal electrode layer 30 exposed on the surface of the laminate 10 and the gaps between the multiple internal electrode layers 30 exposed on the surface of the laminate 10 are narrow, the plating layer is also deposited in these gap regions. Therefore, the openings H described above are formed in the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A.

[0122] The first Ni plating layer 62A is disposed so as to cover the first Cu plating layer 61 A. The first Sn plating layer 63A is disposed so as to cover the first Ni plating layer 62 A. In this embodiment, the first plating layer 60A is directly electrically connected to the first internal electrode layer 31.

[0123] The second Cu plating layer 61B is arranged to cover the second end face LS2 of the laminate 10 and the second thin film layer 51B serving as the second base electrode layer 50B arranged on the first and second main surfaces TS1 and TS2 of the laminate 10. In this embodiment, the second Cu plating layer 61B is also arranged to cover the exposed portions of the internal electrode layer 30 on the first and second side surfaces WS1 and WS2 of the laminate 10. Since the gaps between the second thin film layer 51B and the internal electrode layer 30 exposed on the surface of the laminate 10 and the gaps between the multiple internal electrode layers 30 exposed on the surface of the laminate 10 are narrow, the plating layer is also deposited in these gap regions. Therefore, the above-described openings H are formed in the ninth surface portion 40B4 and the tenth surface portion 40B5 of the second external electrode 40B.

[0124] The second Ni plating layer 62B is disposed so as to cover the second Cu plating layer 61B. The second Sn plating layer 63B is disposed so as to cover the second Ni plating layer 62B. In this embodiment, the second plating layer 60B is directly electrically connected to the second internal electrode layer 32.

[0125] By providing a plating layer consisting of a Cu plating layer and a Ni plating layer so as to cover the base electrode layer, the base electrode layer is prevented from being eroded by solder when mounting the multilayer ceramic capacitor 1. Furthermore, by providing an Sn plating layer on the surface of the Ni plating layer, the wettability of the solder when mounting the multilayer ceramic capacitor 1 is improved. This allows the multilayer ceramic capacitor 1 to be easily mounted.

[0126] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less. That is, the average thickness of each of the first Cu plating layer 61A, the first Ni plating layer 62A, the first Sn plating layer 63A, the second Cu plating layer 61B, the second Ni plating layer 62B, and the second Sn plating layer 63B is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of each of the first Cu plating layer 61A and the second Cu plating layer 61B is more preferably 5 μm or more and 8 μm or less. Furthermore, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is more preferably 2 μm or more and 4 μm or less.

[0127] The lengthwise dimension connecting the first end face LS1 and the second end face LS2 of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as L, and the L dimension is preferably 0.1 mm or more and 0.8 mm or less. The widthwise dimension connecting the first side face WS1 and the second side face WS2 of the multilayer ceramic capacitor 1 is defined as W, and the W dimension is preferably 0.2 mm or more and 1.6 mm or less. The heightwise dimension connecting the first main face TS1 and the second main face TS2 of the multilayer ceramic capacitor 1 is defined as T, and the T dimension is preferably 0.05 mm or more and 0.2 mm or less. The lengthwise dimension L of the multilayer ceramic capacitor 1 of this embodiment is smaller than the widthwise dimension W of the multilayer ceramic capacitor 1. In this embodiment, the heightwise direction connecting the first main face TS1 and the second main face TS2 of the multilayer ceramic capacitor 1 is the stacking direction of the dielectric layers 20 and the internal electrode layers 30.

[0128] As described above, the multilayer ceramic capacitor 1 of this embodiment is an LW-reversed multilayer ceramic capacitor, and openings H exposing the surface of the laminate 10 are formed on the fourth surface 40A4 and the fifth surface 40A5 of the first external electrode 40A and the ninth surface 40B4 and the tenth surface 40B5 of the second external electrode 40B. This prevents deterioration of the self-alignment effect and enables stable mounting. The self-alignment effect is an effect in which, during soldering, a force that reduces the surface area of ​​molten solder, i.e., surface tension, acts on the molten solder, causing the electronic element to move and be positioned. This self-alignment effect prevents misalignment during mounting.

[0129] Furthermore, the multilayer ceramic capacitor 1 of this embodiment is an LW-reversed type multilayer ceramic capacitor, and the fourth and fifth surface portions 40A4 and 40A5 of the first external electrode 40A and the ninth and tenth surface portions 40B4 and 40B5 of the second external electrode 40B have protrusions K that protrude toward the center in the length direction L. This allows the amount of solder to flow to the protrusions K, even if more solder than necessary is used when soldering each external electrode to the land of the substrate for mounting. This allows the amount of solder between the first and second external electrodes 40A and 40B and the land to be adjusted to an amount appropriate for mounting. As a result, the mountability of the multilayer ceramic capacitor 1 can be stabilized.

[0130] Modified examples of the layer structure of the external electrodes 40 of the multilayer ceramic capacitor 1 of this embodiment will be described below. In the following description, the same components as those in the above embodiment will be denoted by the same reference numerals, and detailed description will be omitted. Figures 11A and 11B are cross-sectional views showing modified examples of the layer structure of the external electrodes 40 of the multilayer ceramic capacitor 1 of this embodiment, and correspond to Figures 10A and 10B.

[0131] In this modification, the configuration of the external electrode 40 is different from that of the above embodiment.

[0132] The first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A. The first base electrode layer 50A of this modification is composed of a first baked layer 52A. The first plating layer 60A of this modification has a first Ni plating layer 62A and a first Sn plating layer 63A.

[0133] The second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B. The second base electrode layer 50B of this modification is composed of a second baked layer 52B. The second plating layer 60B of this modification has a second Ni plating layer 62B and a second Sn plating layer 63B.

[0134] In this modification, the first base electrode layer 50A has, for example, a first surface portion located on the first end face LS1, a second surface portion located on a portion of the first main surface TS1, a third surface portion located on a portion of the second main surface TS2, a fourth surface portion located on a portion of the first side surface WS1, and a fifth surface portion located on a portion of the second side surface WS2, similar to the above-described first external electrode 40A. Note that openings corresponding to the aforementioned opening H are formed in the fourth and fifth surfaces of the first base electrode layer 50A. Note that in this modification, the first base electrode layer 50A is connected to the first internal electrode layer 31.

[0135] The first Ni plating layer 62A is disposed so as to cover the first base electrode layer 50A. The first Sn plating layer 63A is disposed so as to cover the first Ni plating layer 62A.

[0136] In this modification, the second base electrode layer 50B has, for example, a sixth surface portion located on the second end face LS2, a seventh surface portion located on a portion of the first main surface TS1, an eighth surface portion located on a portion of the second main surface TS2, a ninth surface portion located on a portion of the first side surface WS1, and a tenth surface portion located on a portion of the second side surface WS2, similar to the above-described second external electrode 40B. Note that openings corresponding to the aforementioned opening H are formed in the ninth and tenth surfaces of the second base electrode layer 50B. Note that in this modification, the second base electrode layer 50B is connected to the second internal electrode layer 32.

[0137] The second Ni plating layer 62B is disposed so as to cover the second base electrode layer 50B. The second Sn plating layer 63B is disposed so as to cover the second Ni plating layer 62B.

[0138] The first baking layer 52A constituting the first base electrode layer 50A and the second baking layer 52B constituting the second base electrode layer 50B may be formed by applying a conductive paste containing glass and metal to the laminate and baking it, for example. When simultaneously baking the unfired laminated chip and the conductive paste applied to the laminated chip, it is preferable to form the baking layer by baking a layer containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the ceramic material to be added.

[0139] When the base electrode layer is formed as a baked layer, the first plating layer 60A and the second plating layer 60B preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer. In this case, the Ni plating layer prevents the base electrode layer from being eroded by solder when mounting the multilayer ceramic capacitor 1. Furthermore, the Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. This makes it easier to mount the multilayer ceramic capacitor 1.

[0140] The first plating layer 60A and the second plating layer 60B are not limited to a two-layer structure, but may be formed as a three-layer structure including Cu plating, as in the above embodiment, or may have other layer configurations.

[0141] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less. That is, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is more preferably 2 μm or more and 4 μm or less.

[0142] Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described.

[0143] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The conductive paste for the dielectric sheet and the internal electrode contains a binder and a solvent. The binder and solvent may be known. The paste made of the conductive material is, for example, a metal powder to which an organic binder and an organic solvent are added.

[0144] A conductive paste for the internal electrode layer 30 is printed on a dielectric sheet by, for example, screen printing or gravure printing using a printing plate patterned to the shape of the internal electrode layer 30 of this embodiment. This prepares a dielectric sheet on which the pattern of the first internal electrode layer 31 is formed and a dielectric sheet on which the pattern of the second internal electrode layer 32 is formed. Here, the size of the opening H can be adjusted by controlling the distance between the first lead portion 31B and the second lead portion 31C and the third lead portion 31D, and the distance between the fourth lead portion 32B and the fifth lead portion 32C and the sixth lead portion 32D.

[0145] The conductive paste for the first internal electrode layer 31 is printed so that the dimensions in the length direction L of the plurality of second lead portions 31C and third lead portions 31D located in the central portion in the height direction T are longer than the dimensions in the length direction L of the plurality of second lead portions 31C and third lead portions 31D located in a portion other than the central portion in the height direction T, thereby forming the protrusions 31C1 and 31D1. This makes it possible to form the convex portion K when forming the first external electrode 40A. Furthermore, the conductive paste for the second internal electrode layer 32 is printed so that the dimensions in the length direction L of the plurality of fifth lead portions 32C and sixth lead portions 32D located in the central portion in the height direction T are longer than the dimensions in the length direction L of the plurality of second lead portions 32C and sixth lead portions 32D located in a portion other than the central portion in the height direction T, thereby forming the protrusions 32C1 and 32D1. This makes it possible to form the convex portion K when forming the second external electrode 40B.

[0146] In addition, by adjusting the dimensions in the length direction L and the positions in the height direction T of the above-mentioned protrusions 31C1, 31D1, 32C1 and 32D1, which are the parts corresponding to the protrusion K at this time, the dimensions in the length direction L and the positions in the height direction T of the protrusions K can be controlled.

[0147] A predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed are stacked to form a portion that will become the first main surface-side outer layer portion 12 on the first main surface TS1 side. Dielectric sheets on which the pattern of the first internal electrode layer 31 is printed and dielectric sheets on which the pattern of the second internal electrode layer 32 is printed are stacked alternately in sequence on top of that to form a portion that will become the internal layer portion 11. A predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed are stacked on top of this portion that will become the second main surface-side outer layer portion 13 on the second main surface TS2 side. In this way, a laminated sheet is produced.

[0148] The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0149] The laminated block is cut to a predetermined size to obtain laminated chips, and at this time, corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0150] The laminated chip is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric layers 20 and the internal electrode layers 30, but is preferably 900°C or higher and 1400°C or lower.

[0151] In this embodiment, the base electrode layer is formed of a thin film layer. When forming the base electrode layer of a thin film layer, the thin film layer is formed by masking or the like in the portion of the laminate 10 where the external electrode is to be formed. The thin film layer is formed by a thin film formation method such as sputtering or vapor deposition. In this embodiment, a sputtered electrode is formed as a thin film layer by sputtering.

[0152] 12 to 14 are diagrams showing intermediate states in the manufacturing process of the multilayer ceramic capacitor of this embodiment, showing a state after thin film layers have been arranged on the laminate 10 but before plating layers have been arranged. FIG. 12 is a diagram showing a state in which a first thin film layer 51A and a second thin film layer 51B have been arranged as thin film layers on the laminate 10, and is a diagram corresponding to the LT cross section of FIG. 6. FIG. 13 is a diagram showing a state in which a first thin film layer 51A has been arranged as a thin film layer on the laminate 10, and is a diagram corresponding to the WT cross section of FIG. 7. FIG. 14 is a diagram showing a state in which the first thin film layer 51A and the second thin film layer 51B have been arranged on the laminate 10, and is a diagram showing the surface of the first side surface WS1 of the laminate 10, corresponding to FIG. 9A.

[0153] First thin film layer 51A formed by a sputtered electrode is disposed on a portion of first main surface TS1 facing first end face LS1 and a portion of second main surface TS2 facing first end face LS1. Second thin film layer 51B formed by a sputtered electrode is disposed on a portion of first main surface TS1 facing second end face LS2 and a portion of second main surface TS2 facing second end face LS2.

[0154] In this embodiment, the thin film layer formed by the sputtered electrode is disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, and is disposed continuously from the portion of the first main surface TS1 and the portion of the second main surface TS2 to a portion of the first side surface WS1 and a portion of the second side surface WS2. This makes it possible to control the distance between the thin film layer disposed on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode film exposed on the first side surface WS1 and the second side surface WS2. This makes it possible to deposit a plating layer on the surface of the laminate 10 between the thin film layer disposed on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer exposed on the first side surface WS1 and the second side surface WS2.

[0155] Thereafter, plating layers are formed on the surfaces of the base electrode layer made of the thin film layer and the laminate. In this embodiment, three plating layers are formed, namely, a Cu plating layer, a Ni plating layer, and a Sn plating layer.

[0156] The plating layer is formed by electrolytic plating, preferably barrel plating.

[0157] Here, when the thin film layer is formed so as to extend over a portion of the first side surface WS1 and a portion of the second side surface WS2, it is possible to control the distance between the thin film layer and the internal electrode layer exposed on the first side surface WS1 and the second side surface WS2 of the laminate 10. This makes it easy to deposit a plating layer also on the surface of the laminate 10 between the thin film layer disposed on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer exposed on the first side surface WS1 and the second side surface WS2.

[0158] The plating layer is also disposed so as to cover the exposed portions of the internal electrode layers on the first side surface WS1 and the second side surface WS2 of the laminate 10. At this time, since the gaps between the thin film layers and the internal electrode layers exposed on the surface of the laminate 10 and the gaps between the multiple internal electrode layers exposed on the surface of the laminate 10 are narrow, the plating layer is also deposited in these gap regions. As a result, the plating layer is formed in the portions excluding the opening H in this embodiment.

[0159] In addition, for example, when the area of ​​the opening H is small and it is difficult to control the formation of the plating layer, the plating layer may be formed by masking the area where the opening is to be provided. This makes it easier to form the opening H.

[0160] When the base electrode layer is formed as a baked layer, a conductive paste to form the first base electrode layer is applied to a first surface portion located on the first end face LS1 of the laminate 10, a second surface portion located on a portion of the first main surface TS1, a third surface portion located on a portion of the second main surface TS2, a fourth surface portion located on a portion of the first side surface WS1, and a fifth surface portion located on a portion of the second side surface WS2 on the first end face LS1 side of the laminate 10. Furthermore, a conductive paste to form the second base electrode layer is applied to a sixth surface portion located on the second end face LS2 of the laminate 10, a seventh surface portion located on a portion of the first main surface TS1, an eighth surface portion located on a portion of the second main surface TS2, a ninth surface portion located on a portion of the first side surface WS1, and a tenth surface portion located on a portion of the second side surface WS2 on the second end face LS2 side of the laminate 10.

[0161] Note that areas where the base electrode layer is not to be formed, such as areas that will become openings H, are masked in advance. After masking, a conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping or screen printing. A baking process is then performed to form the base electrode layer. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0162] When the unfired laminated chip and the conductive paste applied to the laminated chip are simultaneously fired, the fired layer is preferably formed by firing a material containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as that of the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the unfired laminated chip, and the laminated chip and the conductive paste applied to the laminated chip are simultaneously fired to form the laminate 10 with the fired layer.

[0163] Thereafter, a plating layer is formed on the surface of the base electrode layer made of a baked layer and the laminate 10. When the base electrode layer is formed of a baked layer, for example, two plating layers, a Ni plating layer and a Sn plating layer, are formed as the plating layer. The plating layer is formed by an electrolytic plating method. As the plating method, barrel plating is preferably used.

[0164] Note that, for example, when the area of ​​the openings H is small and it is difficult to control the formation of the plating layer, the plating layer may be formed by masking the areas where the openings H are to be provided. This makes it easier to form the openings H.

[0165] Through these manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0166] The configuration of the external electrodes 40 is not limited to the above configuration. Modified examples of the arrangement positions of the external electrodes 40 of the multilayer ceramic capacitor 1 of this embodiment will be described below. In the following description, the same components as those in the above embodiment will be given the same reference numerals, and detailed description will be omitted. Fig. 15 is a cross-sectional view showing a modified example of the arrangement positions of the external electrodes 40 of the multilayer ceramic capacitor 1 of this embodiment, and is a view corresponding to Fig. 1.

[0167] This modification differs from the above embodiment in the arrangement positions of the external electrodes 40. In this modification, the first external electrode 40A and the second external electrode 40B are arranged on only one of the first main surface TS1 or the second main surface TS2.

[0168] For example, the first external electrode 40A of this modification has a first surface 40A1 located on the first end face LS1, a third surface 40A3 located on a portion of the second main surface TS2, a fourth surface 40A4 located on a portion of the first side surface WS1, and a fifth surface 40A5 located on a portion of the second side surface WS2. In other words, the first external electrode 40A of this modification is not formed on the first main surface TS1.

[0169] For example, the second external electrode 40B of this modification has a sixth surface 40B1 located on the second end face LS2, an eighth surface 40B3 located on a portion of the second main surface TS2, a ninth surface 40B4 located on a portion of the first side surface WS1, and a tenth surface 40B5 located on a portion of the second side surface WS2. In other words, the second external electrode 40B of this modification is not formed on the first main surface TS1.

[0170] In this modified example, the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A and the ninth surface portion 40B4 and the tenth surface portion 40B5 of the second external electrode 40B have openings H through which the surface of the laminate 10 is exposed, as in the above embodiment.

[0171] This configuration also suppresses deterioration of the self-alignment effect and enables stable mounting. Furthermore, by not arranging the first external electrode 40A and the second external electrode 40B on either the first main surface TS1 or the second main surface TS2, the dimension of the multilayer ceramic capacitor 1 in the height direction T can be reduced, thereby further reducing the height of the multilayer ceramic capacitor 1. Furthermore, by not arranging the first external electrode 40A and the second external electrode 40B on either the first main surface TS1 or the second main surface TS2, the height dimension of the multilayer body 10 can be secured by the thickness of the external electrodes 40. This makes it possible to increase the volume of the effective layer portion of the multilayer body 10, thereby enabling the multilayer ceramic capacitor 1 to have a higher capacitance.

[0172] The multilayer ceramic capacitor 1 of this embodiment provides the following advantages.

[0173] (1) The multilayer ceramic capacitor 1 of this embodiment includes a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20, and includes a laminate 10 having a first main surface TS1 and a second main surface TS2 that face each other in a height direction, a first end surface LS1 and a second end surface LS2 that face each other in a length direction perpendicular to the height direction, and a first side surface WS1 and a second side surface WS2 that face each other in a width direction perpendicular to the height direction and the length direction; and a first side surface WS1 located on the first end surface LS1. a first external electrode 40A having a sixth surface 40B1 located on the second end face LS2, a seventh surface 40B2 located on a portion of the first main surface TS1, and a fifth surface 40A5 located on a portion of the second main surface TS2; a sixth surface 40B1 located on the second end face LS2; a seventh surface 40B2 located on a portion of the first main surface TS1; and a third surface 40A3 located on a portion of the second main surface TS2. a ninth surface portion 40B4 located on a portion of the first side surface WS1, and a tenth surface portion 40B5 located on a portion of the second side surface WS2, wherein the length in the longitudinal direction connecting the first end surface LS1 and the second end surface LS2 of the multilayer body 10 is l, the length in the width direction connecting the first side surface WS1 and the second side surface WS2 is w, and the length in the width direction connecting the first main surface TS1 and the second main surface TS When the length in the height direction connecting 2 is defined as t, the dimensional relationship is w>l>t, and the fourth and fifth surface portions 40A4 and 40A5 and the ninth and tenth surface portions 40B4 and 40B5 have openings H through which the surface of the laminate 10 is exposed, and the fourth and ninth surface portions 40A4 and 40B4 arranged in the length direction L and the fifth and tenth surface portions 40A5 and 40B5 arranged in the length direction L each have protrusions K that protrude in the length direction L from the opposing center sides in the length direction. This makes it possible to provide an LW-reversed multilayer ceramic capacitor that suppresses deterioration of the self-alignment effect and enables stable mounting.

[0174] (2) In the multilayer ceramic capacitor 1 of this embodiment, the protrusions K are disposed at the center of the fourth surface portion 40A4, the fifth surface portion 40A5, and the ninth surface portion 40B4, and the tenth surface portion 40B5 in the height direction T. This makes the above-described effect more pronounced.

[0175] (3) In the multilayer ceramic capacitor 1 of this embodiment, the dimension of the protrusion K in the height direction T is 10% or more and 90% or less of the dimension in the height direction T. This makes the above-mentioned effect more pronounced.

[0176] (4) In the multilayer ceramic capacitor 1 of this embodiment, the dimension of the protrusion K in the length direction L is 2% to 18% of the dimension in the length direction L. This makes the above-mentioned effect more pronounced. (5) In the multilayer ceramic capacitor 1 of this embodiment, the internal electrode layer 30 has a first internal electrode layer 31 and a second internal electrode layer 32, and the first internal electrode layer 31 has a first opposing electrode portion 31A located inside the laminate 10, a first lead portion 31B connected to the first opposing electrode portion 31A and exposed on the first end face LS1, a part of the first side face WS1, and a part of the second side face WS2, and a part of the first lead portion 31B led out to the first side face WS1 with a gap therebetween. The second internal electrode layer 32 has a second lead portion 31C connected to the first counter electrode portion 31A and exposed on a part of the first side surface WS1, and a third lead portion 31D connected to the first counter electrode portion 31A and exposed on a part of the second side surface WS2, with a gap between the part of the first lead portion 31B that is led to the second side surface WS2 of the first lead portion 31B. The second internal electrode layer 32 has a second counter electrode portion 32A located inside the laminate 10, and a third lead portion 31D connected to the second counter electrode portion 32A and exposed on a part of the second side surface WS2, the second end surface LS2, a part of the first side surface WS1, the second side surface WS a fourth lead portion 32B exposed to a part of the first side surface WS1; a fifth lead portion 32C connected to the second counter electrode portion 32A and exposed to a part of the first side surface WS1, with a gap between the part of the fourth lead portion 32B extended to the first side surface WS1 and the part of the fourth lead portion 32B extended to the second side surface WS2; and a sixth lead portion 32D connected to the second counter electrode portion 32A and exposed to a part of the second side surface WS2, with a gap between the part of the fourth lead portion 32B extended to the second side surface WS2 and the part of the sixth lead portion 32D. The dimension in the length direction L of each of the lead portions 31C and the third lead portion 31D is longer than the dimension in the length direction L of each of the second lead portion 31C and the third lead portion 31D located other than the center in the height direction T, and the dimension in the length direction L of each of the fifth lead portion 32C and the sixth lead portion 32D located at the center in the height direction T is longer than the dimension in the length direction L of each of the fifth lead portion 32C and the sixth lead portion 32D located other than the center in the height direction T. This makes it possible to easily form the protrusions K protruding from the center sides of the length direction of the fourth face portion 40A4 and the ninth face portion 40B4 that face each other in the length direction L, and the protrusions K protruding from the center sides of the length direction of the fifth face portion 40A5 and the tenth face portion 40B5 that face each other in the length direction L.Furthermore, the distance between the second lead portion 31C of the first internal electrode layer 31 and the fifth lead portion 32C of the second external electrode 40B, and the distance between the third lead portion 31D of the first internal electrode layer 31 and the sixth lead portion 32D of the second external electrode 40B can be shortened, thereby shortening the path through which current flows, thereby reducing the ESL.

[0177] (6) In the multilayer ceramic capacitor 1 of this embodiment, the longitudinal center sides of the second lead portion 31C and the third lead portion 31D located at the center in the height direction T protrude toward the longitudinal center from the longitudinal center ends 40A9 of the second surface portion 40A2 and the third surface portion 40A3. The longitudinal center sides of the fifth lead portion 32C and the sixth lead portion 32D located at the center in the height direction T protrude toward the longitudinal center from the longitudinal center ends 40B9 of the seventh surface portion 40B2 and the eighth surface portion 40B3. This shortens the distance between the second lead portion 31C of the first internal electrode layer 31 and the fifth lead portion 32C of the second external electrode 40B, and the distance between the third lead portion 31D of the first internal electrode layer 31 and the sixth lead portion 32D of the second external electrode 40B. This shortens the current path. This reduces the ESL.

[0178] (7) The openings H of the multilayer ceramic capacitor 1 of this embodiment are located at the center in the height direction of the fourth and fifth surface portions 40A4, 40A5, and the ninth and tenth surface portions 40B4, 40B5. This allows the solder to properly wet up and surround the openings H.

[0179] (8) In the multilayer ceramic capacitor 1 of this embodiment, the openings H formed in the fourth and fifth surface portions 40A4 and 40A5 are positioned closer to the first end face LS1 than the longitudinal center of the fourth and fifth surface portions 40A4 and 40A5, and the openings H formed in the ninth and tenth surface portions 40B4 and 40B5 are positioned closer to the second end face LS2 than the longitudinal center of the ninth and tenth surface portions 40B4 and 40B5. This allows appropriate solder wetting and rising areas to be secured on both sides of the openings H.

[0180] (9) The area of ​​the opening H of the multilayer ceramic capacitor 1 of this embodiment is 3% to 20% of the area of ​​each of the fourth face portion 40A4, the fifth face portion 40A5, the ninth face portion 40B4, and the tenth face portion 40B5 where the opening H is located. This provides a self-alignment effect, and more significantly suppresses tilting or rotation of the multilayer ceramic capacitor 1, which can lead to short-circuit defects.

[0181] (10) The length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 of the multilayer ceramic capacitor 1 of this embodiment is 150 μm or less. In such a low-profile multilayer ceramic capacitor, the effects of this embodiment can be appropriately obtained.

[0182] (11) The length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 of the multilayer ceramic capacitor 1 of this embodiment is 100 μm or less. In such a low-profile multilayer ceramic capacitor, the effects of this embodiment can be appropriately obtained.

[0183] (12) The length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 of the multilayer ceramic capacitor 1 of this embodiment is 50 μm or less. In such a low-profile multilayer ceramic capacitor, the effects of this embodiment can be appropriately obtained.

[0184] (13) In the multilayer ceramic capacitor 1 of this embodiment, the first lead portion 31B, the second lead portion 31C, and the third lead portion 31C are all connected to the first external electrode 40A, and the fourth lead portion 32B, the fifth lead portion 32C, and the sixth lead portion 32D are all connected to the second external electrode. This allows the ESL to be reduced while forming openings H that expose the surface of the laminate 10 in the fourth face portion 40A4, the fifth face portion 40A5, and the ninth face portion 40B4, and the tenth face portion 40B5.

[0185] (14) The first external electrode 40A of the multilayer ceramic capacitor 1 of this embodiment has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A, and the second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B, with the first base electrode layer 50A and the second base electrode layer 50B being sputtered electrodes. This allows the external electrodes to be formed thin, making it easier to ensure the thickness of the laminate 10, and therefore ensuring the capacitance and strength of the laminate 10.

[0186] <Experimental Example> As a sample of the experimental example, a multilayer ceramic capacitor was fabricated and its mountability was evaluated.

[0187] First, as a sample of the example, a multilayer ceramic capacitor 1 having the following specifications and shown in Figures 1 to 10B was fabricated according to the manufacturing method described above. Furthermore, as a sample of Comparative Example 1, a multilayer ceramic capacitor 101 was fabricated as shown in Figure 16A, in which the external electrodes 140 (first external electrode 140A, second external electrode 140B) were not provided with openings H and protrusions K. Furthermore, as a sample of Comparative Example 2, a multilayer ceramic capacitor 201 was fabricated as shown in Figure 17A, in which the external electrodes 240 (first external electrode 240A, second external electrode 240B) were not provided with openings H and protrusions K, and recesses R were formed recessed from the edge of the external electrodes toward the end face of the laminate 10.

[0188] FIG. 16A is an external perspective view of the multilayer ceramic capacitor 101 of Comparative Example 1, and corresponds to FIG. 1. FIG. 16B is a view showing a first internal electrode layer 131 of the multilayer ceramic capacitor 101 of Comparative Example 1, and corresponds to FIG. 8A. FIG. 16C is a view showing a second internal electrode layer 132 of the multilayer ceramic capacitor 101 of Comparative Example 1, and corresponds to FIG. 8B. FIG. 17A is an external perspective view of the multilayer ceramic capacitor 201 of Comparative Example 2, and corresponds to FIG. 1. FIG. 17B is a view showing a first internal electrode layer 231 of the multilayer ceramic capacitor 201 of Comparative Example 2, and corresponds to FIG. 8A. FIG. 17C is a view showing a second internal electrode layer 232 of the multilayer ceramic capacitor 201 of Comparative Example 2, and corresponds to FIG. 8B. Note that external electrodes are omitted in FIGS. 16B, 16C, 17B, and 17C.

[0189] (Configuration of the Example) Multilayer ceramic capacitor dimensions: L×W×T=0.520mm×1.000mm×0.100mm Ceramic material of dielectric layer: BaTiO3 Capacitance: 0.47μF Rated voltage: 4V Internal electrode layer material: Ni Internal electrode layer pattern: the pattern shown in Figures 8A and 8B External electrode structure: Base electrode layer: thin film layer (sputtered electrode) Material of the base electrode layer: Two-layer structure of NiCr layer and NiCu layer Thickness of the base electrode layer: 0.2 μm of main surface thickness (thickness of the base electrode layer disposed on each of the first main surface TS1 and the second main surface TS2) Plating layer: Three-layer structure of Cu plating, Ni plating, and Sn plating Cu plating thickness: 5.5 μm Ni plating thickness: 2.5 μm Sn plating thickness: 3.2 μm Area ratio of openings H where the laminate of the fourth, fifth, ninth and tenth surfaces is exposed: 13% Height dimension of the convex portion of the fourth surface portion and the convex portion of the fifth surface portion: 50% of the height dimension of the laminate Height dimension of the convex portion of the ninth surface portion and the convex portion of the tenth surface portion: 50% of the height dimension of the laminate Lengthwise dimension of the convex portion of the fourth surface portion and the convex portion of the fifth surface portion: 10% of the lengthwise dimension of the laminate The lengthwise dimension of the convex portion of the ninth surface portion and the convex portion of the tenth surface portion: 10% of the lengthwise dimension of the laminate

[0190] (Configuration of Comparative Example 1) Multilayer ceramic capacitor dimensions: L×W×T=0.520mm×1.000mm×0.100mm Ceramic material of dielectric layer: BaTiO3 Capacitance: 0.47μF Rated voltage: 4V Internal electrode layer material: Ni Internal electrode layer pattern: the pattern shown in Figures 16B and 16C External electrode structure: Base electrode layer: A baked layer made by applying and baking conductive paste Material of the base electrode layer: Ni Thickness of the base electrode layer: end surface thickness 10 μm, side surface thickness 5 μm, main surface thickness 5 μm (thickness of the base electrode layer disposed on each of the first main surface TS1 and the second main surface TS2) Plating layer: Three-layer structure of Cu plating, Ni plating, and Sn plating Cu plating thickness: 5.5 μm Ni plating thickness: 2.5 μm Sn plating thickness: 3.2 μm

[0191] (Configuration of Comparative Example 2) Multilayer ceramic capacitor dimensions: L×W×T=0.520mm×1.000mm×0.100mm Ceramic material of dielectric layer: BaTiO3 Capacitance: 0.47μF Rated voltage: 4V Internal electrode layer material: Ni Internal electrode layer pattern: the pattern shown in Figures 17B and 17C External electrode structure: Base electrode layer: thin film layer (sputtered electrode) Material of the base electrode layer: Two layers: NiCr layer and NiCu layer Thickness of the base electrode layer: 0.2 μm of main surface thickness (thickness of the base electrode layer disposed on each of the first main surface TS1 and the second main surface TS2) Plating layer: Three-layer structure of Cu plating, Ni plating, and Sn plating Cu plating thickness: 5.5 μm Ni plating thickness: 2.5 μm Sn plating thickness: 3.2 μm

[0192] Next, the fabricated samples were used to evaluate the mountability.

[0193] (Implementation evaluation) Mountability was evaluated using the sample of the example having an area ratio of the openings H of 13% and the samples of comparative examples 1 and 2. The evaluation was performed using 100 samples for each. Table 1 shows the results of the evaluation of mountability.

[0194] [Table 1]

[0195] In Comparative Example 1, eight samples exhibited poor rotation. It is presumed that the evaluation was performed with a large amount of solder, which resulted in differences in the way the solder wetted onto the first external electrode and the second external electrode, causing the poor rotation.

[0196] In Comparative Example 2, 15 samples exhibited rotation defects. Two of these samples had a large amount of rotation, resulting in short circuits due to mounting with one external electrode straddling lands of opposite polarity. In the samples of Comparative Example 2, variations in the position and thickness of the base electrode layer and the plating layer formed thereon caused variations in the area and shape of the external electrodes covering the ridges of the first and second side surfaces of the laminate. This likely led to variations in the way the solder wetted the external electrodes on the first and second side surfaces, resulting in significant differences in the amount of solder wetting. It is believed that this resulted in variations in the way the tensile stress of the solder was applied to the multilayer ceramic capacitor, causing the rotation defects.

[0197] The evaluation methods used in this experiment are as follows.

[0198] (Method for evaluating implementation) 18A to 18D are diagrams illustrating a method for evaluating mountability. First, solder (solder composition Sn-3.0Ag-0.5Cu) is printed on each of two lands 310A and 310B arranged on a glass epoxy substrate 300 shown in FIG. 18A. The amount of solder used was 1.5 times that used in a normal test to create conditions that were more severe than those used in a normal test. Specifically, a 150 μm thick solder was printed on each land. As shown in FIG. 18A, the width of the land was 1.0 mm, the length of the land in the longitudinal direction was 0.3 mm, and the distance between the two lands was 0.2 mm.

[0199] Next, the multilayer ceramic capacitor is placed on the solder-coated lands. At this time, as shown in Fig. 18B, a reference line is drawn perpendicular to the width of the land at the center of the land's width, and the multilayer ceramic capacitor is placed so that the center of the width direction W of the multilayer ceramic capacitor is located 0.1 mm away from that reference line in the width direction of the land. At this time, the angle θ formed by the land and the multilayer ceramic capacitor shown in Fig. 18C, i.e., the acute angle θ formed between one of the opposing inner sides of the two lands and the surface of the external electrode of the multilayer ceramic capacitor facing the first end face LS1 or the surface facing the second end face LS2, is within 5°.

[0200] The external electrodes of the multilayer ceramic capacitor are then soldered to the lands by reflow soldering, and the multilayer ceramic capacitor is mounted on the board. After mounting, the mounted state of the multilayer ceramic capacitor is observed, and a rotation defect is detected when the angle θ between the land and the multilayer ceramic capacitor is 5° or more. Furthermore, as shown in Figure 18D, a short defect is detected when the multilayer ceramic capacitor is rotated significantly and the first or second external electrode straddles two lands.

[0201] (Calculation method for the area ratio of openings H) The area ratio of the openings H is measured using an optical microscope. First, the field of view of the microscope is set to a magnification such that the first external electrode 40A located on the first side surface WS1 of the multilayer ceramic capacitor 1 is included within the field of view of the microscope. Next, the contour of the openings H is identified, and the dimension d1 of the openings H in the length direction L and the dimension d2 of the openings H in the height direction T are measured (see FIG. 2). Then, the area A1 of the openings H is calculated using the formula A1 = d1 × d2. Next, the contour of the first external electrode 40A is identified, and the dimension D1 of the openings H in the length direction L and the dimension D2 of the openings H in the height direction T are measured (see FIG. 2). Then, the area A2 of the openings H in the fourth surface portion 40A4 is calculated using the formula A2 = D1 × D2. Then, the area ratio of the openings H located on the fourth surface portion 40A4 to the area of ​​the fourth surface portion 40A4 is calculated using the formula A1 ÷ A2. Similarly, the area ratios of the openings H located on the fifth surface portion 40A5, the ninth surface portion 40B4, and the tenth surface portion 40B5 are also calculated. Then, the average value of the area ratios of the four openings H, that is, the average value of the area ratios of the openings H located on the fourth surface portion 40A4, the fifth surface portion 40A5, the ninth surface portion 40B4, and the tenth surface portion 40B5, is calculated as the area ratio of the openings H in the multilayer ceramic capacitor 1.

[0202] (Method for measuring the height of the protrusion K) The dimension in the height direction T of each of the protrusions K arranged on the fourth surface 40A4 and the fifth surface 40A5 is measured with a microscope at a position halfway along the length direction L of each of the protrusions K arranged on the fourth surface 40A4 and the fifth surface 40A5 when observed from the first side surface WS1 of the laminate 10. Similarly, the dimension in the height direction T of each of the protrusions K arranged on the ninth surface 40B4 and the tenth surface 40B5 is measured with a microscope at a position halfway along the length direction L of each of the protrusions K arranged on the ninth surface 40B4 and the tenth surface 40B5 when observed from the second side surface WS2 of the laminate 10.

[0203] (Method for measuring the length of the protrusion K) The dimension in the length direction L of each of the protrusions K arranged on the fourth surface 40A4 and the fifth surface 40A5 is measured with a microscope at a position halfway in the height direction T of each of the protrusions K arranged on the fourth surface 40A4 and the fifth surface 40A5 when observed from the first side surface WS1 of the laminate 10. Similarly, the dimension in the length direction L of each of the protrusions K arranged on the ninth surface 40B4 and the tenth surface 40B5 is measured with a microscope at a position halfway in the height direction T of each of the protrusions K arranged on the ninth surface 40B4 and the tenth surface 40B5 when observed from the second side surface WS2 of the laminate 10.

[0204] The present invention is not limited to the configurations of the above-described embodiments, and can be appropriately modified and applied within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments.

[0205] (1) A laminate including a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in a height direction, and having a first main surface and a second main surface opposing each other in the height direction, a first end face and a second end face opposing each other in a length direction perpendicular to the height direction, and a first side face and a second side face opposing each other in a width direction perpendicular to the height direction and the length direction; a first external electrode having a first surface portion located on the first end face, at least one of a second surface portion located on a portion of the first main surface and a third surface portion located on a portion of the second main surface, a fourth surface portion located on a portion of the first side surface, and a fifth surface portion located on a portion of the second side surface; a second external electrode having a sixth surface portion located on the second end surface, at least one of a seventh surface portion located on a portion of the first main surface and an eighth surface portion located on a portion of the second main surface, a ninth surface portion located on a portion of the first side surface, and a tenth surface portion located on a portion of the second side surface, where l is the length in the length direction connecting the first end face and the second end face of the laminate, w is the length in the width direction connecting the first side face and the second side face, and t is the length in the height direction connecting the first main face and the second main face, a dimensional relationship of w>l>t is satisfied, the fourth surface portion, the fifth surface portion, the ninth surface portion, and the tenth surface portion have openings through which the surfaces of the laminate are exposed; The fourth and ninth surface portions, and the fifth and tenth surface portions, each have a protrusion that protrudes in the longitudinal direction from the center side of the longitudinal direction facing each other, in the multilayer ceramic capacitor.

[0206] (2) The multilayer ceramic capacitor according to (1), wherein the convex portions are arranged at the center in the height direction of the fourth and fifth surface portions and the ninth and tenth surface portions.

[0207] (3) The multilayer ceramic capacitor according to (1) or (2), wherein the dimension of the protrusion in the height direction is 10% to 90% of the dimension in the height direction.

[0208] (4) The multilayer ceramic capacitor according to any one of (1) to (3), wherein the dimension of the protrusion in the length direction is 2% to 18% of the dimension in the length direction.

[0209] (5) The internal electrode layers include first internal electrode layers and second internal electrode layers, the first internal electrode layer has: a first opposing electrode portion located inside the laminate; a first lead portion connected to the first opposing electrode portion and exposed to the first end face, a portion of the first side face, and a portion of the second side face; a second lead portion connected to the first opposing electrode portion with a gap between it and the portion of the first lead portion that is led to the first side face and exposed to the portion of the first side face; and a third lead portion connected to the first opposing electrode portion with a gap between it and the portion of the first lead portion that is led to the second side face and exposed to the portion of the second side face, the second internal electrode layer has: a second opposing electrode portion located inside the laminate; a fourth lead portion connected to the second opposing electrode portion and exposed to the second end face, a portion of the first side face, and a portion of the second side face; a fifth lead portion connected to the second opposing electrode portion with a gap between it and the portion of the fourth lead portion that is led to the first side face and exposed to a portion of the first side face; and a sixth lead portion connected to the second opposing electrode portion with a gap between it and the portion of the fourth lead portion that is led to the second side face and exposed to a portion of the second side face, the lengthwise dimensions of the second drawer portion and the third drawer portion located at the center in the height direction are longer than the lengthwise dimensions of the second drawer portion and the third drawer portion located at a position other than the center in the height direction; The multilayer ceramic capacitor according to any one of (1) to (4), wherein the lengthwise dimension of each of the fifth and sixth lead portions located at the center of the height direction is longer than the lengthwise dimension of each of the fifth and sixth lead portions located outside the center of the height direction.

[0210] (6) The center side of the second drawer portion and the third drawer portion located at the center in the height direction protrudes toward the center in the length direction further than the center side end of the second surface portion and the third surface portion, The multilayer ceramic capacitor according to (5), wherein the longitudinal center side of the fifth and sixth lead portions located in the center of the height direction protrudes toward the longitudinal center more than the longitudinal center side ends of the seventh and eighth surface portions.

[0211] (7) The multilayer ceramic capacitor according to any one of (1) to (6), wherein the opening is located at the center of the fourth and fifth surface portions and the ninth and tenth surface portions in the height direction.

[0212] (8) The openings formed in the fourth and fifth surfaces are positioned closer to the first end surface than the center of the fourth and fifth surfaces in the length direction, The multilayer ceramic capacitor according to any one of (1) to (7), wherein the openings formed in the ninth surface portion and the tenth surface portion are positioned biased toward the second end surface side from the center of the ninth surface portion and the tenth surface portion in the longitudinal direction.

[0213] (9) The multilayer ceramic capacitor according to any one of (1) to (8), wherein the area of ​​the opening is 3% or more and 20% or less of the area of ​​each of the fourth surface portion, the fifth surface portion, the ninth surface portion, and the tenth surface portion in which the opening is arranged.

[0214] (10) The multilayer ceramic capacitor according to any one of (1) to (9), wherein the length in the height direction connecting the first main surface and the second main surface of the laminate is 150 μm or less.

[0215] (11) The multilayer ceramic capacitor according to any one of (1) to (10), wherein the length in the height direction connecting the first main surface and the second main surface of the laminate is 100 μm or less.

[0216] (12) The multilayer ceramic capacitor according to any one of (1) to (11), wherein the length in the height direction connecting the first main surface and the second main surface of the laminate is 50 μm or less.

[0217] (13) The first lead portion, the second lead portion, and the third lead portion are all connected to the first external electrode, The multilayer ceramic capacitor according to (5), wherein the fourth lead portion, the fifth lead portion, and the sixth lead portion are all connected to the second external electrode.

[0218] (14) The first external electrode has a first base electrode layer and a first plating layer disposed on the first base electrode layer, the second external electrode has a second base electrode layer and a second plating layer disposed on the second base electrode layer, The multilayer ceramic capacitor according to any one of (1) to (13), wherein the first and second underlying electrode layers are sputtered electrodes. [Explanation of symbols]

[0219] 1. Multilayer ceramic capacitors 10 Laminate 11 Inner layer 12 First main surface side outer layer portion 13 Second main surface side outer layer 20 dielectric layer 30 Internal electrode layer 31 First internal electrode layer 31A First opposing electrode portion 31B First drawer 31C Second drawer 31D Third drawer 32 Second internal electrode layer 32A Second opposing electrode part 32B 4th drawer 32C Fifth drawer 32D 6th drawer 40 External electrode 40A First outer electrode 40A1 First side 40A2 2nd side 40A3 Third side 40A4 4th side 40A5 5th side 40B Second external electrode 40B1 6th side 40B2 7th side 40B3 8th side 40B4 9th side 40B5 10th side 50A First base electrode layer 50B Second base electrode layer 51A First thin film layer 51B Second thin film layer 60A First plating layer 60B Second plating layer H opening K convex part L lengthwise W width direction T Stacking direction LS1 First end face LS2 Second end face WS1 First Aspect WS2 Second Aspect TS1 First principal surface TS2 Second principal surface l Length in the longitudinal direction w Width t Height

Claims

1. a laminate including a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in a height direction, and having a first main surface and a second main surface opposing each other in the height direction, a first end face and a second end face opposing each other in a length direction perpendicular to the height direction, and a first side face and a second side face opposing each other in a width direction perpendicular to the height direction and the length direction; a first external electrode having a first surface portion located on the first end face, at least one of a second surface portion located on a portion of the first main surface and a third surface portion located on a portion of the second main surface, a fourth surface portion located on a portion of the first side surface, and a fifth surface portion located on a portion of the second side surface; a second external electrode having a sixth surface portion located on the second end surface, at least one of a seventh surface portion located on a portion of the first main surface and an eighth surface portion located on a portion of the second main surface, a ninth surface portion located on a portion of the first side surface, and a tenth surface portion located on a portion of the second side surface, where l is the length in the length direction connecting the first end face and the second end face of the laminate, w is the length in the width direction connecting the first side face and the second side face, and t is the length in the height direction connecting the first main face and the second main face, a dimensional relationship of w>l>t is satisfied, the fourth surface portion, the fifth surface portion, the ninth surface portion, and the tenth surface portion have openings through which the surfaces of the laminate are exposed, The fourth and ninth surface portions, and the fifth and tenth surface portions, each have a protrusion that protrudes in the longitudinal direction from a center side in the longitudinal direction facing each other.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein the protrusions are arranged at central portions in the height direction of the fourth and fifth surface portions and the ninth and tenth surface portions.

3. 3. The multilayer ceramic capacitor according to claim 1, wherein the dimension of the protrusion in the height direction is 10% to 90% of the dimension in the height direction.

4. 3. The multilayer ceramic capacitor according to claim 1, wherein the dimension of the protrusion in the length direction is 2% to 18% of the dimension in the length direction.

5. the internal electrode layers include a first internal electrode layer and a second internal electrode layer, the first internal electrode layer has: a first opposing electrode portion located inside the laminate; a first lead portion connected to the first opposing electrode portion and exposed to the first end face, a portion of the first side face, and a portion of the second side face; a second lead portion connected to the first opposing electrode portion with a gap between it and the portion of the first lead portion that is led to the first side face and exposed to the portion of the first side face; and a third lead portion connected to the first opposing electrode portion with a gap between it and the portion of the first lead portion that is led to the second side face and exposed to the portion of the second side face, the second internal electrode layer has: a second opposing electrode portion located inside the laminate; a fourth lead portion connected to the second opposing electrode portion and exposed to the second end face, a portion of the first side face, and a portion of the second side face; a fifth lead portion connected to the second opposing electrode portion with a gap between it and the portion of the fourth lead portion that is led to the first side face and exposed to a portion of the first side face; and a sixth lead portion connected to the second opposing electrode portion with a gap between it and the portion of the fourth lead portion that is led to the second side face and exposed to a portion of the second side face, the lengthwise dimensions of the second drawer portion and the third drawer portion located at the center in the height direction are longer than the lengthwise dimensions of the second drawer portion and the third drawer portion located at a position other than the center in the height direction; 3. The multilayer ceramic capacitor according to claim 1, wherein the lengthwise dimensions of the fifth and sixth lead portions located at the center of the height direction are longer than the lengthwise dimensions of the fifth and sixth lead portions located other than the center of the height direction.

6. the second and third drawer portions located at the center in the height direction have their longitudinal center sides protruding toward the longitudinal center further than the longitudinal center ends of the second and third surface portions, 6. The multilayer ceramic capacitor according to claim 5, wherein the longitudinal center sides of the fifth and sixth lead portions located in the central portion in the height direction protrude toward the longitudinal center further than the longitudinal center side ends of the seventh and eighth surface portions.

7. 3. The multilayer ceramic capacitor according to claim 1, wherein the openings are disposed at central portions in the height direction of the fourth surface portion, the fifth surface portion, the ninth surface portion, and the tenth surface portion.

8. the openings formed in the fourth surface portion and the fifth surface portion are positioned closer to the first end surface than central portions in the length direction of the fourth surface portion and the fifth surface portion, 3. The multilayer ceramic capacitor according to claim 1, wherein the openings formed in the ninth surface portion and the tenth surface portion are positioned offset toward the second end surface from a center portion in the longitudinal direction of the ninth surface portion and the tenth surface portion.

9. 3. The multilayer ceramic capacitor according to claim 1, wherein an area of ​​the opening is 3% or more and 20% or less of an area of ​​each of the fourth surface portion, the fifth surface portion, the ninth surface portion, and the tenth surface portion in which the opening is arranged.

10. 3. The multilayer ceramic capacitor according to claim 1, wherein the length in the height direction connecting the first main surface and the second main surface of the laminate is 150 [mu]m or less.

11. 3. The multilayer ceramic capacitor according to claim 1, wherein a length in a height direction connecting said first main surface and said second main surface of said laminate is 100 [mu]m or less.

12. 3. The multilayer ceramic capacitor according to claim 1, wherein a length in a height direction connecting said first main surface and said second main surface of said laminate is 50 [mu]m or less.

13. the first lead portion, the second lead portion, and the third lead portion are all connected to the first external electrode; 6. The multilayer ceramic capacitor according to claim 5, wherein the fourth lead portion, the fifth lead portion, and the sixth lead portion are all connected to the second external electrode.

14. the first external electrode has a first base electrode layer and a first plating layer disposed on the first base electrode layer; the second external electrode has a second base electrode layer and a second plating layer disposed on the second base electrode layer, 3. The multilayer ceramic capacitor according to claim 1, wherein the first and second underlying electrode layers are sputtered electrodes.

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