Multilayer electronic components

Abstract

To provide a laminated electronic component capable of ensuring reliability by reducing the difference in shrinkage rate between the core and margin, in which internal electrodes are placed, and between the core and the cover.SOLUTION: A laminated electronic component in an embodiment includes: an active part, in which multiple first dielectric layers and internal electrodes are arranged alternately; a body that includes a cover including second dielectric layers each placed at both ends of the active part in a first direction in which the multiple first dielectric layers are stacked; and a pair of external electrodes that are placed outside of the body and are connected to the internal electrode. The body may include a margin part that has a dielectric pattern with higher porosity than the first dielectric layer and covers the remaining sides except the side connected to the external electrode in the internal electrode.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a multilayer electronic component. [Background technology]

[0002] Multi-layered ceramic capacitors (MLCCs), a type of multilayer electronic component, are chip-type capacitors that are mounted on printed circuit boards of various electronic products, such as visual devices such as liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones, and mobile phones, and serve to charge and discharge electricity.

[0003] Such multilayer ceramic capacitors have the advantages of being small, yet having high capacitance, and being easy to mount, and can be used as components in various electronic devices. Recently, with the trend toward miniaturization of electronic device components, there has been an increasing demand for miniaturization and high capacitance of multilayer ceramic capacitors.

[0004] To achieve miniaturization and high capacitance of multilayer ceramic capacitors, internal electrodes and dielectric layers are formed thin and then laminated in multiple layers. However, differences in physical properties, particularly differences in shrinkage rates during sintering, between the alternately laminated dielectric layers and internal electrodes can cause mismatches between the components, resulting in reduced reliability of the multilayer ceramic capacitor.

[0005] Unlike the core (active part) where dielectric layers and internal electrodes are alternately arranged, the margin and cover parts where no internal electrodes are arranged are made up of pure dielectric sheets, which causes differences in the degree of shrinkage or expansion during plasticization and sintering. As a result, deformation such as distortion can occur due to uneven stress between the core and margin or between the core and cover, which can lead to product defects such as cracks or breakage due to reverse bonding in the multilayer ceramic capacitor.

[0006] As a result, along with the technical demand for miniaturization and higher capacitance of multilayer ceramic capacitors, there is a need for technology to ensure product reliability by reducing the difference in shrinkage rate between the core where the internal electrodes are located and the margin, and between the core and the cover. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Korean Patent Publication No. 2019-0015453 Summary of the Invention [Problem to be solved by the invention]

[0008] One of the objects of the present invention is to provide a multilayer electronic component with ensured reliability by reducing the difference in shrinkage rate between the core where the internal electrodes are arranged and the margin, and between the core and the cover portion.

[0009] However, the object of the present invention is not limited to the above-mentioned contents, and can be more easily understood in the course of describing specific embodiments of the present invention. [Means for solving the problem]

[0010] A multilayer electronic component according to one embodiment of the present invention includes: an active portion in which a plurality of first dielectric layers and internal electrodes are alternately arranged; a main body including cover portions each of which is disposed at both ends of the active portion in a first direction in which the plurality of first dielectric layers are stacked, the cover portions including a second dielectric layer; and external electrodes disposed outside the main body and connected to the internal electrodes, wherein the main body includes a margin portion covering the remaining sides of the internal electrodes except for the side connected to the external electrode, the margin portion including a dielectric pattern having a higher porosity than the first dielectric layer.

[0011] According to another embodiment of the present invention, a method for manufacturing a multilayer electronic component includes the steps of: providing a plurality of first ceramic green sheets each having a plurality of first internal electrode patterns formed thereon and a plurality of first ceramic green sheets each having a plurality of second internal electrode patterns formed thereon; providing a dielectric material in at least a portion of a remaining region of each of the plurality of first ceramic green sheets excluding the first and second internal electrode patterns; stacking the plurality of first ceramic green sheets so that the first and second internal electrode patterns intersect, and stacking second ceramic green sheets on both ends in the stacking direction to form a multilayer body; and firing the multilayer body to provide a body including an active portion including a first dielectric layer, internal electrodes, and the dielectric patterns, and a cover portion including a second dielectric layer, wherein the dielectric patterns may have a higher porosity than the first dielectric layer. [Effects of the Invention]

[0012] According to one embodiment of the present invention, the difference in shrinkage rate between the active part of the composite structure in which the internal electrodes and dielectric layers are arranged and the dielectric layers arranged in the side margin part is reduced, thereby preventing uneven deformation and reverse bonding in the side margin part.

[0013] In addition, according to one embodiment of the present invention, the difference in shrinkage rate between the active part of a composite structure in which internal electrodes and dielectric layers are arranged and the cover parts arranged above and below it is reduced, thereby preventing cracks at the boundary between the active part and the cover and ensuring reliability.

[0014] However, the various beneficial advantages and effects of the present invention are not limited to the above, and can be more easily understood in the course of describing specific embodiments of the present invention. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a schematic perspective view of a multilayer electronic component according to an embodiment of the present invention; [Figure 2] FIG. 2 is a cross-sectional view taken along line II' in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line II-II' in FIG. [Figure 4] 1 is an exploded perspective view showing a main body in which dielectric layers and internal electrodes are stacked according to an embodiment of the present invention; [Figure 5] 5 is a planar front view showing a modification of the main body of FIG. 4, cut along line XZ. FIG. [Figure 6] 1A and 1B are enlarged photographs of the boundary between the active portion and the margin portion of a multilayer electronic component according to one embodiment of the present invention. [Figure 7] Photographs (a) and (b) are enlarged photographs of the boundary between the active portion and the margin portion of a conventional multilayer electronic component. [Figure 8] 10 is an exploded perspective view showing a main body in which dielectric layers and internal electrodes are stacked according to another embodiment of the present invention; FIG. [Figure 9] 3 is a cross-sectional view taken along line II' showing a modification of the multilayer electronic component of FIG. 2. FIG. [Figure 10] 10 is a planar front view showing the first internal electrode of FIG. 9 cut along line XY. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, the embodiments of the present invention are provided to more completely explain the present invention to those having average knowledge in the art. Therefore, the shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

[0017] In addition, to clearly explain the present invention, parts not relevant to the description are omitted in the drawings, thicknesses are exaggerated to clearly show multiple layers and regions, and components having the same function within the same concept are described using the same reference numerals. Furthermore, throughout the specification, the term "comprises" a certain component does not exclude other components, but means that the component may further include other components, unless otherwise specified.

[0018] To clearly explain the embodiments of the present invention, directions are defined as follows: X, Y, and Z shown in the drawings respectively indicate the length direction, width direction, and thickness direction of the multilayer electronic component.

[0019] In this specification, the length direction may be the X direction or the second direction, the width direction may be the Y direction or the third direction, and the thickness direction may be the Z direction, the first direction or the stacking direction, all of which may be used with the same concept.

[0020] Multilayer electronic components FIG. 1 is a schematic perspective view of a multilayer electronic component according to one embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line II' in FIG. 1, FIG. 3 is a cross-sectional view taken along line II-II' in FIG. 1, and FIG. 4 is an exploded perspective view showing a schematic exploded view of a main body in which dielectric layers and internal electrodes are laminated according to one embodiment of the present invention.

[0021] First, a multilayer electronic component according to one embodiment of the present invention will be described with reference to FIGS.

[0022] A multilayer electronic component 100 according to one embodiment of the present invention includes a plurality of first dielectric layers 111, a plurality of internal electrodes 121, 122 sandwiched between the first dielectric layers 111, a main body 110 including a plurality of second dielectric layers 116, and external electrodes 131, 132 arranged outside the main body 110 and connected to the internal electrodes 121, 122.

[0023] The shape of the body 110 is not particularly limited, but may be a hexahedron as shown in the figure or a similar shape. Due to shrinkage of the ceramic powder contained in the body 110 during the firing process, the body 110 may not be a perfect rectangular parallelepiped, but may have a substantially hexahedron shape.

[0024] The main body 110 may have first and second surfaces (1, 2) facing each other in the stacking direction (Z direction), third and fourth surfaces (3, 4) connected to the first and second surfaces (1, 2) and facing each other in the length direction (X direction), and fifth and sixth surfaces (5, 6) connected to the first to fourth surfaces (1, 2, 3, 4) and facing each other in the width direction (Y direction).

[0025] The main body 110 may include an active portion in which a plurality of first dielectric layers 111 and internal electrodes 121, 122 are alternately arranged, and cover portions 112, 113 each including a second dielectric layer 116, which are arranged at both ends of the active portion in a first direction in which the first dielectric layers 111 are stacked.

[0026] The active portion is a portion that contributes to forming the capacitance of the capacitor, and may be formed by repeatedly arranging a plurality of internal electrodes 121 and 122 with the first dielectric layer 111 sandwiched therebetween.

[0027] The plurality of first dielectric layers 111 included in the active portion are in a fired state, and the boundaries between adjacent first dielectric layers 111 can be integrated to the extent that they are difficult to identify without the use of a scanning electron microscope (SEM).

[0028] There are no particular limitations on the raw material for forming the first dielectric layer 111, as long as sufficient capacitance can be obtained. For example, a barium titanate-based material, a lead complex perovskite-based material, or a strontium titanate-based material can be used.

[0029] Furthermore, the material forming the first dielectric layer 111 may be a powder such as barium titanate (BaTiO3) to which various ceramic additives, organic solvents, plasticizers, binders, dispersants, etc. have been added according to the purpose of the present invention.

[0030] The cover parts 112 and 113 include an upper cover part 112 and a lower cover part 113, and basically serve to prevent damage to the internal electrodes due to physical or chemical stress. The cover parts 112 and 113 may not include internal electrodes.

[0031] According to this embodiment, the cover parts 112 and 113 can be formed by laminating second dielectric layers 116 on the upper and lower parts of the active parts in the thickness direction.

[0032] The plurality of second dielectric layers 116 included in the cover portions 112, 113 are in a fired state, and the boundaries between adjacent second dielectric layers 116 can be integrated to the extent that they are difficult to identify without the use of a scanning electron microscope (SEM).

[0033] There are no particular limitations on the raw material for forming the second dielectric layer 116, as long as it can provide sufficient capacitance. For example, a barium titanate-based material, a lead complex perovskite-based material, or a strontium titanate-based material can be used.

[0034] In addition, the material forming the second dielectric layer 116 may be a powder such as barium titanate (BaTiO3) to which various ceramic additives, organic solvents, plasticizers, binders, dispersants, etc. have been added depending on the purpose of the present invention.

[0035] The first dielectric layer 111 included in the active part and the second dielectric layer 116 included in the cover parts 112 and 113 may have different dielectric compositions. For example, the first dielectric layer 111 and the second dielectric layer 116 may be formed of different types of ceramic materials or may contain different compositions of minor components such as lithium (Li) and sodium (Na).

[0036] Alternatively, the first dielectric layer 111 included in the active portion and the second dielectric layer 116 included in the cover portions 112 and 113 may have the same dielectric composition. In this case, even if the dielectric composition is the same, the sizes of the ceramic particles included in the first dielectric layer 111 and the second dielectric layer 116 may be different from each other.

[0037] Alternatively, the porosity of the first dielectric layer 111 included in the active portion may be different from the porosity of the second dielectric layer 116 included in the cover portions 112 and 113. As a result, the average porosities of the first dielectric layer 111 included in the active portion and the cover portions 112 and 113 in the final product may be different from each other.

[0038] The plurality of internal electrodes 121, 122 are arranged alternately with the plurality of first dielectric layers 111 sandwiched therebetween.

[0039] External electrodes 131 and 132 are formed on both end surfaces of the body 110 in the second direction (X direction), and the plurality of internal electrodes 121 and 122 may include first and second internal electrodes 121 and 122 connected to the external electrodes 131 and 132, respectively.

[0040] The first and second internal electrodes 121, 122 are alternately arranged to face each other with the first dielectric layer 111, which constitutes the active part of the body 110, sandwiched therebetween, and can be exposed to the third and fourth surfaces (3, 4) of the body 110, respectively.

[0041] Referring to Figures 1 to 3, the first internal electrode 121 can be spaced apart from the fourth, fifth, and sixth surfaces (4, 5, 6) and exposed to the third surface (3), and the second internal electrode 122 can be spaced apart from the third, fifth, and sixth surfaces (3, 5, 6) and exposed to the fourth surface (4).

[0042] A first external electrode 131 may be disposed on the third surface (3) of the body 110 and connected to the first internal electrode 121, and a second external electrode 132 may be disposed on the fourth surface (4) of the body and connected to the second internal electrode 122.

[0043] In this case, the first external electrode 131 and the second internal electrode 122, and the second external electrode 132 and the first internal electrode 121 are arranged to be spaced apart from each other in the second direction (X direction), and the shortest separation distance between them may be the same.

[0044] Referring to FIG. 4, the body 110 can be formed by alternately stacking first dielectric layers 111 on which first internal electrodes 121 are printed and first dielectric layers 111 on which second internal electrodes 122 are printed in the thickness direction (Z direction) and then firing the stack.

[0045] At this time, the first and second internal electrodes 121 and 122 can be electrically isolated from each other by the first dielectric layer 111 disposed therebetween.

[0046] Furthermore, the material for forming the first and second internal electrodes 121, 122 is not particularly limited, and may be formed using a conductive paste made of one or more of a noble metal material, nickel (Ni), and copper (Cu).

[0047] The conductive paste may be printed by a screen printing method or a gravure printing method, but the present invention is not limited thereto.

[0048] A margin may be disposed on the side of the active part of the body 110. The margin may essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0049] The margin portions may cover the remaining side surfaces of the internal electrodes 121 and 122 except for the side surfaces connected to the external electrodes 131 and 132. In this case, the margin portions may be formed by applying a conductive paste to the ceramic green sheets to form the internal electrodes except for the areas where the margin portions are to be formed.

[0050] According to this embodiment, the internal electrodes 121, 122 may include a first internal electrode 121 connected to the third surface (3) of the body 110 and spaced apart from the fourth, fifth, and sixth surfaces (4, 5, 6), and a second internal electrode 122 connected to the fourth surface (4) of the body 110 and spaced apart from the third, fifth, and sixth surfaces (3, 5, 6). These may then be connected to external electrodes 131, 132 on the third surface (3) and fourth surface (4), respectively.

[0051] Therefore, in this case, the margin portions may be arranged so as to cover the side surfaces of the internal electrodes 121, 122 facing the fourth, fifth, and sixth surfaces (4, 5, 6) of the main body 110 and the side surfaces facing the third, fifth, and sixth surfaces (3, 5, 6), respectively.

[0052] 3, the margin portion may include a margin portion 114 disposed on the sixth surface (6) of the main body 110 and a margin portion 115 disposed on the fifth surface (5). That is, the margin portion may include margin portions 114 and 115 disposed on both sides of the ceramic body 110 in the width direction.

[0053] 2 to 4, the margin portion may include dielectric patterns 141 and 142. That is, the internal electrodes 121 and 122 are arranged on the plurality of first dielectric layers 111, respectively, and margin portions may be formed in areas where the internal electrodes 121 and 122 are not arranged, and the dielectric patterns 141 and 142 may be arranged in each margin portion.

[0054] As shown in FIG. 2, the dielectric patterns 141 and 142 are arranged to fill the tolerances that occur between the first dielectric layers 111 due to the alternating arrangement of the first and second internal electrodes 121 and 122, thereby preventing cracks and breakage of the multilayer electronic component 100.

[0055] In addition, as shown in FIG. 3, the dielectric patterns 141 and 142 are arranged in the active portion of the main body 110 so as to fill the tolerances that occur in the margin portions 114 and 115 at both ends in the third direction (Y direction), thereby preventing damage due to uneven contraction or expansion between the active portion and the margin portions when the laminated electronic component 100 is sintered.

[0056] The dielectric patterns 141, 142 may include a first dielectric pattern 141 arranged around the first internal electrode 121 spaced apart from the fourth, fifth, and sixth surfaces (4, 5, 6) of the main body 110, and a second dielectric pattern 142 arranged around the second internal electrode 122 spaced apart from the third, fifth, and sixth surfaces (3, 5, 6) of the main body 110.

[0057] That is, as shown in FIG. 4, the first dielectric pattern 141 may be arranged in the first dielectric layer 111 so as to fill the area where the first internal electrode 121 is not formed, and the second dielectric pattern 142 may be arranged in the first dielectric layer 111 so as to fill the area where the second internal electrode 122 is not formed.

[0058] The dielectric patterns 141 and 142 may be formed of a dielectric material. The raw material of the dielectric material forming the dielectric patterns 141 and 142 is not particularly limited as long as it can provide sufficient capacitance. For example, a barium titanate-based material, a lead complex perovskite-based material, or a strontium titanate-based material may be used.

[0059] Furthermore, the material forming the dielectric patterns 141, 142 may be a powder such as barium titanate (BaTiO3) to which various ceramic additives, organic solvents, plasticizers, binders, dispersants, etc. have been added according to the purpose of the present invention.

[0060] In this case, the dielectric patterns 141 and 142 and the first dielectric layer 111 may have different porosities. In particular, the porosity of the dielectric patterns 141 and 142 may be higher than the porosity of the first dielectric layer 111.

[0061] The porosity of the dielectric patterns 141 and 142 and the first dielectric layer 111 may vary depending on the difference in the binder content contained in the dielectric material and the ceramic green sheet used in forming them. That is, as the dielectric material forming the dielectric patterns 141 and 142 contains a larger amount of binder, the dielectric patterns 141 and 142 may have a relatively high porosity, and the first dielectric layer 111 may have a relatively low porosity.

[0062] In the multilayer electronic component 100 according to this embodiment, the dielectric material forming the dielectric patterns 141, 142 contains a larger amount of binder, so that the dielectric patterns 141, 142 can have a higher shrinkage rate than the first dielectric layer 111 during sintering.

[0063] More specifically, in the technical field to which the present invention pertains, the shrinkage rate of the internal electrodes is generally lower than that of the dielectric layers, which results in variations in shrinkage rate during the sintering process of the electronic components, and this uneven shrinkage can cause deformation such as reverse bonding of the electronic components, which can reduce reliability.

[0064] Therefore, the dielectric patterns 141, 142 according to this embodiment have a shrinkage rate that is between the shrinkage rate of the first dielectric layer 111 and the shrinkage rate of the internal electrodes 121, 122, thereby achieving the effect of suppressing a decrease in reliability due to variations in the shrinkage rates of the first dielectric layer 111 and the internal electrodes 121, 122.

[0065] Furthermore, the first dielectric layer 111 and the dielectric patterns 141 and 142 included in the active portion may have different dielectric compositions. For example, the first dielectric layer 111 and the dielectric patterns 141 and 142 may be formed of different types of ceramic materials or may contain different compositions of minor components such as lithium (Li) and sodium (Na).

[0066] Alternatively, the first dielectric layer 111 and the dielectric patterns 141 and 142 may have the same dielectric composition except for the binder content before sintering. In this case, even if the dielectric composition is the same, the sizes of the ceramic particles contained in the first dielectric layer 111 and the dielectric patterns 141 and 142 may be different.

[0067] Meanwhile, according to an embodiment of the present invention, the dielectric compositions of the dielectric patterns 141 and 142 and the second dielectric layer 116 may be the same. That is, the dielectric patterns 141 and 142 formed in the margin portions and the cover portions 112 and 113 of the body 110 formed by the second dielectric layer 116 may have the same dielectric composition.

[0068] In this case, the dielectric patterns 141 and 142 may have the same average porosity as the second dielectric layer 116. In other words, the binder content of the dielectric material forming the dielectric patterns 141 and 142 may be the same as that of the ceramic green sheet forming the second dielectric layer 116. This allows the dielectric patterns 141 and 142 and the second dielectric layer 116 to have approximately the same shrinkage rate during sintering.

[0069] In the multilayer electronic component 100 according to this embodiment, the shrinkage rates of the dielectric patterns 141 and 142 and the cover portions 112 and 113 are matched to each other, so that the cover portions 112 and 113 have a shrinkage rate similar to the average shrinkage rate of the active portion. That is, the cover portions 112 and 113 have a shrinkage rate similar to the average value of the shrinkage rates of the first dielectric layer 111, the internal electrodes 121 and 122, and the dielectric patterns 141 and 142 included in the active portion, so that the variation in shrinkage rate between the active portion and the cover portions 112 and 113 can be reduced.

[0070] This makes it possible to prevent separation and damage of main body 110 that occurs when multilayer electronic component 100 is sintered due to variations in the shrinkage rate between active section and cover sections 112 and 113.

[0071] The outer electrodes 131 and 132 are disposed on the body 110 and connected to the inner electrodes 121 and 122 .

[0072] As shown in Figures 1 to 3, the external electrodes 131, 132 may include first and second external electrodes 131, 132 arranged on the third and fourth surfaces (3, 4) of the main body 110, respectively, and connected to the first and second internal electrodes 121, 122, respectively.

[0073] In this embodiment, the multilayer electronic component 100 has a structure having two external electrodes 131 and 132, but the number and shape of the external electrodes 131 and 132 can be changed depending on the shape of the internal electrodes 121 and 122 and other purposes.

[0074] The external electrodes 131 and 132 may be formed using various electrically conductive materials such as metals, and the specific material may be determined in consideration of electrical properties, structural stability, and the like.

[0075] For example, the external electrodes 131 and 132 may be fired electrodes containing a conductive metal and glass, or resin-based electrodes containing a conductive metal and resin.

[0076] The external electrodes 131 and 132 may be formed by sequentially forming a fired electrode and a resin-based electrode on the main body 110. The external electrodes 131 and 132 may be formed by transferring a sheet containing a conductive metal onto the main body 110, or by transferring a sheet containing a conductive metal onto a fired electrode.

[0077] There are no particular limitations on the conductive metal contained in the external electrodes 131 and 132, and any material with excellent electrical conductivity can be used. For example, the conductive metal may be one or more of nickel (Ni), copper (Cu), and alloys thereof.

[0078] The first and second external electrodes 131 and 132 may further include plating layers, which may include first and second nickel (Ni) plating layers and first and second tin (Sn) plating layers covering the first and second nickel plating layers, respectively.

[0079] FIG. 5 is a plan front view showing a modified example of the main body of FIG. 4, cut along line XZ.

[0080] Referring to FIG. 5, the main body 110-1 according to this modification may include dielectric patterns 141, 142 having limited heights.

[0081] First, in the main body 110-1 according to this modification, first dielectric layers 111 and internal electrodes 121 and 122 may be alternately arranged to form an active portion, similar to the main body 110 shown in Fig. 4. Also, second dielectric layers 116 may be stacked on both ends of the active portion in the stacking direction (first direction) to form cover portions 112 and 113.

[0082] Here, the dielectric patterns 141 and 142 may have a filling rate of 30% to 90% in the marginal areas. For example, when the average height of the dielectric patterns 141 and 142 in the first direction is defined as t1 and the average height of the internal electrodes 121 and 122 in the first direction is defined as t2, t1 may satisfy 0.3t2≦t1≦0.9t2.

[0083] The dielectric patterns 141, 142 may be formed to have the same height as the internal electrodes 121, 122, but in this case, reverse bonding or discontinuities may occur due to shrinkage or expansion during the sintering step of the multilayer electronic component. Therefore, it is preferable that the dielectric patterns 141, 142 be formed to have a height of 90% or less of the total height of the margin portion in the first direction. That is, the average height t1 of the dielectric patterns 141, 142 in the first direction may satisfy t1≦0.9t2.

[0084] Conversely, if the dielectric patterns 141, 142 are formed with an excessively low height, the fill factor of the marginal portions will be low, and the effect of filling the tolerances occurring between the first dielectric layers 111 may not be fully achieved. As a result, uneven deformation such as reverse bonding of the multilayer electronic component 100 may not be effectively suppressed. Furthermore, if the fill factor of the marginal portions is low, less than 30%, the withstand voltage (BDV) of the multilayer electronic component 100 may not reach a required value.

[0085] Therefore, preferably, the dielectric patterns 141 and 142 may be formed to have a height of 30% or more of the total height of the margin portion in the first direction, i.e., the average height t1 of the dielectric patterns 141 and 142 in the first direction may satisfy 0.3t2≦t1.

[0086] Meanwhile, the average heights t11 and t12 in the first direction of the second dielectric layer 116 forming the cover portion are not particularly limited. For example, as shown in Fig. 5, the average heights t11 and t12 in the first direction of the second dielectric layer 116 may be the same as the average height t1 in the first direction of the dielectric patterns 141 and 142.

[0087] Furthermore, the average height t3 of the first dielectric layer 111 in the first direction is not particularly limited. For example, as shown in Fig. 5, the average height t3 of the first dielectric layer 111 in the first direction may be greater than the average height t1 of the dielectric patterns 141 and 142 in the first direction. Furthermore, the average height t3 of the first dielectric layer 111 in the first direction may be the same as the average height t2 of the internal electrodes 121 and 122 in the first direction.

[0088] However, the above is merely an example, and the height of each of the dielectric layers 111 and 116 in the first direction can be formed in various ways as needed.

[0089] Here, the average height of each component is calculated by measuring the height of each component in the first direction from multiple cross sections (e.g., 10 cross sections each spaced equally apart) parallel to the XZ plane and the YZ plane of the multilayer electronic component, and calculating the average value.

[0090] Therefore, the heights of the components in the first direction for different cross sections may be different from each other. That is, the dielectric patterns 141 and 142, the first dielectric layer 111, the second dielectric layer 116, and the internal electrodes 121 and 122 may not have a uniform height, but may be formed in a shape that protrudes or recesses in some areas.

[0091] A method for manufacturing the multilayer electronic component 100 according to one embodiment of the present invention will now be described.

[0092] First, a plurality of first ceramic green sheets are prepared. The first ceramic green sheet is used to form the first dielectric layer 111 of the body 110, and can be prepared by mixing ceramic powder, a polymer, and a solvent to prepare a slurry, and then forming the slurry into a sheet using a method such as a doctor blade.

[0093] Here, the ceramic powder contained in the slurry forming the first dielectric layer can contain BaTiO3 as a main component.

[0094] Thereafter, a conductive paste for internal electrodes is printed on at least one surface of each of the first ceramic green sheets to form the internal electrodes 121 and 122. The conductive paste for internal electrodes can be formed by mixing Ni powder and Cu powder, or by containing Ni-Cu alloy powder, for example.

[0095] The conductive paste for the internal electrodes can be printed by screen printing, gravure printing, or the like.

[0096] When the first internal electrode pattern or the second internal electrode pattern is formed on the plurality of first ceramic green sheets, a dielectric material may be provided in at least a portion of the remaining area of ​​each of the plurality of first ceramic green sheets excluding the first and second internal electrode patterns.

[0097] Here, the dielectric material corresponds to a material forming the dielectric patterns 141 and 142, and the dielectric patterns 141 and 142 may be characterized by having a higher porosity than the first dielectric layer 111.

[0098] In addition, when the volume fraction of the binder contained in the first ceramic green sheet is defined as A, the volume fraction of the binder contained in the first and second internal electrode patterns is defined as B, and the volume fraction of the binder contained in the dielectric material is defined as C, the relationship A>C≧B may be satisfied. In other words, the binder content of the dielectric material forming the dielectric patterns 141 and 142 may be an intermediate value between the binder contents of the first ceramic green sheet and the internal electrode patterns, or may be the same as the binder content of the internal electrode patterns.

[0099] As a result, the shrinkage rate of the dielectric patterns 141 and 142 during sintering may be an intermediate value between the shrinkage rates of the first dielectric layer 111 and the internal electrodes 121 and 122, or may be substantially the same as the shrinkage rate of the internal electrodes 121 and 122. As a result, the porosity of the dielectric patterns 141 and 142 included in the margin portion may be higher than the porosity of the first dielectric layer 111 included in the active portion.

[0100] Referring to FIG. 4, a plurality of first ceramic green sheets are alternately stacked so that the first internal electrode patterns and the second internal electrode patterns intersect, and pressure is applied from the stacking direction to compress the stacked plurality of first ceramic green sheets and the internal electrodes formed on the first ceramic green sheets to each other, thereby forming a laminate.

[0101] In addition, at least one second ceramic green sheet may be laminated on the top and bottom of the laminate to form cover parts 112 and 113. The cover parts 112 and 113 may have the same composition as the first dielectric layer 111 located inside the laminate, but differ from the first dielectric layer 111 in that they do not include internal electrodes.

[0102] In this case, the second ceramic green sheets may form the second dielectric layers 116, and the dielectric composition of the second ceramic green sheets and the composition of the dielectric material forming the dielectric patterns 141 and 142 may be the same.

[0103] The first and second ceramic green sheets may contain different amounts of binder, which may result in the porosity of the first dielectric layer 111 included in the active portion being different from the porosity of the cover portions 112 and 113.

[0104] The laminate is then cut into chips each corresponding to a capacitor, and then fired at a high temperature to complete the main body 110, which includes an active part including the first dielectric layer 111, internal electrodes 121, 122, and dielectric patterns 141, 142, and cover parts 112, 113 including the second dielectric layer 116.

[0105] In addition, first and second external electrodes 131 and 132 may be formed to cover the exposed portions of the first and second internal electrodes 121 and 122 exposed on both sides of the body 110 and to be electrically connected to the first and second internal electrodes 121 and 122.

[0106] At this time, the surfaces of the first and second external electrodes 131, 132 may be plated with nickel (Ni) or tin (Sn) as needed.

[0107] 6(a) and 6(b) are enlarged photographs of the boundary between the active portion and the margin portion of a multilayer electronic component according to one embodiment of the present invention, and FIG. 7(a) and 7(b) are enlarged photographs of the boundary between the active portion and the margin portion of a conventional multilayer electronic component.

[0108] 6 and 7, the left side shows the active area including the internal electrode, the right side shows the marginal area without the internal electrode, and the midpoint shows the tip of the internal electrode, i.e., the boundary between the active area and the marginal area.

[0109] 6 and 7, it can be seen that more pores are observed in the photograph of the multilayer electronic component according to an embodiment of the present invention shown in Fig. 6 compared to the conventional multilayer electronic component shown in Fig. 7. In particular, in Fig. 6(a) and (b), more pores are observed in the margin area on the right side than in the active area on the left side.

[0110] This is interpreted as a result of including a large amount of binder in the dielectric material forming the dielectric patterns 141, 142 included in the margin portion during the step of forming the body 110 according to an embodiment of the present invention. That is, it is interpreted that the dielectric patterns 141, 142 in the margin portion and the first dielectric layer 111 in the active portion have different porosities due to the difference in the binder contents included in the dielectric material and the ceramic green sheet used during the steps of forming them. As the dielectric material forming the dielectric patterns 141, 142 includes a larger amount of binder, the dielectric patterns 141, 142 have a relatively high porosity, and the first dielectric layer 111 has a relatively low porosity.

[0111] In the multilayer electronic component 100 according to this embodiment, the dielectric material forming the dielectric patterns 141, 142 contains a larger amount of binder, so that the dielectric patterns 141, 142 can have a higher shrinkage rate during sintering than the first dielectric layer 111. This reduces variations in shrinkage rate that occur during the sintering stage of the electronic component, thereby ensuring the reliability of the multilayer electronic component 100.

[0112] Table 1 below shows the shrinkage rates measured according to the binder content of the materials forming each component when manufacturing the multilayer electronic component 100 according to an embodiment of the present invention shown in FIG. 6.

[0113] Here, the shrinkage rates listed in Table 1 correspond to calculated values ​​of theoretical linear shrinkage rates. In this specification, the theoretical linear shrinkage rate may refer to the shrinkage rate when an object having a porosity of a therein experiences isotropic shrinkage in the X, Y, and Z directions, respectively, and the object reaches full densification. Therefore, the theoretical linear shrinkage rate may refer to the linear shrinkage rate in any one of the X, Y, and Z directions.

[0114] Based on this definition, the theoretical linear shrinkage of each material in the experimental examples in Table 1 was calculated using the following formula.

[0115] In other words, when the porosity of each material is a, the theoretical linear shrinkage rate (S_linear) (%) of the material is: S_linear={1-(1-a) (1 / 3)}*100 It can be calculated as follows.

[0116] Furthermore, the binder content of the first dielectric layer refers to the volume ratio of the binder to the total volume, including ceramic materials such as BaTiO3, of the first ceramic green sheet that forms the first dielectric layer before sintering. The binder content of the internal electrode refers to the volume ratio of the binder to the total volume, including conductive metals such as Ni, of the internal electrode paste that forms the internal electrode pattern before sintering. The binder content of the second dielectric layer refers to the volume ratio of the binder to the total volume, including ceramic materials such as BaTiO3, of the second ceramic green sheet that forms the second dielectric layer before sintering. The binder content of the dielectric pattern refers to the volume ratio of the binder to the total volume, including ceramic materials such as BaTiO3, of the dielectric material that forms the dielectric pattern before sintering.

[0117] [Table 1]

[0118] Referring to Table 1 above, it can be seen that the higher the binder content in each component, the higher the theoretical linear shrinkage. Furthermore, in the multilayer electronic component 100 according to one embodiment of the present invention shown in Table 1, the binder content of the dielectric patterns 141 and 142 is set to an intermediate value between the binder contents of the first dielectric layer 111 and the internal electrodes 121 and 122, thereby reducing the variation in shrinkage between the first dielectric layer 111 and the internal electrodes 121 and 122. This reduces the variation in shrinkage between the active portion and the margin portion, and is expected to prevent deterioration in reliability of the multilayer electronic component 100 due to deformation or reverse bonding.

[0119] In addition, when the binder content in the first dielectric layer 111 is the same as that in the internal electrodes 121 and 122, the shrinkage rates between the first dielectric layer 111 and the internal electrodes 121 and 122 are almost the same, which is thought to be why the effects of the above experimental example can be achieved.

[0120] Therefore, according to the present embodiment, when the volume fraction of the binder contained in the first ceramic green sheet is defined as A, the volume fraction of the binder contained in the internal electrode pattern is defined as B, and the volume fraction of the binder contained in the dielectric material is defined as C, the relationship A>C≧B is satisfied.

[0121] In addition, the multilayer electronic component 100 according to an embodiment of the present invention shown in Table 1 has a binder content in the second dielectric layer 116 forming the cover portions 112 and 113 set to an intermediate value between the binder contents in the first dielectric layer 111 and the internal electrodes 121 and 122, thereby reducing variations in shrinkage rate between the active portion and the cover portions 112 and 113. This is expected to prevent the cover portions 112 and 113 from being separated and damaged due to uneven deformation of the multilayer electronic component 100.

[0122] 6 and 7, it can be seen that the multilayer electronic component 100 according to an embodiment of the present invention shown in Fig. 6 has a relatively small variation between the average size of the dielectric crystal grains included in the active portion and the average size of the dielectric crystal grains included in the margin portion. In contrast, the conventional multilayer electronic component shown in Fig. 7 has a relatively large variation between the average size of the dielectric crystal grains included in the active portion and the average size of the dielectric crystal grains included in the margin portion.

[0123] More specifically, the average size of each dielectric crystal grain was measured from each photograph, and in Figure 7(a), the average size of the dielectric crystal grains in the dielectric layer included in the active section was 0.28 μm, and the average size of the dielectric crystal grains arranged in the margin section was 0.42 μm. Also, in Figure 7(b), the average size of the dielectric crystal grains in the dielectric layer included in the active section was 0.32 μm, and the average size of the dielectric crystal grains arranged in the margin section was 0.42 μm.

[0124] That is, in conventional multilayer electronic components, the average size of the dielectric crystal grains in the dielectric layer included in the active section and the marginal section differs by approximately 100 nm to 140 nm.

[0125] In contrast, in Figure 6(a), the average size of the dielectric crystal grains in the first dielectric layer included in the active section was 0.27 μm, and the average size of the dielectric crystal grains in the margin section was 0.32 μm. Also, in Figure 6(b), the average size of the dielectric crystal grains in the first dielectric layer included in the active section was 0.31 μm, and the average size of the dielectric crystal grains in the margin section was 0.32 μm.

[0126] That is, according to one embodiment of the present invention, the average size of the dielectric crystal grains of the first dielectric layer 111 arranged in the area overlapping with the internal electrodes 121, 122 in the active portion and the average size of the dielectric crystal grains arranged in the margin portion can have a variation of 50 nm or less.

[0127] In this way, in the active portion, the variation between the average size of the dielectric crystal grains of the first dielectric layer 111 arranged in the area overlapping with the internal electrodes 121, 122 and the average size of the dielectric crystal grains arranged in the margin portion is relatively small, which has the effect of suppressing the occurrence of leakage current at the tip portions of the internal electrodes 121, 122.

[0128] FIG. 8 is an exploded perspective view showing a main body in which dielectric layers and internal electrodes are stacked according to another embodiment of the present invention.

[0129] The main body 110-2 according to this embodiment includes an active portion including a plurality of first dielectric layers 111 and a plurality of internal electrodes 121, 122 arranged alternately with the first dielectric layers 111 sandwiched therebetween, and cover portions 112', 113' arranged at both ends in the stacking direction.

[0130] At this time, dielectric patterns 141 and 142 may be formed on the first dielectric layers 111 on which the first and second internal electrodes 121 and 122 are disposed, respectively.

[0131] 8, the covers 112' and 113' according to this embodiment may be formed by alternately arranging first dielectric layers 111 and second dielectric layers 116a. For example, the covers 112' and 113' may be formed by alternately laminating the first dielectric layers 111 and the second dielectric layers 116a, or by first coating the second dielectric layers 116a on each first dielectric layer 111 and then laminating the second dielectric layers 116a.

[0132] Here, the first dielectric layer 111 may be the same as the first dielectric layer 111 included in the active portion where the internal electrodes 121 and 122 are formed.

[0133] According to this embodiment, the second dielectric layer 116a included in the cover portions 112' and 113' may have the same or different dielectric composition as the dielectric patterns 141 and 142, as described above. In addition, the second dielectric layer 116a and the dielectric patterns 141 and 142 may have the same or different porosities.

[0134] In this case, the second dielectric layer 116a may be formed to have some or all of the same properties as the internal electrodes 121 and 122, such as having the same porosity or shrinkage rate as the internal electrodes 121 and 122.

[0135] 8, unlike the embodiment shown in FIG. 4, first and second dielectric layers 111 and 116a are alternately stacked. By including the first dielectric layer 111 in common between the cover portions 112 and 113 and the active portion, the variation in the average size of the dielectric crystal grains can be reduced. Furthermore, the variation in the shrinkage rate between the cover portions 112 and 113 and the active portion can be more effectively reduced.

[0136] 9 is a cross-sectional view taken along line II' showing a modified example of the multilayer electronic component of FIG. 2, and FIG. 10 is a planar front view showing the first internal electrode of FIG. 9 cut along line XY.

[0137] 9 and 10, the multilayer electronic component 101 according to this modified example includes a main body 110-3 including a plurality of first dielectric layers 111 and a plurality of internal electrodes 121, 122 arranged alternately with the first dielectric layers 111 sandwiched therebetween, and external electrodes 131, 132 arranged outside the main body 110-3 and connected to the internal electrodes 121, 122.

[0138] Here, dielectric patterns 141a, 141b, 142a, and 142b may be formed in marginal portions where the plurality of internal electrodes 121 and 122 are not formed. The dielectric patterns 141a, 141b, 142a, and 142b according to this modification may include first dielectric patterns 141a and 141b formed in the same layer as the first internal electrode 121 and second dielectric patterns 142a and 142b formed in the same layer as the second internal electrode 122.

[0139] 10, the first dielectric patterns 141a and 141b may include a peripheral portion 141a that does not overlap with the first internal electrode 121 and an overlapping portion 141b that overlaps with the first internal electrode 121. That is, the first dielectric patterns 141a and 141b may overlap with the first internal electrode 121 in at least a portion of the area in the stacking direction (first direction).

[0140] Similarly, the second dielectric patterns 142a, 142b may include a peripheral portion 142a that does not overlap with the second internal electrode 122 and an overlapping portion 142b that overlaps with the second internal electrode 122. That is, the second dielectric patterns 142a, 142b may overlap with the second internal electrode 122 in at least a portion of the region in the stacking direction (first direction).

[0141] In this way, by forming the dielectric patterns 141a, 141b, 142a, and 142b of this modified example so that they overlap with the internal electrodes 121 and 122 in some areas, it becomes easier to print the dielectric material that forms the dielectric patterns 141a, 141b, 142a, and 142b.

[0142] In this case, the adhesive strength between the dielectric patterns 141a, 141b, 142a, 142b and the internal electrodes 121, 122 can be further strengthened. This in turn strengthens the bonding strength between the margin portion and the active portion of the body 110-3, thereby ensuring the durability and reliability of the multilayer electronic component 101. That is, despite deformation due to sintering, reverse bonding or separation between the margin portion and the active portion can be prevented.

[0143] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments and the accompanying drawings, but is limited only by the appended claims. Therefore, various substitutions, modifications, and changes may be made by a person skilled in the art without departing from the technical spirit of the present invention as set forth in the claims, and these also fall within the scope of the present invention. [Explanation of symbols]

[0144] 100, 101: Multilayer electronic components 110, 110-1, 110-2, 110-3: Main body 111: First dielectric layer 112, 113: Cover part 114, 115: Margin 116: Second dielectric layer 121, 122: First and second internal electrodes 131, 132: First and second external electrodes 141, 142: Dielectric pattern

Claims

1. a main body including an active section in which a plurality of first dielectric layers and internal electrodes are alternately arranged, and cover sections each including a second dielectric layer, the cover sections being arranged on both ends of the active section in a first direction in which the plurality of first dielectric layers are stacked; an external electrode disposed outside the body and connected to the internal electrode, the main body includes a margin portion covering the remaining side surfaces of the internal electrodes except for the side surfaces connected to the external electrodes, a first dielectric layer included in the active portion and a dielectric pattern included in the margin portion each include pores, and the dielectric pattern has a higher porosity than the first dielectric layer.

2. The multilayer electronic component according to claim 1 , wherein the porosity of the first dielectric layer included in the active portion is different from the porosity of the cover portion.

3. 3. The multilayer electronic component according to claim 1, wherein the cover portion is formed by laminating the second dielectric layer.

4. The multilayer electronic component according to claim 1 , wherein the cover portion is formed by alternately arranging the first dielectric layers and the second dielectric layers.

5. 5. The multilayer electronic component according to claim 1, wherein the dielectric composition of the dielectric pattern and the dielectric composition of the second dielectric layer are the same.

6. 6. The multilayer electronic component according to claim 1, wherein, in the active portion, an average size of the dielectric crystal grains of the first dielectric layer arranged in a region overlapping with the internal electrode and an average size of the dielectric crystal grains arranged in the margin portion have a variation of 50 nm or less.

7. The multilayer electronic component according to claim 1 , wherein the dielectric pattern and the internal electrode overlap each other in at least a portion of the first direction.

8. 8. The multilayer electronic component according to claim 1, wherein, when an average height of the dielectric pattern in the first direction is defined as t1 and an average height of the internal electrodes in the first direction is defined as t2, t1 satisfies 0.3t2≦t1≦0.9t2.

9. The body includes: the first and second surfaces facing each other in the first direction, the third and fourth surfaces connected to the first and second surfaces and facing each other in a second direction perpendicular to the first direction, and the fifth and sixth surfaces connected to the first and fourth surfaces and facing each other in a third direction perpendicular to the first and second directions, The internal electrode is 9. The multilayer electronic component according to claim 1, comprising: a first internal electrode connected to the third surface of the main body and spaced apart from the fourth, fifth, and sixth surfaces; and a second internal electrode connected to the fourth surface and spaced apart from the third, fifth, and sixth surfaces.

10. providing a plurality of first ceramic green sheets on which a plurality of first internal electrode patterns are formed and a plurality of first ceramic green sheets on which a plurality of second internal electrode patterns are formed; providing a dielectric material on at least a portion of a remaining area of ​​each of the plurality of first ceramic green sheets excluding the first internal electrode pattern and the second internal electrode pattern; laminating the plurality of first ceramic green sheets so that the first internal electrode patterns and the second internal electrode patterns intersect, and laminating second ceramic green sheets on both ends of the first ceramic green sheets in a lamination direction to form a laminate body; and firing the laminated body to provide a body including an active portion including a first dielectric layer, an internal electrode, and a dielectric pattern, and a cover portion including a second dielectric layer; each of the first dielectric layer and the dielectric pattern includes pores; The method for manufacturing a multilayer electronic component, wherein the dielectric pattern has a higher porosity than the first dielectric layer.

11. The method of manufacturing a multilayer electronic component according to claim 10 , wherein the porosity of the first dielectric layer included in the active portion is different from the porosity of the cover portion.

12. 12. The method for manufacturing a multilayer electronic component according to claim 10, wherein the dielectric composition of the second ceramic green sheet and the composition of the dielectric material are the same.

13. The step of providing a dielectric material on at least a portion of the remaining area of ​​each of the plurality of first ceramic green sheets excluding the first internal electrode pattern and the second internal electrode pattern includes: The method for manufacturing a multilayer electronic component according to claim 10 , further comprising providing the dielectric material so that the first internal electrode pattern and the second internal electrode pattern partially overlap each other.

14. 14. The method for manufacturing a multilayer electronic component according to claim 10, wherein, when an average height of the dielectric pattern in the stacking direction is defined as t1 and an average height of the internal electrodes in the stacking direction is defined as t2, t1 satisfies 0.3t2≦t1≦0.9t2.

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