Signal transmission devices, electronic devices, vehicles

Abstract

A signal transmitting device, according to the present invention, for example, transmits a drive signal of a gate drive transistor between a primary circuit system and a secondary circuit system while insulating between the primary circuit system and the secondary circuit system, and comprises: a first external terminal configured to connect a grounding end of the secondary circuit system; a second external terminal configured so that the terminal voltage changes depending on whether the first external terminal is in an open state; and an open detection circuit that monitors the terminal voltage of the second external terminal and detects whether the first external terminal is open.

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to a signal transmission device, and an electronic device and a vehicle using the same. [Background technology]

[0002] Conventionally, signal transmission devices that transmit signals between a primary circuit system and a secondary circuit system while electrically insulating the primary circuit system and the secondary circuit system have been used in a variety of applications (such as power supply devices or motor drive devices).

[0003] An example of the prior art related to the above is Patent Document 1 by the applicant of the present application. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-011108 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in conventional signal transmission devices, there is room for improvement in detecting GND open in the secondary circuit system.

[0006] In view of the above-mentioned problems discovered by the inventors of the present application, the invention disclosed in this specification aims to provide a signal transmission device capable of detecting a GND open in a secondary circuit system, and an electronic device and a vehicle using the same. [Means for solving the problem]

[0007] For example, the signal transmission device disclosed in this specification transmits a drive signal for a gate drive transistor between a primary circuit system and a secondary circuit system while isolating the primary circuit system from the secondary circuit system, and includes a first external terminal configured to connect to the ground terminal of the secondary circuit system, a second external terminal configured such that the terminal voltage changes depending on whether the first external terminal is in an open state, and an open detection circuit that monitors the terminal voltage of the second external terminal to detect whether the first external terminal is open.

[0008] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto. [Effects of the Invention]

[0009] According to the invention disclosed in this specification, it is possible to provide a signal transmission device capable of detecting a GND open in a secondary circuit system, as well as an electronic device and a vehicle using the same. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. [Figure 2] FIG. 2 is a diagram showing the basic structure of a transformer chip. [Figure 3] FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. [Figure 4] FIG. 4 is a plan view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 8]FIG. 8 is an enlarged view (isolation structure) of region XIII shown in FIG. [Figure 9] FIG. 9 is a diagram schematically illustrating an example of the layout of a transformer chip. [Figure 10] FIG. 10 is a diagram showing an embodiment of a signal transmission device. [Figure 11] FIG. 11 is a diagram showing an example of the configuration of an electronic device in which a signal transmission device is installed. [Figure 12] FIG. 12 is a diagram showing a first connection example (DESAT method) of the short circuit detection terminal. [Figure 13] FIG. 13 is a diagram showing a second connection example (emitter sense system) of the short circuit detection terminal. [Figure 14] FIG. 14 is a diagram illustrating an example of the configuration of an open detection circuit. [Figure 15] FIG. 15 is a diagram illustrating an example of an open detection operation. [Figure 16] FIG. 16 is a diagram showing the appearance of a vehicle in which an electronic device is installed. DETAILED DESCRIPTION OF THE INVENTION

[0011] <Signal transmission device (basic configuration)> 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is configured by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0012] The controller chip 210 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC1 (for example, up to 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0013] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signals S11 or S21 in response to the logic level of the input pulse signal IN.

[0014] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0015] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0016] The driver chip 220 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC2 (for example, up to 30 V with respect to GND2). The driver chip 220 has buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 integrated therein.

[0017] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0018] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0019] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0020] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0021] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0022] More specifically, the transformer 231 outputs a reception pulse signal S12 from the secondary coil 231s in response to a transmission pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a reception pulse signal S22 from the secondary coil 232s in response to a transmission pulse signal S21 input to the primary coil 232p.

[0023] In this way, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0024] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0025] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby enabling reduction in manufacturing costs.

[0026] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs) / plug-in hybrid vehicles (PHVs), or xEVs such as fuel cell electric vehicles (FCEVs) / FCVs (fuel cell electric vehicles)).

[0027] <Trans chip (basic structure)> Next, the basic structure of transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of transformer chip 230. In transformer chip 230 shown in this figure, transformer 231 includes primary coil 231p and secondary coil 231s that face each other in the vertical direction. Transformer 232 includes primary coil 232p and secondary coil 232s that face each other in the vertical direction.

[0028] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0029] The primary coil 231p is laid spirally, starting from a first end connected to the internal terminal X21, so as to surround the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. Meanwhile, the primary coil 232p is laid spirally, starting from a first end connected to the internal terminal X23, so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0030] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged linearly and are used for wire bonding with the controller chip 210.

[0031] The secondary coil 231s is laid in a spiral shape, starting from a first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with a second end corresponding to the end point connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape, starting from a first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with a second end corresponding to the end point connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0032] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0033] <Transformer chip (2-channel type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6.

[0034] 3 to 7, semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. Semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0035] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0036] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0037] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0038] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0039] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0040] The insulating side walls 53A to 53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A to 44D. Specifically, the insulating side walls 53A to 53D are formed flush with the chip side walls 44A to 44D. The insulating side walls 53A to 53D form ground surfaces that are flush with the chip side walls 44A to 44D.

[0041] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0042] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0043] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0044] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0045] The semiconductor device 5 includes a first functional device 45 formed on an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inside the insulating layer 51 at intervals from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0046] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0047] 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0048] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0049] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0050] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0051] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0052] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the shapes shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0053] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0054] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a planar view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a planar view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0055] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0056] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0057] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0058] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0059] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0060] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0061] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0062] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0063] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in plan view.

[0064] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0065] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0066] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0067] The multiple high potential terminals 12 are each formed in an area close to the corresponding transformer 21A to 21D in a plan view. The high potential terminals 12 being close to the transformers 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0068] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0069] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0070] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0071] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0072] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0073] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0074] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0075] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0076] The plurality of first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The plurality of first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first low potential wirings 31, and will not be repeated here.

[0077] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0078] The through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0079] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0080] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0081] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0082] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0083] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0084] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0085] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0086] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0087] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0088] 6 and 7, the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high-potential coils 23), respectively. The plurality of first high-potential wirings 33 each have a similar structure. In the following, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0089] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (multiple in this embodiment) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0090] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulation layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (the first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connection wiring 81 is formed at an interval from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z. Thereby, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the breakdown voltage of the insulation layer 51 is enhanced.

[0091] The plurality of pad plug electrodes 82 are formed in the region between the high-potential terminal 12 (the first high-potential terminal 12A) and the high-potential connection wiring 81 within the uppermost insulation layer 56 and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81, respectively. The plurality of pad plug electrodes 82 each have a planar area less than the planar area of the high-potential connection wiring 81 in a plan view.

[0092] Referring to FIG. 7, it is preferable that the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). It is preferable that the distance D1 exceeds the total thickness DT of the plurality of interlayer insulation layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. It is preferable that the distance D1 is 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the breakdown voltage to be achieved.

[0093] Referring to FIGS. 6 and 7, the semiconductor device 5 includes dummy patterns 85 embedded in the insulation layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0094] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A to 21D. In other words, the dummy pattern 85 does not function as a part of the transformers 21A to 21D. The dummy pattern 85 is formed as a shielding conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses electric field concentration on the high-potential coil 23. In this embodiment, the dummy pattern 85 is routed at a line density per unit area equal to that of the high-potential coil 23. The line density of the dummy pattern 85 being equal to that of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within a range of ±20% of the line density of the high-potential coil 23.

[0095] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0096] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The shorter the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0097] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0098] Dummy patterns 85 include floating dummy patterns formed in an electrically floating state within insulating layer 51 so as to be positioned around transformers 21A to 21D.

[0099] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0100] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0101] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0102] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0103] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0104] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The passive device may include a circuit network in which any two or more of the passive device, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0105] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0106] 5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape at a distance from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0107] The device region 62 is a region including the first functional device 45 (plurality of transformers 21), the second functional device 60, plural low potential terminals 11, plural high potential terminals 12, first low potential wiring 31, second low potential wiring 32, first high potential wiring 33, second high potential wiring 34, and dummy patterns 85. The outer region 63 is a region outside the device region 62.

[0108] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0109] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in plan view.

[0110] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0111] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0112] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, a plurality) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0113] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0114] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) shape.

[0115] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0116] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined as the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0117] 7 and 8, the semiconductor device 5 further includes an isolation structure 130 that is interposed between the semiconductor chip 41 and the seal conductor 61 and electrically isolates the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0118] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0119] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a strip shape along the seal conductor 61 in plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 bites in toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0120] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0121] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0122] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0123] 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0124] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high-potential coil 23 can be increased.

[0125] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0126] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0127] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the low potential terminals 11. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the high potential terminals 12.

[0128] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0129] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0130] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0131] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0132] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0133] The embodiments of the present invention can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0134] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0135] In the above embodiment, an example was described in which the second functional device 60 was formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0136] In the above embodiment, an example was described in which the dummy pattern 85 was formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0137] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes multiple transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0138] <Transformer arrangement> 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0139] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s that forms a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s that forms a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0140] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0141] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0142] That is, pads a5 and b5 are connected to one end of the primary coil forming first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0143] Pads a7 and b7 are connected to one end of the primary coil forming third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0144] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0145] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0146] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break occurs in each coil, but also to appropriately reject defective products in which an abnormal resistance value occurs in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0147] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0148] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0149] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminal of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0150] Here, the first transformer 301 to the fourth transformer 304 are arranged in a manner that couples them in the respective signal transmission directions, as shown in Fig. 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302 that transmit signals from the primary-side chip to the secondary-side chip are connected as a first pair by a first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 that transmit signals from the secondary-side chip to the primary-side chip are connected as a second pair by a second guard ring 306.

[0151] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0152] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0153] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0154] 9, the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are preferably wound in a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. This configuration increases the area where the primary coil and secondary coil overlap, thereby improving the transmission efficiency of the transformer.

[0155] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0156] <Signal transmission device (embodiment)> 10 is a diagram showing an embodiment of a signal transmission device. The signal transmission device 400 of this embodiment is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 400p to the secondary circuit system 400s and drives the gate of a power transistor (not shown) provided in the secondary circuit system 400s while electrically insulating the primary circuit system 400p (VCC1-GND1 system) from the secondary circuit system 400s (VCC2-GND2 system). The signal transmission device 400 can be understood as corresponding to the signal transmission device 200 described above.

[0157] The signal transmission device 400 has a plurality of external terminals (in this figure, power supply terminals VCC1 and VCC2, ground terminals GND1 and GND2, negative power supply terminal VEE2, input terminals INA and INB, output terminals OUT1H and OUT1L, fault terminal FLT, ready terminal RDY, and short circuit detection terminal SCPIN) as means for establishing electrical connection with the outside of the device.

[0158] On a first side (= the left side in this drawing) of the package forming the signal transmission device 400, there are arranged, from top to bottom, a ground terminal GND1, a fault terminal FLT, an input terminal INA, an input terminal INB, a ready terminal RDY, a power supply terminal VCC1, and a ground terminal GND1. On the other hand, on a second side (= the side opposite to the first side, and the right side in this drawing) of the same package, there are arranged, from top to bottom, a negative power supply terminal VEE2, an output terminal OUT1L, an output terminal OUT1H, a power supply terminal VCC2, a short-circuit detection terminal SCPIN, a ground terminal GND2, and a negative power supply terminal VEE2.

[0159] In this way, the external terminals of the primary circuit system 400p (GND1, FLT, INA and INB, RDY, and VCC1) can be concentrated on the first side of the package, and the external terminals of the secondary circuit system 400s (VEE2, OUT1L, OUT1H, VCC2, SCPIN, and GND2) can be concentrated on the second side of the package.

[0160] A ground terminal GND1 and a negative power supply terminal VEE2 should be disposed at both ends of each of the first and second sides of the package. That is, two ground terminals GND1 and two negative power supply terminals VEE2 should be provided.

[0161] The signal transmission device 400 can be widely applied to a wide range of applications (such as motor drivers or DC / DC converters that handle high voltages) that require signal transmission between the primary circuit system 400p and the secondary circuit system 400s while isolating them from each other.

[0162] Continuing with reference to Fig. 10, the internal configuration of the signal transmission device 400 will be described. The signal transmission device 400 of this configuration example is configured by sealing a controller chip 410 (corresponding to the first chip), a driver chip 420 (corresponding to the second chip), and a transformer chip 430 (corresponding to the third chip) in a single package.

[0163] The controller chip 410 is a semiconductor chip that integrates circuit elements of a primary circuit system 400p that operates upon receiving a power supply voltage VCC1 (for example, a maximum of 7 V relative to GND1). The controller chip 410 also integrates, for example, a logic circuit 411, a UVLO (under-voltage lock out) / OVLO (over-voltage lock out) circuit 412, and NMOSFETs 413 and 414.

[0164] The logic circuit 411 generates a drive pulse signal PWM for a power transistor (not shown) in response to the input pulse signals INA and INB. For example, if INB=H (logical level when disabled), PWM=L (fixed value), and if INB=L (logical level when enabled), PWM=INA. The logic circuit 411 also monitors various abnormality detection signals (low voltage, overvoltage, short circuit, open circuit, overheat, load power supply abnormality, etc.) from the signal transmission device 400 and drives NMOSFETs 413 and 414 based on the monitoring results, thereby determining the logical levels of the fault signal FLT and the ready signal RDY.

[0165] The UVLO / OVLO circuit 412 detects an undervoltage / overvoltage of the power supply voltage VCC1, and outputs the detection result to the logic circuit 411.

[0166] The NMOSFET 413 connects / disconnects the fault terminal FLT and the ground terminal in response to an instruction from the logic circuit 411. For example, when the driver chip 420 detects overheating or an abnormality in the load power supply, the NMOSFET 413 turns on and the fault terminal FLT goes low (= the logic level when an abnormality is detected).

[0167] The NMOSFET 414 connects / disconnects the ready terminal RDY and the ground terminal in response to an instruction from the logic circuit 411. For example, when a low voltage or an overvoltage is detected in either the controller chip 410 or the driver chip 420, the NMOSFET 414 turns on and the ready terminal RDY goes low (= the logic level when an abnormality is detected).

[0168] The driver chip 420 is a semiconductor chip that integrates circuit elements of the secondary circuit system 400s that operates upon receiving a supply of power supply voltage VCC2 (for example, up to 30 V with respect to GND2). The driver chip 420 integrates, for example, a logic circuit 421, a UVLO / OVLO circuit 422, a comparator 423, a PMOSFET 424, and NMOSFETs 425 and 426.

[0169] The logic circuit 421 drives the gates of power transistors (not shown) connected to the output terminals OUT1H and OUT1L by turning on / off the PMOSFET 424 and the NMOSFET 425 in response to a drive pulse signal PWM input via the transformer chip 430. The output terminals OUT1H and OUT1L may be short-circuited to each other outside the signal transmission device 400. The logic circuit 421 also has a function of transmitting various abnormality detection signals (low voltage, overvoltage, short circuit, open, overheat, load power supply abnormality, etc.) from the driver chip 420 to the controller chip 410 via the transformer chip 430.

[0170] The UVLO / OVLO circuit 422 detects an undervoltage / overvoltage of the power supply voltage VCC2, and outputs the detection result to the logic circuit 421.

[0171] The comparator 423 monitors the terminal voltage of the short-circuit detection terminal SCPIN to detect a short circuit in the power transistor (details will be described later).

[0172] The PMOSFET 424 is one of the gate drive transistors, and connects / disconnects the power supply terminal and the output terminal OUT1H in response to an instruction from the logic circuit 421. For example, when the drive pulse signal PWM is at a high level, the PMOSFET 424 turns on, and the output terminal OUT1H (and therefore the output pulse signal applied to the gate of the power transistor) becomes a high level.

[0173] The NMOSFET 425 is one of the gate drive transistors, and connects / disconnects the output terminal OUT1L and the ground terminal in response to an instruction from the logic circuit 421. For example, when the drive pulse signal PWM is at a low level, the NMOSFET 425 turns on, and the output terminal OUT1L (and therefore the output pulse signal applied to the gate of the power transistor) becomes a low level.

[0174] In this way, the PMOSFET 424 and the NMOSFET 425 function as a half-bridge output stage (CMOS (complementary MOS) inverter stage) for gate driving.

[0175] The NMOSFET 426 establishes / disconnects conduction between the ground terminal GND2 and the short-circuit detection terminal SCPIN in response to an instruction from the logic circuit 421. For example, the NMOSFET 426 is turned off when OUT1H=H, and turned on when OUT1H=L. The NMOSFET 426 functions as a discharge switch that discharges an external capacitor (not shown) connected between SCPIN and GND2 by turning on / off complementary to the PMOSFET 424 (and hence a power transistor not shown) (details will be described later).

[0176] The transformer chip 430 is a semiconductor chip that integrates a transformer for transmitting signals in both directions while insulating the controller chip 410 and the driver chip 420 from each other.

[0177] The signal transmission device 400 of this embodiment has an independent transformer chip 430 equipped with only a transformer, in addition to the controller chip 410 and the driver chip 420, and these three chips are sealed in a single package.

[0178] With this configuration, the controller chip 410 and the driver chip 420 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby enabling reduction in manufacturing costs.

[0179] Furthermore, the controller chip 410 and the driver chip 420 can both be manufactured using existing processes with a proven track record, and there is no need to conduct new reliability tests, which contributes to shortening development time and reducing development costs.

[0180] Furthermore, even when a DC isolation element other than a transformer (e.g., a photocoupler) is used, it can be easily accommodated by simply replacing the transformer chip 430, eliminating the need to redevelop the controller chip 410 and the driver chip 420, thereby contributing to shortening the development period and reducing development costs.

[0181] <Electronic equipment> 11 is a diagram showing an example of the configuration of an electronic device equipped with a signal transmission device 400. Electronic device A of this example configuration has an upper gate driver IC1H(u / v / w), a lower gate driver IC1L(u / v / w), upper power transistors 2H(u / v / w), lower power transistors 2L(u / v / w), an ECU 3, and a motor 4.

[0182] The upper gate drivers IC1H(u / v / w) drive the upper power transistors 2H(u / v / w) by generating upper gate drive signals in response to upper gate control signals input from the ECU 3 while insulating the ECU 3 from the upper power transistors 2H(u / v / w).

[0183] The lower gate drivers IC1L(u / v / w) drive the lower power transistors 2L(u / v / w) by generating lower gate drive signals in response to lower gate control signals input from the ECU 3 while insulating the ECU 3 from the lower power transistors 2L(u / v / w).

[0184] The signal transmission device 400 described above can be suitably used as the upper gate driver IC1H(u / v / w) and the lower gate driver IC1L(u / v / w).

[0185] The upper power transistors 2H (u / v / w) are connected between the power system power supply terminal (= application terminal of the load power supply voltage PVDD) and each phase input terminal of the motor 4 as upper switches that form a three-phase (U phase / V phase / W phase) half-bridge output stage.

[0186] The lower power transistors 2L (u / v / w) are connected between each phase input terminal of the motor 4 and the power system ground terminal as lower switches that form a three-phase (U phase / V phase / W phase) half-bridge output stage.

[0187] In this figure, an IGBT [insulated gate bipolar transistor] is used as the upper power transistor 2H(u / v / w) and the lower power transistor 2L(u / v / w), but it is also possible to use, for example, a MOSFET [metal oxide semiconductor field effect transistor] instead of the IGBT.

[0188] The ECU 3 drives the upper power transistors 2H (u / v / w) and the lower power transistors 2L (u / v / w) via the upper gate driver IC1H (u / v / w) and the lower gate driver IC1L (u / v / w), respectively, thereby controlling the rotational drive of the motor 4. The ECU 3 also has the function of monitoring the fault terminals FLT and ready terminals RDY of the upper gate driver IC1H (u / v / w) and the lower gate driver IC1L (u / v / w), and performing various safety controls based on the monitoring results.

[0189] The motor 4 is a three-phase motor that is rotationally driven in response to three-phase drive voltages U / V / W input from three-phase (U-phase / V-phase / W-phase) half-bridge output stages.

[0190] <Short circuit (through) detection> FIG. 12 is a diagram showing a first connection example (DESAT method) of the short circuit detection terminal SCPIN, and for convenience of illustration, only one phase of the electronic device A is extracted and shown.

[0191] As shown in this figure, outside the lower gate driver IC1L (signal transmission device 400) that performs short - circuit detection in the DESAT method, a diode D1, resistors R0 to R3, and a capacitor C1 are connected. The first end of resistor R0 is connected to both output terminals OUT1H and OUT1L. The second end of resistor R0 is connected to the gate of the lower power transistor 2L. The first end of resistor R1 is connected to the applied end of the power supply voltage VCC2. The second end of resistor R1 and the first end of resistor R2 are both connected to the anode of diode D1. The cathode of diode D1 is connected to the connection node between the emitter of the upper power transistor 2H and the collector of the lower power transistor 2L. The second end of resistor R2 and the first ends of resistor R3 and capacitor C1 are all connected to the short - circuit detection terminal SCPIN. The second ends of resistor R3 and capacitor C1 are both connected to the ground terminal GND2.

[0192] Also, inside the lower gate driver IC1L, a comparator 423, an NMOSFET 426, and a diode 427 are connected to the short - circuit detection terminal SCPIN.

[0193] The comparator 423 compares the short - circuit detection voltage SCPIN ( = the terminal voltage of the short - circuit detection terminal SCP) input to the inverting input terminal (-) with a predetermined threshold voltage Vth to generate a short - circuit detection signal SCP. The short - circuit detection signal SCP becomes a high level ( = the normal logic level) when SCPIN < Vth, and becomes a low level ( = the abnormal logic level) when SCPIN > Vth.

[0194] The NMOSFET 426 functions as a discharge switch that discharges the externally attached capacitor C1 between SCPIN and GND2 by turning on / off complementarily with the lower power transistor 2L and the PMOSFET 424 to conduct / block between the ground terminal GND2 and the short - circuit detection terminal SCPIN. For example, the NMOSFET 426 turns off during the on - period of the lower power transistor 2L and the PMOSFET 424, and turns on during the off - period of the lower power transistor 2L and the PMOSFET 424.

[0195] The diode 427 is an electrostatic protection diode having an anode connected to the ground terminal GND2 and a cathode connected to the short circuit detection terminal SCPIN.

[0196] In a normal state (= a state in which the upper power transistor 2H is off and the lower power transistor 2L is on), the cathode voltage Vx of the diode D1 drops to approximately the ground voltage GND2. Therefore, the diode D1 is forward biased, and the anode voltage Vy of the diode D1 becomes approximately the forward drop voltage Vf. At this time, the short-circuit detection voltage SCPIN (= {R3 / (R2+R3)×Vf}) becomes lower than the threshold voltage Vth, and the short-circuit detection signal SCP becomes high level (= normal logic level).

[0197] On the other hand, in a short-circuit state (= a state in which the upper power transistor 2H and the lower power transistor 2L are simultaneously turned on and an excessive short-circuit current may flow), the cathode voltage Vx of diode D1 rises to approximately the load power supply voltage PVDD. Therefore, diode D1 is reverse biased, and the anode voltage Vy of diode D1 becomes approximately the power supply voltage VCC2. At this time, the short-circuit detection voltage SCPIN (= {R3 / (R2+R3)×VCC2}) becomes higher than the threshold voltage Vth, and the short-circuit detection signal SCP becomes low level (= logic level during abnormality).

[0198] In this way, in the DESAT method, by monitoring the short-circuit detection voltage SCPIN, it is possible to detect whether the collector-emitter of the lower power transistor 2L is in an unsaturated state, i.e., whether the upper power transistor 2H and the lower power transistor 2L are in a short-circuited state (simultaneous ON state).

[0199] The logic circuit 421 has a protection function of forcibly turning off the lower power transistor 2L when the short-circuit detection signal SCP becomes low level (=logical level during abnormality). After forcibly turning off the lower power transistor 2L, the logic circuit 421 can release the short-circuit detection state by turning on the NMOSFET 426 and discharging the capacitor C1.

[0200] FIG. 13 is a diagram showing a second connection example (emitter sense method) of the short circuit detection terminal SCPIN, and like the above-mentioned FIG. 12, only one phase of the electronic device A is extracted and shown.

[0201] As shown in the figure, resistors R0, R4, and R5 and a capacitor C1 are connected to the outside of the lower gate driver IC1L (signal transmission device 400) that performs emitter-sensing short-circuit detection. A first terminal of the resistor R0 is connected to both output terminals OUT1H and OUT1L. A second terminal of the resistor R0 is connected to the gate of the lower power transistor 2L. The first terminals of the resistor R4 and the capacitor C1 are both connected to the short-circuit detection terminal SCPIN. The second terminal of the resistor R4 and the first terminal of the resistor R5 are both connected to the emitter (sensing emitter) of the lower power transistor 2L. The second terminals of the resistor R5 and the capacitor C1 are both connected to the ground terminal GND2.

[0202] In the normal state (= the state where the upper power transistor 2H is off and the lower power transistor 2L is on), an excessive short-circuit current does not flow through the resistor R5, so the voltage Vz across the resistor R5 drops to approximately the ground voltage GND2. At this time, the short-circuit detection voltage SCPIN (≈Vz) becomes lower than the threshold voltage Vth, so the short-circuit detection signal SCP becomes high level (= the normal logic level).

[0203] On the other hand, in a short-circuit state (a state in which the upper power transistor 2H and the lower power transistor 2L are simultaneously turned on and an excessive short-circuit current may flow), the voltage Vz across resistor R5 rises to a voltage value (=Isc×R5) corresponding to the short-circuit current Isc. At this time, the short-circuit detection voltage SCPIN (≒Vz) becomes higher than the threshold voltage Vth, so the short-circuit detection signal SCP becomes low level (=logical level during an abnormality).

[0204] In this way, with the emitter sense method, by monitoring the short circuit detection voltage SCPIN, it is possible to detect whether or not an excessively large short circuit current Isc is flowing through the lower power transistor 2L, i.e., whether or not the upper power transistor 2H and the lower power transistor 2L are in a short circuit state (simultaneous ON state).

[0205] <Open detection circuit> 14 is a diagram showing an example of the configuration of an open circuit detection circuit. The open circuit detection circuit 429 of this example is a circuit block provided in the driver chip 420 for detecting whether the ground terminal GND2 of the secondary circuit system 400s is in an open state, and includes a comparator 4291 and a mask processing unit 4292. This diagram also shows an electrostatic protection diode 428 connected between the negative power supply terminal VEE2 and the ground terminal GND2. In the following description, the terminal voltage of the ground terminal GND2 (the voltage inside the IC) may be referred to as the internal GND2.

[0206] The comparator 4291 generates a comparison signal SC by comparing the terminal voltage of the ground terminal GND2 input to the non-inverting input terminal (+) with the short-circuit detection terminal SCPIN input to the inverting input terminal (-). The comparison signal SC goes high when the difference between the terminal voltages of the ground terminal GND2 and the short-circuit detection terminal SCPIN (=internal GND2-SCPIN) is higher than a predetermined threshold, and goes low when it is lower than the predetermined threshold. The circuit configuration of the comparator 4291 may be the same as that of the comparator 423.

[0207] The mask processing unit 4292 performs mask processing on the comparison signal SC for a predetermined mask period. For convenience of illustration, the figure depicts the fault signal FLT as being directly output from the mask processing unit 4292, but in reality, the output signal of the mask processing unit 4292 (corresponding to the open detection result of the ground terminal GND2) is subjected to a logical operation with other abnormality detection signals (e.g., detection signals of overheating or load power supply abnormality) in the driver chip 420, and then transmitted to the logic circuit 411 of the controller chip 410 via the transformer chip 430. The logic circuit 411 switches the NMOSFET 413 on / off to determine the logical level of the fault signal FLT.

[0208] As described above, the lower gate driver IC1L (signal transmission device 400) of this configuration example has a first external terminal (e.g., ground terminal GND2) configured to connect to the ground end of the secondary circuit system 400s, a second external terminal (e.g., short circuit detection terminal SCPIN) configured such that the terminal voltage changes depending on whether the first external terminal is in an open state or not, and an open detection circuit 429 that monitors the terminal voltage of the second external terminal to detect whether the first external terminal is in an open state.

[0209] The open circuit detection operation by the open circuit detection circuit 429 will be described in detail below with reference to FIG. 15 as well as this figure.

[0210] 15 is a diagram showing an example of open circuit detection operation, and depicts, from top to bottom, the input pulse signal INA, the output pulse signal OUT1H, the on / off state of the NMOSFET 426, the terminal voltages (solid and dashed lines) of the ground terminal GND2 and the short circuit detection terminal SCPIN, the comparison signal SC, and the fault signal FLT. Note that in the following description, the terminal voltage of the ground terminal GND2 (voltage inside the IC) may be referred to as internal GND2, and the ground voltage outside the IC may be referred to as external GND2 to distinguish between them.

[0211] When the input pulse signal INA is at a low level, the output pulse signal OUT1H also becomes low level, so that the lower-side power transistor 2L is turned off (the upper-side power transistor 2H is turned on). At this time, the NMOSFET 426, which functions as a discharge switch for the capacitor C1, turns on, so that a short circuit occurs between the ground terminal GND2 and the short-circuit detection terminal SCPIN. Therefore, the terminal voltages of the ground terminal GND2 and the short-circuit detection terminal SCPIN become approximately the same value (SCPIN ≈ internal GND2). As a result, the comparison signal SC becomes high level (= normal logic level), and by extension, the fault signal FLT becomes high level (= a state in which the NMOSFET 413 is turned off and the fault terminal FLT is at high impedance).

[0212] On the other hand, when the ground terminal GND2 is in an open state, as shown by the thin dashed-dotted arrow in Figure 14, a circuit current IGND2 flows from the power supply terminal VCC2 toward the short-circuit detection terminal SCPIN through the circuit group of the secondary circuit system 400s (indicated as GND2SYS in the figure), the internal wiring connected to the ground terminal GND2 (= the ground line inside the IC), and the NMOSFET 426 in the on state.

[0213] This circuit current IGND2 flows from the short-circuit detection terminal SCPIN to the outside of the low-side gate driver IC1L (signal transmission device 400) and reaches the ground terminal of the secondary circuit system 400s via resistors R4 and R5. As a result, the terminal voltage of the short-circuit detection terminal SCPIN rises to a voltage value (= IGND2 × (R4 + R5)) based on the circuit current IGND2 and resistors R4 and R5, relative to the external GND2. However, since the NMOSFET 426 is on during the low-level period of the output pulse signal OUT1H, the terminal voltages of the ground terminal GND2 and the short-circuit detection terminal SCPIN remain the same (SCPIN ≈ internal GND2). Therefore, the comparison signal SC is maintained at a high level, and consequently, the fault signal FLT also remains at a high level.

[0214] The resistance values ​​of the resistors R4 and R5 should be set appropriately so that even if the terminal voltage of the ground terminal GND2 (internal GND2) rises, it will not exceed the withstand voltage of the diode 428 connected between the ground terminal GND2 and the negative power supply terminal VEE.

[0215] Thereafter, when the input pulse signal INA rises to a high level, the output pulse signal OUT1H also rises to a high level, so that the lower-side power transistor 2L turns on (the upper-side power transistor 2H turns off). At this time, the NMOSFET 426 turns off, so that the circuit current IGND2 flows through the forward-biased diode 427 or the body diode of the NMOSFET 426, as indicated by the thin two-dot chain arrow in FIG.

[0216] Therefore, the terminal voltage of the ground terminal GND2 is higher than the terminal voltage of the short-circuit detection terminal SCPIN by the forward drop voltage Vf of the diode 427 (or the body diode of the NMOSFET 426) (internal GND2 = SCPIN + Vf, i.e., internal GND2 > SCPIN). As a result, the comparison signal SC goes low (= the logic level when an open circuit is detected), and ultimately, the fault signal FLT is latched low (= the NMOSFET 413 is on) in the logic circuit 411 of the controller chip 410. The threshold value (= GND2 open circuit detection voltage) of the comparator 4291 should be set appropriately taking into account variations in the forward drop voltage Vf (approximately 0.2 V, lower than the minimum value of the forward drop voltage Vf).

[0217] The ECU3 can detect abnormalities in the lower gate driver IC1L (including an open circuit at the ground terminal GND2) by monitoring the fault signal FLT. The fault signal FLT can be unlatched, for example, by restarting the enable signal for the lower gate driver IC1L (signal transmission device 400) from the ECU3.

[0218] As mentioned above, the open detection circuit 429 includes a mask processing unit 4292, which performs mask processing on the comparison signal SC so that the logic level of the fault signal FLT does not change until the mask period T2 (for example, a minimum of 10 μs) has elapsed since the comparison signal SC was pulled down to low level. This makes it possible to prevent erroneous open detection due to noise.

[0219] When the NMOSFET 426 is on, SCPIN is approximately equal to the internal GND2, and therefore open detection of the ground terminal GND2 cannot be performed. Conversely, open detection of the ground terminal GND2 must be performed when the NMOSFET 426 is off. The NMOSFET 426 is off during the high-level period of the output pulse signal OUT1H (and therefore during the on-period of the lower-side power transistor 2L), and open detection of the ground terminal GND2 must be performed during this period.

[0220] For example, if the switching frequency of the output pulse signal OUT1H is 10 kHz and the duty is 50%, the high-level period of the output pulse signal OUT1H is 50 μs (assuming that the high-level period T1 of the input pulse signal INA is 50 μs or more). In view of this, the mask period T2 should be set shorter than the on-period of the lower power transistor 2L (for example, the high-level period T1 of the input pulse signal INA), and it is desirable to set T2 to, for example, 20 μs (at most 35 μs).

[0221] Furthermore, the delay time from when an open circuit is detected until the fault signal FLT falls to low level (the time required for transformer transmission and logic processing) is preferably about 10 to 36 μs.

[0222] The external terminal to which the open detection circuit 429 is connected is not limited to the short detection terminal SCPIN, but may be any external terminal configured such that the terminal voltage changes depending on whether the ground terminal GND2 is in an open state or not (for example, an external terminal that is connected to the ground terminal GND2 via a diode and through which a circuit current flows from the ground line inside the device via a forward-biased diode when the ground terminal GND2 is in an open state).

[0223] Therefore, if the terminal voltage of the short circuit detection terminal SCPIN is not monitored by the open detection circuit 429, in other words, if there is no element that shorts between the external terminal whose terminal voltage is to be monitored and the ground terminal GND2, there is no need to consider the constraint of the mask period T2 as described above.

[0224] Furthermore, although not shown in the figure, even if the ground terminal GND2 is in an open state when the input pulse signal INA is at a high level, the difference value (= internal GND2 - SCPIN) between the terminal voltages of the ground terminal GND2 and the short circuit detection terminal SCPIN will be higher than a predetermined threshold value, as described above, so open detection will be possible.

[0225] In the above description, an example has been given in which the fault signal FLT is used to notify the ECU 3 of the open detection result of the ground terminal GND2, but a similar notification can also be made using, for example, the ready signal RDY. In this case, the output signal of the mask processing unit 4292 (corresponding to the open detection result of the ground terminal GND2) is logically operated with the UVLO / OVLO detection signal in the driver chip 420, and then transmitted to the logic circuit 411 of the controller chip 410 via the transformer chip 430. The logic circuit 411 switches the NMOSFET 414 on and off, thereby determining the logical level of the ready signal RDY.

[0226] <Application to vehicles> 16 is a diagram showing the appearance of a vehicle equipped with electronic devices. Vehicle B of this configuration example is equipped with electronic devices B11 to B18 that operate by receiving power supply from a battery (not shown).

[0227] Vehicle B includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0228] It should be noted that the mounting positions of the electronic devices B11 to B18 in this figure may differ from the actual positions for the sake of convenience.

[0229] The electronic device B11 is an electronic control unit that performs engine-related controls (such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto-cruise control) or motor-related controls (such as torque control and power regeneration control).

[0230] The electronic device B12 is a lamp control unit that controls the turning on and off of a high intensity discharged lamp (HID) or a daytime running lamp (DRL).

[0231] The electronic device B13 is a transmission control unit that controls the transmission.

[0232] The electronic device B14 is a braking unit that performs control related to the movement of the vehicle B (ABS (anti-lock brake system) control, EPS (electric power steering) control, electronic suspension control, etc.).

[0233] The electronic device B15 is a security control unit that controls the driving of door locks, burglar alarms, and the like.

[0234] Electronic equipment B16 is electronic equipment that is installed in vehicle B at the factory as standard equipment or manufacturer options, such as wipers, electric door mirrors, power windows, dampers (shock absorbers), an electric sunroof, and electric seats.

[0235] The electronic device B17 is an electronic device that is optionally installed in the vehicle B as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0236] The electronic device B18 is an electronic device equipped with a high-voltage motor, such as an in-vehicle blower, an oil pump, a water pump, or a battery cooling fan.

[0237] The electronic devices B11 to B18 can be understood as specific examples of the previously described electronic device A. That is, the signal transmitters 200 and 400 described above can be incorporated into any of the electronic devices B11 to B18.

[0238] <Summary> The following will provide a general overview of the various embodiments described above.

[0239] For example, the signal transmission device disclosed in this specification transmits a drive signal for a gate drive transistor between a primary circuit system and a secondary circuit system while isolating the primary circuit system from the secondary circuit system, and is configured (first configuration) to have a first external terminal configured to connect to the ground terminal of the secondary circuit system, a second external terminal configured so that the terminal voltage changes depending on whether the first external terminal is in an open state, and an open detection circuit that monitors the terminal voltage of the second external terminal and detects whether the first external terminal is open.

[0240] The signal transmission device having the first configuration may be configured (second configuration) to further include a diode having an anode connected to the first external terminal and a cathode connected to the second external terminal.

[0241] Furthermore, the signal transmission device having the above-mentioned first or second configuration may be configured (third configuration) to further include a discharge switch that establishes / disconnects conduction between the first external terminal and the second external terminal in a complementary manner to the gate drive transistor.

[0242] In addition, in the signal transmission device having the third configuration, the open detection circuit may be configured (fourth configuration) to perform the open detection when the discharge switch is turned off.

[0243] Furthermore, in a signal transmission device having any of the first to fourth configurations, the open detection circuit may be configured (fifth configuration) to include a comparator that compares the terminal voltages of the first external terminal and the second external terminal to generate a comparison signal.

[0244] Furthermore, in the signal transmission device having the fifth configuration, the open detection circuit may be configured (sixth configuration) to further include a mask processing section that performs mask processing on the comparison signal over a mask period.

[0245] Furthermore, in the signal transmission device having the sixth configuration, the mask period may be shorter than the on-period of the gate drive transistor (seventh configuration).

[0246] Furthermore, in a signal transmission device having any of the first to seventh configurations, the open detection circuit may be configured (eighth configuration) to perform a logical operation on the open detection result of the first external terminal and another abnormality detection signal and output the result.

[0247] Furthermore, a signal transmission device having any of the above first to eighth configurations may have a configuration (ninth configuration) in which a first chip integrating circuit elements of the primary circuit system, a second chip integrating circuit elements of the secondary circuit system, and a third chip integrating insulating elements that provide insulation between the primary circuit system and the secondary circuit system are sealed in a single package.

[0248] Furthermore, for example, an electronic device disclosed in this specification has a power transistor and a gate driver IC that drives the gate of the power transistor, and the gate driver IC is configured to be a signal transmission device having any one of the first to ninth configurations (tenth configuration).

[0249] Furthermore, for example, the vehicle disclosed in this specification has a configuration (eleventh configuration) including the electronic device having the tenth configuration.

[0250] <Other variations> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0251] 1H(u / v / w) High-side gate driver IC 1L(u / v / w) Lower gate driver IC 2H(u / v / w) Upper power transistor 2L(u / v / w) Lower power transistor 3 ECU 4 motors 5. Semiconductor Devices 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42 First main surface 43 Second main surface 44A~44D Chip sidewall 45 First Functional Device 51 Insulating layer 52 Main insulating surface 53A~53D Insulated sidewall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulation layer 58 First insulating layer 59 Second insulating layer 60 Second Function Device 61 Sealed conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Seal via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-potential connection wiring 73 Lead Wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 PCB plug electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connection wiring 82 Pad plug electrode 85 Dummy Pattern 86 High-potential dummy pattern 87 First high potential dummy pattern 88 Second high potential dummy pattern 89 First area 90 Second area 91 Third area 92 First connection part 93 First Pattern 94 Second Pattern 95 Third Pattern 96 First Outer Line 97 Second Outer Line 98 First Intermediate Line 99 First connecting line 100 slits 130 Separation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal Transmission Device 200p primary circuit system 200s Secondary circuit system 210 Controller Chip (1st Chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 buffer 220 Driver Chip (Second Chip) 221, 222 buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer Chip (3rd Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Trans Chip 301 1st transformer 302 2nd transformer 303 Third Transformer 304 4th Transformer 305 1st Guard Ring 306 Second Guard Ring 400 Signal Transmission Device (Insulated Gate Driver IC) 400p primary circuit system 400s secondary circuit system 410 controller chip 411 Logic Circuits 412 UVLO / OVLO Circuit 413, 414 NMOSFET 420 driver chip 421 Logic Circuits 422 UVLO / OVLO circuit 423 Comparator 424 PMOSFET 425 NMOSFET 426 NMOSFET (discharge switch) 427, 428 Diodes 429 Open Circuit Detection Circuit 4291 Comparator 4292 Mask processing unit 430 Transformer Chip A Electronic equipment B vehicle B11~B18 Electronic equipment C1 capacitor D1 Diode a1 to a8 pads (corresponding to the first current supply pads) b1~b8 pads (corresponding to the first voltage measurement pads) c1 to c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil R0, R1, R2, R3, R4, R5 resistance T21, T22, T23, T24, T25, T26 external terminals X 1st direction X21, X22, X23 internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 vias

Claims

1. 1. A signal transmission device that transmits a drive signal for a gate drive transistor between a primary circuit system and a secondary circuit system while isolating the primary circuit system from the secondary circuit system, comprising: a first external terminal configured to connect to a ground terminal of the secondary circuit system; a second external terminal configured such that a terminal voltage changes depending on whether the first external terminal is in an open state; an open circuit detection circuit that monitors a terminal voltage of the second external terminal and detects an open circuit of the first external terminal; a diode having an anode connected to the first external terminal and a cathode connected to the second external terminal; A signal transmission device having the following.

2. 2. The signal transmission device according to claim 1, further comprising a discharge switch that connects / disconnects the first external terminal and the second external terminal in a manner complementary to the gate drive transistor.

3. A signal transmission device that transmits a drive signal for a gate drive transistor between a primary circuit system and a secondary circuit system while isolating the primary circuit system from the secondary circuit system, comprising: a first external terminal configured to connect to a ground terminal of the secondary circuit system; a second external terminal configured such that a terminal voltage changes depending on whether the first external terminal is in an open state; an open circuit detection circuit that monitors a terminal voltage of the second external terminal and detects an open circuit of the first external terminal; a discharge switch that connects / disconnects the first external terminal and the second external terminal in a complementary manner to the gate drive transistor; A signal transmission device having:

4. 4. The signal transmission device according to claim 2, wherein the open circuit detection circuit performs the open circuit detection when the discharge switch is turned off.

5. 5. The signal transmission device according to claim 1, wherein the open detection circuit includes a comparator that compares the terminal voltages of the first external terminal and the second external terminal to generate a comparison signal.

6. A signal transmission device that transmits a drive signal for a gate drive transistor between a primary circuit system and a secondary circuit system while insulating the primary circuit system from the secondary circuit system, comprising: a first external terminal configured to connect to a ground terminal of the secondary circuit system; a second external terminal configured such that a terminal voltage changes depending on whether the first external terminal is in an open state; an open circuit detection circuit that monitors a terminal voltage of the second external terminal and detects an open circuit of the first external terminal; and The open detection circuit includes a comparator that compares the terminal voltages of the first external terminal and the second external terminal to generate a comparison signal.

7. 7. The signal transmission device according to claim 5, wherein the open detection circuit further includes a mask processing section that performs mask processing on the comparison signal over a mask period.

8. 8. The signal transmission device according to claim 7, wherein the mask period is shorter than an on-period of the gate drive transistor.

9. 9. The signal transmission device according to claim 1, wherein the open detection circuit performs a logical operation on the open detection result of the first external terminal and another abnormality detection signal, and outputs the result.

10. a first chip on which circuit elements of the primary circuit system are integrated; a second chip on which circuit elements of the secondary circuit system are integrated; a third chip on which an insulating element for insulating between the primary circuit system and the secondary circuit system is integrated; 10. The signal transmission device according to claim 1, wherein the signal transmission device is sealed in a single package.

11. 11. An electronic device comprising: a power transistor; and a gate driver IC that drives a gate of the power transistor, wherein the gate driver IC is the signal transmission device according to claim 1.

12. A vehicle comprising the electronic device according to claim 11.

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