Semiconductor device and power conversion device

Abstract

To provide a semiconductor device and a power conversion device including the same capable of reducing an ON-voltage and a switching loss and of suppressing high-frequency oscillation caused by a noise at switching even when the semiconductor device becomes thin.SOLUTION: Provided is a semiconductor device that comprises: a drift layer of a first conductivity type; an anode layer of a second conductivity type formed on a first principal surface side of the drift layer; a field stop layer of the first conductivity type formed on a second principal surface side of the drift layer, and having an impurity concentration higher than that of the drift layer; and a cathode layer of the first conductivity type having an impurity concentration higher than that of the field stop layer. The semiconductor device has a first defect layer for carrier lifetime control that is formed by light ion irradiation. For the defect layer, a region within a half value width ΔLp in a light ion concentration profile from a concentration peak of light ions does not cover a depletion layer extending in the drift layer, nor a position where a first conductivity type carrier concentration of the field stop layer is 1016 cm-3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a power conversion device. [Background technology]

[0002] Vertical semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and PIN diodes (P-Intrinsic-N diodes) have a vertical structure in which current flows vertically. In an IGBT, the region including an N-type drift layer, an N-type buffer layer, and a P-type collector layer forms the vertical structure, while in a diode, the region including a P+ anode layer, an N-type drift layer, an N-type buffer layer, and an N+ cathode layer forms the vertical structure.

[0003] In order to reduce the on-state voltage and switching loss of the above semiconductor devices, it is effective to make the N-type drift layer thinner, but with regard to switching noise, if the current drop during switching is rapid and there is no time for the accumulated carriers to naturally disappear, known as the tail current, the current will suddenly disappear, generating a surge voltage (L·dI / dt) proportional to the parasitic inductance in the main circuit, which will oscillate at frequencies of several MHz or more. There are concerns that this noise may cause motor insulation damage, overvoltage element destruction, element malfunction, etc.

[0004] As a prior art for reducing the loss and noise of a semiconductor device, for example, there is Patent Document 1 below. Patent Document 1 discloses a semiconductor device including a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the first main surface side of the semiconductor substrate, a second conductivity type anode layer selectively formed along the drift layer and having a lower resistance than the drift layer, a cathode layer of the first conductivity type formed on the surface layer on the second main surface side of the semiconductor substrate and in contact with the drift layer, and a vacancy-oxygen composite defect region formed by a composite defect of vacancies and oxygen. The vacancy-oxygen composite defect region is provided at a depth in the direction from the interface between the cathode layer and the drift layer toward the first main surface of the semiconductor substrate, where the depth is R. For a semiconductor substrate having a resistivity of ρ, a thickness t from the pn junction between the anode layer and the drift layer to the cathode layer, and a depletion layer width W that spreads from the pn junction into the drift layer under an inverse bias voltage V applied to the pn junction, where W = 0.54×√(ρ×V) (ρ: resistivity, V: inverse bias voltage), it is characterized in that 0 < R ≤ t - W. According to the above configuration of Patent Document 1, it is said that both reduction of switching loss and soft recovery characteristics can be obtained by an inexpensive and simple process.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in Patent Document 1, when calculating W with each resistivity and inverse bias voltage and calculating the minimum device thickness of a semiconductor device in which the vacancy-oxygen composite defect region is provided at a depth represented by 0 < R ≤ t - W, it was found that there is a limit to thinning, especially in the high voltage region.

[0007] In view of the above circumstances, the present invention provides a semiconductor device that can reduce on-voltage, switching loss, and suppress high-frequency oscillation due to noise during switching, even when the semiconductor device is made thinner, and a power conversion device using the same. [Means for solving the problem]

[0008] One aspect of the semiconductor device of the present invention for solving the above-mentioned problems is a semiconductor device including: a semiconductor substrate having a drift layer of a first conductivity type; an anode layer of a second conductivity type formed on a first main surface side of the drift layer; a field stop layer of the first conductivity type formed on a second main surface side of the drift layer and having a higher impurity concentration than the drift layer; and a cathode layer of the first conductivity type having a higher impurity concentration than the field stop layer, the field stop layer being formed on a second main surface side of the drift layer; 1st The defect layer is formed when the region from the light ion concentration peak to the half-width ΔLp of the light ion concentration profile does not overlap the depletion layer extending in the drift layer, and the first conductivity type carrier concentration of the field stop layer is 10 16 cm -3 Regardless of the position First, the distance Lp from the second main surface side of the light ion concentration peak, the resistivity ρ of the drift layer, the power supply voltage V during recovery switching, and the first conductivity type carrier concentration of the layer consisting of the drift layer, field stop layer, and cathode layer are determined. 16 cm -3 The thickness from the second main surface side at the position of is tb, and the first conductivity type carrier concentration is 10 16 cm -3 When the thickness from the position to the anode layer is tn and the thickness Dw of the depletion layer spreading in the drift layer is 0.322 × √(ρ × V), the first defect layer is formed in the depth range of the following formula (1): The semiconductor device is characterized by the above. ΔLp+tb < Lp < tn-0.322×√(ρ×V)-ΔLp…Equation (1)

[0009] The present invention also provides a power conversion device using the semiconductor device of the present invention.

[0010] More specific configurations of the present invention are set forth in the claims. [Effects of the Invention]

[0011] According to the present invention, it is possible to provide a semiconductor device that can reduce on-voltage, switching loss, and suppress high-frequency oscillation due to noise during switching, even when the semiconductor device is made thinner, and a power conversion device using the same.

[0012] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to Example 1 and a graph showing the distribution of n-type concentration (Cn) and light ion concentration (In). [Figure 2] 1 is a manufacturing flow diagram showing an example of a manufacturing method for a semiconductor device according to Example 1. [Figure 3] Graph showing the relationship between n-type carrier concentration and carrier lifetime [Figure 4] Graph showing the relationship between the implantation depth of light ions and the recovery loss RL and ringing peak voltage VLp [Figure 5] Graph showing recovery waveform of Example 1 [Figure 6] 1 is a cross-sectional view of a semiconductor device according to Example 2 and a graph showing the distribution of n-type concentration (Cn) and light ion concentration (In). [Figure 7] Graph showing recovery waveform of Example 2 [Figure 8] FIG. 1 is a circuit diagram showing a schematic configuration of a power conversion device according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present invention will be described in detail below with reference to the drawings. [Example]

[0015] 1 is a cross-sectional view of a semiconductor device according to Example 1 and a graph showing the distribution of n-type concentration (Cn) and light ion concentration (In). In this example, a PIN diode is used as an example of the semiconductor device.

[0016] As described above, the semiconductor device of the present invention includes a semiconductor substrate having a drift layer of the first conductivity type (n-type), a second conductivity type (p-type) anode layer 102 formed on the first main surface side of the drift layer, a first conductivity type field stop layer 108 formed on the second main surface side of the drift layer and having a higher impurity concentration than the drift layer, and a first conductivity type cathode layer 110 having a higher impurity concentration than the field stop layer 108. In the semiconductor device, it has a first defect layer 121 for carrier lifetime control formed by light ion irradiation. The defect layer 121 is such that the region from the concentration peak of the light ions to the half-value width ΔLp of the light ion concentration profile does not cover the depletion layer extending in the drift layer 101, and the first conductivity type carrier concentration of the field stop layer 108 is 10 16 cm -3 and does not cover the position of, which is a semiconductor device characterized in that.

[0017] More specifically, the distance Lp from the second main surface side of the concentration peak of the light ions, the half-value width ΔLp of the light ion concentration profile, the resistivity ρ of the drift layer 101, the power supply voltage V during recovery switching, and the first conductivity type carrier concentration among the layers composed of the drift layer 101, the field stop layer 108, and the cathode layer is 10 16 cm -3 Let tb be the thickness from the second main surface side at the position where, and let tn be the thickness from the position where the first conductivity type carrier concentration is 10 16 cm -3 to the anode layer 102. When the depletion layer thickness Dw extending in the drift layer 101 is 0.322×√(ρ×V), the defect layer 121 is formed in the depth range represented by the following formula (1).

[0018] ΔLp + tb < Lp < tn - 0.322×√(ρ×V) - ΔLp … Formula (1) Figure 3 is a graph showing the relationship between the n-type carrier concentration (horizontal axis) and the carrier lifetime (vertical axis). As shown in Figure 3, when the carrier concentration (electrons e, holes h) is 1×10 16 cm -3Above this level, the higher the carrier concentration, the shorter the carrier lifetime becomes. 16 cm -3 If the defect layer 121 is formed at a position where the concentration is 10, the lifetime is further shortened, and as a result, the reverse recovery switching of the diode is deteriorated. 16 cm -3 It is desirable to keep a certain distance from the position.

[0019] 4 is a graph showing the relationship between the implantation depth of light ions (horizontal axis) and the recovery loss RL (left vertical axis) and the ringing peak voltage VRp (right vertical axis). As shown in FIG. 4, the present invention's Lp existence range (PILp) shows lower recovery loss RL and ringing peak voltage VRp than the conventional method (CA).

[0020] FIG. 5 is a graph showing the recovery waveform of Example 1. FIG. 5 shows the changes over time in current I and voltage V when a forward voltage is applied and then reverse biased. The graph shown by solid line E represents this Example, and the graph shown by dashed line CE represents the Comparative Example. As shown in FIG. 5, the configuration of the present invention makes it possible to reduce noise during diode recovery in both current I and voltage V.

[0021] Next, a method for manufacturing the semiconductor device of the present embodiment will be described. FIG. 2 is a manufacturing flow diagram showing an example of a method for manufacturing the semiconductor device of Example 1. Referring to FIG. 2, the manufacturing process of the PIN diode of the present invention will be described along with the cross-sectional structure of the semiconductor device. First, in FIG. 2(a), a silicon (Si) wafer for fabricating the PIN diode is prepared. For example, the Si wafer thickness is 725 μm for an 8-inch wafer and 775 μm for a 12-inch wafer. Here, the above-mentioned Si wafer has a drift layer 101 with a resistivity corresponding to the breakdown voltage. For example, the resistivity can be approximately 55 Ωcm for a diode with a breakdown voltage of 1.2 kV and approximately 250 Ωcm for a diode with a breakdown voltage of 3.3 kV. In the first step (not shown), a silicon oxide film is formed on the entire surface of the Si substrate by thermal oxidation.

[0022] Next, a photolithography process is performed to form a region where the anode P-type semiconductor layer 102 will be provided. In this photolithography process, a resist material is applied to the surface of the Si substrate, exposed to light, and developed to form a resist with an opening in the region where the anode P-type semiconductor layer 102 will be formed. Then, p-type impurity ions are implanted. Examples of p-type impurity ions include boron (B) ions. The resist is then removed, and annealing is performed to activate the impurities, thereby forming the anode P-type semiconductor layer 102 as shown in FIG. 2(a).

[0023] 2(b), a silicon oxide film is formed on the Si substrate by thermal oxidation, and a silicon oxide film 103, for example, is deposited by chemical vapor deposition (CVD), followed by a photolithography process to form a contact portion connecting the anode P-type semiconductor layer 102 and the anode electrode. A resist material is applied, exposed, and developed, and the silicon oxide film 103 is etched using the formed resist as a mask, thereby forming a contact portion connecting the anode P-type semiconductor layer 102 and the anode electrode.

[0024] Subsequently, as shown in FIG. 1(c), an anode electrode made of aluminum (Al) or an Al alloy is formed by sputtering, and a resist is patterned by a photolithography process, followed by etching to form an anode electrode 104.

[0025] Next, as shown in Fig. 1(d), a surface protective film 105 is formed. For example, the protective film can be formed by applying a solution containing a polyimide precursor material and a photosensitive material, and exposing the solution to light to convert the precursor into polyimide.

[0026] Next, as shown in Figure 1(e), the Si wafer is thinned using back-grinding and a hydrofluoric acid / nitric acid mixture. An n-type field-stop layer (n-buffer layer) 108 is then formed from the backside by ion implantation. According to the inventors' investigations, a depth of 7 μm or less for the n-type field-stop layer 108 can increase leakage current during breakdown voltage maintenance due to scratches on the backside that occur in subsequent manufacturing processes and inspection processes. Since the processing accuracy of back-grinding and the hydrofluoric acid / nitric acid mixture is approximately ±3 μm, a depth of 10 μm or more is desirable, taking into account processing variations.

[0027] 1(f), n-type impurity ions are implanted from the second main surface opposite the main surface (first main surface) on which the anode P-type semiconductor layer 102 is formed. Examples of n-type impurity ions include phosphorus (P) ions and arsenic (As) ions. Laser annealing is then performed to activate the implanted n-type impurity ions, thereby forming the n+-type semiconductor layer 110. The cathode electrode 111 is formed by sputtering, for example, to have a layered structure of AlSi alloy / titanium (Ti) / nickel (Ni) / gold (Au).

[0028] Next, as shown in FIG. 1(g), light ions (protons, helium, etc.) are irradiated from the side opposite to the main surface on which the anode P-type semiconductor layer 102 is formed (the second main surface side) to form a light ion implanted layer (defect layer) 121.

[0029] Here, the irradiation energy and dose of the light ions are adjusted so that the defect position after annealing falls within the above-mentioned range. Light ion irradiation may also be performed after pre-polishing, which processes the wafer to a thickness of, for example, 600 μm, to prevent wafer cracking due to its own weight or excessive warpage associated with larger diameters. Light ion irradiation may also be performed after the process shown in FIG. 1(d) or FIG. 1(e). [Example]

[0030] 6 is a cross-sectional view of the semiconductor device of Example 2 and a graph showing the distribution of n-type concentration (Cn) and light ion concentration (In). In this example, in addition to a defect layer (first defect layer) 121 that controls the lifetime on the cathode side, a defect layer (second defect layer) 122 that controls the lifetime on the anode side is formed.

[0031] When the drive element of an IGBT element is high speed, the recovery switch also becomes faster, increasing the recovery peak voltage and causing noise due to the di / dt. In this case, light ion implantation on the anode side can suppress hole injection on the anode side, thereby suppressing the peak voltage and thereby reducing recovery noise.

[0032] To suppress the recovery tail current and increase the switching speed by reducing the thickness, it is particularly desirable to have a structure characterized in that the peak of the light ion concentration In2 in the second defect layer 122 is greater than the peak of the light ion concentration In1 in the first defect layer 121. By achieving the above relationship, the lifetime is relatively long on the cathode side, and the maximum recovery current can be reduced while suppressing abrupt changes in the recovery tail current, making it possible to suppress noise even in a faster recovery switch.

[0033] Fig. 7 is a graph showing the recovery waveform of Example 2. As shown in Fig. 7, according to the configuration of this example, it is possible to reduce noise during diode recovery. [Example]

[0034] Fig. 8 is a circuit diagram showing a schematic configuration of a power conversion device of the present invention. Fig. 8 shows an example of the circuit configuration of a power conversion device 500 of this embodiment and the connection relationship between a DC power supply and a three-phase AC motor (AC load).

[0035] In the power converter 500 of this embodiment, the semiconductor device of the present invention is used as elements 521 to 526 (for example, diodes).

[0036] As shown in FIG. 8, the power conversion device 500 of this embodiment includes a pair of DC terminals, namely, a P terminal 531 and an N terminal 532, and AC terminals, namely, a U terminal 533, a V terminal 534, and a W terminal 535, the number of which is the same as the number of phases of the AC output.

[0037] The inverter also includes a switching leg consisting of a pair of power switching elements 501 and 502 connected in series, with U-terminal 533 connected to their series connection point as its output. It also includes a switching leg consisting of power switching elements 503 and 504 connected in series with the same configuration, with V-terminal 534 connected to their series connection point as its output. It also includes a switching leg consisting of power switching elements 505 and 506 connected in series with the same configuration, with W-terminal 535 connected to their series connection point as its output.

[0038] Three-phase switching legs consisting of power switching elements 501 to 506 are connected between DC terminals P terminal 531 and N terminal 532, and DC power is supplied from a DC power supply (not shown). Three-phase AC terminals of power conversion device 500, namely U terminal 533, V terminal 534, and W terminal 535, are connected to a three-phase AC motor (not shown) as a three-phase AC power supply.

[0039] Diodes 521 to 526 are connected in anti-parallel to the power switching elements 501 to 506, respectively. Gate circuits 511 to 516 are connected to the input terminals of the gates of the power switching elements 501 to 506, which are each made of an IGBT, and the power switching elements 501 to 506 are controlled by the gate circuits 511 to 516, respectively. The gate circuits 511 to 516 are controlled in an integrated manner by an integrated control circuit (not shown).

[0040] Gate circuits 511-516 comprehensively and appropriately control power switching elements 501-506, converting DC power from DC power supply Vcc into three-phase AC power, which is output from U terminal 533, V terminal 534, and W terminal 535.

[0041] By applying the semiconductor device of the present invention to the power conversion device 500, even if the semiconductor device is made thinner, it is possible to reduce the on-state voltage, reduce switching loss, and suppress high-frequency oscillation due to noise during switching.

[0042] As described above, it has been shown that the present invention can provide a semiconductor device that can reduce on-voltage, switching loss, and suppress high-frequency oscillation due to noise during switching, even when the semiconductor device is made thinner, and a power conversion device using the same.

[0043] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0044] For example, in this specification, the "first conductivity type" has been described as the "n type" and the "second conductivity type" as the "p type," but the "first conductivity type" may also be the "p type" and the "second conductivity type" may also be the "n type." [Explanation of symbols]

[0045] 101...drift layer, 102...anode layer, 103...silicon oxide film, 104...anode electrode, 105...surface protection film, 108...field stop layer, 110...cathode layer, 121...defect layer, Dw...thickness of depletion layer, ΔLp...half width of light ion concentration profile, 500...power conversion device, 501 to 506...power switching elements, 511 to 516...gate circuits, 521 to 526...diodes, 531...P terminal, 532...N terminal, 533...U terminal, 534...V terminal, 535...W terminal.

Claims

1. a semiconductor substrate having a drift layer of a first conductivity type; an anode layer of a second conductivity type formed on the first main surface side of the drift layer; a field stop layer of a first conductivity type formed on a second main surface side of the drift layer and having an impurity concentration higher than that of the drift layer; a cathode layer of a first conductivity type having an impurity concentration higher than that of the field stop layer, a first defect layer for carrier lifetime control formed by light ion irradiation; The first defect layer is formed such that a region from the concentration peak of the light ions to a half-value width ΔLp of the light ion concentration profile does not overlap a depletion layer extending in the drift layer, and the first conductivity type carrier concentration of the field stop layer is 10 １６ cm －３ Regardless of the position of a thickness of a depletion layer extending within the drift layer from the second main surface side to which the first conductive type carrier concentration is 10 16 cm −3; a thickness of a layer formed from the drift layer, the field stop layer, and the cathode layer from the second main surface side to which the first conductive type carrier concentration is 10 16 cm −3; a thickness of a depletion layer extending within the drift ... ΔLp+tb < Lp < tn-0.322×√(ρ×V)-ΔLp…Equation (1)

2. 2. The semiconductor device according to claim 1, further comprising, in addition to the first defect layer, a second defect layer for carrier lifetime control in the depletion layer in the drift layer.

3. 3. The semiconductor device according to claim 2, wherein the peak concentration of light ions forming said second defect layer is greater than the peak concentration of light ions forming said first defect layer.

4. A pair of DC terminals; The same number of AC terminals as the number of AC output phases, a switching leg, the number of which is equal to the number of phases of the AC output, in which two parallel circuits, each of which is connected in series and is configured with a switching element and a diode connected in anti-parallel to the switching element, are connected between the pair of DC terminals; A power conversion device having a gate circuit that controls the switching element, 4. A power conversion device, wherein the diode is a semiconductor device according to claim 1.

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