Gate control circuit, semiconductor device, electronic device, vehicle

Abstract

To perform appropriate gate control between different voltage domains.SOLUTION: A gate control circuit 25 generates a gate control signal VG of an output transistor 9 connected between an application end of a power supply voltage VB and an application end of an output voltage VOUT. The gate control circuit 25 includes: a first current source CS21 connected between the application end of the power supply voltage VB and the application end of the output voltage VOUT; a second current source CS22 connected between an application end of a booster voltage VCP and an application end of a reference voltage GND, the booster voltage being raised to a voltage value higher than that of the power supply voltage VB in a steady state; an output stage OUTS that uses at least one of the first and second current sources CS21 and CS22 to generate a gate charge current Ichg for charging a gate capacitance of the output transistor 9; and a controller CTRL that uses at least one of the first and second current sources CS21 and CS22 in accordance with the output voltage VOUT.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to a gate control circuit, and a semiconductor device, electronic equipment, and vehicle using the same. [Background technology]

[0002] The applicant of the present application has proposed many new technologies relating to semiconductor devices such as in-vehicle IPDs (intelligent power devices) (see, for example, Patent Document 1).

[0003] Furthermore, for example, Patent Document 2 can be cited as a related technique for a gate control circuit incorporated in a semiconductor device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2017 / 187785 [Patent Document 2] U.S. Patent No. 9,787,180 Summary of the Invention [Problem to be solved by the invention]

[0005] However, conventional gate control circuits have room for improvement in gate control between different voltage domains.

[0006] In particular, in recent years, automotive ICs have been required to comply with ISO26262 (an international standard for functional safety related to electrical and electronic components in automobiles), making it important for automotive IPDs to be designed with higher reliability.

[0007] In view of the above-mentioned problems discovered by the inventors of the present application, the invention disclosed in this specification aims to provide a gate control circuit capable of appropriately performing gate control between different voltage domains, and a semiconductor device, electronic device, and vehicle using the same. [Means for solving the problem]

[0008] For example, the gate control circuit disclosed in this specification is configured to generate a gate control signal for an output transistor configured to be connected between an application terminal of a power supply voltage and an application terminal of an output voltage, and includes: a first current source configured to be connected between the application terminal of the power supply voltage and the application terminal of the output voltage; a second current source configured to be connected between an application terminal of a boosted voltage that is boosted to a voltage value higher than the power supply voltage in a steady state and an application terminal of a reference voltage; an output stage configured to generate a gate charging current for charging a gate capacitance of the output transistor using at least one of the first current source and the second current source; and a controller configured to use at least one of the first current source and the second current source depending on the output voltage.

[0009] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto. [Effects of the Invention]

[0010] According to the invention disclosed in this specification, it is possible to provide a gate control circuit capable of appropriately performing gate control between different voltage domains, and a semiconductor device, an electronic device, and a vehicle using the same. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of an electronic device equipped with a semiconductor device. [Figure 2] FIG. 2 is a block circuit diagram showing the electrical structure of the semiconductor device. [Figure 3] FIG. 3 is a diagram illustrating a comparative example of a gate control circuit. [Figure 4] FIG. 4 is a diagram showing a first embodiment of a gate control circuit. [Figure 5] FIG. 5 is a diagram showing a second embodiment of the gate control circuit. [Figure 6] FIG. 6 is a diagram showing a third embodiment of the gate control circuit. [Figure 7] FIG. 7 is a diagram showing signal waveforms at various parts of the gate control circuit. [Figure 8] FIG. 8 is a diagram showing a fourth embodiment of the gate control circuit. [Figure 9] FIG. 9 is a diagram showing a fifth embodiment of the gate control circuit. [Figure 10] FIG. 10 is an external view showing an example of the configuration of a vehicle. DETAILED DESCRIPTION OF THE INVENTION

[0012] <Electronic equipment> 1 is a diagram showing an example of the configuration of an electronic device including a semiconductor device. The electronic device A of this configuration example includes a semiconductor device 1, a DC power supply 2, and a load 3.

[0013] The semiconductor device 1 is a high-side switch IC (a type of IPD) that connects / disconnects a DC power supply 2 and a load 3, and is composed of an integrated power MISFET (metal insulator semiconductor field effect transistor) 9 and a control IC (integrated circuit) 10.

[0014] The semiconductor device 1 also includes a plurality of external electrodes as means for establishing electrical connection with the outside of the device. Referring to the figure, the semiconductor device 1 includes a drain electrode 11 (corresponding to a power supply electrode VBB), a source electrode 12 (corresponding to an output electrode OUT), and a reference voltage electrode 14 (corresponding to a ground electrode GND).

[0015] The power MISFET 9 is an example of an insulated gate power transistor (=output transistor), and functions as a high-side switch element that connects / disconnects the drain electrode 11 and the source electrode 12.

[0016] The control IC 10 includes a plurality of functional circuits for realizing various functions, including, for example, a circuit for generating a gate control signal VG for driving and controlling the power MISFET 9 based on an external electrical signal.

[0017] The drain electrode 11 transmits a power supply voltage VB to the drain of the power MISFET 9 and various circuits in the control IC 10. The source electrode 12 is connected to the source of the power MISFET 9 and transmits an output voltage VOUT and an output current IOUT to the load 3. Note that a signal line (e.g., a wire harness) laid between the source electrode 12 and the load 3 generally has an inductance component L (and a resistance component). The input electrode 13 transmits an input voltage (=input signal IN) for driving the control IC 10. The reference voltage electrode 14 transmits a reference voltage (e.g., ground voltage GND) to the control IC 10. Note that a resistance component R generally exists between the reference voltage electrode 14 and the ground terminal.

[0018] <Semiconductor device> Fig. 2 is a block circuit diagram showing the electrical structure of the semiconductor device 1 shown in Fig. 1. The following description will be given taking as an example a case where the semiconductor device 1 is mounted on a vehicle. When mounted on a vehicle, the semiconductor device 1 can be used as a high-side switch for controlling the supply of electricity to a light source such as a bulb lamp or an LED (light emitting diode) lamp, or to other types of electronic control devices.

[0019] The semiconductor device 1 includes a drain electrode 11 , a source electrode 12 , an input electrode 13 , a reference voltage electrode 14 , an enable electrode 15 , a sense electrode 16 , a gate control wiring 17 , a power MISFET 9 , and a control IC 10 .

[0020] The drain electrode 11 (=power supply electrode VBB) is connected to a DC power supply 2. The drain electrode 11 provides a power supply voltage VB to the power MISFET 9 and the control IC 10. The power supply voltage VB may be 10 V or more and 20 V or less. On the other hand, the source electrode 12 (=output electrode OUT) is connected to a load 3.

[0021] The input electrode 13 (=input electrode IN) may be connected to an MCU (micro controller unit), a DC / DC converter, an LDO (low drop out) regulator, etc. The input electrode 13 provides an input voltage to the control IC 10. The input voltage may be between 1 V and 10 V. The reference voltage electrode 14 is connected to a reference voltage wiring (ground terminal). The reference voltage electrode 14 provides a reference voltage to the power MISFET 9 and the control IC 10.

[0022] The enable electrode 15 may be connected to an MCU. An electrical signal for enabling or disabling some or all of the functions of the control IC 10 is input to the enable electrode 15. The sense electrode 16 transmits an electrical signal for detecting an abnormality in the control IC 10 to an external device. The sense electrode 16 may be pulled up or down by a resistor.

[0023] The gate of the power MISFET 9 is connected to a control IC 10 (a gate control circuit 25 described later) via a gate control wiring 17. The drain of the power MISFET 9 is connected to a drain electrode 11. The source of the power MISFET 9 is connected to the control IC 10 (a current detection circuit 27 described later) and a source electrode 12.

[0024] The control IC 10 includes a sensor MISFET 21 , an input circuit 22 , a current / voltage control circuit 23 , a protection circuit 24 , a gate control circuit 25 , an active clamp circuit 26 , a current detection circuit 27 , a power supply reverse connection protection circuit 28 , and an abnormality detection circuit 29 .

[0025] The gate of the sensor MISFET 21 is connected to the gate control circuit 25. The drain of the sensor MISFET 21 is connected to the drain electrode 11. The source of the sensor MISFET 21 is connected to the current detection circuit 27.

[0026] The input circuit 22 is connected to the input electrode 13 and the current / voltage control circuit 23. The input circuit 22 may include a Schmitt trigger circuit. The input circuit 22 shapes the waveform of the electrical signal applied to the input electrode 13. The signal generated by the input circuit 22 is input to the current / voltage control circuit 23.

[0027] The current / voltage control circuit 23 is connected to the protection circuit 24, the gate control circuit 25, the power supply reverse connection protection circuit 28, and the abnormality detection circuit 29. The current / voltage control circuit 23 may include a logic circuit.

[0028] The current / voltage control circuit 23 generates various voltages in response to the electrical signals from the input circuit 22 and the protection circuit 24. In this embodiment, the current / voltage control circuit 23 includes a drive voltage generation circuit 30, a first constant voltage generation circuit 31, a second constant voltage generation circuit 32, and a reference voltage / reference current generation circuit 33.

[0029] The drive voltage generation circuit 30 generates a drive voltage for driving the gate control circuit 25. The drive voltage may be set to a value obtained by subtracting a predetermined value from the power supply voltage VB. The drive voltage generation circuit 30 may generate a drive voltage between 5V and 15V, which is obtained by subtracting 5V from the power supply voltage VB. The drive voltage is input to the gate control circuit 25.

[0030] The first constant voltage generating circuit 31 generates a first constant voltage for driving the protection circuit 24. The first constant voltage generating circuit 31 may include a Zener diode or a regulator circuit (here, a Zener diode). The first constant voltage may be equal to or greater than 1 V and equal to or less than 5 V. The first constant voltage is input to the protection circuit 24 (more specifically, to the open load detection circuit 35, etc., which will be described later).

[0031] The second constant voltage generating circuit 32 generates a second constant voltage for driving the protection circuit 24. The second constant voltage generating circuit 32 may include a Zener diode or a regulator circuit (here, a regulator circuit). The second constant voltage may be equal to or greater than 1 V and equal to or less than 5 V. The second constant voltage is input to the protection circuit 24 (more specifically, an overheat protection circuit 36 ​​and an undervoltage lockout circuit 37, which will be described later).

[0032] The reference voltage / reference current generating circuit 33 generates a reference voltage and a reference current for various circuits. The reference voltage may be 1 V or more and 5 V or less. The reference current may be 1 mA or more and 1 A or less. The reference voltage and the reference current are input to the various circuits. If the various circuits include a comparator, the reference voltage and the reference current may be input to the comparator.

[0033] The protection circuit 24 is connected to the current / voltage control circuit 23, the gate control circuit 25, the abnormality detection circuit 29, the source of the power MISFET 9, and the source of the sensor MISFET 21. The protection circuit 24 includes an overcurrent protection circuit 34, an open load detection circuit 35, an overheat protection circuit 36, and an undervoltage malfunction suppression circuit 37.

[0034] The overcurrent protection circuit 34 protects the power MISFET 9 from an overcurrent. The overcurrent protection circuit 34 is connected to the gate control circuit 25 and the source of the sensor MISFET 21. The overcurrent protection circuit 34 may include a current monitor circuit. A signal generated by the overcurrent protection circuit 34 is input to the gate control circuit 25 (more specifically, to a drive signal output circuit 40, which will be described later).

[0035] The open load detection circuit 35 detects a short state and an open state of the power MISFET 9. The open load detection circuit 35 is connected to the current / voltage control circuit 23 and the source of the power MISFET 9. A signal generated by the open load detection circuit 35 is input to the current / voltage control circuit 23.

[0036] The overheat protection circuit 36 ​​monitors the temperature of the power MISFET 9 and protects the power MISFET 9 from an excessive temperature rise. The overheat protection circuit 36 ​​is connected to the current / voltage control circuit 23. The overheat protection circuit 36 ​​may include a temperature-sensing device such as a temperature-sensing diode or a thermistor. A signal generated by the overheat protection circuit 36 ​​is input to the current / voltage control circuit 23.

[0037] The low voltage malfunction suppression circuit 37 suppresses malfunction of the power MISFET 9 when the power supply voltage VB is less than a predetermined value. The low voltage malfunction suppression circuit 37 is connected to the current / voltage control circuit 23. A signal generated by the low voltage malfunction suppression circuit 37 is input to the current / voltage control circuit 23.

[0038] The gate control circuit 25 controls the on and off states of the power MISFET 9 and the on and off states of the sensor MISFET 21. The gate control circuit 25 is connected to the current / voltage control circuit 23, the protection circuit 24, the gate of the power MISFET 9, and the gate of the sensor MISFET 21.

[0039] The gate control circuit 25 outputs a gate control signal VG to the gate control wiring 17 in response to an electrical signal from the current / voltage control circuit 23 and an electrical signal from the protection circuit 24. The gate control signal VG is input to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 via the gate control wiring 17. Specifically, the gate control circuit 25 controls the gate control signal VG in response to an electrical signal (input signal IN) applied to the input electrode 13 to turn the power MISFET 9 on / off.

[0040] More specifically, the gate control circuit 25 includes an oscillation circuit 38, a charge pump circuit 39, and a drive signal output circuit 40. The oscillation circuit 38 oscillates in response to an electrical signal from the current / voltage control circuit 23, and generates a predetermined electrical signal. The electrical signal generated by the oscillation circuit 38 is input to the charge pump circuit 39. The charge pump circuit 39 generates a boost voltage VCP based on the electrical signal from the oscillation circuit 38. The boost voltage VCP generated by the charge pump circuit 39 is input to the drive signal output circuit 40.

[0041] The drive signal output circuit 40 operates by receiving the boosted voltage VCP output from the charge pump circuit 39, and generates a gate control signal VG in response to an electrical signal from the protection circuit 24 (more specifically, the overcurrent protection circuit 34). The gate control signal VG is input to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 via gate control wiring 17. The sensor MISFET 21 and the power MISFET 9 are simultaneously controlled by a gate control circuit 25.

[0042] The active clamp circuit 26 protects the power MISFET 9 from back electromotive force. The active clamp circuit 26 is connected to the drain electrode 11, the gate of the power MISFET 9, and the gate of the sensor MISFET 21. The active clamp circuit 26 may include a plurality of diodes.

[0043] The active clamp circuit 26 may include a plurality of diodes connected together in a forward bias. The active clamp circuit 26 may include a plurality of diodes connected together in a reverse bias. The active clamp circuit 26 may include a plurality of diodes connected together in a forward bias and a plurality of diodes connected together in a reverse bias.

[0044] The multiple diodes may include p-n junction diodes, Zener diodes, or a combination of p-n junction diodes and Zener diodes. The active clamp circuit 26 may include multiple Zener diodes connected to each other in a biased manner. The active clamp circuit 26 may include a Zener diode and a p-n junction diode connected to each other in a reverse biased manner.

[0045] The current detection circuit 27 detects the currents flowing through the power MISFET 9 and the sensor MISFET 21. The current detection circuit 27 is connected to the protection circuit 24, the abnormality detection circuit 29, the source of the power MISFET 9, and the source of the sensor MISFET 21. The current detection circuit 27 generates a current detection signal in response to the electrical signal (=output current IOUT) generated by the power MISFET 9 and the electrical signal (=sense current exhibiting the same behavior as the output current IOUT) generated by the sensor MISFET 21. The current detection signal is input to the abnormality detection circuit 29.

[0046] The power supply reverse connection protection circuit 28 protects the current / voltage control circuit 23, the power MISFET 9, etc. from reverse voltage when the DC power supply 2 is reverse connected. The power supply reverse connection protection circuit 28 is connected to the reference voltage electrode 14 and the current / voltage control circuit 23.

[0047] Abnormality detection circuit 29 monitors the voltage of protection circuit 24. Abnormality detection circuit 29 is connected to current / voltage control circuit 23, protection circuit 24, and current detection circuit 27. If an abnormality (such as a voltage fluctuation) occurs in any of overcurrent protection circuit 34, open load detection circuit 35, overheat protection circuit 36, and low voltage malfunction suppression circuit 37, abnormality detection circuit 29 generates an abnormality detection signal corresponding to the voltage of protection circuit 24 and outputs it to the outside.

[0048] More specifically, the abnormality detection circuit 29 includes a first multiplexer circuit 41 and a second multiplexer circuit 42. The first multiplexer circuit 41 includes two input sections, one output section, and one selection control input section. The protection circuit 24 and the current detection circuit 27 are connected to the input sections of the first multiplexer circuit 41. The second multiplexer circuit 42 is connected to the output section of the first multiplexer circuit 41. The current / voltage control circuit 23 is connected to the selection control input section of the first multiplexer circuit 41.

[0049] The first multiplexer circuit 41 generates an abnormality detection signal in response to the electrical signal from the current / voltage control circuit 23, the voltage detection signal from the protection circuit 24, and the current detection signal from the current detection circuit 27. The abnormality detection signal generated by the first multiplexer circuit 41 is input to the second multiplexer circuit 42.

[0050] The second multiplexer circuit 42 includes two inputs and one output. The inputs of the second multiplexer circuit 42 are connected to the output of the second multiplexer circuit 42 and the enable electrode 15. The output of the second multiplexer circuit 42 is connected to the sense electrode 16.

[0051] When an MCU is connected to enable electrode 15 and a pull-up or pull-down resistor is connected to sense electrode 16, an ON signal is input from the MCU to enable electrode 15, and an abnormality detection signal is extracted from sense electrode 16. The abnormality detection signal is converted into an electrical signal by the resistor connected to sense electrode 16. An abnormal state of semiconductor device 1 is detected based on this electrical signal.

[0052] <Considerations on gate control between different voltage domains> N-channel MISFETs have an on-resistance that is two to three times better (lower on-resistance) than P-channel MISFETs with the same device area. In light of this, N-channel MISFETs are preferentially used as power switch elements (e.g., high-side switch elements). However, to fully turn on an N-channel MISFET, a positive gate-source voltage must be applied to the N-channel MISFET. Therefore, semiconductor devices often incorporate a circuit that generates a boost voltage higher than the power supply voltage (e.g., battery voltage), such as a relatively inexpensive charge pump circuit. In particular, in IPDs that handle large currents and high voltages, charge pump circuits and other floating power supply circuits are integrated to appropriately control vertically structured N-channel MISFETs.

[0053] Incidentally, in almost all semiconductor devices, low-voltage devices (e.g., 5V withstand voltage) and high-voltage devices (e.g., 40V withstand voltage) are combined and monolithically packaged. The use of high-voltage devices can improve the voltage robustness of the semiconductor device. However, in consideration of reducing the cost of the entire system, it is desirable to minimize the use of high-voltage devices and use low-voltage devices whenever possible.

[0054] In this way, in a semiconductor device in which low-voltage devices and high-voltage devices are mixed, a level shifter is generally required to transmit internal signals between different voltage domains (between a low-potential system and a high-potential system). This will be explained in detail below with reference to the drawings.

[0055] <Gate control circuit (comparison example)> 3 is a diagram showing a comparative example (= a general configuration to be compared with various embodiments described later) of the gate control circuit 25. The gate control circuit 25 of this comparative example includes a level shifter LVS, transistors M11 to M13 (e.g., P-channel MISFETs), transistors M14 and M15 (e.g., N-channel MISFETs), a current source CS11, and switches SW11 and SW12.

[0056] The level shifter LVS receives an input control signal S1 from the current / voltage control circuit 23, generates a switch control signal S2, and outputs it to the switches SW11 and SW12.

[0057] The input control signal S1 is a logic signal of a low potential system (VB / GND domain) that is pulse-driven between a power supply voltage VB and a ground voltage GND. For example, the input control signal S1 is at a high level (=VB) when the input signal IN is at a high level (=the logic level when the power MISFET 9 is in an on state), and is at a low level (=GND) when the input signal IN is at a low level (=the logic level when the power MISFET 9 is in an off state). In other words, the input control signal S1 corresponds to an on / off control signal for the power MISFET 9.

[0058] On the other hand, the switch control signal S2 is a logic signal of a high potential system (VCP / VOUT domain) that is pulse-driven between the boost voltage VCP and the output voltage VOUT. For example, the switch control signal S2 becomes high level (=VCP) when the input control signal S1 is high level (=logical level when the power MISFET 9 is in the on state), and becomes low level (=VOUT) when the input control signal S1 is low level (=logical level when the power MISFET 9 is in the off state). The switch control signal S2 is used as an on / off control signal for each of the switches SW11 and S12.

[0059] The sources of the transistors M11 to M13 are all connected to the node to which the boost voltage VCP is applied. The gates of the transistors M11 to M13 are all connected to the drain of the transistor M11. The transistors M11 to M13 connected in this manner function as a current mirror CM11 that mirrors the reference current Igate input to the drain of the transistor M11 and outputs the mirror current Im and gate charge current Ichg from the drains of the transistors M12 and M13, respectively.

[0060] The sources of the transistors M14 and M15 are both connected to the terminal to which the output voltage VOUT is applied. The gates of the transistors M14 and M15 are both connected to the drain of the transistor M14. The drain of the transistor M14 is connected to the drain of the transistor M12. The transistors M14 and M15 connected in this manner function as a current mirror CM12 that mirrors the mirror current Im input to the drain of the transistor M14 and outputs it as a gate discharge current Idchg from the drain of the transistor M15.

[0061] A first terminal of the switch SW11 is connected to the drain of the transistor M11. A second terminal of the switch SW11 is connected to the first terminal of the current source CS11. A second terminal of the current source CS11 is connected to the application terminal of the output voltage VOUT. The drain of the transistor M13 and a first terminal of the switch SW12 are both connected to the gate of the power MISFET 9. A second terminal of the switch SW12 is connected to the drain of the transistor M15.

[0062] The current source CS11 generates a reference current Igate. The current source CS11 is generally implemented as a current mirror that receives an input of a current that is the source of the reference current Igate from a low potential system (VB-GND system).

[0063] When the switch control signal S2 is at a high level (=the logical level when the power MISFET 9 is turned on), the switch SW11 is turned on and the switch SW12 is turned off. As a result, the gate capacitance (not shown) of the power MISFET 9 is charged by the gate charging current Ichg, so that the gate control signal VG rises to a high level (=VCP) and the power MISFET 9 is turned on.

[0064] On the other hand, when the switch control signal S2 is at a low level (=the logical level when the power MISFET 9 is in an OFF state), both switches SW11 and SW12 are in an ON state. As a result, the gate capacitance (not shown) of the power MISFET 9 is discharged by the gate discharge current Idchg (where Idchg>Ichg), so that the gate control signal VG falls to a low level (=VOUT) and the power MISFET 9 is in an OFF state.

[0065] Incidentally, for example, when the semiconductor device 1 is an in-vehicle IPD connected to a battery, the output voltage VOUT may have a wide operating range from a positive voltage (for example, +tens of V) to a negative voltage (for example, -tens of V). In this case, a problem occurs when an internal signal (current signal or voltage signal) of the semiconductor device 1 is level-shifted from a low-potential system (VB / GND domain) to a high-potential system (VCP-VOUT).

[0066] As described above, both low-voltage devices and high-voltage devices are incorporated into the semiconductor device 1. The boost voltage VCP is higher than the power supply voltage VB, and in most cases is clamped to a voltage that is a predetermined value (e.g., 5 V) higher than the output voltage VOUT. When the power MISFET 9 is in the on state, the gate capacitance (not shown) of the power MISFET 9 needs to be charged by the gate charging current Ichg from the charge pump circuit 39.

[0067] On the other hand, when the power MISFET 9 is in the on state, the output voltage VOUT must be pulled up to a voltage approximately equal to the power supply voltage VB (within a few mV of the power supply voltage VB). However, when VOUT≈VB, there is insufficient headroom voltage for the level shifter LVS to function properly. Specifically, there is no headroom voltage margin for turning the switch SW11 or SW12 on and off, or for generating the reference current Igate with the current source CS11.

[0068] If a depletion N-channel MISFET with a shorted gate-source is used as the current source CS11, it becomes easier to ensure a margin for the headroom voltage. However, depletion N-channel MISFETs have very large characteristic variations (such as temperature characteristics and manufacturing variations) (for example, when all characteristic variations are combined, it is more than ±50%). Therefore, it becomes difficult to accurately control the slew rate during the on-transition of the power MISFET9, and consequently, it becomes difficult to achieve both an improvement in EMC [electromagnetic compatibility] and a reduction in power consumption.

[0069] Also, due to the operation of the active clamp circuit 26, when the output voltage VOUT is a negative voltage (<GND), the reference current Igate cannot flow. Therefore, in an application where the on / off control of the power MISFET9 is repeatedly performed at high speed, it is difficult to perform appropriate gate control.

[0070] Hereinafter, in view of the above considerations, a first embodiment of a gate control circuit 25 that can appropriately perform gate control between different voltage domains will be proposed.

[0071] <Gate control circuit (first embodiment)> FIG. 4 is a diagram showing a first embodiment of the gate control circuit 25. The gate control circuit 25 of the first embodiment is a circuit block that generates a gate control signal VG for the power MISFET9 connected between the application terminal of the power supply voltage VB and the application terminal of the output voltage VOUT, and includes a controller CTRL, an output stage OUTS, current sources CS21 and CS22, switches SW21 and SW22, and a reverse current prevention element MX (for example, a high breakdown voltage N-channel MISFET).

[0072] The controller CTRL receives the input of the input control signal S20 from the current-voltage control circuit 23, generates switch control signals S21 and S22 respectively, and outputs them to the switches SW21 and SW22 respectively.

[0073] The input control signal S20 is a logic signal of a low potential system (VB / GND domain) that is pulse-driven between a power supply voltage VB and a ground voltage GND. For example, the input control signal S20 is at a high level (=VB) when the input signal IN is at a high level (=the logic level when the power MISFET 9 is in an on state), and is at a low level (=GND) when the input signal IN is at a low level (=the logic level when the power MISFET 9 is in an off state). In other words, the input control signal S1 corresponds to an on / off control signal for the power MISFET 9.

[0074] The switch control signal S21 is a logic signal of a low potential system (VB / VBM5 domain) that is pulse-driven between the power supply voltage VB and a first intermediate voltage VBM5 (=VB-5V). The switch control signal S21 becomes a low level (=VBM5) when, for example, the input control signal S20 is at a high level (=the logic level when the power MISFET 9 is in an on state) and the output voltage VOUT is lower than a threshold voltage Vth (for example, the first intermediate voltage VBM5). The switch control signal S21 becomes a high level (=VB) when, for example, the input control signal S20 is at a high level and the output voltage VOUT is higher than the threshold voltage Vth. The switch control signal S21 corresponds to an on / off control signal for the switch SW21.

[0075] The switch control signal S22 is a logic signal of a low potential system (VREF / GND domain) that is pulse-driven between a second intermediate voltage VREF (=5V) and a ground voltage GND. The switch control signal S22 becomes low level (=GND) when, for example, the input control signal S20 is at high level and the output voltage VOUT is lower than the threshold voltage Vth. The switch control signal S22 becomes high level (=VREF) when, for example, the input control signal S20 is at high level and the output voltage VOUT is higher than the threshold voltage Vth. The switch control signal S22 corresponds to an on / off control signal for the switch SW22.

[0076] Also, between the power supply voltage VB, the first intermediate voltage VBM5, the second intermediate voltage VREF, and the ground voltage GND, the magnitude relationship of GND < VREF ≤ VBM5 < VB holds.

[0077] In this way, when charging the gate capacitance of the power MISFET9, the controller CTRL switches (details will be described later) which of the current sources CS21 and CS22 to use in the output stage OUTS by exclusively (complementarily) turning on / off the switches SW21 and SW22 according to the output voltage VOUT.

[0078] The current source CS21 is connected between the applied end of the power supply voltage VB and the applied end of the output voltage VOUT, and generates a source-side reference current Igate flowing from the applied end of the power supply voltage VB toward the output stage OUTS.

[0079] The current source CS22 is connected between the applied end of the boosted voltage VCP and the applied end of the ground voltage GND, and generates a sink-side reference current Igate flowing from the output stage OUTS toward the applied end of the ground voltage GND. Note that the boosted voltage VCP is raised to a voltage value higher than the power supply voltage VB during the steady state of the semiconductor device 1.

[0080] The switch SW21 is connected between the current source CS21 and the output stage OUTS (the drain of the transistor M25 to be described later in this figure), and is turned on / off according to the switch control signal S21. For example, the switch SW21 is in the on state when the switch control signal S21 is at the low level (= VB), and is in the off state when the switch control signal S21 is at the high level (= VBM5).

[0081] The switch SW22 is connected between the current source CS22 and the output stage OUTS (the drain of the transistor M21 to be described later in this figure), and is turned on / off according to the switch control signal S22. For example, the switch SW22 is in the on state when the switch control signal S22 is at the high level (= VREF), and is in the off state when the switch control signal S22 is at the low level (= GND).

[0082] The backflow prevention element MX is connected between the switch SW22 and the output stage OUTS (in this figure, the drain of a transistor M21, which will be described later), and cuts off the backflow path of current from the application terminal of the output voltage VOUT when the output voltage VOUT becomes lower than the ground voltage GND.

[0083] The source of the backflow prevention element MX is connected to the output stage OUTS (the drain of a transistor M21, which will be described later, in this diagram). The drain of the backflow prevention element MX is connected to the switch SW22. The gate and source of the backflow prevention element MX are short-circuited.

[0084] Next, we will discuss parasitic elements associated with the reverse current prevention element MX. When the reverse current prevention element MX is formed on a P-type semiconductor substrate, the reverse current prevention element MX is accompanied by a body diode whose anode is the back gate of the reverse current prevention element MX and whose cathodes are the source and drain of the reverse current prevention element MX. When the power MISFET 9 has a vertical structure, the P-type semiconductor substrate is electrically connected to the application terminal (=source electrode 12) of the output voltage VOUT.

[0085] Therefore, the body diode associated with the reverse current prevention element MX becomes reverse biased when the output voltage VOUT becomes lower than the ground voltage GND (for example, during active clamp operation), and therefore, when the output voltage VOUT becomes lower than the ground voltage GND, it is possible to block the reverse current path from the application terminal of the output voltage VOUT.

[0086] The output stage OUTS is a circuit block that generates a gate charging current Ichg for charging the gate capacitance of the power MISFET 9 using one of the current sources CS21 and CS22, and includes transistors M21 to M24 (e.g., P-channel MISFETs), transistors M25 and M26 (e.g., N-channel MISFETs), and a current source CS23.

[0087] The sources of the transistors M25 and M26 are both connected to the application terminal of the output voltage VOUT. The gates of the transistors M25 and M26 are both connected to the drain of the transistor M25. The drain of the transistor M25 is connected to a current source CS21 via a switch SW21. The transistors M25 and M26 connected in this manner function as a current mirror CM21 that mirrors the reference current Igate input to the drain of the transistor M25 to the drain of the transistor M26.

[0088] The sources of the transistors M21 and M22 are both connected to the node to which the boost voltage VCP is applied. The gates of the transistors M21 and M22 are both connected to the drain of the transistor M21. The drain of the transistor M21 is connected to the drain of the transistor M26 and the source of the backflow prevention element MX. The drain of the transistor M22 is connected to the gate of the power MISFET 9. The transistors M21 and M22 connected in this manner function as a current mirror CM22 that mirrors the reference current Igate (corresponding to the reference current input from one of the current sources CS21 and CS22) input to the drain of the transistor M21 and outputs it as a gate charging current Ichg from the drain of the transistor M22.

[0089] The sources of the transistors M23 and M24 are both connected to the node to which the boost voltage VCP is applied. The gates of the transistors M23 and M24 are both connected to the drain of the transistor M24. The drain of the transistor M24 is connected to the current source CS23. The drain of the transistor M23 is connected to the gates of the transistors M21 and M22. The transistors M23 and M24 connected in this manner function as a current mirror CM23 that mirrors the depletion current Idepl input to the drain of the transistor M24 to the drain of the transistor M26.

[0090] The current source CS23 is connected between the drain of the transistor M24 and the application terminal of the output voltage VOUT, and generates a small depletion current Idepl. Note that the current source CS23 may be, for example, a depletion N-channel MISFET with its gate and source short-circuited.

[0091] Next, the high level transition operation of the gate control signal VG (=gate capacitance charging operation) by the gate control circuit 25 of this embodiment will be described in detail.

[0092] When the output voltage VOUT is lower than the threshold voltage Vth (=VBM5=VB-5V), the switch SW21 is turned on and the switch SW22 is turned off. As a result, a source-side reference current Igate flowing from the application terminal of the power supply voltage VB to the output stage OUTS via the current source CS21 and the switch SW21 is input to the output stage OUTS. The output stage OUTS mirrors the reference current Igate using current mirrors CM21 and CM22, thereby outputting a gate charging current Ichg flowing from the application terminal of the boost voltage VCP to the gate of the power MISFET 9. Therefore, the gate capacitance of the power MISFET 9 is charged, and the power MISFET 9 is turned on.

[0093] On the other hand, when the output voltage VOUT is higher than the threshold voltage Vth, the switch SW21 is turned off and the switch SW22 is turned on. As a result, a sink-side reference current Igate is input to the output stage OUTS, flowing from the output stage OUTS through the backflow prevention element MX, the switch SW22, and the current source CS22 toward the terminal to which the ground voltage GND is applied. The output stage OUTS mirrors the reference current Igate using the current mirror CM22, thereby outputting a gate charging current Ichg that flows from the terminal to which the boost voltage VCP is applied toward the gate of the power MISFET 9. Therefore, the gate capacitance of the power MISFET 9 is charged, and the power MISFET 9 is turned on.

[0094] As described above, the gate control circuit 25 of this embodiment, unlike the comparative example (FIG. 3), does not require a level shifter LVS for transferring voltage control signals between the low-potential system (VB-GND domain) and the high-potential system (VCP-VOUT domain). Therefore, it is possible to appropriately perform gate control between different voltage domains without considering the headroom voltage of the level shifter LVS.

[0095] Furthermore, with the gate control circuit 25 of this embodiment, there is no need to use depletion N-channel MISFETs, which have difficulty in accuracy, as the current sources CS21 and CS22. Therefore, the slew rate at the time of the on transition of the power MISFET 9 can be controlled with high accuracy, making it possible to achieve both improved EMC and reduced power consumption.

[0096] Furthermore, in the gate control circuit 25 of this embodiment, the aforementioned current mirror CM23 constantly injects a minute depletion current Idepl from the terminal to which the boost voltage VCP is applied toward the gates of the transistors M21 and M22. Therefore, when the reference current Igate is not input to the current mirrors CM21 and CM22, the gate-source voltages of the transistors M21 and M22 decrease, and the current mirror CM22 is completely inactive. As a result, for example, when the power MISFET 9 is in the off state, it is possible to prevent the generation of an unintended gate charging current Ichg.

[0097] The depletion current Idepl generated by the current source CS23 is sufficiently smaller than the reference current Igate, and therefore does not affect the accuracy of the gate charging current Ichg.

[0098] Furthermore, if a short-circuit switch were provided between the gate and source of transistors M21 and M22, a level shifter would be required to transfer the control signal of the short-circuit switch between different voltage domains, which would re-emerge the aforementioned problem of ensuring headroom voltage.On the other hand, with the gate control circuit 25 of this embodiment, a control signal for completely deactivating the current mirror CM22 is not required, so there is no need to provide a level shifter.

[0099] <Gate Control Circuit (Second Embodiment)> 5 is a diagram showing a second embodiment of the gate control circuit 25. The gate control circuit 25 of the second embodiment is based on the first embodiment (FIG. 4) described above, but the gate of the backflow prevention element MX is connected to the source of the transistor M21 (= the application terminal of the boost voltage VCP) instead of the drain of the transistor M21.

[0100] By adopting such a configuration, it is possible to obtain the same functions and effects as those of the first embodiment (FIG. 4), while ensuring a larger margin during normal operation of the semiconductor device 1, and to maintain the drain voltage of the backflow prevention element MX at a potential higher than the output voltage VOUT.

[0101] That is, when the switch SW22 is in the on state and the gate charging current Ichg is generated using the current source CS22, the drain voltage of the backflow prevention element MX becomes close to the gate voltage of the transistor M21.

[0102] <Gate Control Circuit (Third Embodiment)> FIG. 6 is a diagram illustrating a third embodiment of the gate control circuit 25. The gate control circuit 25 of the third embodiment is based on the second embodiment (FIG. 5) described above, but uses a transistor M31 (e.g., a high-voltage P-channel MISFET) and a transistor M32 (e.g., a high-voltage N-channel MISFET) as switches SW21 and SW22, respectively. A current source CS22 is connected between the application terminal of the boost voltage VCP and a reference voltage VBM5 (which corresponds to the first intermediate voltage VBM5 described above). Furthermore, a single switch control signal EN is used instead of the switch control signals S21 and S22 described above. Below, a description of the components already described will be omitted, and only the features of this embodiment will be described in detail.

[0103] The source of the transistor M31 is connected to the current source CS21. The drain of the transistor M31 is connected to the drain of the transistor M25. The gate of the transistor M31 is connected to an application terminal of the switch control signal EN. The transistor M31 is turned on when the switch control signal EN is at a low level (=VBM5), and turned off when the switch control signal EN is at a high level (=VB).

[0104] The drain of the transistor M32 is connected to the drain of the backflow prevention element MX. The source of the transistor M32 is connected to the current source CS22. The gate of the transistor M32 is connected to the application terminal of the switch control signal EN. The transistor M32 is turned on when the switch control signal EN is at a high level (=VB), and turned off when the switch control signal EN is at a low level (=VBM5).

[0105] The switch control signal EN may be generated by, for example, a comparator (not shown) that monitors the drain-source voltage Vds of the power MISFET 9. However, the method for generating the switch control signal EN is not limited to this, and other generation methods may be adopted.

[0106] FIG. 7 is a diagram showing signal waveforms of each part of the gate control circuit 25 in the third embodiment, with the input signal IN depicted in the upper row and the output voltage VOUT (solid line), the boost voltage VCP (small dashed line), and the switch control signal EN (large dashed line) depicted in the lower row.

[0107] The boost voltage VCP generated by the charge pump circuit 39 is always higher than the output voltage VOUT by a predetermined value (=a voltage value defined by an internal clamp or other adjustment structure, for example, about 5 V).

[0108] Immediately after the input signal IN rises to high level, the output voltage VOUT is low, providing sufficient headroom voltage. Therefore, the switch control signal EN goes low (=VBM5). At this time, transistor M31 is turned on, and transistor M32 is turned off. As a result, the source-side reference current Igate can be supplied to the output stage OUTS using the current source CS21, which is provided between the power supply voltage VB application terminal and the output stage OUTS.

[0109] The threshold voltage Vth for determining whether the output voltage VOUT is low may be, for example, a reference voltage VBM5. Of course, the threshold voltage Vth is not limited to this, and any other internal floating voltage may be used.

[0110] Thereafter, when the output voltage VOUT exceeds the threshold voltage Vth (=reference voltage VBM5), the switch control signal EN goes high (=VB). At this time, the transistor M31 is turned off and the transistor M32 is turned on. Therefore, the sink-side reference current Igate can be supplied to the output stage OUTS using the current source CS22 provided between the output stage OUTS and the application terminal of the reference voltage VBM5.

[0111] Furthermore, when the input signal IN falls to low level and the active clamp circuit 26 operates, the output voltage VOUT falls below the ground voltage GND. At this time, the drain-source voltage Vds of the power MISFET 9 naturally becomes higher than VB-VBM5 (=5V). Therefore, the switch control signal EN goes low, turning on the transistor M31 and turning off the transistor M32. As mentioned above, this state is nothing other than a state in which there is sufficient headroom voltage margin.

[0112] Therefore, for example, it becomes possible to perform appropriate gate control even in applications where the on / off control of the power MISFET 9 is repeated at high speed, and by extension, it becomes possible to meet the strict demands of customers.

[0113] <Gate Control Circuit (Fourth Embodiment)> 8 is a diagram showing a fourth embodiment of the gate control circuit 25. The gate control circuit 25 of the fourth embodiment is based on the third embodiment (FIG. 6) described above, but the gate of the backflow prevention element MX is connected to the source of the transistor M21 (= the application terminal of the boost voltage VCP) instead of the drain of the transistor M21.

[0114] By adopting such a configuration, it is possible to obtain the same functions and effects as those of the third embodiment (FIG. 6), while ensuring a larger margin during normal operation of the semiconductor device 1, and to maintain the drain voltage of the backflow prevention element MX at a potential higher than the output voltage VOUT.

[0115] That is, when the switch SW22 is in the on state and the gate charge current Ichg is generated using the current source CS22, the drain voltage of the backflow prevention element MX becomes close to the gate voltage of the transistor M21. These points are the same as those in the second embodiment (FIG. 5) described above.

[0116] <Gate Control Circuit (Fifth Embodiment)> 9 is a diagram showing a fifth embodiment of the gate control circuit 25. The gate control circuit 25 of the fifth embodiment is based on the first embodiment (FIG. 4) described above, and further includes transistors M27 and M28 (e.g., P-channel MISFETs), a transistor M29 (e.g., depletion N-channel MISFET), and a current source CS24 as components of the output stage OUTS.

[0117] The source of the transistor M27 is connected to the node to which the boosted voltage VCP is applied, the gate of the transistor M27 is connected to the gate of the transistor M21, and the drain of the transistor M27 is connected to the gate of the transistor M28 and the drain of the transistor M29.

[0118] The transistor M27 connected in this way functions as part of the current mirror CM22 mentioned above, and mirrors the reference current Igate flowing through the drain of the transistor M21 as the drain current Id of the transistor M27.

[0119] The source of the transistor M28 is connected to the gate of the power MISFET 9. The drain of the transistor M28 is connected to a first terminal of the current source CS24. The second terminal of the current source CS24 and the gate and source of the transistor M29 are all connected to the application terminal of the output voltage VOUT.

[0120] The current source CS24 generates a predetermined gate discharge current Idchg. The transistor M29 functions as a logic fixed element for pulling down the gate voltage of the transistor M28 to a low level (=VOUT) when the drain current Id is not flowing.

[0121] In the gate control circuit 25 of this embodiment, when charging the gate capacitance of the power MISFET 9, as described above, the switch SW21 or SW22 is turned on. Therefore, the reference current Igate is input to the output stage OUTS, and a gate charge current Ichg is supplied to the gate of the power MISFET 9. At this time, a drain current Id flows through the transistor M27, and the gate voltage of the transistor M28 becomes high, so that the transistor M28 is turned off. As a result, the gate of the power MISFET 9 is disconnected from the current source CS24, and the gate discharge current Idchg is not drawn from the gate of the power MISFET 9.

[0122] On the other hand, when discharging the gate capacitance of the power MISFET 9, for example, both switches SW21 and SW22 are turned off. Therefore, the reference current Igate is not input to the output stage OUTS, so the current mirror CM22 is in an inactive state, and the gate charge current Ichg is not supplied to the gate of the power MISFET 9. At this time, the drain current Id of the transistor M27 also stops flowing, and the gate voltage of the transistor M28 is pulled down to a low level, so that the transistor M28 is turned on. As a result, conduction is established between the gate of the power MISFET 9 and the current source CS24, and the gate discharge current Idchg is drawn from the gate of the power MISFET 9.

[0123] As described above, in the gate control circuit 25 of this embodiment, the output stage OUTS has a function of generating a gate discharge current Idchg for discharging the gate capacitance of the power MISFET 9 when the reference current Igate is not input to the current mirror CM22. Therefore, the topologies described above can be applied not only to the turn-on phase of the power MISFET 9 but also to the turn-off phase.

[0124] <Modification> In the first to fifth embodiments, examples have been given in which the current source CS21 or CS22 is switched to be used when charging the gate of the power MISFET 9, but the controller CTRL may use at least one of the current sources CS21 and CS22 depending on the output voltage. In other words, both the current sources CS21 and CS22 may be used when charging the gate of the power MISFET 9.

[0125] <Application to vehicles> 10 is an external view showing an example of the configuration of a vehicle X. The vehicle X of this example is equipped with a battery (not shown in this figure) and various electronic devices X11 to X18 that operate by receiving power supply from the battery.

[0126] Vehicle X includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0127] It should be noted that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions for the sake of convenience.

[0128] The electronic device X11 is an electronic control unit that performs engine-related controls (such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto-cruise control) or motor-related controls (such as torque control and power regeneration control).

[0129] The electronic device X12 is a lamp control unit that controls the turning on and off of HID (high intensity discharged lamp) and DRL (daytime running lamp).

[0130] The electronic device X13 is a transmission control unit that controls transmission-related functions.

[0131] The electronic device X14 is a braking unit that performs control related to the movement of the vehicle X (ABS (anti-lock brake system) control, EPS (electric power steering) control, electronic suspension control, etc.).

[0132] The electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, and the like.

[0133] The electronic device X16 is an electronic device that is installed in the vehicle X at the time of shipment from the factory as a standard equipment or a manufacturer option, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat.

[0134] The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0135] The electronic device X18 is an electronic device equipped with a high-voltage motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.

[0136] The electronic device A described above can be understood as any of the electronic devices X11 to X18. That is, the semiconductor device 1 described above can be incorporated into any of the electronic devices X11 to X18.

[0137] <Summary> The various embodiments described above will be generally described below.

[0138] For example, the gate control circuit disclosed in this specification is configured to generate a gate control signal for an output transistor configured to be connected between an application terminal of a power supply voltage and an application terminal of an output voltage, and is configured (first configuration) to include a first current source configured to be connected between the application terminal of the power supply voltage and the application terminal of the output voltage, a second current source configured to be connected between an application terminal of a boosted voltage that is raised to a voltage value higher than the power supply voltage in a steady state and an application terminal of a reference voltage, an output stage configured to generate a gate charging current for charging the gate capacitance of the output transistor using at least one of the first current source and the second current source, and a controller configured to use at least one of the first current source and the second current source depending on the output voltage.

[0139] The gate control circuit according to the first configuration may further include a first switch configured to be connected between the first current source and the output stage, and a second switch configured to be connected between the second current source and the output stage, and the controller may be configured to turn on / off the first switch and the second switch depending on the output voltage (second configuration).

[0140] Furthermore, in the gate control circuit according to the second configuration, the controller may be configured (third configuration) to accept an input of an input control signal that is pulse-driven between the power supply voltage and the reference voltage, generate a first switch control signal that is pulse-driven between the power supply voltage and a first intermediate voltage (where the first intermediate voltage<the power supply voltage), and generate a second switch control signal that is pulse-driven between a second intermediate voltage and the reference voltage (where the reference voltage<the second intermediate voltage≦the first intermediate voltage), and output the first switch control signal and the second switch control signal to the first switch and the second switch, respectively.

[0141] Furthermore, the gate control circuit according to the third configuration may be configured (fourth configuration) such that the reference voltage<the second intermediate voltage≦the first intermediate voltage<the power supply voltage holds.

[0142] Furthermore, in the gate control circuit according to any one of the first to fourth configurations, the output stage may be configured (fifth configuration) to include a current mirror configured to mirror a reference current input from one of the first current source and the second current source to generate the gate charging current.

[0143] Furthermore, in the gate control circuit according to the fifth configuration, the output stage may be configured (sixth configuration) to have a function of putting the current mirror into a non-operating state when the reference current is not input to the current mirror.

[0144] In the gate control circuit according to the fifth or sixth configuration, the output stage may be configured (seventh configuration) to have a function of generating a gate discharge current for discharging the gate of the output transistor when the reference current is not input to the current mirror.

[0145] Furthermore, the gate control circuit according to any one of the first to seventh configurations may be configured (eighth configuration) to further include a backflow prevention element configured to cut off a current backflow path from the application terminal of the output voltage when the output voltage becomes lower than the reference voltage.

[0146] Furthermore, for example, the semiconductor device disclosed in this specification is configured (ninth configuration) to include an output transistor configured to be connected between an application terminal of a power supply voltage and an application terminal of an output voltage, and a gate control circuit having any one of the first to eighth configurations configured to generate a gate control signal for the output transistor.

[0147] Furthermore, for example, the electronic device disclosed in this specification has a configuration (tenth configuration) including the semiconductor device according to the ninth configuration.

[0148] Furthermore, for example, the vehicle disclosed in this specification is configured (eleventh configuration) to include the electronic device according to the tenth configuration.

[0149] <Other variations> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. For example, bipolar transistors can be substituted for MOS field-effect transistors, or the logic levels of various signals can be inverted. In other words, the above-described embodiments are illustrative in all respects and should not be considered limiting. The technical scope of the present invention is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope of the claims. [Explanation of symbols]

[0150] 1. Semiconductor device (high-side switch IC) 2 DC power supply 3. Load 9 Power MISFET (output transistor) 10 Control IC 11 Drain electrode (power electrode) 12 Source electrode (output electrode) 13 Input electrode 14 Reference voltage electrode 15 Enable electrode 16 Sense electrode 17 Gate control wiring 21 Sensor MISFET 22 Input circuit 23 Current / Voltage Control Circuit 24 Protection circuit 25 Gate control circuit 26 Active clamp circuit 27 Current detection circuit 28 Power supply reverse connection protection circuit 29 Abnormality detection circuit 30 Drive voltage generation circuit 31 First constant voltage generating circuit 32 Second constant voltage generating circuit 33 Reference voltage and reference current generation circuit 34 Overcurrent protection circuit 35 Open load detection circuit 36 Overheat protection circuit 37 Undervoltage lockout circuit 38 Oscillator Circuit 39 Charge pump circuit 40 Drive signal output circuit 41 First multiplexer circuit 42 Second multiplexer circuit A Electronic equipment CM11, CM12, CM21 to CM23 current mirror CS11, CS21~CS24 Current source CTRL Controller L inductance component LVS Level Shifter M11~M13 Transistors (P-channel MISFET) M14, M15 transistors (N-channel MISFET) M21 to M24, M27, M28 transistors (P-channel MISFET) M25~M26 Transistors (N-channel MISFET) M29 Transistor (Depletion N-channel MISFET) M31 Transistor (P-channel MISFET) M32 Transistor (N-channel MISFET) MX reverse current prevention element (high-voltage N-channel MISFET) OUTS Output stage R resistance component SW11, SW12, SW21, SW22 switches X vehicle X11~X18 Electronic equipment

Claims

1. A gate control circuit configured to generate a gate control signal for an output transistor configured to be connected between an application terminal of a power supply voltage and an application terminal of an output voltage, a first current source configured to be connected between an application terminal of the power supply voltage and an application terminal of the output voltage; a second current source that is connected between an application terminal of a boosted voltage that varies depending on the output voltage and is raised to a voltage value higher than the power supply voltage in a steady state, and an application terminal of a reference voltage; an output stage configured to generate a gate charging current for charging a gate of the output transistor using at least one of the first current source and the second current source; a controller configured to select at least one of the first current source and the second current source as the current source used in the output stage in response to the output voltage; A gate control circuit comprising:

2. a first switch configured to be connected between the first current source and the output stage; a second switch configured to be connected between the second current source and the output stage; Furthermore, The gate control circuit according to claim 1 , wherein the controller turns on / off the first switch and the second switch in response to the output voltage.

3. 3. The gate control circuit according to claim 2, wherein the controller receives an input of an input control signal that is pulse-driven between the power supply voltage and the reference voltage, generates a first switch control signal that is pulse-driven between the power supply voltage and a first intermediate voltage, and a second switch control signal that is pulse-driven between a second intermediate voltage and the reference voltage, and outputs the first switch control signal and the second switch control signal to the first switch and the second switch, respectively.

4. 4. The gate control circuit according to claim 3, wherein the reference voltage<the second intermediate voltage≦the first intermediate voltage<the power supply voltage.

5. 5. The gate control circuit according to claim 1, wherein the output stage includes a current mirror configured to mirror a reference current input from one of the first current source and the second current source to generate the gate charging current.

6. 6. The gate control circuit according to claim 5, wherein said output stage has a function of putting said current mirror into an inactive state when said reference current is not input to said current mirror.

7. 7. The gate control circuit according to claim 5, wherein the output stage has a function of generating a gate discharge current for discharging the gate of the output transistor when the reference current is not input to the current mirror.

8. 8. The gate control circuit according to claim 1, further comprising a backflow prevention element configured to block a current backflow path from an application terminal of the output voltage when the output voltage becomes lower than the reference voltage.

9. 9. A semiconductor device comprising: an output transistor configured to be connected between an application terminal of a power supply voltage and an application terminal of an output voltage; and the gate control circuit according to claim 1 configured to generate a gate control signal for the output transistor.

10. An electronic device comprising the semiconductor device according to claim 9.

11. A vehicle comprising the electronic device according to claim 10.

Images