Transistor, power electronic switch device, and method for manufacturing transistor

Abstract

The invention relates to a transistor (10), in particular a wide bandgap semiconductor power transistor (40), comprising an epitaxial layer (11) of a first conductivity type, at least one well region (13) of a second conductivity type formed in a selected region of the epitaxial layer (11), at least one terminal region, in particular a source region (29), of the first conductivity type formed in or adjacent to the at least one well region (13), at least one terminal electrode (15), in particular a source electrode (21), formed at least partially on a surface (12) of a first portion of the at least one terminal region (14), and at least one resistor region (16) formed in the at least one terminal region (14), the at least one resistor region (16) including an amphoteric impurity. The invention further relates to a power electronic switch device comprising a plurality of switch cells, and to a method for manufacturing the transistor (10), in particular a wide bandgap semiconductor power transistor (40).

Description

[Technical Field]

[0001] The present disclosure relates to a transistor, particularly a wide bandgap power transistor, comprising an epitaxial layer, at least one well region, and at least one terminal region, particularly a source region. The present disclosure further relates to a power electronic switch device comprising a plurality of switch cells, and a method for manufacturing a transistor, particularly a SiC power transistor. [Background technology]

[0002] Transistors are used in many applications, including power electronics. It is generally desirable for transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), to be able to withstand so-called short-circuit conditions for a specified period of time. For example, it may be desirable to provide a power transistor with a short-circuit withstand time (SCWT) of at least 10 μs. The SCWT can be used by control circuits to identify faults in the corresponding power circuits and de-energize them.

[0003] At the same time, it is desirable to minimize conduction losses in transistors, especially power transistors. Lower conduction losses generally result in higher saturation current densities in semiconductor materials, and consequently shorter SCWTs. Summary of the Invention [Problem to be solved by the invention]

[0004] It is therefore a challenge to describe an improved device and method of manufacture that allows for balancing the objectives of low conduction losses with a given SCWT objective. [Means for solving the problem]

[0005] Embodiments of the present disclosure relate to transistors, power electronic switching devices, and methods of fabricating transistors that selectively increase the resistivity within one of the terminal regions to enable control of the voltage drop within the transistor structure and, therefore, the corresponding SCWT of the transistor. This is achieved, at least in part, by the introduction of at least one resistive region that includes an amphoteric impurity.

[0006] According to a first aspect, a transistor, particularly a wide bandgap semiconductor power transistor, is disclosed, comprising an epitaxial layer of a first conductivity type, at least one well region of a second conductivity type formed in a selected region of the epitaxial layer, at least one terminal region, particularly a source region, of the first conductivity type formed in or adjacent to the at least one well region, at least one terminal electrode, particularly a source electrode, formed at least partially on a surface of a first portion of the at least one terminal region, and at least one resistor region formed in the at least one terminal region, wherein the at least one resistor region contains an amphoteric impurity.

[0007] By introducing at least one resistor region formed within at least one terminal region, the resistance of the terminal region can be increased, and other portions of the transistor structure can be protected by reducing the voltage drop therein. The use of amphoteric impurities allows for precise control of the resistivity of the resistor region, and therefore the overall resistance of the terminal region. In particular, the inventors have discovered that the resistivity of the terminal region implanted with amphoteric species can be controlled based on, for example, the implant dose or the activation temperature of the resistor region.

[0008] Furthermore, the present inventors have found that the use of an amphoteric dopant results in no or only a small amount of crystalline defects in the epitaxial layer in general, and in at least one resistor region formed in at least one terminal region in particular. For example, when manganese (Mn) is implanted into silicon carbide (SiC), which is used as a wide bandgap semiconductor material, the density of Z1 / 2 lattice defects is 1e11 cm -3For other amphoteric species and / or implant doses, the density of Z1 / 2 lattice defects may still be at a relatively low level, e.g., 1e13 cm -3 This can be attributed to the formation of C interstitials, i.e., C atoms that are knocked out of their sites in the crystal lattice during implantation. Such interstitials can diffuse even at room temperature and annihilate the Z1 / 2 corresponding to the vacant C sites in the crystal lattice. In contrast, implantation of other types of dopants can result in an increase in the density of lattice defects. For example, implantation of protons, helium (He) or argon (Ar) can result in an increase in the density of lattice defects of 1e15 cm -3 This can result in a relatively high density of Z1 / 2 lattice defects, for example, an order of magnitude higher than the density of Z1 / 2 lattice defects achieved using amphoteric dopants.

[0009] At least one resistive region may include at least one of manganese (Mn) and vanadium (V) as amphoteric dopants that can selectively act as charge acceptors or donors in common wide bandgap semiconductor materials useful in power electronics, particularly silicon carbide (SiC), such as 4H-SiC or 6H-SiC.

[0010] Using common semiconductor processing steps and parameters, the resistivity of the terminal region can be modulated to be greater than 10 Ωcm, for example, anywhere in the range between 20 Ωcm and 20 kΩcm, a range useful for controlling the SCWT of power transistors.

[0011] Different structures within the terminal region can be obtained by using various implantation techniques. For example, a second subregion of the terminal region, essentially free of amphoteric impurities, can be completely separated by one or more first subregions in which amphoteric impurities are present. By patterning at least one terminal region, the current density in different parts of the terminal region can be precisely controlled.

[0012] The described terminal structures are applicable to many different transistor types, including metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), junction field-effect transistors (JFETs), and insulated gate bipolar transistors (IGBTs). Additionally, the described terminal structures can be used in a variety of configurations, including planar and trench configurations.

[0013] According to a second aspect, a power electronic switch device is disclosed, the device comprising a plurality of switch cells electrically connected in parallel, each switch cell comprising a transistor according to the first aspect. By using several of these transistors in parallel, relatively high current ratings can be achieved, as is often required in power electronics.

[0014] The features and advantages described in connection with individual transistors may also be used in more complex devices, such as power electronic switching devices, comprising multiple transistor cells disposed on a common substrate and / or electrically connected in parallel.

[0015] A transistor or power electronic switch device according to the above embodiments may have a voltage rating of 600 volts or greater.

[0016] According to a third aspect, there is provided a method for manufacturing a transistor, in particular a wide bandgap semiconductor power transistor, the method comprising: epitaxially growing a semiconductor layer of a first conductivity type; forming at least one well region of a second conductivity type formed within a selected region of the epitaxial layer; forming at least one terminal region of a first conductivity type, in particular a source region, in or adjacent to the at least one well region; implanting at least a portion of at least one terminal region with an amphoteric dopant; Includes:

[0017] The above steps allow for the fabrication of a transistor according to the first aspect using established processing steps used in the manufacture of power electrical devices.

[0018] For example, the implant depth of the amphoteric dopant, and therefore the shape of the resistor region, can be controlled using an appropriate implant energy in the range of 50 to 1000 keV.

[0019] Furthermore, the overall resistivity of the resistive region is 10 10 cm -2 ~10 14 cm -2 This can be controlled by implanting amphoteric dopants using a dose in the range of .

[0020] In at least one embodiment, the method further includes annealing the at least one resistive region containing the implanted amphoteric dopant at a first temperature T1, where the first temperature T1 is selected based on a target resistivity ρ of the terminal region. Experiments by the inventors have shown that there is a relationship between the activation temperature and the resistivity of the doped and activated resistive region, which can be utilized to limit the peak current through the transistor during a short-circuit condition. In particular, when the source region is doped with an amphoteric dopant, the current density in the neighboring channel region can be reduced, which in turn reduces the gate-source potential (V GS ) is defined by

[0021] The present disclosure includes several embodiments of semiconductor devices, particularly transistor terminal structures, and methods for fabricating such transistors and terminals. All features described with respect to one of the embodiments are also disclosed herein with respect to the other embodiments, even if the respective feature is not explicitly mentioned in the context of the particular embodiment.

[0022] The accompanying drawings are included to provide a further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. [Brief explanation of the drawings]

[0023] [Figure 1] 1 shows a schematic cross section through the terminal area of ​​a transistor. [Figure 2A] 1 shows a schematic cross-sectional view of a vertical power transistor in a planar configuration. [Figure 2B] 1 shows a schematic cross-sectional view of a vertical power transistor in a trench configuration. [Figure 3] 1 illustrates the various steps in the process for manufacturing a vertical power MOSFET. [Figure 4] 1 illustrates the various steps in the process for manufacturing a vertical power MOSFET. [Figure 5] 1 illustrates the various steps in the process for manufacturing a vertical power MOSFET. [Figure 6] 1 illustrates the various steps in the process for manufacturing a vertical power MOSFET. [Figure 7] 1 illustrates the various steps in the process for manufacturing a vertical power MOSFET. [Figure 8] 1 illustrates the various steps in the process for manufacturing a vertical power MOSFET. [Figure 9] 1 illustrates the various steps in the process for manufacturing a vertical power MOSFET. [Figure 10]1 shows the relationship between the resistivity of a semiconductor region with amphoteric impurities and the annealing temperature. [Figure 11] 1 illustrates different characteristics of a transistor device with a resistive region having amphoteric impurities. [Figure 12] 1 illustrates different characteristics of a transistor device with a resistive region having amphoteric impurities. [Figure 13] 1 illustrates different characteristics of a transistor device with a resistive region having amphoteric impurities. [Figure 14] 1 shows cross-sectional views of five possible configurations of the terminal area. [Figure 15] 10A-10C show perspective views of seven further possible configurations of the terminal area. [Figure 16] A method for fabricating a transistor is presented. DETAILED DESCRIPTION OF THE INVENTION

[0024] While the disclosed invention is applicable to many different types of semiconductor transistors, it focuses specifically on power MISFETs, particularly those implemented using wide-bandgap semiconductor materials such as SiC. A key feature of MISFETs is their ability to withstand short-circuit conditions for a given period of time, e.g., greater than 10 μs. During this time, known as short-circuit withstand time (SCWT), associated control circuitry can identify the fault and turn off power. In power electronics, SiC MISFETs are typically designed with relatively short channel lengths and small pitches between neighboring switch cells. Such compact designs are beneficial for minimizing conduction losses in individual transistors as well as complex power electronic switch devices. This, in turn, results in a relatively high saturation current density, thereby shortening the SCWT.

[0025] To achieve the desired design tradeoff between low conduction loss and the desired SCWT, according to at least one implementation, a high-resistivity region is implanted in the terminal region of the SiC MISFET, e.g., the n++ source region, to achieve the tradeoff between conduction loss and SCWT. The resistivity ρ of the high-resistivity region can be modulated by various processing parameters, as described below.

[0026] FIG. 1 illustrates an example of such a terminal structure. In particular, a cross section of a portion of a transistor 10 is shown, including an epitaxial layer 11, also referred to hereinafter as an epilayer 11 or drift layer. The epilayer 11 may be formed of n-type SiC. A well region 13 may be formed in the epilayer 11 near its front or top surface 12 by doping the epilayer 11 with an appropriate dopant. For example, the epilayer 11 may be selectively doped with an electron-accepting element to form a p-well. In the example illustrated in FIG. 1, the channel region of the transistor 10 is located within this well region 13. In subsequent processing steps, a terminal region 14, such as a source region, may be formed in part of the well region 13. The terminal region 14 typically has the same conductivity type as the epilayer 11, but may have a higher doping concentration. For example, an n++ source region may be formed by implanting a dopant that acts as an electron donor. At least a portion of the top surface 12 of the terminal region 14 is in contact with a terminal electrode 15. For example, a metallization layer may be used to connect external terminals to the terminal areas 14 .

[0027] In the described example, the terminal region 14 further comprises a resistor region 16. Within the meaning of the present disclosure, the resistor region has a significantly higher resistivity than the remainder of the terminal region 14. This is achieved, at least in part, by introducing amphoteric impurities into the resistor region 16. Amphoteric impurities can act as both donors and acceptors of charge carriers, thereby significantly reducing the conductivity of all types of doped semiconductor materials, including the highly doped p++ or n++ regions of a SiC epilayer.

[0028] Resistor region 16 can take many different configurations. As shown in FIG. 1, it can extend from top surface 12 partially through terminal region 14, thereby forming a relatively narrow connection 17 connecting left and right subregions 18 and 19 of terminal region 14, respectively. Within resistor region 16, depletion of charge carriers by amphoteric dopants reduces the current. Within connection 17, its limited spatial extent also limits the overall current. Therefore, the short-circuit current flowing through epilayer 11, well region 13, terminal region 14, and terminal electrode 15 can be significantly reduced, with the majority of the corresponding voltage drop occurring within terminal region 14.

[0029] 2A and 2B show how such terminal electrodes can be used in a vertical power transistor.

[0030] 2A shows a modified planar VDMOS 20. The VDMOS 20 comprises a source electrode 21 and a drain electrode 22 disposed on opposite surfaces of a semiconductor transistor structure 23. Between the source electrode 21 and the top surface of the semiconductor transistor structure 23 is formed an insulated gate structure comprising a gate electrode 24 and a surrounding insulating layer 25. From bottom to top, the semiconductor transistor structure 23 is divided into n-type and n-type regions, which act as drain regions. + The n-type substrate layer 26 corresponds to the epitaxial layer 11 in FIG. - 1. The semiconductor device includes a n-type drift layer 27, an optional n+ buffer layer (not shown) between the substrate layer 26 and the epi layer 11, two p-type well regions 13a and 13b, and two n-type well regions 13b corresponding to the terminal region 14 of FIG. + and two p-type source regions 29a and 29b, which electrically connect the source electrode 21 to the well regions 13a and 13b. + and well contact regions 28a and 28b.

[0031] In the example shown in Figure 2A, each of source regions 29a and 29b comprises resistive regions 16a and 16b as described above with respect to Figure 1. That is, in modified VDMOS 20 according to Figure 2, the resistivity of portions of both source regions 29a and 29b is increased and controlled as described above and below.

[0032] Figure 2B shows two n + 2A shows a trench-gated power transistor 30 with a gate electrode 24 in a trench disposed between p-type source regions 29a and 29b and p-type well regions 13a and 13b. The gate electrode is insulated from source electrode 21 by an upper insulating layer 25a and from semiconductor transistor structure 23 by a lower insulating layer 25b. Most other components of trench-gated power transistor 30 correspond to corresponding portions of planar VDMOS 20 described above with respect to FIG. 2A and therefore will not be repeated here.

[0033] In the example shown in FIG. 2B, each of the source regions 29a and 29b includes a resistor region 16a and 16b, respectively, that is configured as a vertical sublayer of the respective terminal region 29a and 29b.

[0034] It should be noted that the particular configurations of resistor regions 16a and 16b shown in Figures 2A and 2B are presented as examples, and that other configurations, such as those shown in Figures 14(a)-15(g), may be used in each of the disclosed transistor devices.

[0035] The various stages in the manufacture of a power transistor 40, such as a vertical power MOSFET, will now be described with reference to FIGS. 3 to 9 and the flow chart according to FIG.

[0036] Referring first to FIG. 3, in a first step S1, a substrate 41 is provided. For example, an n-type SiC substrate may be provided. The substrate 41 may correspond to the backside layer or drain region of the completed power transistor 40. For example, nitrogen (N) or phosphorus (P) may be used as a dopant to create the n-type region. The maximum doping concentration of the drain region is 1·10 17 cm -3 ~5·10 20 cm -3 It can be in the range of

[0037] In a next step S2, as further shown in FIG. 3, an epilayer 11 is grown on the substrate 41. In the described example, an n-type SiC epilayer may be grown on the substrate 41. The epilayer 11 may correspond to the drift layer of the completed power transistor 40. Depending on the voltage class of the power transistor 40, the maximum doping concentration of the drift layer may be 1·10 14 cm -3 ~1·10 17 cm -3 The range may be:

[0038] 4, a photolithography mask (not shown) may be formed on top surface 12 of epilayer 11 to selectively cover a portion of top surface 12 before the remainder of surface 12 is doped with an appropriate dopant in step S3 to form well region 13. For example, aluminum (Al), boron (B), or gallium (Ga) species, or any combination of the above, with or without an n-type dopant, may be implanted to form a p-type well. That is, the p-type region may be formed by implanting Al or B or Ga, but may also be formed by co-implanting Al / B, Al / Ga, B / Ga, or by implanting Al / N, B / N, etc. The maximum doping concentration of well region 13 is 1·10 16 cm -3 It may be more than that.

[0039] 5, in optional step S4, a modified or new mask may be used to form well contact regions 28. Well contact regions 28 may be p++ doped regions. The maximum doping concentration of well contact regions 28 is 1·10 17 cm -3 ~5·10 20 cm -3 In the completed power transistor 40, the well contact region 28 may prevent the potential of the well region 13 from floating during operation of the transistor device.

[0040] 6, in step S5, a further photolithography mask may be used to form terminal region 14. For example, a heavily doped n++ region may be formed in p-well region 13 to form the source region of power transistor 40. The maximum doping concentration of the source region is 1·10 17 cm -3 ~5·10 20 cm -3 The terminal region 14 shown in Figure 6 may be formed by implanting nitrogen (N) or phosphorus (P) into the SiC substrate.

[0041] Then, in a further step S6, the dopant species implanted in step S5 may be activated, for example, the implanted dopants may be activated at a relatively high temperature, for example at a temperature of 1600° C. for 30 minutes.

[0042] 7, in a further step S7, an amphoteric dopant may be implanted into at least a portion of the terminal region 14 to form the resistor region 16. This may be accomplished using another photolithography mask (not shown). The SiC material of the epilayer 11 is doped through one or more openings in the mask using an amphoteric dopant species. In the described process, either Mn or V is used as the dopant. However, in certain circumstances, other amphoteric dopants may be used.

[0043] For example, ion implantation and / or plasma ion implantation may be used. Step S7 may be performed at room temperature with an implant energy selected so that the depth d of the implanted amphoteric impurities matches the depth of the terminal region 14, as shown in Figure 7. Alternatively, a lower implant energy may be used, resulting in a shallower implant of the amphoteric impurities.

[0044] The introduction of amphoteric impurities significantly increases the resistivity of the terminal region 14 within the resistor region 16. For example, the initial resistivity ρ of the n++ source region of about 0.02 Ω cm can be increased by doping with Mn or V to obtain an initial resistivity of about 20 kΩ cm. The presence of deep Mn or V acceptor and donor levels at the top and bottom of the SiC bandgap, respectively, compensates for the N donor or Al acceptor doping of the surrounding wide bandgap semiconductor material. The table below shows the conduction band energy E C and the valence band energy E V The positions of the acceptor and donor levels of Mn and V are shown relative to the

[0045] [Table 1]

[0046] In particular, the use of amphoteric dopants allows for precise control of the resistivity ρ of resistor region 16 in optional annealing step S8. As shown in the logarithmic graph of Figure 10, the resistivity ρ of resistor region 16 can be controlled by the selection of the corresponding annealing temperature T1.

[0047] Without annealing, the resistivity ρ is initially about 20 kΩ-cm. As the applied annealing temperature T1 increases over a given period of time, e.g., 30 minutes, the resistivity ρ can be reduced to about 2 kΩ-cm for the tested sample structure. Note that the resistance of the terminal region 14 also depends on the dose of the amphoteric impurity implant. Therefore, the resistance of the terminal region 14 can be controlled by at least two parameters during the fabrication of the power transistor 40.

[0048] Referring now to FIG. 8, in a further step S9, one or more insulating layers and / or electrodes may be formed on the top surface 12 of the epilayer 11.

[0049] 8, an insulating layer 25a is first formed on a portion of the terminal region 14, and a portion of the well region 13 near the top surface 12 will later form the channel region 42 of the transistor structure (shown by the dashed line in FIG. 8) as well as the adjacent region of the epitaxial layer 11. A gate electrode 24 is formed on the first insulating layer 25a. The gate electrode 24 is then covered with a second insulating layer 25b that insulates the top surface of the gate electrode 24.

[0050] Thereafter, a source electrode 21 is formed on the remaining portion of the top surface 12 of the epitaxial layer 11 in the well contact region 28 and a portion of the terminal region 14. As shown in Figure 8, the source electrode 21 also covers the top surface of the second insulating layer 25b, as is generally the case in a vertical power transistor 40.

[0051] FIG. 9 shows a cross-sectional view of a portion of a completed vertical power transistor 40 after a drain electrode 22 has been formed on the opposite backside 43 of the substrate 41.

[0052] 9 also shows a current path 44 from the drain electrode 22 through the substrate 41, which is the drift layer formed by the epilayer 11, to the source electrode 21, where the p-well region 13 includes a channel region 42 (dashed line) and the terminal region 14 includes two distinct n++ subregions 18, 19 that do not contain amphoteric dopants and another subregion in the form of a resistive region 16. By modulating the resistivity ρ of the resistive region 16, and therefore the terminal region 14, the short circuit current can be controlled without excessively increasing the total source-drain resistance RDSon during normal operation.

[0053] To prove the proposed solution, technology computer-aided design (TCAD) simulations were used and the results are shown in Figures 11 to 13.

[0054] In particular, FIG. 11 shows the J of power transistor 40 in a linear chart. D / V DS Figure 12 shows the simulated electrothermal short circuit current density waveform J over time t in a linear chart. D It can be seen that compared to the reference design without additional zwitterion implantation, RDSon increases by about 9% (Fig. 11) and the peak SC current decreases by about 18% (Fig. 12). Thus, the trade-off between conduction loss and SCWT is improved.

[0055] Generally, during a short circuit condition, a semiconductor device will conduct a current I MAX As shown in Figures 11 and 12, the disclosed design improves SCWT by minimizing the effect of source-drain resistivity RDSon. MAX The decrease in is due to the presence of the implanted amphoteric impurity in the resistor region 16. It does not affect the channel region 42 because it is implanted in the source region.

[0056] 13 shows in a linear chart the transfer characteristics of the power transistor 40. The characteristics of the power transistor 40 with different resistive region depths d are compared to the characteristic J of the reference design without amphoteric dopants. D / V GS Noting the fact that the curves match confirms that the threshold voltage values ​​are not affected.

[0057] 14 and 15 show various configurations of terminal region 14 having one or more resistor regions 16 formed therein. Note the fact that the amphoteric impurities do not diffuse into the wide bandgap semiconductor material used, thereby remaining localized in resistor region 16 after doping. Thus, by using conventional doping techniques, different patterns can be achieved as shown.

[0058] For example, horizontal segmentation, as shown in FIG. 14(a), may be used as an alternative to the vertical segmentation shown in FIG. 7. For example, a single resistor region 16 may be formed as shown in FIG. 14(a), or multiple resistor regions 16 may be formed, separated by intermediate portions of the terminal region 14 that are not implanted with amphoteric impurities, as shown in FIG. 14(b). Furthermore, by selection of implant energy, individual portions of the resistor region 16 may be located at the top surface 12 or may be embedded deeper into the terminal region as shown, producing, for example, a checkerboard pattern as shown in FIG. 14(c) or isolated islands of amphoteric dopant as shown in FIG. 14(d). Of course, horizontal separation, as already described above with respect to FIG. 7, may also include multiple resistor regions 16, as shown in FIG. 14(e).

[0059] 15(a)-15(g) illustrate the formation of various first (dark) sub-regions 45 of the terminal region 14 that are doped with amphoteric impurities, and second (light) sub-regions 46 of the terminal region 14 that are essentially free of amphoteric impurities. Such designs can be obtained, for example, by appropriate masks or interference patterns or combinations thereof used during the implantation of the amphoteric species.

[0060] The dimensions and implementation depth d of the resistor region 16 and the resistivity can be varied by varying the implantation energy, for example, in the range of 50-500 keV and / or by varying the implantation energy, for example, in the range of 10 11 ~10 14 cm -2 By adjusting the amount within the range of , it can be adjusted to extend along the entire depth of the terminal area 14.

[0061] The disclosed transistor structures and fabrication techniques offer several advantages, including the ability to modulate the resistivity ρ of terminal regions 14, such as source regions, to adjust and control the tradeoff between conduction losses and SCWT. Furthermore, amphoteric impurities can be implanted regardless of the substrate used, such as that used to form and dope n++ or p++ source or drain regions. This allows the implant energy of the selected amphoteric species to remain the same regardless of the dopant used to dope the corresponding terminal region, such as N, P, Al, or B, among others.

[0062] The embodiments illustrated in Figures 1-16 above represent exemplary embodiments of improved transistor structures and methods for fabricating the same. As such, they do not constitute an exhaustive list of all embodiments of the improved apparatus and / or methods. Actual apparatus, systems, and methods may differ from the illustrated embodiments with respect to, for example, semiconductor substrates, dopants, and processing parameters. [Explanation of symbols]

[0063] Reference sign 10 transistors 11 Epitaxial layer 12 Top side 13 well area 14 Terminal area 15 terminal electrode 16 resistance region 17 Connection 18 Left Sub-area 19 Right Sub-area 20 VDMOS 21 Source electrode 22 drain electrode 23 Semiconductor transistor structure 24 gate electrode 25 insulating layer 26 substrate layers 27 Drift Layer 28 well contact area 29 Source Region 30 Trench gate power transistor 40 Power transistor 41 PCB 42 channel region 43 Back side 44 Current Path 45 Subregion 1 (both sexes) 46 Second subregion (non-bisexual)

Claims

1. A transistor (10), an epitaxial layer (11) of a first conductivity type; at least one well region (13) of a second conductivity type formed in a selected region of said epitaxial layer (11); at least one terminal region (14) of said first conductivity type formed within or adjacent to said at least one well region (13); at least one terminal electrode (15) at least partially formed on a surface (12) of the first portion of the at least one terminal area (14); At least one resistor region (16) formed within the at least one terminal region (14), the at least one resistor region (16) including manganese (Mn) as an amphoteric dopant; A transistor (10) comprising:

2. The transistor (10) of claim 1, wherein the at least one resistive region (16) further comprises vanadium (V) as an amphoteric dopant.

3. The concentration of the amphoteric dopant in the at least one resistive region (16) is 10 １４ ~10 １８ cm －３ 3. The transistor (10) of claim 1 or 2, wherein:

4. The transistor (10) of claim 1 or 2, wherein the resistivity ρ of the terminal region (14) is greater than 10 Ωcm.

5. The transistor (10) of claim 1 or 2, wherein the short-circuit withstand time (SCWT) of the transistor is greater than 3 μs.

6. 3. The transistor (10) of claim 1, wherein the implantation depth d of the at least one resistor region (16) is in the range of 0 to 100% of the maximum thickness of the at least one terminal region (14).

7. The at least one terminal region (14) comprises at least three subregions, namely, at least one first subregion (45) containing amphoteric impurities and at least one second subregion (18, 19, 46) essentially free of amphoteric impurities. one first sub-region (45) horizontally disposed between and / or separating two adjacent second sub-regions (18, 19, 46); one first sub-region (45) vertically disposed between and / or separating two adjacent second sub-regions (46); a plurality of first sub-regions (45) partially or completely embedded as resistive islands within a common second sub-region (46); a first plurality of first sub-regions (45) and a second plurality of second sub-regions (46) forming at least one of a horizontal grid, a vertical grid, a comb structure, and a checkerboard pattern; The transistor (10) of claim 1 or 2, comprising one of:

8. 3. The transistor (10) of claim 1 or 2, wherein the transistor (10) is one of a metal-oxide-semiconductor field-effect transistor (MOSFET), a metal-insulator-semiconductor field-effect transistor (MISFET), a junction field-effect transistor (JFET), and an insulated-gate bipolar transistor (IGBT) in one of a planar or trench configuration.

9. a substrate (41) of the first conductive region carrying said epitaxial layer (11); at least one highly doped well contact region (28) of said second conductivity type electrically connecting said at least one well region (13) to said at least one terminal electrode (15); a second terminal region and a second electrode formed at least partially on a surface of the second terminal region; at least one channel region (42) formed in said at least one well region (13) adjacent to a gate structure (23); a first insulating layer (25a) formed on the surface (12) of the epitaxial layer (11), and a gate electrode (24) formed on the surface of the first insulating layer (25a); The transistor (10) of claim 1 or 2, further comprising at least one of:

10. 3. A power electronic switching device comprising a plurality of transistor cells arranged on a common substrate and / or electrically connected in parallel, each transistor cell comprising a transistor (10) according to claim 1 or 2.

11. A method for fabricating a transistor (10), comprising the steps of: epitaxially growing a semiconductor layer of a first conductivity type (S2); forming (S3) at least one well region (13) of a second conductivity type formed in a selected region of the epitaxial layer (11); forming (S5) at least one terminal region (14) of said first conductivity type within or adjacent to said at least one well region (13); implanting manganese (Mn) as an amphoteric dopant into at least a portion of said at least one terminal region (14) (S7); A method comprising:

12. 12. The method of claim 11, wherein the amphoteric dopant is implanted using an implant energy in the range of 50 to 1000 keV.

13. The amphoteric dopant is 10 １０ cm －２ ~10 １４ cm －２ 13. The method of claim 11 or 12, wherein the injection is performed using an injection volume in the range of

14. At least one resistive region (16) containing the implanted amphoteric dopant is heated to a first temperature T １ Annealing (S8) at the first temperature T １ is selected based on the target resistivity ρ of the terminal region (14), 13. The method of claim 11 or 12, further comprising:

15. Before annealing (S8) the at least one resistor region (16), the at least one terminal region (14) is heated to the first temperature T １ A second temperature T ２ (S6), and / or After implanting the amphoteric dopant (S7), forming at least one terminal electrode (15) at least partially on the surface (12) of at least a portion of the at least one terminal region (14) (S9).

15. The method of claim 14, further comprising:

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