Frequency generation for multi-antenna transceiver systems

Abstract

A multi-antenna transceiver system is disclosed. The system includes a group of transceiver chips and a reference frequency generator configured to provide a reference frequency to each transceiver chip of the group. Each transceiver chip has a respective chip-associated (e.g., on-chip) frequency generator configured to provide a respective conversion frequency based on the reference frequency, each of the respective conversion frequencies being higher than the reference frequency. Each transceiver chip is configured to use the respective conversion frequency for on-chip frequency conversion of transceiver signals. The reference frequency can be provided directly to each transceiver chip of the group. Alternatively, the reference frequency can be provided directly to a first transceiver chip of the group and provided via the first transceiver chip to a second transceiver chip of the group. The multi-antenna transceiver system may also include baseband processing circuitry configured to process transceiver signals for the transceiver chips, and the baseband processing circuitry can be further configured to estimate a first respective phase shift of each of the respective chip-associated frequency generators and compensate the transceiver signals based on the first respective phase shift. Also disclosed are corresponding baseband processors, network nodes, wireless communication devices, methods and computer program products.

Description

[Technical Field]

[0001] Technical Field The present disclosure relates generally to the field of multi-antenna transceiver systems, and more particularly to generating conversion frequencies in multi-antenna transceiver systems. [Background technology]

[0002] background A multi-antenna transceiver can be constructed using multiple transceiver chips, each associated with one or more corresponding antenna elements, and a frequency generator can provide a signal indicative of a translation frequency to each of the transceiver chips for on-chip frequency translation of the transceiver signal in each of the transceiver chips. Summary of the Invention [Problem to be solved by the invention]

[0003] Providing signals from the frequency generator to each of the transceiver chips can pose problems, particularly the relatively high conversion frequency. For example, the transmission of signals between the frequency generator and the transceiver chips can cause interference. Alternatively or additionally, the transmission of signals between the frequency generator and the transceiver chips can cause power dissipation.

[0004] Therefore, there is a need for an alternative approach to providing conversion frequencies for multi-antenna transceiver systems. [Means for solving the problem]

[0005] overview It should be emphasized that the term "comprises / comprising" (which is interchangeable with "includes / including"), when used in this specification, is introduced to specify the presence of the stated features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps, components or groups thereof. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0006] Generally, when reference is made herein to an array, it should be understood to be a physical product (e.g., a device), which may include one or more components, such as control circuitry in the form of one or more controllers, one or more processors, or the like.

[0007] It is an object of some embodiments to solve, mitigate, alleviate or eliminate at least some of the above or other disadvantages.

[0008] A first aspect is a multi-antenna transceiver system that includes a group of transceiver chips and a reference frequency generator configured to provide a reference frequency for each transceiver chip of the group.

[0009] Each transceiver chip has a respective chip-associated frequency generator configured to provide a respective conversion frequency based on a reference frequency, each of the respective conversion frequencies being higher than the reference frequency, and each transceiver chip is configured to use the respective conversion frequency for on-chip frequency conversion of transceiver signals.

[0010] In some embodiments, the group of transceiver chips includes two or more disjoint groups of transceiver chips, and the reference frequency generator includes a respective reference frequency generator for each group of transceiver chips.

[0011] In some embodiments, the reference frequency is provided directly to each transceiver chip in the group.

[0012] In some embodiments, the reference frequency is provided directly to a first transceiver chip of the group, and the reference frequency is provided via the first transceiver chip to a second transceiver chip of the group.

[0013] In some embodiments, the multi-antenna transceiver system further includes baseband processing circuitry configured to process transceiver signals for the transceiver chip.

[0014] In some embodiments, the baseband processing circuitry is further configured to estimate a first respective phase shift of each of the respective chip-associated frequency generators and compensate the transceiver signal based on the first respective phase shift.

[0015] In some embodiments, the baseband processing circuitry is further configured to estimate a frequency error for each chip-associated frequency generator and to control the reference frequency generator based on the frequency error.

[0016] In some embodiments, the baseband processing circuitry is further configured to estimate baseband correlation timing for at least one transceiver chip and control baseband correlation for at least one other transceiver chip based on the estimated baseband correlation timing.

[0017] In some embodiments, the baseband processing circuitry is further configured to obtain a second respective phase shift for each transceiver chip, and to compensate the transceiver signal based on the second respective phase shift.

[0018] In some embodiments, the second respective phase shift is associated with the relative mounting position of the transceiver chips.

[0019] In some embodiments, each of the respective conversion frequencies is greater than 24 GHz (eg, between 24 and 300 GHz) and / or the reference frequency is less than 1 GHz (eg, between 150 and 500 MHz).

[0020] A second aspect is a baseband processor for a multi-antenna transceiver system, the baseband processor configured to process transceiver signals for a group of transceiver chips included in the multi-antenna transceiver system, each transceiver chip having a respective chip-associated frequency generator configured to provide a respective conversion frequency based on a reference frequency provided by a reference frequency generator included in the multi-antenna transceiver system, each of the respective conversion frequencies being higher than the reference frequency.

[0021] The baseband processor includes a baseband processing circuit configured to estimate a first respective phase shift of each of the respective chip-associated frequency generators and to compensate the transceiver signal based on the first respective phase shift.

[0022] A third aspect is a network node including the multi-antenna transceiver system of the first aspect and / or the baseband processor of the second aspect.

[0023] A fourth aspect is a wireless communication device including the multi-antenna transceiver system of the first aspect and / or the baseband processor of the second aspect.

[0024] A fifth aspect is a method for operating a multi-antenna transceiver system including a group of transceiver chips and a reference frequency generator, wherein the reference frequency generator is configured to provide a reference frequency to each transceiver chip of the group, each transceiver chip having a respective chip-associated frequency generator configured to provide a respective conversion frequency based on the reference frequency, each of the respective conversion frequencies being higher than the reference frequency, and each transceiver chip configured to use the respective conversion frequency for on-chip frequency conversion of transceiver signals.

[0025] The method includes estimating a first respective phase shift of each of the respective chip-associated frequency generators and compensating the transceiver signal based on the first respective phase shift.

[0026] A sixth aspect is a computer program product comprising a non-transitory computer readable medium having a computer program comprising program instructions, the computer program being loadable into a data processing unit and configured to cause the computer program to perform a method according to the fifth aspect when run by the data processing unit.

[0027] In some embodiments, any of the above aspects may have additional features that are the same as or equivalent to any of the various features as described above for any of the other aspects.

[0028] An advantage of some embodiments is that an alternative (eg, improved) approach to providing conversion frequencies for a multi-antenna transceiver system is provided.

[0029] An advantage of some embodiments is that interference and / or power dissipation caused by signal transmission between a common frequency generator and a transceiver chip is reduced compared to prior art approaches. Because the signal transmission is for a reference frequency that is lower than the conversion frequency, transmission problems that are more severe at relatively high frequencies are mitigated. Signal transmission at the conversion frequency may be constrained to on-chip transmission only or to relatively short and / or advantageous inter-chip distances.

[0030] An advantage of some embodiments is that the implementation (e.g., printed circuit board (PCB) design) for the multi-antenna transceiver is simplified compared to the prior art, e.g., the impact of process variations on any implementation can be reduced.

[0031] An advantage of some embodiments is that the combining of received signals across transceiver chips can be performed coherently. Coherent combining is possible because phase differences between transceiver chips (e.g., due to phase offsets in chip-related frequency generators and / or phase shifts introduced by the transmission of received signals from the transceiver chip to the baseband circuitry) are estimated and compensated for.

[0032] BRIEF DESCRIPTION OF THE DRAWINGS Further objects, features, and advantages will become apparent from the following detailed description of the embodiments, taken in conjunction with the accompanying drawings, in which: The drawings are not necessarily to scale, emphasis instead being placed upon illustrating illustrative embodiments. [Brief explanation of the drawings]

[0033] [Figure 1] 1 is a schematic block diagram illustrating an exemplary multi-antenna transceiver system with a single frequency generator. [Figure 2] 1 is a schematic block diagram illustrating an exemplary multi-antenna transceiver system according to some embodiments. [Figure 3]1 is a schematic block diagram illustrating an exemplary multi-antenna transceiver system according to some embodiments. [Figure 4] 1 is a schematic block diagram illustrating an exemplary multi-antenna transceiver system according to some embodiments. [Figure 5] 1 is a schematic block diagram illustrating an exemplary multi-antenna transceiver system according to some embodiments. [Figure 6] 1 is a schematic block diagram illustrating an exemplary transceiver chip for a multi-antenna transceiver system according to some embodiments. [Figure 7] 1 is a schematic block diagram illustrating an example baseband processor for a multi-antenna transceiver system according to some embodiments. [Figure 8] 1 is a schematic block diagram illustrating an example phase shifter for a multi-antenna transceiver system according to some embodiments. [Figure 9] 1 is a flowchart illustrating exemplary method steps according to some embodiments. [Figure 10] 1 is a schematic diagram illustrating an exemplary computer-readable medium according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0034] Detailed Description As already mentioned above, it should be emphasized that the term "comprises / comprising" (which is interchangeable with "includes / including"), when used in this specification, is taken to specify the presence of the stated features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps, components or groups thereof. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0035]

[0023] Embodiments of the present disclosure will now be more fully described and illustrated with reference to the accompanying drawings, in which:

[0024] However, the solutions disclosed herein may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein;

[0036] In general, when reference is made herein to the provision / use etc. of a frequency, this can be understood to include the provision / use etc. of a signal indicative of the frequency.

[0037] Also generally, when reference is made herein to an antenna element, it may be, for example, an antenna that is a component of a multi-antenna arrangement (eg, an antenna array, antenna matrix, antenna panel, etc.).

[0038] Also, while up-conversion and down-conversion are generally illustrated herein as being between high frequency and baseband frequencies, it should be understood that the embodiments are equally applicable to up-conversion and / or down-conversion through one or more intermediate frequencies.

[0039] Furthermore, when reference is made herein to a functional unit of a transceiver chain (e.g., an ADC, a DAC, a frequency converter, a mixer, a filter, etc.), it should be understood that such reference may include a pair of functional units for in-phase / quadrature-phase processing.

[0040] Multi-antenna transceivers can be used for multiple-input multiple-output (MIMO, e.g., massive MIMO or conventional MIMO) communications and / or for beamforming communications (e.g., transmit precoding and / or receive combining). In such applications, transmit / receive signals typically differ between antenna elements, while baseband components are typically the same for some (e.g., all) transceiver chips. Thus, baseband processing may typically include processing of radio frequency signals that are simultaneously received or transmitted by different antenna elements on the same carrier frequency.

[0041] In some embodiments, the multi-antenna transceiver systems presented herein, or portions thereof, may be particularly suitable for massive MIMO and / or beamforming.

[0042] In general, transceiver architectures for massive MIMO and / or beamforming can be implemented using analog multi-antenna control, digital multi-antenna control or hybrid multi-antenna control.

[0043] In analog multi-antenna control, beamforming is typically performed at radio frequency (RF) using a bank of phase shifters (one per antenna element), an analog power combiner for the receiver, and a power splitter for the transmitter. This typically requires only one analog-to-digital converter (ADC) instance for the receiver (typically a pair of ADCs for in-phase / quadrature-phase conversion) and one digital-to-analog converter (DAC) instance for the transmitter (typically a pair of DACs for in-phase / quadrature-phase conversion), thereby reducing complexity compared to requiring more ADC / DAC instances. Antenna elements can be clustered and implemented in the form of an antenna panel.

[0044] In digital multi-antenna control, beamforming is typically performed at baseband frequencies (e.g., in a digital baseband processor). Typically, each transceiver chain requires an ADC instance (typically, a pair of ADCs) and a DAC instance (typically, a pair of DACs). Digital beamforming transceivers can, at least in theory, be configured to point beams in an infinite number of directions simultaneously. Thus, digital beamforming transceivers excel at tracking high-frequency signals (e.g., when a mobile device moves at high speed relative to a high-frequency base station).

[0045] As previously mentioned, a multi-antenna transceiver (digital) can be built using multiple transceiver chips and a frequency generator that provides conversion frequencies to each of the transceiver chips.

[0046] 1 schematically illustrates an exemplary multi-antenna transceiver system 100 comprising multiple transceiver chips (TX / RX) 101, 102 and a single frequency generator (FG) 110 that provides a conversion frequency 111 to each of the transceiver chips. The exemplary system 100 also includes a baseband processor (BBP) 120 configured to process transceiver signals for the transceiver chips.

[0047] FIG. 1 shows an exemplary schematic architecture of a transceiver chip 101, 102.

[0048] The exemplary architecture includes a receiver path (RX) 191 and a transmitter path (TX) 192. The receiver path includes a downconverter (DC) 195, and the transmitter path includes an upconverter (UC) 196. Each of the downconverter and upconverter receives a conversion frequency from a frequency generator for on-chip frequency conversion of transceiver signals (i.e., downconversion of received signals in the receiver path and / or upconversion of signals to be transmitted in the transmitter path).

[0049] Receiver path 191 and transmitter path 192 may generally include any suitable functional and / or physical components (e.g., as known in the art). The receiver path may include, for example, a low noise amplifier (LNA), a mixer circuit (for down-conversion), one or more filters (e.g., low-pass filters LPF), and a variable gain amplifier. The transmitter may include, for example, one or more filters (e.g., low-pass filters LPF), a mixer circuit (for up-conversion), and a power amplifier (PA).

[0050] Additionally, an exemplary architecture for a transceiver chip includes a front end (FE) 194 and an interface (IF) 193. The interface 193 is for connection to the baseband processor 120 and may have any suitable functionality and / or physical components (e.g., as known in the art).

[0051] The front end 194 may be for connection to or may include one or more on-chip antenna elements. Thus, each transceiver chip 101, 102 of the multi-antenna transceiver system 100 is associated with one or more corresponding antenna elements. Moreover, the front end 194 may include any suitable functional and / or physical components (e.g., as known in the art). For example, the front end 194 may include duplexer or diplexer circuitry (e.g., switching circuitry, filters, etc.) for separating received signals from signals to be transmitted.

[0052] Thus, in a typical digital beamforming solution using transceivers associated with different antenna elements provided on different RF chips (compared to transceiver chips 101, 102), the carrier (frequency f c A single local oscillator (LO, compared to frequency generator 110) is used to generate the carriers (LO, compared to 111), which are then distributed to all RF chips.

[0053] The RF signal for RF chip i (i=1, ..., N) is

number

number

[0054] However, as previously mentioned, providing signals from a frequency generator to each of the transceiver chips can pose problems (e.g., in terms of interference and / or power dissipation), particularly for relatively high conversion frequencies. For example, when the digital beamforming architecture described in connection with FIG. 1 is applied to millimeter wavelength (mmWave) frequencies (e.g., above 24 GHz), routing the mmWave frequency conversion frequency signal 111 on a printed circuit board (PCB) typically creates significant power dissipation and interference challenges. Therefore, such an approach is generally not feasible for mmWave frequencies, particularly in size- and / or power-constrained devices (e.g., handheld user devices).

[0055] The following describes embodiments in which conversion frequencies for on-chip frequency conversion of transceiver signals in a multi-antenna transceiver system are provided in a novel and advantageous manner.

[0056] In general, some embodiments are particularly suited to scenarios that employ relatively high conversion frequencies (eg, mmW frequencies), although application of the embodiments is not limited thereto.

[0057] Also, in general, some embodiments are particularly suited for massive MIMO and / or precise beamforming, although application of the embodiments is not limited thereto.

[0058] Also, in general, any of the multi-antenna transceiver systems, transceiver chips / packages, baseband processors and / or frequency generators (referenced, on-chip or chip-related) described herein may be for use with (e.g., can be included in or are included in) any suitable communications device. Exemplary suitable communications devices include network nodes (e.g., base stations, access points (APs), fixed wireless access (FWA) units, extraterrestrial transceivers (e.g., satellites or unmanned aerial vehicles (UAVs)), etc.) and wireless communications devices (e.g., user equipment (UE), stations (STAs), Internet of Things (IoT) devices, etc.).

[0059] 2 illustrates an exemplary multi-antenna transceiver system 200 according to some embodiments. The exemplary system 200 includes multiple (e.g., groups of) transceiver chips (TX / RX) 201, 202 and a reference frequency generator (RFG) 210. The exemplary system 200 may also include a baseband processor (BBP) 220 configured to process transceiver signals for the transceiver chips. For example, the baseband circuitry may include one or more baseband processing chips.

[0060] Similar to frequency generator 110 of FIG. 1, reference frequency generator 210 is configured to provide a signal indicative of a frequency to each of the transceiver chips.

[0061] However, in contrast to system 100 of FIG. 1 , the frequency provided by reference frequency generator 210 in exemplary system 200 is reference frequency 211, which is lower (as compared to 111 in FIG. 1 ) than the conversion frequency used for on-chip conversion in each of the transceiver chips. Reference frequency generator 210 may be implemented in any suitable manner. For example, reference frequency generator 210 may be a crystal oscillator (XO) and / or a voltage-controlled oscillator. Providing a relatively lower frequency between chips typically results in less power dissipation and / or interference than providing a relatively higher frequency between chips.

[0062] Similar to the exemplary schematic architecture of the transceiver chips 101, 102 of FIG. 1, the exemplary architecture of the transceiver chips 201, 202 includes a front end (FE) 294, an interface (IF) 293, a receiver path (RX) 291 and a transmitter path (TX) 292, where the receiver path includes a downconverter (DC) 295 and the transmitter path includes an upconverter (UC) 296.

[0063] The receiver path 291 and the transmitter path 292 may generally include any suitable functional and / or physical components. The receiver path may include, for example, a low noise amplifier (LNA), a mixer circuit (for down-conversion), one or more filters (e.g., a low pass filter LPF), a variable gain amplifier, and possibly an analog-to-digital converter (ADC) instance. The transmitter may include, for example, one or more filters (e.g., a low pass filter LPF), a mixer circuit (for up-conversion), a power amplifier (PA), and possibly a digital-to-analog converter (DAC) instance.

[0064] Interface 293 is for connection to baseband processor 220 and may have any suitable functionality and / or physical components.

[0065] The front end 294 may be for connection to or may include one or more on-chip antenna elements. Thus, each transceiver chip 201, 202 of the multi-antenna transceiver system 200 is associated with one or more corresponding antenna elements. Moreover, the front end 294 may include any suitable functional and / or physical components. For example, the front end 294 may include duplexer or diplexer circuitry (e.g., switching circuitry, filters, etc.) for separating received signals from signals to be transmitted.

[0066] In general, duplexers or diplexers can be implemented using surface acoustic wave (SAW) technology, bulk acoustic wave (BAW) technology, waveguide technology, lumped RLC elements (on-chip and / or discrete components) and / or transmission lines.

[0067] 1, each of the downconverters 295 and upconverters 296 of the exemplary transceiver chip architecture of FIG. 2 receives a conversion frequency from an on-chip frequency generator (OFG) 297 (for on-chip frequency conversion of transceiver signals). The on-chip frequency generator 297 is configured to provide the conversion frequency based on a reference frequency 211 provided by a reference frequency generator 210. As mentioned above, although the conversion frequency is higher than the reference frequency, on-chip provision of a relatively high frequency is much less problematic (e.g., in terms of power dissipation and / or interference) than inter-chip provision.

[0068] Typically, the conversion frequency should be the same for all transceiver chips. However, due to instantiation variations, the phase of the signal indicating each conversion frequency for each transceiver chip may be different. Alternatively or additionally, due to instantiation variations, there may be slight frequency differences between the respective conversion frequencies provided for each transceiver chip.

[0069] Generally, the conversion frequency is higher than the reference frequency. Typically, the conversion frequency may be significantly higher than the reference frequency. For example, the conversion frequency may be higher than 24 GHz and / or the reference frequency may be lower than 1 GHz.

[0070] In the example of Figure 2, the frequency generator configured to provide the conversion frequency is an on-chip frequency generator (i.e., implemented on the transceiver chip, e.g., may be an integrated circuit IC chip), and a reference frequency is provided to each transceiver chip.

[0071] In other embodiments, the frequency generator configured to provide the conversion frequency is implemented separately from the transceiver chip (e.g., on a separate chip), but may be implemented in association with the transceiver chip, and a reference frequency may be provided to the frequency generator (i.e., for the transceiver chip).

[0072] For example, the chip-associated frequency generator may be implemented on a separate chip that is included in the same package (e.g., encapsulation) as the transceiver chip. One example of an implementation in which the chip-associated frequency generator is implemented on a separate chip that is included in the same package as the transceiver chip is referred to as a system-in-package (SIP).

[0073] Alternatively or additionally, the chip-associated frequency generator may be implemented on a separate chip with shorter and / or more efficient wiring (e.g., package wiring) to the transceiver chip than the reference frequency generator has.

[0074] In some embodiments, a chip-associated frequency generator may be shared by two or more (but not all) transceiver chips.

[0075] In some embodiments, a separate chip may implement other (eg, digital) functionality in addition to chip-related frequency generation.

[0076] When referring to a chip-related frequency generator, both on-chip and separate frequency generator implementation possibilities are included.

[0077] In general, the chip-related frequency generator may be implemented using any suitable technique capable of generating an output frequency based on an input frequency. For example, the chip-related frequency generator may be implemented using a phase-locked loop (PLL).

[0078] 2, the reference frequency is provided directly to each transceiver chip 201, 202 (which in the general case would correspond to providing the reference frequency directly to each of the chip-associated frequency generators). Thus, the reference frequency 211 is provided to the transceiver chips in parallel.

[0079] An alternative form is shown in FIG. 3, in which the reference frequency is provided directly to one, first, transceiver chip (or generally, one, first, chip-related frequency generator) and provided via the first transceiver chip (or generally, via the first chip-related frequency generator) to other transceiver chips (or generally, other chip-related frequency generators).

[0080] 3 illustrates an exemplary multi-antenna transceiver system 300 according to some embodiments. The exemplary system 300 includes multiple (e.g., groups of) transceiver chips (TX / RX) 301, 302 and a reference frequency generator (RFG) 310. The exemplary system 300 may also include a baseband processor (BBP) 320 configured to process transceiver signals for the transceiver chips. Any aspect of the baseband processor 220 described in connection with FIG. 2 may be applied to the baseband processor 320.

[0081] Similar to reference frequency generator 210 of Figure 2, reference frequency generator 310 is configured to provide a signal indicative of a reference frequency 311 to each of the transceiver chips. Any aspect of reference frequency generator 210 described in relation to Figure 2 can be applied to reference frequency generator 310.

[0082] 2, however, the reference frequency 311 is not provided directly to each transceiver chip 301, 302. Instead, the reference frequency 311 is provided directly only to the first transceiver chip 302 and, via the first transceiver chip 302, to the other transceiver chips 301.

[0083] In a typical example, the reference frequency 311 is provided sequentially from a first transceiver chip to a second transceiver chip, from the second transceiver chip to a third transceiver chip, and so on, until the last transceiver chip (i.e., the reference frequency 311 is provided sequentially to the transceiver chips), but other providing patterns are also possible (e.g., the reference frequency is provided from a first transceiver chip to multiple second transceiver chips).

[0084] Similar to the exemplary schematic architecture of transceiver chips 201, 202 of Figure 2, the exemplary architecture of transceiver chips 301, 302 includes a front end (FE) 394, an interface (IF) 393, a receiver path (RX) 391, and a transmitter path (TX) 392, the receiver path including a downconverter (DC) 395, and the transmitter path including an upconverter (UC) 396, each receiving a conversion frequency from an on-chip, or generally chip-associated, frequency generator (OFG) 397 (for on-chip frequency conversion of transceiver signals). Any aspect of the exemplary schematic architecture described in connection with Figure 2 can be applied to the exemplary schematic architecture of Figure 3.

[0085] However, in contrast to the exemplary architecture of Figure 2, at least one (e.g., first) transceiver chip (typically all transceiver chips) of Figure 3 includes a reference frequency output (in addition to the reference frequency input) for providing a reference frequency to one or more additional (e.g., second) transceiver chips. In some embodiments, the signal at the reference frequency input is repeated and provided at the reference frequency output.

[0086] More generally, a package containing a transceiver chip and its associated frequency generator includes a reference frequency input and a reference frequency output, the latter for providing a reference frequency to one or more additional transceiver chip packages, and thus the wiring from the reference frequency input to the reference frequency output does not necessarily have to be on the transceiver chip itself.

[0087] An advantage of these embodiments is that the effort (e.g., wire length) of routing the reference frequency signal on the PCB can be reduced and / or the risk of PCB leakage of the reference frequency signal can be reduced, resulting in less power loss and / or interference.

[0088] In the example of FIGS. 2 and 3, multiple transceiver chips are all arranged in a single group, and a single reference frequency generator provides reference frequencies for all the transceiver chips.

[0089] An alternative embodiment is shown in Figures 4 and 5, in which the multiple transceiver chips of an exemplary multi-antenna transceiver system 400, 500 are arranged into two or more groups (401a-402a and 401b-402b, and 501a-502a and 501b-502b), and each of two or more respective reference frequency generators (i.e., one reference frequency generator per group) 410a-410b and 510a-510b provides a reference frequency for all the transceiver chips in the corresponding group. The groups are typically disjoint (i.e., no transceiver chip is included in more than one group).

[0090] In general, the reference frequency may be the same for all groups or may differ between at least two (eg, some or all) of the groups.

[0091] By arranging multiple transceiver chips in two or more groups (instead of one group), the wiring for providing the reference frequencies (e.g., the total length of wiring from the reference frequency generator to the transceiver chips and / or the maximum length of wiring) can be reduced. Furthermore, flexibility is increased. For example, such a system can be used for operation in multi-band scenarios (e.g., carrier aggregation and / or dual connectivity) by controlling the reference frequency generator to provide different reference frequencies.

[0092] 2 or 3 may be applied to the exemplary systems of FIGS. 4 and 5 (e.g., with respect to baseband processors (BBPs) 420, 520, exemplary architectures of transceiver chips (or transceiver chip packages), frequency characteristics, etc.). In this regard, it should be noted that system 400 of FIG. 4 (in which a reference frequency is provided to each group of transceiver chips in parallel) may be compared to single-group system 200 of FIG. 2, and system 500 of FIG. 5 (in which a reference frequency is provided to each group of transceiver chips sequentially) may be compared to single-group system 300 of FIG. 3.

[0093] 6 illustrates an exemplary transceiver chip 600 for a multi-antenna transceiver system according to some embodiments. For example, the transceiver chip 600 can be used as any of the transceiver chips of FIGS.

[0094] The transceiver chip 600 includes a front end 694 , an interface 693 , a receiver path 691 and a transmitter path 692 .

[0095] The receiver path 691 includes a low noise amplifier 602, a downconverter in the form of a mixer (MIX) 695, a low pass filter (LPF) 603, a variable gain amplifier (VGA) 604 and possibly an analog-to-digital converter (ADC) instance 605.

[0096] The transmitter path 692 includes a low pass filter (LPF) 607 , an up-converter in the form of a mixer (MIX) 696 , a power amplifier 606 and possibly a digital-to-analog converter (DAC) instance 608 .

[0097] Interface 693 is for connection to the baseband processing circuitry and may have any suitable functionality and / or physical components. Interface 693 is a digital interface when ADC instance 605 and DAC instance 608 are included on the transceiver chip, and interface 693 is an analog interface when the transceiver chip does not include an ADC or DAC (the ADC / DAC are implemented in separate circuitry or in the baseband processing circuitry).

[0098] The front end 694 may be for connection to one or more antenna elements (e.g., via an antenna port on the transceiver chip) or may include one or more on-chip antenna elements, as indicated by the dashed schematic antenna element 698 in Figure 6. Thus, the transceiver chip 600 is associated with one or more corresponding antenna elements.

[0099] Additionally, the front end 694 may include any suitable functional and / or physical components. For example, the front end 694 may include a duplexer or diplexer circuit (DP) 601 for separating a received signal from a signal to be transmitted.

[0100] Each of the down-converter mixers 695 and up-converter mixers 696 of the transceiver chip 600 receives a conversion frequency (for on-chip frequency conversion of the transceiver signals) from an on-chip (or chip-related) frequency generator (OFG) 697. As explained above, the on-chip frequency generator 697 is configured to provide the conversion frequency based on a reference frequency 611 provided to the transceiver chip 600. More generally, the chip-related frequency generator is configured to provide the conversion frequency based on a reference frequency provided to a chip-related frequency generator for the transceiver chip.

[0101] 3 and 5, the transceiver chip 600 may include a reference frequency output (in addition to a reference frequency input) for providing a reference frequency 611 to one or more additional transceiver chips. More generally, a package containing a transceiver chip and its associated frequency generator may include a reference frequency input and a reference frequency output, the latter for providing a reference frequency to one or more additional transceiver chip packages.

[0102] In some embodiments, a transceiver chip for time division duplex (TDD) operation includes a transmitter path and a receiver path, and at least one of a single filter circuit (e.g., a single quadrature-phase filter circuit, a pair of filters for in-phase / quadrature-phase filtering) and a single mixer circuit (e.g., a single quadrature-phase mixer circuit, a pair of mixers for in-phase / quadrature-phase mixing) is shared by the transmitter path and the receiver path. Such a transceiver chip can be used, for example, for a multi-antenna transceiver system. Any aspects of other transceiver chips described herein (e.g., in connection with FIG. 6) can be applied to the transceiver chips of these embodiments.

[0103] This transceiver chip can be implemented by configurable (e.g., by a controller or baseband processor) a single mixer circuit for a receive mode or a transmit mode. In the receive mode, the mixer circuit is configured to select a signal at a first input node connected to a receiver path (e.g., an LNA output) for conversion and provide a mixed signal at a first output node of the mixer circuit connected to a filter circuit of the receiver path. In the transmit mode, the mixer circuit is configured to select a signal at a second input node connected to a filter circuit of the transmitter path for conversion and provide a mixed signal at a second output node of the mixer circuit connected to the transmitter path (e.g., a PA input). If the filter circuit is a single shared filter circuit, the first output node and the second input node can be coincident.

[0104] Alternatively or additionally, the transceiver chip can be implemented by providing a single filter circuit configurable for a receive mode or a transmit mode. In the receive mode, the filter circuit is configured to select a signal at a first input node connected to a mixer circuit of a receiver path for filtering and provide a filtered signal at a first output node of the filter circuit connected to the receiver path (e.g., a VGA input). In the transmit mode, the filter circuit is configured to select a signal at a second input node connected to a transmitter path (e.g., an interface or DAC output) for filtering and provide a filtered signal at a second output node of the filter circuit connected to the mixer circuit of the transmitter path. If the mixer circuit is a single shared mixer circuit, the first input node and the second output node may be coincident.

[0105] Thus, a transceiver chip for TDD operation may include a front end, an interface, a receiver path, and a transmitter path. The receiver path may include a low noise amplifier, a downconverter in the form of a shared mixer, a shared low pass filter, a variable gain amplifier, and possibly an analog-to-digital converter. The transmitter path may include a shared low pass filter, an upconverter in the form of a shared mixer, a power amplifier, and possibly a digital-to-analog converter.

[0106] A shared mixer on the transceiver chip receives a conversion frequency from an on-chip (or chip-associated) frequency generator (for on-chip frequency conversion of transceiver signals). In receive mode, the shared mixer selects the signal output from the LNA for conversion and provides the result to the shared low-pass filter. In transmit mode, the shared mixer selects the signal from the shared low-pass filter for conversion and provides the result at the input of the PA.

[0107] In a shared low-pass filter implementation, a selector (e.g., a switch) controls filter operation for receive or transmit mode. In receive mode, a first selector is set to direct a signal provided by the mixer circuit to the input of the actual filter circuit, a second selector is set to direct a signal provided at the output of the actual filter circuit to a third selector, and the third selector is set to direct a signal provided by the second selector to the VGA. In transmit mode, the third selector is set to direct a signal provided by the transmitter path (interface or DAC) to the second selector, the second selector is set to direct a signal provided by the third selector to the input of the actual filter circuit, and the first selector is set to direct a signal provided at the output of the actual filter circuit to the mixer circuit.

[0108] In an alternative implementation of the shared low-pass filter, a selector (e.g., a switch) controls filter operation for receive or transmit mode. In receive mode, the first selector is set to direct the signal provided by the mixer circuit to the third selector, the third selector is set to direct the signal provided by the first selector to the input of the actual filter circuit, and the second selector is set to direct the signal provided at the output of the actual filter circuit to the VGA. In transmit mode, the third selector is set to direct the signal provided by the transmitter path (interface or DAC) to the input of the actual filter circuit, the second selector is set to direct the signal provided at the output of the actual filter circuit to the first selector, and the first selector is set to direct the signal provided by the second selector to the mixer circuit.

[0109] It should be noted that the example of Figure 8 can be implemented in variations according to some embodiments. For example, one or more of the switches can be omitted or replaced with wiring nodes. Alternatively or additionally, the low-pass filter can include a single pair of in-phase / quadrature-phase connection points for the VGA / DAC, and distribution to the VGA or DAC is via the wiring nodes.

[0110] A controller (whether associated with the chip or not) can be adapted to configure the shared mixer circuit and the shared low pass filter circuit in a receive mode or a transmit mode.

[0111] 7 illustrates an exemplary baseband processor (BBP, e.g., baseband processing circuit or module) 720 for a multi-antenna transceiver system according to some embodiments. For example, the baseband processor 720 may be used as any of the baseband processors of FIGS. 2-5.

[0112] As mentioned above, the phase of the signal representing each conversion frequency for each transceiver chip may vary due to variations in instantiation. Thus, for transceiver chip i (i=1, ..., N), there is an unknown, chip-specific phase φ i is the baseband signal S i (t) to S i (t)e jφi , which impairs the possibility of coherent operation (e.g., coherent combining for reception).

[0113] To mitigate the impact of that disadvantage, the baseband processor 720 may be configured to estimate a first respective phase shift for each of the respective transceiver chips (typically with respect to each of the chip-associated frequency generators) and compensate the transceiver signals based on the first respective phase shift. The first respective phase shift for the chip-associated frequency generators may be determined in any suitable manner (e.g., by correlating the received signal with known signal components).

[0114] For example, the baseband processor may generate an estimated first phase shift associated with a chip-related frequency generator of a transceiver chip i (i=1, . . . , N).

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[0115] To this end, the baseband processor may include a first phase shifter (PS, e.g., a phase shift circuit or phase shift module) 721. The first phase shifter may be configured to estimate a first respective phase shift of each of the respective chip-associated frequency generators and to compensate the transceiver signal based on the first respective phase shift.

[0116] Alternatively or additionally, the phase of the baseband signal for each transceiver chip may be affected differently by the physical placement of the different transceiver chips / packages (e.g., different wiring lengths between the reference frequency generator and the transceiver chips / packages and / or different physical locations of the antenna elements, resulting in constructive or destructive coupling). For example, such phase differences may be associated with the relative mounting locations of the transceiver chips / packages within a multi-antenna transceiver system.

[0117] To mitigate the impact of that disadvantage, the baseband processor 720 may be configured to obtain a second respective phase shift for each of the respective transceiver chips (typically for each of the chip-associated frequency generators) and compensate the transceiver signals based on the second respective phase shift.

[0118] To this end, the baseband processor may include a second phase shifter (PS, e.g., a phase shift circuit or a phase shift module), which may be combined with the first phase shifter 721. The second phase shifter may be configured to obtain a second respective phase shift for each of the respective chip-associated frequency generators and to compensate the transceiver signal based on the first respective phase shift.

[0119] For example, the second respective phase shift of each of the respective chip-associated frequency generators may be pre-computed based on the relative physical positions of the transceiver chips / packets (e.g., the distance between them) and stored in a database or memory included in (or associated with) the baseband processor, e.g., in the form of a look-up table LuT that provides a mapping between the transceiver chips / packets and the second respective phase shifts. Obtaining the second respective phase shift of each of the respective chip-associated frequency generators may then include reading the corresponding value from the memory.

[0120] In general, compensation for the phase shift (first and / or second) is preferably performed separately for each transceiver chip signal before combining for signal reception and before providing the signal to the transceiver chip for signal transmission.

[0121] Alternatively or additionally, due to variations in instantiation, there may be slight frequency differences between the respective conversion frequencies provided for each transceiver chip and / or between the respective conversion frequencies and the carrier frequency of the received radio frequency signal.

[0122] To mitigate the impact of that disadvantage, the baseband processor 720 can be configured to estimate the frequency error for the chip-related frequency generators and control the reference frequency generators based on the frequency error (e.g., by mapping the frequency error via a look-up table to an electrical signal that can be provided to the reference frequency generator to update the reference frequency). The individual frequency errors for the chip-related frequency generators can be determined in any suitable manner (e.g., by correlating the received signal with known signal components).

[0123] Typically, a common (e.g., combined) frequency error value can be determined for all chip-associated frequency generators of the group (e.g., an average of the individual frequency errors or a selected one of the individual frequency errors for each of the chip-associated frequency generators), and the reference frequency generator can be controlled to thereafter eliminate the common frequency error value.

[0124] To this end, the baseband processor may include a frequency controller (FC, e.g., frequency control circuit or frequency control module) 722. The frequency controller may be configured to estimate a frequency error for a chip-related frequency generator and to control a reference frequency generator based on the frequency error.

[0125] Alternatively or additionally, the baseband processor 720 may be further configured to estimate baseband correlation timing for at least one transceiver chip (typically for at least one chip-associated frequency generator) and to control baseband correlation for at least one other chip-associated frequency generator based on the estimated baseband correlation timing. The baseband correlation timing for the chip-associated frequency generator may be determined in any suitable manner (e.g., by correlating the received signal with known signal components).

[0126] Typically, a common (e.g., combined) baseband correlation timing value can be determined for all active chip-associated frequency generators of the group (e.g., an average value of the individual baseband correlation timings for each of the chip-associated frequency generators or a selected one of the individual baseband correlation timings).

[0127] The baseband correlation timing value can be used, for example, to calibrate the correlation timing for one of the other chip-related frequency generators (e.g., align the correlation timing for the other chip-related frequency generator with the baseband correlation timing value), which can be particularly useful in achieving initial correlation timing when the other chip-related frequency generators included in the transceiver chip / package become available (e.g., upon recovery from being unavailable in a low-power mode).

[0128] Thus, baseband correlation timing values ​​(e.g., from one or several transceiver chips / packages) can be used as input values ​​for a correlation unit of another transceiver chip / package, so that the correlation timing of the latter is based on the correlation timing values ​​of the former.

[0129] To this end, the baseband processor may include a correlation timer (CT, e.g., correlation timing circuit or correlation timing module) 723. The correlation timer may be configured to estimate baseband correlation timing for at least one transceiver chip and to control baseband correlation for at least one other chip-associated frequency generator based on the estimated baseband correlation timing.

[0130] 8 illustrates an exemplary phase shifter for a multi-antenna transceiver system according to some embodiments. For example, a collection of phase shifters according to FIG. 8 (e.g., one per transceiver chip) can be used as phase shifter 721 of FIG.

[0131] The phase shifter of FIG.

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[0132] The correlator may, for example, include a matched filter, and the correlation process involves multiple (k=1, . . . , K) phase shift hypotheses.

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[0133] The phase shifter also provides a first phase shift 892 (e.g., a complex conjugate of the first phase shift)

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[0134] Optionally, the control unit 802 obtains a second phase shift 894 φ(D i ) The phase shift signal 893 may then be further based on a second phase shift 894. For example, the phase shift signal 893 may be the sum or difference (e.g., the complex conjugate of the sum) of the first phase shift 892 and the second phase shift 894.

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[0135] As previously mentioned, the second phase shift 894 may be related to the relative physical location of the transceiver chips / packages. For example, the second phase shift 894 may be related to the distance D from a reference point of the multi-antenna system to the respective transceiver chips / packages. i (i=1, ..., N).

[0136] For example, the reference point may be the reference frequency generator, for purposes of compensating for phase shifts introduced by transmission wires from the reference frequency generator to each chip-associated frequency generator.

[0137] Depending on the direction of arrival of the radio frequency signal, different radio frequency channel phases are introduced, and the radio frequency channel phase difference between transceiver chips / packages depends on the carrier frequency (i.e., the wavelength of the radio frequency signal) and the relative positions / coordinates of the antenna elements.

[0138] When aiming to compensate for phase shifts caused by the relative positions / coordinates of the antenna elements (perhaps contained in the respective transceiver chips / packages), the reference point may be the position of one of the antenna elements (perhaps corresponding to the position of one of the transceiver chips / packages, for example, on a PCB).

[0139] The phase shifter also includes a multiplier (MULT, e.g., multiplication circuit or module) 803 configured to multiply the received signal 890 by a phase-shifted signal 893, thereby compensating for the first (and possibly second) phase shift. Thus, if the estimate of the first phase shift and the obtained second phase shift are correct, a correctly phase-compensated compensation signal S i (t) 895 is provided. Another variation involves compensating for only the second phase shift.

[0140] Alternatively or additionally, correlator 801 may be used to estimate individual frequency errors (e.g., to control reference frequency generators) and / or individual baseband correlation timing (e.g., to control baseband correlation of one or more asynchronous transceiver chips) compared to 722 and / or 723 of FIG. 7.

[0141] The correlator may include, for example, a matched filter, and the correlation process involves multiple (l=1, . . . , L) frequency error hypotheses.

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[0142] To achieve correlation between the received signal 890 and the known signal component 891, the known signal component can be transmitted from a transmitter separate from the multi-antenna system under consideration (e.g., an external transmitter such as a network node that does not include the multi-antenna system). The known signal component can relate to, for example, a reference signal, a pilot signal, or a synchronization signal (primary and / or secondary synchronization signal (PSS / SSS, e.g., as transmitted in a synchronization signal burst in 5G-NR, a fifth generation new radio technology)).

[0143] Alternatively, to achieve correlation between the received signal 890 and the known signal component 891, one (or some) of the transceiver chips / packages can be configured (e.g., by a baseband processor) to transmit the known signal component, and the correlation can be performed for the other transceiver chip / package acting as a receiver. The known signal component can relate to a reference signal, a pilot signal, or a synchronization signal, for example, as described above. Alternatively, the known signal component can relate to any signal, as it is inherently known to the multi-antenna system under consideration.

[0144] In summary, according to some embodiments, a baseband processor is configured to control a multi-antenna transceiver system including at least two transceiver chips / packages, where the control is for beamforming and / or massive MIMO communications (transmit and / or receive) and can be achieved by configuring the transceiver chips / packages to simultaneously receive or transmit radio frequency signals on the same carrier frequency in at least two of the transceiver chips / packages.

[0145] Typically, the configuration is such that all transceiver chips / packages receive simultaneously or transmit simultaneously, but the baseband processor may also configure a first subset of the transceiver chips / packages to transmit simultaneously and a second subset of the transceiver chips / packages to receive simultaneously.

[0146] Each transceiver chip / package includes a respective chip-associated frequency generator (e.g., local oscillator, LO) that generates a carrier frequency signal that should typically have substantially the same frequency for all of the transceiver chips / packages. The chip-associated LO signal can be used to downconvert (in a mixer) high-frequency signals received via (e.g., integrated within) antenna elements of the transceiver chips / packages to baseband or intermediate-frequency signals, and / or to upconvert (in a mixer) baseband or intermediate-frequency signals to high-frequency signals to be transmitted via (e.g., integrated within) antenna elements of the transceiver chips / packages.

[0147] Chip-related LO signals are generated based on the same reference frequency (typically by using a phase-locked loop (PLL)) by a single reference frequency generator (e.g., a crystal oscillator, XO) that is shared by at least some (e.g., all) of the transceiver chips / packages.

[0148] In some embodiments, the reference frequency is controllable via an electrical input signal (e.g., by a baseband processor), and thus the reference signal can be tuned based on an estimated frequency error of the LO signal.

[0149] Some embodiments relate to a multi-antenna transceiver system including a baseband processor (e.g., a baseband processing unit) and a first group of two or more transceiver chips. Each transceiver chip has a chip-associated (e.g., on-chip) frequency generator (e.g., a local oscillator, LO) configured to generate a first carrier frequency (which is substantially the same for each transceiver chip). The first carrier frequency is for downconverting (e.g., in a mixer) a received high-frequency signal to a signal having a carrier frequency lower than the first carrier frequency and / or for upconverting (e.g., in a mixer) a signal having a carrier frequency lower than the first carrier frequency to a high-frequency signal to be transmitted. The first carrier frequencies of the at least two transceiver chips are generated based on the same reference frequency and are generated by a single reference frequency generator (e.g., a crystal oscillator, XO). The baseband processor is further configured to process reception and / or transmission of high-frequency signals for the at least two transceiver chips simultaneously. The transmission / reception of high frequency signals typically uses the same, second, carrier frequency (e.g., equal to the first carrier frequency when the signal having a carrier frequency lower than the first carrier frequency is a baseband signal, or higher than the first carrier frequency when the signal having a carrier frequency lower than the first carrier frequency is an intermediate frequency signal).

[0150] An advantage of these embodiments is that routing a reference frequency signal, for example, having a frequency below 1 GHz, on a PCB results in fewer interference problems than routing a first carrier frequency signal (e.g., a conversion signal) having an mmWave frequency. The PCB design becomes simpler and is particularly applicable to massive MIMO and beamforming implementations for mobile devices or Internet of Things (IoT) devices. Furthermore, when the second carrier frequency is equal to the first carrier frequency, direct conversion between high-frequency carrier and baseband is applied, thereby enabling a low-complexity implementation of the transceiver chip.

[0151] Some embodiments further relate to a baseband processor configuring the transceiver chip i to receive a signal corresponding to a known signal component (e.g., a reference signal) on a second carrier frequency, wherein the baseband processor determines a phase shift based on a correlation of a down-converted version of the received signal to the signal component.

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[0152] An advantage of these embodiments is that they allow coherent combining for reception, which is beneficial in optimizing beamforming.

[0153] Some embodiments further relate to signals corresponding to known signal components being generated by an external transmitter (eg, a transmitter not controlled by the baseband processor).

[0154] An advantage of these embodiments is that the implementation can be simplified since signals corresponding to known signal components are not generated internally.

[0155] Some embodiments further relate to a baseband processor that configures a transceiver chip j, where j≠i, to transmit a signal corresponding to the known signal component using a second carrier frequency.

[0156] An advantage of these embodiments is that because the transmitted signal is perfectly known and / or the high frequency transmission channel is closer to the perfect channel than if a signal corresponding to the known signal component were generated by an external transmitter, the phase offset estimation is improved, thereby achieving a performance advantage in the beamforming step.

[0157] Some embodiments further relate to a baseband processor configured to estimate a frequency error based on the correlation and send an electrical signal based on the frequency error to a reference frequency generator to update the reference frequency.

[0158] An advantage of these embodiments is that the frequency error of the received signal is reduced, thereby achieving improved performance.

[0159] Some embodiments further relate to a baseband processor configured to determine a timing value based on correlation for one transceiver chip and use the timing value to set correlation timing for another transceiver chip.

[0160] An advantage of these embodiments is that the correlation timing error is reduced, thereby achieving improved performance.

[0161] Some embodiments use a phase compensation φ(D i ) (e.g., by applying a phase shift

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[0162] An advantage of these embodiments is that it may be easier to distinguish between phase shifts caused by chip-related frequency generators and phase shifts arising from the high frequency channel.

[0163] Some embodiments further relate to a second carrier frequency above 24 GHz and a reference frequency below 1 GHz.

[0164] Advantages of these embodiments include having a relatively low frequency for the signals routed from the reference frequency generator to the respective transceiver chips, which can reduce interference on the PCB (allowing for a simplified design), reduce the impact of PCB process variations, and / or reduce power consumption in the routing (power losses are typically higher when routing relatively high frequency signals).

[0165] Some embodiments further relate to a reference frequency generator connected in series with the transceiver chips (i.e., the reference frequency is input directly to a first transceiver chip, input from an output of the first transceiver chip to a second transceiver chip, input from an output of the second transceiver chip to a third transceiver chip, etc.).

[0166] An advantage of these embodiments is that the series connection can reduce the effort (e.g., wire length) of routing the reference frequency signal on the PCB and / or reduce the risk of PCB leakage of the reference frequency signal, thereby resulting in less power loss and / or interference.

[0167] Some embodiments further relate to a multi-antenna transceiver system including a second reference frequency generator (e.g., a second XO) and a second group of two or more other transceiver chips. Each transceiver chip has a chip-associated (e.g., including an on-chip) frequency generator (e.g., a local oscillator, LO) configured to generate a third carrier frequency (which may be equal to or different from the first carrier frequency). The third carrier frequency is for downconverting (e.g., in a mixer) a received high-frequency signal to a signal having a carrier frequency lower than the third carrier frequency and / or for upconverting (e.g., in a mixer) a signal having a carrier frequency lower than the third carrier frequency to a high-frequency signal to be transmitted. The third carrier frequencies of at least two transceiver chips are generated based on the same reference frequency and are generated by the second reference frequency generator.

[0168] An advantage of these embodiments is that by partitioning the transceiver chips into two or more subsets (groups), each with its own reference frequency signal, the effort to route the reference frequency signals on the PCB can be reduced and / or the risk of interference arising from PCB leakage of the reference frequency signals can be reduced.

[0169] 9 illustrates an exemplary method 900 according to some embodiments. For example, at least some of the steps of method 900 may be performed or caused by control circuitry (e.g., included in or associated with a baseband processor) of a multi-antenna transceiver system, such as any of the multi-antenna transceiver systems of FIGS.

[0170] Accordingly, method 900 is for operating a multi-antenna transceiver system including a group of transceiver chips and a reference frequency generator, the reference frequency generator configured to provide a reference frequency for each transceiver chip of the group, each transceiver chip having a respective chip-associated frequency generator configured to provide a respective translation frequency based on the reference frequency for on-chip frequency translation of transceiver signals.

[0171] In optional step 910, a reference frequency generator and / or a chip-associated frequency generator of the multi-antenna transceiver system are configured to provide respective conversion frequencies as detailed above. This step can be performed before operation of the multi-antenna transceiver system begins and / or during operation of the multi-antenna transceiver system (e.g., periodically and / or by being triggered by an event).

[0172] During operation of the multi-antenna transceiver system, each conversion frequency is used for on-chip frequency conversion of transceiver signals, as detailed above and indicated by optional step 920 .

[0173] In step 930, a first respective phase shift of each of the respective chip-related frequency generators is estimated, as detailed above.

[0174] In optional step 940, a second respective phase shift for each of the respective chip-related frequency generators is obtained, as detailed above.

[0175] In step 970, the transceiver signal is compensated based on the first respective phase shift and possibly the second respective phase shift, as detailed above.

[0176] Optional steps 950 and 980 illustrate the estimation of frequency error for the chip-related frequency generator and the control of the reference frequency generator based on the frequency error, as detailed above.

[0177] Optional steps 960 and 990 illustrate estimating baseband correlation timing for at least one transceiver chip / package and controlling baseband correlation timing for other transceiver chips / packages based on the estimated baseband correlation timing, as detailed above.

[0178] The described embodiments and their equivalents may be implemented in software or hardware, or a combination thereof. The embodiments may be performed by general-purpose circuitry. Examples of general-purpose circuitry include digital signal processors (DSPs), central processing units (CPUs), co-processing units, field programmable gate arrays (FPGAs), and other programmable hardware. Alternatively or additionally, the embodiments may be performed by special-purpose circuitry, such as application-specific integrated circuits (ASICs). The general-purpose and / or special-purpose circuitry may be associated with or included in an apparatus, such as a wireless communication device or a network node, for example.

[0179] The embodiments may appear in an electronic device (such as a wireless communication device or a network node) that includes arrangements, circuits, and / or logic according to any of the embodiments described herein. Alternatively or additionally, the electronic device (such as a wireless communication device or a network node) may be configured to perform a method according to any of the embodiments described herein.

[0180] According to some embodiments, the computer program product includes a tangible or non-tangible computer-readable medium, such as, for example, a universal serial bus (USB) memory, a plug-in card, an embedded drive, or a read-only memory (ROM). FIG. 10 shows an exemplary computer-readable medium in the form of a compact disc (CD) ROM 1000. The computer-readable medium stores a computer program including program instructions. The computer program is loadable into a data processor (PROC, e.g., data processing circuit or data processing unit) 1020, which may be included in, for example, a wireless communication device or network node 1010. Once loaded into the data processor, the computer program may be stored in a memory (MEM) 1030 associated with or included in the data processor. According to some embodiments, the computer program, when loaded into and run by the data processor, may cause the data processor to perform method steps, for example, according to any of the methods shown in FIG. 9 or described herein.

[0181] In general, all terms used herein should be construed in accordance with their ordinary meaning in the relevant art unless a different meaning is expressly given and / or implied from the context in which it is used.

[0182] Although various embodiments have been referred to herein, those skilled in the art will recognize that many variations of the described embodiments would still fall within the scope of the claims.

[0183] For example, the method embodiments described herein disclose exemplary methods through steps performed in a particular order. However, it is recognized that other orders of events may be performed without departing from the scope of the claims. Moreover, some method steps may be performed in parallel even though they are described as being performed sequentially. Thus, the steps of any method disclosed herein do not have to be performed in the exact order as disclosed, unless a step is explicitly described as following or preceding another step and / or unless it is implicit that a step must follow or precede another step.

[0184] Similarly, it should be noted that in the description of the embodiments, the partitioning of functional blocks into specific units is in no way intended to be limiting. To the contrary, these partitionings are merely examples. Functional blocks described herein as one unit can be divided into two or more units. Moreover, functional blocks described herein as being implemented as two or more units can be merged into fewer (e.g., a single) units.

[0185] Any feature of any of the embodiments disclosed herein may be applied to other embodiments where appropriate, and likewise, any advantage of any of the embodiments may be applied to other embodiments, and vice versa.

[0186] It should therefore be understood that the details of the described embodiments are merely examples brought out for illustrative purposes, and that all modifications that fall within the scope of the claims are intended to be embraced therein.

Claims

1. a group of transceiver chips (201-202, 301-302, 401a-402a, 401b-402b, 501a-502a, 501b-502b); a reference frequency generator (210, 310, 410a, 410b, 510a, 510b) configured to provide a reference frequency for each transceiver chip of the group; A multi-antenna transceiver system (200, 300, 400, 500) comprising: each transceiver chip of the group has a respective chip-associated frequency generator (297, 397, 697) configured to provide a respective conversion frequency based on said reference frequency, each of said respective conversion frequencies being higher than said reference frequency; each transceiver chip of the group is configured to use the respective conversion frequency for on-chip frequency conversion of transceiver signals; further comprising a baseband processing circuit (220, 320, 420, 520, 720) configured to process transceiver signals for the transceiver chip; The baseband processing circuit estimating a first respective phase shift of each of the respective chip-related frequency generators; Compensating the transceiver signal based on the first respective phase shift. The multi-antenna transceiver system further configured as follows:

2. 2. The multi-antenna transceiver system of claim 1, wherein the group of transceiver chips comprises two or more disjoint groups of transceiver chips (401a-402a, 401b-402b, 501a-502a, 501b-502b), and wherein the reference frequency generator comprises a respective reference frequency generator (410a, 410b, 510a, 520b) for each group of transceiver chips.

3. the reference frequency is provided directly to each transceiver chip (201-202, 401a-402a, 401b-402b) of the group, or 3. A multi-antenna transceiver system as claimed in claim 1 or 2, wherein the reference frequency is provided directly to a first transceiver chip (302, 502a, 502b) of the group and the reference frequency is provided to a second transceiver chip (301, 501a, 501b) of the group via the first transceiver chip.

4. The baseband processing circuit estimating a frequency error for each of the chip-related frequency generators; Controlling the reference frequency generator based on the frequency error The multi-antenna transceiver system according to any one of claims 1 to 3, further configured to:

5. The baseband processing circuit estimating baseband correlation timing for at least one transceiver chip of the group; controlling baseband correlation for at least one other transceiver chip of the group based on the estimated baseband correlation timing; A multi-antenna transceiver system according to any one of claims 1 to 4, further configured to:

6. The baseband processing circuit obtaining a second respective phase shift for each of the respective chip-associated frequency generators for each transceiver chip of the group; Compensating the transceiver signal based on the second respective phase shift. The multi-antenna transceiver system of any one of claims 1 to 5, further configured to:

7. 7. The multi-antenna transceiver system of claim 6, wherein the second respective phase shift is associated with a relative mounting position of the transceiver chip.

8. A multi-antenna transceiver system as described in any one of claims 1 to 7, wherein each of the respective conversion frequencies is higher than 24 GHz and / or the reference frequency is lower than 1 GHz.

9. 1. A baseband processor (220, 320, 420, 520, 720) for a multi-antenna transceiver system, the baseband processor configured to process transceiver signals for a group of transceiver chips included in the multi-antenna transceiver system, a baseband processor, each transceiver chip of the group having a respective chip-associated frequency generator configured to provide a respective conversion frequency based on a reference frequency provided by a reference frequency generator included in the multi-antenna transceiver system, each of the respective conversion frequencies being higher than the reference frequency; estimating a first respective phase shift of each of the respective chip-related frequency generators; Compensating the transceiver signal based on the first respective phase shift. a baseband processor including a baseband processing circuit configured to:

10. A network node comprising a multi-antenna transceiver system according to any one of claims 1 to 8 and / or a baseband processor according to claim 9.

11. A wireless communication device comprising a multi-antenna transceiver system according to any one of claims 1 to 8 and / or a baseband processor according to claim 9.

12. 1. A method for operating a multi-antenna transceiver system including a group of transceiver chips and a reference frequency generator, comprising: the reference frequency generator is configured to provide a reference frequency for each transceiver chip of the group; each transceiver chip of the group has a respective chip-associated frequency generator configured to provide a respective conversion frequency based on the reference frequency, each of the respective conversion frequencies being higher than the reference frequency; wherein each transceiver chip of the group is configured to use the respective conversion frequency for on-chip frequency conversion of transceiver signals; estimating (930) a first respective phase shift of each of the respective chip-related frequency generators; compensating the transceiver signal based on the first respective phase shift (970); A method comprising:

13. A computer program configured to cause a data processing unit to carry out the method according to claim 12.

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