Semiconductor devices and electronic devices

Abstract

To provide a semiconductor device that can perform product-sum operation with less power consumption.SOLUTION: In a semiconductor device, a circuit MC includes a holding node nd1, and a circuit MCr includes a holding node nd1r. The circuit MC is electrically connected to input wiring IL, and wirings OL, OLB. The circuit MCr is electrically connected to input wiring ILB and the wirings OL, OLB. The circuits MC, MCr have functions of holding first and second potentials according to first data in the holding nodes nd1, nd1r, respectively. When a potential according to second data is input to the input wirings IL, ILB, the circuit MC outputs a current to one of the wirings OL, OLB, and the circuit MCr outputs a current to the other of the wirings OL, OLB. The currents output by the circuits MC, MCr to the wiring OL or OLB are determined in accordance with the first and second potentials held in the holding nodes nd1, nd1r.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an article, a method, or a manufacturing method. Process, machine, manufacture, or composition of matter Therefore, the technology of one embodiment of the present invention disclosed in this specification more specifically relates to the above. Fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, Storage device, signal processing device, processor, electronic device, system, driving method thereof, Examples of the manufacturing method and the inspection method thereof are as follows. [Background technology]

[0003] Currently, the development of integrated circuits that mimic the mechanisms of the human brain is progressing vigorously. The brain's mechanisms are incorporated as electronic circuits, and the brain's "neurons" and "systems" are connected. Therefore, such an integrated circuit is called a "neuromorph." It is also sometimes called "brain-morphic," "brain-inspired," or "brain-morphic." The integrated circuit has a non-von Neumann architecture, and power consumption decreases as processing speed increases. Compared to the larger von Neumann architecture, parallel processing can be performed with extremely low power consumption. It is expected that this will be possible.

[0004] The information processing model that mimics a neural network with "neurons" and "synapses" is called artificial neural network. These are called neural networks (ANNs). For example, see Non-Patent Document 1 and Non-Patent Document 2 uses SRAM (Static Random Access Memory) The document discloses a computing device that configures an artificial neural network. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] M. Kang et al., “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No.2, p.642-655. [Non-patent document 2] J. Zhang et al., “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No.4, p.915-924. Summary of the Invention [Problem to be solved by the invention]

[0006] In artificial neural networks, the strength of the synapse that connects two neurons is called the Multiply the signal transmitted between two neurons by the degree (sometimes called a weighting coefficient) In particular, in a hierarchical artificial neural network, the first layer consists of multiple first The strength of each synaptic connection between the neuron and one of the second neurons in layer 2, Each signal input from multiple first neurons in the first layer to one of the second neurons in the second layer It is necessary to multiply and add the numbers, and depending on the scale of the artificial neural network, For example, the number of connection strengths and the number of parameters that represent the signal are determined. The more layers and neurons in a neural network, the more "neurons" and The number of circuits corresponding to each "synapse" can increase, and the amount of calculations can become enormous. .

[0007] As the number of circuits that make up a chip increases, power consumption also increases, and the amount of electricity generated when the device is running also increases. The amount of heat also increases. In particular, the higher the amount of heat generated, the more the characteristics of the circuit elements included in the chip deteriorate. Therefore, the circuits that make up the chip must have circuit elements that are less susceptible to temperature changes. It is preferable that

[0008] One aspect of the present invention is a semiconductor device in which a hierarchical artificial neural network is constructed. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of the present invention is to provide a method for manufacturing a semiconductor device that is not affected by the temperature of the environment. Another object of the present invention is to provide a semiconductor device or the like that is less susceptible to cracking. An object of the present invention is to provide a new semiconductor device or the like.

[0009] Note that the problems of one embodiment of the present invention are not limited to the above-listed problems. This does not preclude the existence of other problems. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by understanding the specification or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the above-listed objects and other objects. One aspect of the present invention is to solve the above-listed problems and other problems. You don't need to solve all of them. [Means for solving the problem]

[0010] (1) One embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, has a first holding node, the second circuit has a second holding node, and the first circuit has a first input The second circuit is electrically connected to the wiring, the second input wiring, the first wiring, and the second wiring. The first circuit is electrically connected to the first power wiring, the second input wiring, the first wiring, and the second wiring. The second circuit has a function of holding a first potential corresponding to data at a first holding node, and The first circuit has a function of holding a second potential corresponding to the input voltage at a second holding node, and the first circuit has a function of holding a second potential corresponding to the input voltage at a second holding node. When a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, The function of outputting a current according to the potential to the first wiring and the function of inputting a low-level potential to the first input wiring. When a high level potential is input to the second input wiring, a current corresponding to the first potential is supplied to the second wiring. The function of outputting to the line, and the function of inputting a low level potential to the first input line and outputting a low level potential to the second input line. When a bell potential is input, a current corresponding to the first potential is output to the first wiring and the second wiring. The second circuit has a function of inputting a high level potential to the first input wiring and a function of inputting a high level potential to the second input wiring. When a low-level potential is input to the input wiring, a current corresponding to the second potential is output to the second wiring. The function is to input a low-level potential to the first input wire and a high-level potential to the second input wire. When a voltage is input, the first wiring is supplied with a current corresponding to the second potential. When a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, and a function of not outputting a current corresponding to the first wiring and the second wiring. .

[0011] (2) Alternatively, one aspect of the present invention is a circuit configuration (1) in which the first circuit includes first to fourth transistors. the second circuit includes fifth to eighth transistors and a second capacitance element; a capacitance element, and the first holding node is connected to the first terminal of the first transistor, the second transistor, a first terminal of the second transistor electrically connected to the gate of the second transistor and the first terminal of the first capacitance element; The terminal is electrically connected to the second terminal of the first capacitance element, and the second terminal of the second transistor is electrically connected to a first terminal of the third transistor and a first terminal of the fourth transistor; The gate of the third transistor is electrically connected to the first input wiring, and the gate of the fourth transistor is The second terminal of the third transistor is electrically connected to the second input wiring, and the second terminal of the third transistor is electrically connected to the first wiring. The second terminal of the fourth transistor is electrically connected to the second wiring, and the second terminal of the fourth transistor is electrically connected to the second wiring. The holding node is connected to the first terminal of the fifth transistor, the gate of the sixth transistor, and the second capacitor. the first terminal of the sixth transistor is electrically connected to the first terminal of the second capacitance element; The second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor. a gate of the seventh transistor electrically connected to the first terminal of the eighth transistor; The gate of the eighth transistor is electrically connected to the first input wiring, and the gate of the eighth transistor is electrically connected to the second input wiring. The second terminal of the seventh transistor is electrically connected to the second wiring, and the second terminal of the eighth transistor is electrically connected to the second wiring. The second terminal of the transistor is a semiconductor device electrically connected to the first wiring.

[0012] (3) Alternatively, one embodiment of the present invention is the semiconductor device according to the above item (1), wherein the first circuit includes first to fourth transistors. the second circuit includes the fifth to eighth transistors, the ninth transistor, and the first capacitance element; a first holding node connected to the first transistor, a tenth transistor, and a second capacitance element; a first terminal of the transistor, a gate of the second transistor, a gate of the ninth transistor, and The second terminal of the first capacitance element is electrically connected to the first terminal of the second transistor. the first terminal of the ninth transistor and the first terminal of the second transistor; The second terminal of the transistor is electrically connected to the first terminal of the third transistor, and the second terminal of the ninth transistor is electrically connected to the first terminal of the third transistor. The second terminal is electrically connected to the first terminal of the fourth transistor and the gate of the third transistor. The gate of the fourth transistor is electrically connected to the first input wiring, and the gate of the fourth transistor is electrically connected to the second input wiring. the second terminal of the third transistor is electrically connected to the first wiring, and the fourth The second terminal of the transistor is electrically connected to the second wiring, and the second holding node is connected to the fifth transistor. a first terminal of the sixth transistor, a gate of the tenth transistor, and The second terminal of the second capacitance element is electrically connected to the sixth transistor. the first terminal of the sixth transistor and the first terminal of the tenth transistor; The second terminal of the seventh transistor is electrically connected to the first terminal of the tenth transistor. The second terminal of the transistor is electrically connected to the first terminal of the eighth transistor, and the second terminal of the seventh transistor is electrically connected to the first terminal of the eighth transistor. The gate of the eighth transistor is electrically connected to the first input wiring, and the gate of the eighth transistor is electrically connected to the second input wiring. a second terminal of the seventh transistor electrically connected to the second wiring; The second terminal of the eighth transistor is a semiconductor device electrically connected to the first wiring.

[0013] (4) Alternatively, one aspect of the present invention is a circuit configuration (1) in which the first circuit includes first to fourth transistors. a first logic circuit and a second logic circuit, the second circuit including fifth to eighth transistors. a third logic circuit and a fourth logic circuit, This has a function of outputting from an output terminal an inverted signal of a signal input to an input terminal, and The nodes are the input terminal of the first logic circuit, the output terminal of the second logic circuit, and the first transistor. The first terminal is electrically connected to the gate of the second transistor, and the output terminal of the first logic circuit is , the second terminal of the second transistor is electrically connected to the input terminal of the second logic circuit, and the second terminal of the second transistor is electrically connected to the input terminal of the third logic circuit. a first terminal of the third transistor electrically connected to the first terminal of the fourth transistor and the first terminal of the fourth transistor; The gate of the fourth transistor is electrically connected to the first input wiring, and the gate of the fourth transistor is The second terminal of the third transistor is electrically connected to the second input wiring, and the second terminal of the third transistor is electrically connected to the first wiring. The second terminal of the fourth transistor is electrically connected to the second wiring, and the second terminal of the fourth transistor is electrically connected to the second wiring. The node is the input terminal of the third logic circuit, the output terminal of the fourth logic circuit, and the first terminal of the fifth transistor. and the gate of the sixth transistor, and the output terminal of the third logic circuit is electrically connected to the gate of the fourth transistor. The second terminal of the sixth transistor is electrically connected to the input terminal of the logic circuit. a first terminal of the seventh transistor electrically connected to the first terminal of the eighth transistor and the first terminal of the seventh transistor; The gate of the eighth transistor is electrically connected to the first input wiring, and the gate of the eighth transistor is electrically connected to the second input wiring. The second terminal of the seventh transistor is electrically connected to the input wiring, and the second terminal of the seventh transistor is electrically connected to the second wiring. The second terminal of the eighth transistor is a semiconductor device electrically connected to the first wiring. do.

[0014] (5) Alternatively, one aspect of the present invention is a circuit configuration (1) in which the first circuit includes first to fourth transistors. a first logic circuit and a second logic circuit, the second circuit including sixth to eighth transistors. The first logic circuit and the second logic circuit each have a transistor, and the first logic circuit and the second logic circuit each have a transistor. The first logic circuit has a function of outputting an inverted signal of the first logic circuit from the output terminal. a terminal, an output terminal of the second logic circuit, a first terminal of the first transistor, and a second terminal of the second transistor The output terminal of the first logic circuit is electrically connected to the input terminal of the second logic circuit. the second terminal of the second transistor is connected to the first terminal of the third transistor and the fourth terminal of the fourth transistor. the gate of the third transistor is electrically connected to the first terminal of the first input line; The gate of the fourth transistor is electrically connected to the second input wiring. The second terminal of the third transistor is electrically connected to the first wiring, and the third terminal of the fourth transistor is electrically connected to the first wiring. The second terminal is electrically connected to the second wiring, the second holding node is an input terminal of the second logic circuit, an output terminal of the first logic circuit and a gate of the sixth transistor; The second terminal of the seventh transistor is connected to the first terminal of the eighth transistor. The gate of the seventh transistor is electrically connected to the first input wiring. The gate of the eighth transistor is electrically connected to the second input wiring, and the gate of the seventh transistor is electrically connected to the second input wiring. The second terminal of the eighth transistor is electrically connected to the second wiring, and the second terminal of the eighth transistor is electrically connected to the first wiring. The semiconductor device is electrically connected.

[0015] (6) Another embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, The first circuit has a first load circuit, and the second circuit has a second load circuit, and two load circuits, each having a first terminal and a second terminal. and the load circuit, each of which changes a resistance value between the first terminal and the second terminal in accordance with first data. The first circuit has a function of converting the first input wiring, the second input wiring, the first wiring, and the second wiring. The second circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and the second wiring. The first circuit is electrically connected to the first input wiring, and a high-level potential is input to the first input wiring. When a low-level potential is input to the input wiring, a current according to the resistance value of the first load circuit flows to the first The function of outputting to the wiring, and the function of inputting a low level potential to the first input wiring and a high level potential to the second input wiring. When a level potential is input, a current corresponding to the resistance value of the first load circuit is output to the second wiring. The function of inputting a low-level potential to the first input wiring and a low-level potential to the second input wiring is also When input is made, a current according to the resistance value of the first load circuit is output to the first wiring and the second wiring. The second circuit has a function of not inputting a high level potential to the first input wiring and When a low-level potential is input to the second input wiring, a current according to the resistance value of the second load circuit flows to the first The function of outputting to two wires, and when a low level potential is input to the first input wire and a low level potential is input to the second input wire, When a high-level potential is input, a current corresponding to the resistance value of the second load circuit is output to the first wiring. A low-level potential is input to the first input wiring and a low-level potential is input to the second input wiring. When this signal is input, a current according to the resistance value of the second load circuit is sent to the first wiring and the second wiring. The semiconductor device has a function of not outputting.

[0016] (7) Alternatively, in one aspect of the present invention, in the configuration (6), the first circuit includes a third transistor and a fourth transistor, and the second circuit includes a seventh transistor and an eighth transistor. and a first terminal of the first load circuit is connected to a first terminal of the third transistor and a first terminal of the fourth transistor. The gate of the third transistor is electrically connected to the first input wiring and the second terminal of the third transistor. The gate of the fourth transistor is electrically connected to the second input wiring, and the gate of the third transistor is electrically connected to the second input wiring. The second terminal of the transistor is electrically connected to the first wiring, and the second terminal of the fourth transistor is is electrically connected to the second wiring, and the first terminal of the second load circuit is electrically connected to the first terminal of the seventh transistor. a terminal electrically connected to the first terminal of the eighth transistor and a gate of the seventh transistor; The gate of the eighth transistor is electrically connected to the first input wiring, and the gate of the eighth transistor is electrically connected to the second input wiring. The second terminal of the seventh transistor is electrically connected to the second wiring, and the second terminal of the eighth transistor is electrically connected to the second wiring. The second terminal of the transistor is a semiconductor device electrically connected to the first wiring.

[0017] (8) Alternatively, in one aspect of the present invention, in the configuration (7), the first circuit includes a first transistor the second circuit has a second transistor, and the first terminal of the first transistor is connected to a first negative terminal; the first terminal of the second transistor is electrically connected to the first terminal of the second load circuit; The semiconductor device is electrically connected to the first terminal.

[0018] (9) Alternatively, one aspect of the present invention is the first negative electrode in any one of the above structures (6) to (8). The load circuit includes one of a resistance change element, an MTJ element, and a phase change memory, and the second load circuit The present invention relates to a semiconductor device having any one of a resistance change element, an MTJ element, and a phase change memory.

[0019] (10) Alternatively, one aspect of the present invention is any one of the above-mentioned (1) to (9) configurations, and a fourth circuit, and the third circuit is connected to the first input wiring and the second input wiring, The fourth circuit has a function of inputting a potential according to the second data to the first wiring, the second wiring, and , and compare the current flowing from each of them, and output the first data and the second data from the output terminal of the fourth circuit. The semiconductor device has a function of outputting a potential according to the product of the data.

[0020] (11) Another embodiment of the present invention includes the semiconductor device according to any one of (1) to (10), This is an electronic device that performs neural network calculations using semiconductor devices.

[0021] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics. Circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.) It also refers to any device that can function by utilizing the properties of semiconductors. For example, Integrated circuits, chips with integrated circuits, and electronic components that house chips in packages are semiconductors. In addition, a storage device, a display device, a light-emitting device, a lighting device, an electronic device, etc. It may itself be a semiconductor device and may contain a semiconductor device.

[0022] In addition, in this specification, when it is stated that X and Y are connected, it means that X and Y are connected. When X and Y are electrically connected, when X and Y are functionally connected, and when X and The case where Y is directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text, but may be applied to connections shown in drawings or text. Connections other than those shown in the figure or text are also considered to be disclosed. The object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) .

[0023] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. It has a function to control whether or not water is flushed.

[0024] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (digital-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.) ), potential level conversion circuits (power supply circuits (booster circuits, step-down circuits, etc.), voltage sources, current sources, switching circuits, amplifier circuits (such as level shifter circuits that can Circuits that can increase the amount of current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc. There are one or more circuits between X and Y (e.g., a power supply circuit, a signal generating circuit, a memory circuit, a control circuit, etc.) It is possible to connect X and Y. For example, if another circuit is inserted between X and Y, However, if the signal output from X is transmitted to Y, then X and Y are functionally connected. It shall be.

[0025] When it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically connected. When X and Y are electrically connected (i.e., when another element or circuit is inserted between X and Y) X and Y are functionally connected (i.e., there is no connection between X and Y) When X and Y are connected directly (i.e. when they are connected via another circuit) , when X and Y are connected without any other element or circuit between them) In other words, when explicitly stating that something is electrically connected, it simply means that it is connected. The same applies if it is explicitly stated that the

[0026] Also, for example, "X and Y and the source (or first terminal, etc.) and drain ( or the second terminal, etc.) are electrically connected to each other, and X is the source of the transistor (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y in that order. It can be expressed as "electrically connected to the source ( or the first terminal) is electrically connected to X, and the drain (or second terminal, etc.) is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor. , the drain (or second terminal, etc.) of the transistor, Y, are electrically connected in this order. Alternatively, "X is the source (or first terminal) of the transistor." The transistor is electrically connected to Y through the drain (or second terminal, etc.) and the transistor is electrically connected to X. The source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor (e.g., Y is provided in this connection order). By using a similar expression method to specify the order of connections in a circuit configuration, The source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are connected to each other. The technical scope can be determined by distinguishing between the two. Note that these methods of expression are merely examples. , and is not limited to these representation methods. Here, X and Y represent objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0027] Note that the circuit diagram shows independent components as if they are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both the electrode and the electrode. Electrical connection means that one conductive film has the functions of multiple components. This case will also be included in that category.

[0028] In this specification, a transistor is referred to as a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source and drain are the input and output terminals of the transistor. The two input / output terminals are used to select the transistor conductivity type (n-channel, p-channel) and the Depending on the potential applied to the three terminals of the transistor, one becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain can be interchanged. In addition, in this specification and the like, when describing the connection relationship of a transistor, "One of the source and drain" (or first electrode, or first terminal), "the source or drain The term "second electrode" or "second terminal" is used. In some cases, a back gate is provided in addition to the three terminals described above. In this specification, either the gate or the back gate of a transistor is referred to as a first gate. The other of the gate or back gate of the transistor is sometimes called the second gate. Furthermore, the terms "gate" and "backgate" are interchangeable for the same transistor. In addition, if a transistor has three or more gates, In this specification, each gate is referred to as a first gate, a second gate, a third gate, etc. It is sometimes called.

[0029] In this specification, a node may be a terminal, a wiring, or the like depending on the circuit configuration, device structure, etc. It can be called a line, an electrode, a conductive layer, a conductor, an impurity region, etc. Wiring and the like can be called nodes in other words.

[0030] In addition, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, If we consider the ground potential as the earth potential, we can change the word "voltage" to "potential." The potential does not necessarily mean 0V. Note that the potential is relative and the reference Depending on the potential, the potential applied to the wiring etc. may be changed.

[0031] "Current" refers to the phenomenon of the movement of electric charges (electrical conduction). For example, "the electric current of a positively charged body" The statement "electrical conduction is occurring in the opposite direction" means "electrical conduction is occurring in the negatively charged body." Therefore, in this specification and the like, unless otherwise specified, the term "current" is used. In this case, the term "electrical conduction" refers to the phenomenon of charge transfer accompanying the movement of carriers. Carriers include electrons, holes, anions, cations, complex ions, etc., and are the carriers through which current flows. The carriers differ depending on the system (e.g., semiconductor, metal, electrolyte, vacuum, etc.). The "direction of current" in a wire, etc. is the direction in which positive carriers move, and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of the current, and the negative Therefore, in this specification, the positive and negative currents (or the direction of the current) Unless otherwise specified, statements such as "current flows from element A to element B" should be interpreted as "current flows from element B to element This can be rephrased as "current flows through element A" or "current flows through element A." A statement such as "current is input" can be rephrased as "current is output from element A" Let's say.

[0032] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to indicate constituent elements. Therefore, it does not limit the number of components. In addition, the order of the components is not limited. The element referred to as "first" in the above may be used in other embodiments or in the claims. In addition, for example, in the present specification, A component referred to as "first" in one embodiment may be used in other embodiments or in particular It may be omitted within the scope of the claims.

[0033] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship may be used for convenience in explaining the configuration with reference to the drawings. The positional relationship between them changes depending on the direction in which each component is depicted. The terms are not limited to those explained in the detailed instructions, but can be rephrased appropriately depending on the situation. For example, the expression "insulator on top of conductor" means that the orientation of the drawing shown is rotated 180 degrees. By turning it around, it can be rephrased as "an insulator located on the underside of a conductor."

[0034] In addition, the terms "above" and "below" refer to the positional relationship of the components directly above or below and directly connected to each other. For example, if the expression is "electrode B on insulating layer A," The electrode B does not need to be formed directly on the insulating layer A, and the insulating layer A and the electrode B This does not exclude the inclusion of other components in between.

[0035] In addition, in this specification and the like, the terms "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." In some cases, or depending on the circumstances, it may be possible to change the term to " For example, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be changed to "insulator." It may be possible to change the term to something like this.

[0036] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. This is not a limitation. For example, an "electrode" may be used as part of a "wiring." , and vice versa. Furthermore, the terms "electrode" and "wiring" may be used interchangeably with "electrodes" and "wiring." This also includes cases where the wiring is formed integrally.

[0037] In addition, in this specification, terms such as "wiring," "signal line," and "power line" may be used interchangeably. Depending on the situation, they can be interchanged. For example, "wiring" It may be possible to change the term to "signal line". In some cases, it may be possible to change the term "wiring" to a term such as "power line." The reverse is also true; terms such as "signal line" and "power line" should be changed to "wiring." It may be possible to change terms such as "power line" to terms such as "signal line." In addition, the reverse is also true, and terms such as "signal line" may be used interchangeably with "power line" In some cases, it may be possible to change the term to something like "potential" applied to the wiring. In some cases or depending on the situation, the term "signal" may be changed to "signal" or similar. And vice versa, terms such as "signal" can be used to refer to "potential." It may be possible to change the term.

[0038] In this specification, impurities in a semiconductor are, for example, substances other than the main components constituting a semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are considered impurities. This can result in the formation of DOS (Density of States) in semiconductors. In some cases, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, , Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, other than the main component Transition metals, especially hydrogen (which is also contained in water), lithium, sodium, Silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, if the semiconductor is a silicon layer, In this case, impurities that change the properties of the semiconductor include, for example, oxygen and group 1 elements excluding hydrogen. These include the elements of Group 2, Group 13, and Group 15.

[0039] In this specification, a switch is a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It is a device that has the function of controlling whether or not current flows by entering a state where it is in a switched state. A switch is a device that has the function of selecting and switching the path through which current flows. , electrical switches, mechanical switches, etc. can be used. The device is not limited to a specific one as long as it can control the current.

[0040] An example of an electrical switch is a transistor (e.g., a bipolar transistor, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die MIS (Metal Insulator Semiconductor) die diode-connected transistors, etc.), or logic circuits that combine these When using a transistor as a switch, the "conduction state" of the transistor This means that the source and drain electrodes of the transistor are considered to be electrically short-circuited. The "non-conducting state" of a transistor refers to the state in which the source electrode and drain electrode of the transistor are in a non-conducting state. This refers to a state in which the input electrode can be considered to be electrically disconnected. When operating as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0041] An example of a mechanical switch is a MEMS (microelectromechanical system). There are switches that use stem technology. These switches are electrically operated switches that can be mechanically operated. It has poles, and the movement of these electrodes controls conduction and non-conduction. [Effects of the Invention]

[0042] According to one aspect of the present invention, a semiconductor device in which a hierarchical artificial neural network is constructed is provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one aspect of the present invention, it is possible to provide a device or the like that can reduce the influence of the temperature of the environment. According to one embodiment of the present invention, a semiconductor device or the like that is less susceptible to damage can be provided. It is possible to provide a new semiconductor device.

[0043] The effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to a person skilled in the art from the description or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may have the above-listed effects. In some cases, the [Brief explanation of the drawings]

[0044] [Figure 1] 1A and 1B are diagrams illustrating a hierarchical neural network. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 3] 3A, 3B, 3C, 3D, 3E, and 3F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 4] 4A, 4B, 4C, 4D, 4E, and 4F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 5] 5A, 5B, 5C, 5D, 5E, and 5F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 6] FIG. 6 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 7] FIG. 7 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 8] FIG. 8 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 9] 9A, 9B, and 9C are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 10] 10A and 10B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 11] 11A and 11B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 12] 12A and 12B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 13] 13A, 13B, and 13C are timing charts showing examples of the operation of the circuits included in the semiconductor device. [Figure 14] 14A, 14B, and 14C are timing charts showing examples of the operation of the circuits included in the semiconductor device. [Figure 15] 15A, 15B, and 15C are timing charts showing examples of the operation of the circuits included in the semiconductor device. [Figure 16] 16A and 16B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 17] FIG. 17 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 18] 18A, 18B, 18C, and 18D are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 19] FIG. 19 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 20] 20A and 20B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 21] 21A and 21B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 22] 22A, 22B, and 22C are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 23] 23A, 23B, and 23C are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 24] 24A and 24B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 25] 25A and 25B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 26] 26A and 26B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 27] 27A and 27B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 28] FIG. 28 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 29] FIG. 29 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 30] 30A, 30B, and 30C are cross-sectional views showing examples of the structure of a transistor. [Figure 31]31A, 31B, and 31C are a top view and a cross-sectional view illustrating an example of the structure of a transistor. [Figure 32] 32A, 32B, and 32C are a top view and a cross-sectional view illustrating an example of the structure of a transistor. [Figure 33] 33A, 33B, and 33C are a top view and a cross-sectional view illustrating an example of the structure of a transistor. [Figure 34] 34A, 34B, and 34C are a top view and a cross-sectional view illustrating an example of the structure of a transistor. [Figure 35] 35A, 35B, and 35C are a top view and a cross-sectional view illustrating an example of the structure of a transistor. [Figure 36] 36A and 36B are a top view and a perspective view illustrating an example of the structure of a transistor. [Figure 37] 37A and 37B are cross-sectional views showing examples of the structure of a transistor. [Figure 38] 38A, 38B, and 38C are a top view and a perspective view showing an example of the structure of a capacitive element. [Figure 39] 39A, 39B, and 39C are a top view and a perspective view showing an example of the structure of a capacitive element. [Figure 40] 40A, 40B, 40C, and 40D are perspective views showing examples of a semiconductor wafer and an electronic component. [Figure 41] FIG. 41 is a perspective view showing an example of an electronic device. [Figure 42] FIG. 42A is a front view showing an example of an electronic device, and FIGS. 42B and 42C are perspective views showing examples of the electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0045] In artificial neural networks (hereafter referred to as neural networks), ,The connection strength of the synapses is determined by providing existing information to the neural ,network. In this way, we can feed the neural network with existing information and generate results. The process of determining the combined strength is sometimes called "learning."

[0046] In addition, no action is taken against the neural network that has undergone "learning" (the connection weights have been determined). By providing some information, new information can be output based on the connection strength. In this way, neural networks make decisions based on the given information and connection strengths. The process of generating new information through neural networks is sometimes called "inference" or "cognition."

[0047] Neural network models include, for example, Hopfield and hierarchical types. In particular, neural networks with multi-layer structures are called "deep neural networks." They call machine learning using deep neural networks "DNNs" and call machine learning using deep neural networks " It is sometimes called "deep learning."

[0048] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductors (also called oxide semiconductors or simply OS), For example, when a metal oxide is used in the active layer of a transistor, the metal oxide In other words, metal oxides have amplifying, rectifying, and and forming a channel forming region of a transistor having at least one of a switching function and a If possible, the metal oxide is referred to as a metal oxide semiconductor. It can also be called an OS FET or OS transistor. In the above description, the transistor is referred to as a transistor including a metal oxide or an oxide semiconductor. It is possible.

[0049] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides (metal ox). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0050] In addition, in this specification and the like, the configurations shown in each embodiment may be interchangeable with the configurations shown in other embodiments. The above-described embodiments can be combined appropriately to form one aspect of the present invention. When multiple configuration examples are shown, the configuration examples can be combined with each other as appropriate.

[0051] It should be noted that the contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the embodiment and one or more other embodiments The content described (or a part of the content) is applied to, combined with, or at least one of the contents. or replacement, etc.

[0052] The contents described in the embodiments are explained using various drawings in each embodiment. This refers to the content stated in the specification or the content stated using the text in the specification.

[0053] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. In the embodiment, another figure (or a part thereof) and one or more other embodiments may be used. At least one of the drawings (or a part thereof) described in the embodiment is combined with By adding more, more figures can be constructed.

[0054] The embodiments described in this specification are explained with reference to the drawings. The present invention may be embodied in many different forms without departing from the spirit and scope thereof. It will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiment. In the configuration of the invention of the embodiment, the same parts or parts having similar functions are designated by the same reference numerals. The same elements are used in different drawings, and repeated explanations may be omitted. In some cases, in order to ensure clarity of the drawings, some components may be omitted. be.

[0055] In this specification and the like, when the same reference numeral is used for a plurality of elements, it is not necessary to distinguish them. When necessary, a distinguishing code such as "_1", "[n]", or "[m,n]" is added to the code. It may be stated in writing.

[0056] Also, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely conceptual examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or timing errors This can include variations in signal, voltage, or current.

[0057] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention is a neural network processor. The arithmetic circuit that performs the calculation will be described.

[0058] <Hierarchical neural network> First, we will explain about hierarchical neural networks. For example, the network has one input layer, one or more intermediate layers (hidden layers), and one output layer. The hierarchical neural network shown in Figure 1A has three or more layers. Neural network 100 is an example of such a network. The layer has R layers (where R can be an integer of 4 or greater). The first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to the intermediate layers. In addition, in FIG. 1A, the (k-1)th layer and the kth layer (where k is 3 or more, R-1) are shown as intermediate layers. The following integers are used.) are shown in the figure, and other intermediate layers are omitted from the illustration. .

[0059] Each layer of the neural network 100 has one or more neurons. In this case, the first layer is made up of neurons N1 (1) Neuron N p (1) (where p is 1 or more ) and the (k-1)th layer has neurons N1 (k-1) Neuron N m (k-1) (where m is an integer greater than or equal to 1), and the kth layer has neurons N1 ( k) Neuron N n (k) (where n is an integer equal to or greater than 1), and the Rth layer is Neuron N1 (R) Neuron N q (R) (where q is an integer greater than or equal to 1.) It has.

[0060] In addition, in Figure 1A, neuron N1 (1) , neuron Np (1) , neuron N1 ( k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , Neuron N1 (R) , neuron N q (R) In addition, the (k-1)th layer neuron N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j ( k) (where j is an integer between 1 and n) are also shown. The illustration of the .

[0061] Next, the transmission of signals from the neurons in the previous layer to the neurons in the next layer, and the In this explanation, we will explain the signals input and output in the k-th layer of the neural network. N j (k) We are focusing on the following.

[0062] Figure 1B shows the kth layer neuron N j (k) and neuron N j (k) The signal input to and neuron N j (k) 10 shows the signal output from the

[0063] Specifically, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1 ) The output signal z1 (k-1) ~z m (k-1) But neuron Nj ( k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k) is used as the output signal The output is directed to each neuron in the layer (not shown).

[0064] The signals input from the neurons in the previous layer to the neurons in the next layer are transmitted between those neurons. The strength of the synapse (hereafter referred to as the weighting coefficient) that connects the In the neural network 100, the output from the previous layer neuron is The signal is multiplied by the corresponding weighting coefficient and input to the neuron in the next layer. The (k-1)th layer neuron N i (k-1) and the k-th layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the k-th layer Newron N j (k) The signal input to can be expressed by equation (1.1).

[0065]

number

[0066] That is, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) of From each, the k-th layer neuron Nj (k) When a signal is transmitted to the (k-1) ~z m (k-1) The weighting coefficients (w1 (k-1 ) j (k) Or even w m (k-1) j (k) ) is multiplied by the k-th layer neuron N j (k) has w1 (k-1) j (k) z1 (k-1) Or even w m (k-1) j (k) · z m (k-1) is input. At this time, the k-th layer neuron N j (k) The signal input to The sum of the numbers j (k) is expressed as equation (1.2).

[0067]

number

[0068] Neuron N j (k) u j (k) Depending on j (k) Generate In. Neuron N j (k) Output signal z from j (k) is defined by the following formula:

[0069]

number

[0070] The function f(u j (k) ) is the activation function in a hierarchical neural network , step function, linear ramp function, sigmoid function, etc. The activation function may be the same for all neurons or may be different. Therefore, the activation functions of neurons in each layer may be the same or different.

[0071] Incidentally, the signals output by the neurons in each layer may be analog values ​​or digital values. The digital value may be, for example, a binary value or a ternary value. For analog values, activation functions such as linear ramp functions, sigmoid functions, etc. In the case of binary digital values, for example, the output can be set to -1 or 1, or 0 or A step function with a value of 1 or 2 can be used. can be three or more values, in which case the activation function has three values, e.g., the output is -1, 0, or If we use a step function with 1, or a step function with 0, 1, or 2, good.

[0072] The neural network 100 receives an input signal at the first layer (input layer). Therefore, in each layer from the first layer (input layer) to the last layer (output layer), the input from the previous layer is sequentially Based on the input signal, an output signal is generated using equations (1.1) to (1.3), and the output signal is The signal output from the last layer (output layer) is sent to the next layer. This corresponds to the result calculated by the neural network 100.

[0073] <Example of arithmetic circuit configuration> Here, in the above-mentioned neural network 100, the equations (1.2) and (1 An example of an arithmetic circuit that can perform the operation of .3) will be explained. In this case, as an example, the weight coefficients of the synapse circuits of the neural network 100 are expressed as binary (A combination of "-1" and "+1", or a combination of "0" and "+1", etc.), or 3 The activation function of a neuron is a binary function (e.g., a combination of "-1", "0", and "1"). (A combination of "-1" and "+1", or a combination of "0" and "+1", etc.), or 3 It is a function that outputs a value (such as a combination of "-1", "0", and "1"). In the literature, the weight coefficients and the signals input from the previous layer neurons to the next layer neurons are One of the two values ​​(sometimes called the calculated value) is called the first data. The other data is referred to as second data.

[0074] The arithmetic circuit 110 shown in FIG. 2 includes, for example, an array section ALP, a circuit ILD, and a circuit W The semiconductor device includes an LD, a circuit XLD, and a circuit AFP. Neuron N1 in the kth layer in Figure 1A and Figure 1B (k) Neuron N n (k) to Input signal z1 (k-1) ~z m (k-1) and neuron N1 (k) No To Neuron N n (k) The signal z1 output from each (k) ~z n (k) Generate This is a circuit that:

[0075] The entire arithmetic circuit 110 or a part of it may be implemented as a neural network or It may be used for purposes other than AI, such as graphics calculations or scientific calculations. In the case of performing sum-of-products calculation or matrix calculation in the above, the entire calculation circuit 110, In other words, it can be used not only for AI calculations but also for general For practical calculations, the entire arithmetic circuit 110 or a part thereof may be used.

[0076] The circuit ILD includes, for example, wirings IL[1] to IL[n] and wirings ILB[1]. The circuit WLD is electrically connected to the wirings WL[n] to ILB[n]. The circuit XLD is electrically connected to wirings S[1] to WLS[m]. The circuit AFP is electrically connected to the wiring XLS[1] to the wiring XLS[m]. The wiring OL[1] to wiring OL[n], the wiring OLB[1] to wiring OLB[n], is electrically connected to

[0077] <<Array section ALP>> The array unit ALP has, for example, m×n circuits MP. are arranged in a matrix of m rows and n columns in the array section ALP. In Figure 2, the i-th row and j-th column (where i is an integer between 1 and m, and j is an integer between 1 and n) The circuit MP located at i,j is expressed as circuit MP[i,j]. is the circuit MP[1,1], the circuit MP[m,1], the circuit MP[i,j], the circuit MP[1,n ], only the circuit MP[m,n] is shown, and the other circuits MPC are omitted. is doing.

[0078] For example, the circuit MP[i,j] includes a wiring IL[j], a wiring ILB[j], and a wiring W LS[i], wiring XLS[i], wiring OL[j], and wiring OLB[j] are electrically is connected to.

[0079] The circuit MP[i,j] is, for example, a neuron N i (k-1) and neuron N j (k ) The weighting coefficient between the first data and the second data (sometimes referred to as either the first data or the second data) Specifically, the circuit MP[i,j] has the function of storing the first data. The first data (weighting coefficient) input from the wiring IL[j] and the wiring ILB[j] is It stores information (such as potential, resistance, and current). Also, the circuit MP[i,j] is , neuron N i (k-1) The signal z output from i (k-1) (First data or second data The product of the first data and the second data (sometimes referred to as the other data). As a specific example, the circuit MP[i,j] has a function of outputting the wiring XLS[i ] to the second data z i (k-1) By inputting, the product of the first data and the second data is information (e.g., current, voltage, etc.) according to the first data and the second data, or The information (e.g., current, voltage, etc.) is output to wiring OL[j] and wiring OLB[j]. Although an example in which the wiring IL[j] and the wiring ILB[j] are placed has been shown, One embodiment of the present invention is not limited to this. Only one of the wirings OL[j] and OLB[j] may be arranged. However, one embodiment of the present invention is not limited to this. ] and wiring OLB[j] may be arranged.

[0080] <<Circuit ILD>> The circuit ILD includes, for example, wirings IL[1] to IL[n] and wirings ILB[1]. through wiring ILB[n] and the circuits MP[1,1] to MP[m,n]. For each of these, the first data w1 (k-1) 1 (k) Or even w m (k-1) n (k) The device has a function of inputting information (for example, potential, resistance value, current value, etc.) corresponding to the above. As a specific example, the circuit ILD is a first weighting coefficient for the circuit MP[i,j]. Data W i (k-1) j (k) Information corresponding to the potential, resistance, or current ) are supplied by wiring IL[j] and wiring ILB[j].

[0081] <<Circuit WLD>> For example, the circuit WLD receives information (for example, It has the function of selecting the circuit MP to which data (for example, potential, resistance value, current value, etc.) is written. For example, the circuits MP[i,1] to MP[i,n] located in the i-th row of the array unit ALP When writing information (for example, potential, resistance value, current value, etc.) to the circuit WLD, For example, the write switching elements included in the circuits MP[i,1] to MP[i,n] A signal to turn on or off the child is supplied to the wiring WLS[i], and the child is turned on or off in the other rows. A potential that turns off the write switching element included in the circuit MP is supplied to the wiring WLS. Although an example in which the wiring WLS[i] is arranged has been shown, One embodiment is not limited to this. For example, the wiring WLS[i] is arranged as a plurality of wirings. That's fine.

[0082] <<Circuit XLD>> For example, the circuit XLD is connected to the circuit M via wirings XLS[1] to XLS[m]. For each of P[1,1] to MP[m,n], neuron N1 (k-1) No To Neuron N m (k) The second data z1 corresponds to the calculated value output from (k-1) ~ z m (k-1) Specifically, the circuit XLD has a function of supplying the circuit MP[i,1 ] or circuit MP[i,n], neuron N i (k-1) The second data output from Taz i (k-1) The information corresponding to the wiring XLS[i] (for example, potential, current value, etc.) Although an example in which the wiring XLS[i] is arranged has been shown, For example, the wiring XLS[i] may be arranged as a plurality of wirings. You may do so.

[0083] <<Circuit AFP>> The circuit AFP includes, for example, circuits ACTF[1] to ACTF[n]. For example, the circuit ACTF[j] is composed of wiring OL[j] and wiring OLB[j]. The circuit ACTF[j] is electrically connected to the wiring OL[j]. According to each information (e.g., potential, current value, etc.) input from wiring OLB[j] For example, the signal input from the wiring OL[j] and the wiring OLB[j] is generated. The respective pieces of information (for example, potential or current value) are compared, and a signal corresponding to the comparison result is generated. This signal is sent to neuron N j (k) The signal z output from j (k) Equivalent to That is, the circuits ACTF[1] to ACTF[n] are, for example, It functions as a circuit that calculates the activation function of the neural network. In one embodiment, the circuits ACTF[1] to ACTF[n] are not limited to the above. , may have a function of converting an analog signal into a digital signal. ACTF[1] to ACTF[n] are circuits that amplify and output analog signals. The ACTF circuit may have a function of converting the output impedance. However, one embodiment of the present invention is not limited to this. may not be placed.

[0084] The circuits ACTF[1] to ACTF[n] have the circuit configuration shown in FIG. 3A, for example. FIG. 3A shows an example of input from wiring OL[j] and wiring OLB[j]. Depending on the current, the signal z j (k) Specifically, FIG. 3A shows a circuit that generates Output signal z represented by a binary value j (k) An example of an activation function calculation circuit that outputs are.

[0085] In FIG. 3A, the circuit ACTF[j] includes a resistor RE, a resistor REB, a comparator CM P. The resistor elements RE and REB have the function of converting current into voltage. Therefore, any element or circuit that has the function of converting current into voltage is not limited to a resistive element. The wiring OL[j] is connected to the first terminal of the resistor RE and the first input terminal of the comparator CMP. and the wiring OLB[j] is electrically connected to the first terminal of the resistor REB and the comparator CM The second terminal of the resistor element RE is electrically connected to the second input terminal of the resistor element P. The second terminal of the resistor REB is electrically connected to the wiring VAL. The second terminal of the resistor element RE and the second terminal of the resistor element REB are connected to the same wiring. Alternatively, it may be connected to another wiring having the same potential.

[0086] It is preferable that the resistance values ​​of the resistor elements RE and REB are equal to each other. For example, the difference in resistance value between the resistor element RE and the resistor element REB is preferably within 10%. Preferably, it is within 5%. However, one aspect of the present invention is to In some cases or depending on the situation, the resistance elements RE and REB The resistance values ​​may be different from each other.

[0087] The wiring VAL functions as a wiring that applies a constant voltage, for example. For example, VDD is a high-level potential, VSS is a low-level potential, and GND is a ground potential. ) etc. The constant voltage can be set appropriately depending on the configuration of the circuit MP. It is preferable that a pulse signal, not a constant voltage, is supplied to the wiring VAL. It may also be used.

[0088] The voltage between the first and second terminals of the resistor element RE is the voltage flowing from the wiring OL[j]. Therefore, the resistance value of the resistor RE is input to the first input terminal of the comparator CMP. Similarly, the first and second terminals of the resistor element REB are The voltage between the comparator CM is determined by the current flowing from the wiring OLB[j]. A voltage according to the resistance value of the resistor REB and the current is input to the second input terminal of P.

[0089] As an example, the comparator CMP receives the signals input to the first input terminal and the second input terminal. A function that compares voltages and outputs a signal from the output terminal of the comparator CMP according to the comparison result. For example, the comparator CMP has a function of detecting a voltage at the second input terminal that is higher than the voltage input at the first input terminal. When the voltage input to the terminal is high, a high level potential is output from the output terminal of the comparator CMP. When the voltage input to the first input terminal is higher than the voltage input to the second input terminal, the low level The bell potential can be output from the output terminal of the comparator CMP. The potential output from the output terminal can be either high level or low level. Output signal z output by ACTF[j] j (k) can be binary. For example, the comparison The high-level potential and low-level potential output from the output terminal of the CMP are output signals z j (k) It can correspond to "+1" and "-1". The high-level potential and the low-level potential output from the output terminal of the comparator CMP are signal z j (k)may correspond to "+1" and "0".

[0090] In addition, in the circuit ACTF[j] of FIG. 3A, the resistor element RE and the resistor element REB are used. The element or circuit is not limited to a resistive element, as long as it has the function of converting current into voltage. Therefore, the resistors RE and REB of the circuit ACTF[j] in FIG. 3A are different circuit elements. For example, the circuit ACTF[j] shown in Figure 3B can be replaced by the circuit in Figure 3A. The resistors RE and REB included in the circuit ACTF[j] are replaced with the capacitors CE and This is a circuit in which CEB is replaced by ACTF[j], and it operates in a manner similar to that of the ACTF[j] circuit in Figure 3A. The capacitance values ​​of the capacitance elements CE and CEB are For example, the capacitance values ​​of the capacitance elements CE and CEB are preferably equal to each other. The difference should be within 10%, and more preferably within 5%. However, one embodiment of the present invention is not limited to this. For example, a circuit for initializing the accumulated charge may be provided in parallel with the capacitance element CE. A switch may be provided. That is, a second terminal of the switch is connected to the wiring VAL. The first terminal of the switch is connected to the first terminal of the capacitance element CE, the wiring OL[j], and the comparator Alternatively, the second terminal of the switch may be connected to the first input terminal of the CMP. AL is connected to a wiring different from the first terminal of the switch, and the first terminal of the capacitance element CE is connected to the wiring OL[j] and the first input terminal of the comparator CMP. The circuit ACTF[j] shown in C is a resistor element RE included in the circuit ACTF[j] of FIG. This is a circuit in which the resistor element REB is replaced with the diode element DE and the diode element DEB. , it can perform almost the same operation as the circuit ACTF[j] in FIG. 3A. E, the direction of the diode element DEB (the connection point between the anode and cathode) is It is desirable to change it appropriately depending on the magnitude of the order.

[0091] In addition, the comparator CMP included in the circuit ACTF[j] of FIGS. 3A to 3C is, for example, , can be replaced by an operational amplifier OP. The circuit ACTF[j] shown in Figure 3D can be The circuit diagram shows the circuit ACTF[j] in A, where the comparator CMP is replaced with an operational amplifier OP. do.

[0092] In addition, even if the switch S01a and the switch S01b are provided in the circuit ACTF[j] of FIG. 3B, As a result, the circuit ACTF[j] has the following capacitances for the capacitance elements CE and CEB: It is possible to maintain the potential according to the current input from wiring OL[j] and wiring OLB[j]. As a specific example of the circuit, as shown in FIG. 3E, The wiring OL[j] is electrically connected to the terminal of the switch S01a, and the capacitance element CE The first terminal of the switch S01b is electrically connected to the first input terminal of the comparator CMP, and the The wiring OLB[j] is electrically connected to the first terminal of the switch S01b, and the capacitance element The first terminal of CEB may be electrically connected to the second input terminal of the comparator CMP. In the circuit ACTF[j] of FIG. 3E, the first and second input terminals of the comparator CMP are When the potential of the wiring OL[j] and wiring OLB[j] is input to the switch S01a, This can be done by turning on each of the switches S01b and S01b. , the switch S01a and the switch S01b are turned off, The potentials input to the first and second input terminals of the capacitor CMP are applied to the capacitance elements CE and The switch S01a and the switch S01b are used as switches S01a and S01b. For example, an electrical switch such as an analog switch or a transistor may be used. In addition, the switches S01a and S01b may be, for example, mechanical switches. It is also possible to apply a transistor to the switches S01a and S01b. When using a silicon-doped silicon nitride semiconductor (SiN) transistor, the transistor is an OS transistor or a silicon-doped silicon nitride semiconductor (SiN) transistor. The transistor may be a transistor having a silicon nitride film (hereinafter referred to as a silicon transistor). Alternatively, the periods during which the switches S01a and S01b are kept in the on state are controlled. By doing so, it is possible to control the voltage values ​​of the capacitance elements CE and CEB. For example, when the current flowing through the capacitance elements CE and CEB is large, the switch S01a By shortening the period during which each of the switches S01a and S01b is kept in the ON state, This can prevent the voltage values ​​of the capacitance elements CE and CEB from becoming too large.

[0093] The comparator CMP included in the circuit ACTF[j] of FIGS. 3A to 3C and 3E is, for example, For example, a chopper type comparator can be used. The comparator CMP shown in FIG. 3F is a chopper type comparator. The comparator CMP is a comparator of the type shown in FIG. The inverter circuit INV3 includes a switch S03, a capacitance element CC, and an inverter circuit INV3. Switch S02a, switch S02b, and switch S03 are the same as the switches S01a and S02b. As with 01b, mechanical switches, OS transistors, Si transistors, and other transistors are used. It can be a digital signal.

[0094] The first terminal of the switch S02a is electrically connected to the terminal VinT, and the second terminal of the switch S02b is electrically connected to the terminal VinT. A first terminal of the switch S02a is electrically connected to the terminal VrefT, and a second terminal of the switch S02b is electrically connected to the terminal VrefT. The second terminal of the switch S02b is electrically connected to the first terminal of the capacitance element CC. The second terminal of the capacitor CC is connected to the input terminal of the inverter circuit INV3 and the first terminal of the switch S03. The terminal VoutT is electrically connected to the output terminal of the inverter circuit INV3. The output terminal of the switch S01 is electrically connected to the output terminal of the switch S02 and the second terminal of the switch S03.

[0095] The terminal VinT functions as a terminal for inputting the input potential to the comparator CMP, and the terminal V refT functions as a terminal for inputting a reference potential to the comparator CMP, and the terminal Vout T functions as a terminal for outputting the output potential from the comparator CMP. nT corresponds to either the first terminal or the second terminal of the comparator CMP in FIGS. 3A to 3C and 3E. The terminal VrefT corresponds to the first or second terminal of the comparator CMP shown in FIGS. 3A to 3C and 3E. It can correspond to the other child.

[0096] The circuit ACTF[j] of FIGS. 3A to 3E outputs an output signal z j (k) The activation function circuit ACTF[j] outputs the output signal z j (k) of The output may be three or more values ​​or an analog value.

[0097] 4A to 4F show the currents input from the wiring OL[j] and wiring OLB[j]. , signal z j (k)is a circuit that generates an output signal z represented by a ternary value. j (k) Exit 1 shows an example of a calculation circuit for the input activation function.

[0098] The circuit ACTF[j] shown in FIG. 4A includes a resistor RE, a resistor REB, a comparator CMPa , and comparator CMPb. The wiring OL[j] connects the first terminal of the resistor element RE and the comparator CM The wiring OLB[j] is electrically connected to the first input terminal of the resistor REB. The terminal is electrically connected to the first input terminal of the comparator CMPb. The second input terminal of the comparator Pa and the second input terminal of the comparator CMPb are electrically connected to the wiring VrefL. Furthermore, the second terminal of the resistor element RE is electrically connected to the wiring VAL, A second terminal of the resistor REB is electrically connected to the wiring VAL.

[0099] The wiring VrefL is a constant voltage V ref It acts as a wiring that provides V ref For example, It is preferable that the voltage be higher than GND and lower than VDD. ref is GN It may be a potential lower than D or a potential higher than VDD. ref is the comparator CMPa, It is used as a reference potential (potential for comparison) in comparator CMPb.

[0100] The voltage between the first and second terminals of the resistor element RE is the voltage flowing from the wiring OL[j]. Therefore, the first input terminal of the comparator CMPa is connected to the resistor element RE. Similarly, the first and second terminals of the resistor element REB are connected to the resistor R1 and R2. The voltage between is determined by the current flowing from the wiring OLB[j]. The first input terminal of the resistor CMPb receives a voltage according to the resistance value of the resistor REB and the current. will be done.

[0101] The comparator CMPa compares the voltages input to the first input terminal and the second input terminal. Then, a signal is output from the output terminal of the comparator CMPa according to the comparison result. The comparator CMPa detects that the voltage input to the second input terminal ( V ref ) is high, a high-level potential is output from the output terminal of the comparator CMPa, and a high-level potential is output from the second input terminal The voltage (V ref ) when the voltage input to the first input terminal is higher than , a low level potential can be output from the output terminal of the comparator CMPa.

[0102] Similar to the comparator CMPa, the comparator CMPb has a first input terminal and a second input terminal. The voltage input to the comparator CMPb is compared with the voltage input to the comparator CMPb, and a signal is output from the output terminal of the comparator CMPb according to the comparison result. For example, the comparator CMPb outputs a signal when the voltage input to the second input terminal is lower than the voltage input to the first input terminal. The voltage (V ref ) is high, the high level potential is output from the comparator CMPb. The voltage input to the second input terminal (V ref ) to the first input terminal. When the input voltage is high, a low level potential is output from the output terminal of the comparator CMPb. can be done.

[0103] At this time, the potentials output from the output terminals of the comparators CMPa and CMPb are Depending on j (k) For example, the output of the comparator CMPa can be expressed as A high-level potential is output from the output terminal of the comparator CMPb, and a low-level potential is output from the output terminal of the comparator CMPb. If the output signal z j (k) is set to "+1", and a low level is output from the output terminal of the comparator CMPa. When a high-level potential is output from the output terminal of comparator CMPb, signal z j (k) is set to "-1", and a low level potential is output from the output terminal of the comparator CMPa. When a low-level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) teeth It can be set to "+0".

[0104] In addition, the circuit ACTF[j] is not limited to the circuit configuration shown in FIG. 4A, and may be configured as follows depending on the situation: For example, in the circuit ACTF[j] of FIG. 4A, the comparator CMPa If you want to combine the two output results of the comparator CMPb into one signal, use the circuit ACTF The circuit ACTF[j] in FIG. 4B is the same as the circuit in FIG. 4A. This is a configuration example in which a conversion circuit TRF is provided in ACTF[j]. The output terminals of the converters T and T are electrically connected to the input terminals of the converter circuit T. A specific example of RF is a digital-to-analog converter (in this case, a signal z j (k) Haa (The value is analog.)

[0105] Also, for example, in FIG. 4A, the second inputs of the comparators CMPa and CMPb are The wire VrefL electrically connected to the output terminal is connected to the wires Vref1L and Vref2L. The ACTF[j] circuit in FIG. 4C is the ACTF[j] circuit in FIG. 4A. The second terminal of the comparator CMPa included in [j] is not the wiring VrefL but the wiring Vref1 L, and the second terminal of the comparator CMPb is connected to the line Vref instead of the line VrefL. 2L. The input to the wiring Vref1L and Vref2L By setting the potentials output from the comparators CMPa and CMPb to different values, The reference potentials can be set separately.

[0106] Also, for example, as a configuration different from the circuit ACTF[j] of FIGS. 4A to 4C, an amplifier circuit Alternatively, an impedance conversion circuit or the like may be used. For example, the circuit AC TF[j] can be applied to the circuit AFP of the arithmetic circuit 110 in Figure 2. ACTF[j] is the resistor RE, resistor REB, operational amplifier OPa, and operational amplifier OP b, which functions as an amplifier circuit.

[0107] The wiring OL[j] is connected to the first terminal of the resistor RE and the non-inverting input terminal of the operational amplifier OPa. , and the wiring OLB[j] is electrically connected to the first terminal of the resistor REB and the operational amplifier O It is electrically connected to the non-inverting input terminal of Pb. It is also electrically connected to the inverting input terminal of the operational amplifier OPa. The terminal is electrically connected to the output terminal of the operational amplifier OPa and the inverting input terminal of the operational amplifier OPb. The terminal is electrically connected to the output terminal of the operational amplifier OPb. The second terminal of the resistor REB is electrically connected to the wiring VAL. is electrically connected to

[0108] That is, the operational amplifiers OPa and O Pb is configured as a voltage follower. This allows the operational amplifier OPa to The potential output from the output terminal is the same as the potential input to the non-inverting input terminal of the operational amplifier OPa. The voltage output from the output terminal of the operational amplifier OPb is approximately equal to the voltage In this case, the output signal z j (k) teeth , are output from the circuit ACTF[j] as two analog values. The output terminal of the operational amplifier OPb is connected to the input terminal of the comparator CMP. The output from the comparator CMP may be connected to the output signal z j (k) It may also be possible to use the following.

[0109] Also, for example, as a configuration different from the circuit ACTF[j] of FIGS. 4A to 4D, an integrating circuit A current-voltage conversion circuit may be used. Furthermore, an integrating circuit, a current As an example, a voltage conversion circuit may be configured by replacing the circuit ACTF[j] shown in FIG. 4E with the circuit ACTF[j] shown in FIG. This can be applied to the circuit AFP of the arithmetic circuit 110. The circuit ACTF[j] in FIG. It has operational amplifiers OPa, OPb, load elements LEa, and load elements LEb.

[0110] The wiring OL[j] is connected to the first input terminal (for example, the inverting input terminal) of the operational amplifier OPa and the negative The first terminal of the load element LEa is electrically connected to the line OLB[j]. b and the first terminal of the load element LEb. Also, the second input terminal (for example, the non-inverting input terminal) of the operational amplifier OPa is connected to , electrically connected to the wiring Vref1L, and the second input terminal (for example, non The inverting input terminal of the load element LEa is electrically connected to the wiring Vref2L. The terminal is electrically connected to the output terminal of the operational amplifier OPa, and the second terminal of the load element LEa is , and is electrically connected to the output terminal of the operational amplifier OPb.

[0111] The wiring Vref1L and the wiring Vref2L may have the same voltage or different voltages. Therefore, the wiring Vref1L and wiring Vref2 L can be combined into one wire.

[0112] In the circuit ACTF[j] of FIG. 4E, the load elements LEa and LEb are, for example, For example, it can be a resistance element or a capacitance element. By using a capacitance element as the operational amplifier OPa, the load element LEa, and the operational amplifier OPb and the load element LEb each function as an integrator. Or, depending on the amount of current flowing through the wiring OLB[j], each capacitance element (load element LEa , LEb) charges are stored. That is, charges flow from wiring OL[j] and wiring OLB[j]. The current is integrated by an integrator circuit and converted into a voltage, which is then output as a signal z j (k) year The output terminal of the operational amplifier OPa and the output terminal of the operational amplifier OPb are connected to each other. , may be connected to the input terminals of the comparator CMP. The output signal z j (k) The capacitive elements of the load elements LEa and LEb may be For example, a circuit for initializing the charge stored in the load element LEa( A switch may be provided in parallel with the capacitor element. That is, the second terminal of the switch , the output terminal of the operational amplifier OPa is connected, and the first terminal of the switch is connected to the wiring OL[j], It may also be connected to the first input terminal (for example, the inverting input terminal) of the operational amplifier OPa. stomach.

[0113] In addition, in the circuit ACTF[j] of FIG. 4E, from the wiring OL[j] and wiring OLB[j] When converting the flowing current into a voltage and outputting it, the load elements LEa and LEb are as follows: A resistive element can be used instead of the capacitive element.

[0114] 4F as a configuration different from the circuit ACTF[j] of FIG. 4A to FIG. 4E. The circuit ACTF[j] shown can be applied to the circuit AFP of the arithmetic circuit 110 in FIG. The circuit ACTF[j] in FIG. 4F includes a resistor RE, a resistor REB, and an analog-to-digital converter. It has a circuit ADCa and an analog-to-digital conversion circuit ADCb.

[0115] The wiring OL[j] is connected to the input terminal of the analog-to-digital conversion circuit ADCa and the resistor element RE. The first terminal is electrically connected to the wiring OLB[j], and the wiring OLB[j] is electrically connected to the analog-to-digital conversion circuit AD The input terminal of the resistor element Cb is electrically connected to the first terminal of the resistor element REB. The second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is electrically connected to the wiring VAL. It is electrically connected to VAL.

[0116] In the circuit ACTF[j] of FIG. 4F, the current flows from the wiring OL[j] and wiring OLB[j]. The potentials of the first terminals of the resistors RE and REB are determined according to the current. Then, the circuit ACTF[j] converts the analog value of the potential into an analog-to-digital conversion circuit. By ADCa and ADCb, two-value or three-value or more (for example, 256-value) digital Convert the signal z j (k) It has the function of outputting as

[0117] The resistor elements RE and REB shown in FIGS. 4A to 4F are the same as those shown in FIGS. 3B and 3C. Similarly, the capacitance element CE, the capacitance element CEB, or the diode element DE, the diode element DE In particular, the resistor element RE and the resistor element B shown in FIGS. When REB is replaced with the capacitance element CE and the capacitance element CEB, the switching By providing switches S01a and S01b, the wiring OL[j] and wiring OLB[j] can be The input potential can be maintained.

[0118] The arithmetic circuit 110 in FIG. 2 performs the following operations depending on the circuit configuration of the circuit MP[i,j]. i,j] can be changed. For example, in Figure 2, In the arithmetic circuit 110, the wiring WLS[i ] can be one or more wires. For example, in the circuit MP[i,j], The electrically connected wire XLS[i] can be one or more wires. .

[0119] <<Circuit MP>> Next, a configuration example of the circuit MP[i,j] included in the arithmetic circuit 110 will be described.

[0120] FIG. 5A shows an example of the configuration of a circuit MP[i,j] that can be applied to the arithmetic circuit 110. The path MP[i,j] includes, for example, a circuit MC and a circuit MCr. The circuit MCr is a circuit MP that stores weight coefficients, input signals (calculated values) of neurons, and The circuit MC is a circuit that calculates the product of the two. The circuit MC may have the same configuration as the circuit MCr or a different configuration from the circuit MCr. Therefore, the circuit MCr is designated by the symbol MC in order to distinguish it from the circuit MC. The symbols of the circuit elements included in the circuit MCr, which will be described later, are marked with "r". It also has an "r" attached to it.

[0121] For example, the circuit MC has a holding unit HC, and the circuit MCr has a holding unit HCr. The holding unit HC and the holding unit HCr each store information (for example, potential, resistance value, current value, etc.) ) is stored in the circuit MP[i,j]. i (k -1) j (k) The information (for example, the electric Therefore, the holding part HC and the holding part HCr are determined according to the value of the holding part HC. Each of the first data w i (k-1) j (k) Each piece of information (e.g., potential, resistance) The wires IL[j] and ILB[j] are electrically connected to the wires IL[j] and ILB[j] that supply the There are.

[0122] The wiring WL[i] shown in FIG. 5A corresponds to the wiring WLS[i] in FIG. 2. L[i] is electrically connected to each of the holding unit HC and the holding unit HCr. The first data w is stored in each of the holding unit HC and the holding unit HCr included in P[i,j]. i (k -1) j (k)When writing information (such as potential, resistance, or current) according to the By supplying a predetermined potential to the line WL[i], the wiring IL[j] and the holding unit HC are connected. The wiring ILB[j] and the holding unit HCr are brought into a conductive state. The first data w is added to L[j] and ILB[j]. i (k-1) j (k) The potential according to By supplying the potential etc. to the holding part HC and the holding part HCr, After that, a predetermined potential is applied to the wiring WL[i], and the wiring IL[j ] and the holding unit HC are brought into a non-conductive state, and the wiring ILB[j] and the holding unit HCr are brought into a non-conductive state. Then, the first data w is stored in each of the holding unit HC and the holding unit HCr. i (k-1 ) j (k) Each potential according to the above is maintained.

[0123] For example, the first data i (k-1) j (k) is one of the three values ​​"-1", "0" or "1". Consider the case where either of the first data w i (k-1) j (k) If is "1", for example As a result, a high level potential is held in the holding unit HC, and a low level potential is held in the holding unit HCr. Also, the first data i (k-1) j (k) is "-1", for example, the holding part H C holds a low level potential, and the holding section HCr holds a high level potential. Ta w i (k-1)j (k) is "0", for example, a low level potential is applied to the holding unit HC. As another example, the first data w i (k-1) j (k) is an analog value, specifically a "negative analog value", "0", or , consider the case where the first data w takes a "positive analog value." i (k-1) j (k) is "positive In the case of the "analog value", for example, a high level analog potential is held in the holding unit HC, The holding unit HCr holds a low level potential. i (k-1) j (k) but" In the case of a "negative analog value", for example, a low level potential is held in the holding unit HC, and A high level analog potential is held in HCr. i (k-1) j (k ) is "0", for example, a low level potential is held in the holding unit HC, and the holding unit HCr The analog value is a multi-bit (multi-value) digital value. That is, as an example, the first data w i (k-1) j (k) But, "1", In the case where the numbers are "2" and "3", for example, the holder HC has a number corresponding to "1", "2", and "3". The high level potential having the potential set by the voltage applied to the capacitor is held in the holding section HCr, and the low level potential is held in the holding section HCr. , the first data w i (k-1) j (k)If is "-1", "-2", "-3", for example The holding section HC holds a low level potential, and the holding section HCr holds "-1" and "-2" ", "-3" are the absolute values ​​of "1", "2", "3" and maintain a high level of electric potential. And the first data i (k-1) j (k) is "0", as an example, A low level potential is held in HC, and a low level potential is held in the holding section HCr.

[0124] Also, as an example, the circuit MC stores information (for example, potential, resistance value) stored in the storage unit HC. , current value, etc.) to either wiring OL[j] or wiring OLB[j]. The circuit MCr has a function of outputting information (for example, potential, The current, voltage, etc. according to the resistance value, current value, etc. are connected to the wiring OL[j] or wiring OLB[j]. For example, when a high level potential is held in the holding section HC, In this case, the circuit MC outputs a current having a first current value, and a low level potential is held in the holding section HC. When the holding unit HC is in the ON state, the circuit MC outputs a current having a second current value. When r is held at a high level potential, the circuit MCr outputs a current having a first current value; When the holding section HCr holds a low level potential, the circuit MCr flows a current having a second current value. The magnitudes of the first current value and the second current value are respectively determined by the circuit MC , the configuration of the circuit MCr, the holding unit HC, the holding unit HCr, etc., and the first data w i (k-1) j ( k) For example, when the first current value is greater than the second current value, Furthermore, one of the first current value or the second current value may be zero current, and In other words, the current value may be 0. Or, there may be a current with a first current value and a current with a second current value. In particular, for example, the first data w i (k-1) j (k) When the value of the first current or the second current is "-1", "0", or "1", It is preferable to configure the circuit MC and the circuit MCr so that one of the current values ​​is 0. , the first data w i (k-1) j (k) is an analog value, e.g., "negative analog value", "0 " or "positive analog value", the first current value or the second current value , for example, it can take an analog value.

[0125] In this specification and the like, the information held in the holding unit HC and the holding unit HCr (for example, For example, the current, voltage, etc. according to the potential, resistance, current value, etc. are treated as positive current, voltage, etc. It may be a positive current or voltage, or a negative current or voltage, or both positive and negative currents or voltages may be mixed. That is, for example, the information held in the above-mentioned "holding unit HC" (for example, potential, resistance value, current value, etc.) The current, voltage, etc. according to the current, voltage, etc. are output to either wiring OL[j] or wiring OLB[j]. The circuit MCr has a function of storing information (for example, potential, resistance value, current value, etc.) to the other side of wiring OL[j] or wiring OLB[j]. The phrase "has the function of inputting information stored in the storage unit HC (for example, potential, resistance)" is interpreted as meaning that "the storage unit HC has the function of inputting information stored in the storage unit HC (for example, potential, resistance, resistance)." The current, voltage, etc. according to the resistance, current value, etc. of the wiring OL[j] or wiring OLB[j] The circuit MCr has the function of discharging a voltage corresponding to the potential held in the holding section HCr. The description "has the function of discharging the current from the other of the wiring OL[j] or the wiring OLB[j]" This can be rephrased as:

[0126] The wiring X1L[i] and the wiring X2L[i] shown in FIG. 5A are the wiring XLS in FIG. [i]. The second data z input to the circuit MP[i,j] corresponds to i (k-1) teeth For example, the potentials and currents of the wiring X1L[i] and the wiring X2L[i] Therefore, the circuit MC and the circuit MCr are provided with, for example, wiring X1L[ i] and the second data z i (k-1) Each potential is input according to can be.

[0127] The circuit MC is electrically connected to the wiring OL[j] and the wiring OLB[j]. r is electrically connected to the wiring OL[j] and the wiring OLB[j]. For example, the circuit MCr receives the voltages input to the wiring X1L[i] and the wiring X2L[i]. The first data w is sent to the wiring OL[j] and the wiring OLB[j] according to the position. i (k-1) j (k ) and the second data z i (k-1) The current, potential, etc. according to the product of In this case, the current output destinations from the circuits MC and MCr are the wiring X1L[i] and wiring X2L[i For example, each of the circuits MC and MCr is determined by the potential of the circuit M The current output from C flows to either the wiring OL[j] or the wiring OLB[j], and the circuit MCr A circuit configuration in which the current output from the In other words, the currents output from the circuit MC and the circuit MCr are as follows: The current flows not through the same wiring but through different wirings. There are cases where no current flows from the circuit MCr to either the wiring OL[j] or the wiring OLB[j]. be.

[0128] For example, the second data z i (k-1) can take one of three values: "-1", "0", or "1". For example, the second data z i (k-1) If is "1", the circuit MP The circuit MC and the wiring OL[j] are in a conductive state, and the circuit MCr and the wiring OLB[j] are in a conductive state. is in a conductive state. i (k-1) If is "-1", The path MP is in a conductive state between the circuit MC and the wiring OLB[j], and is in a conductive state between the circuit MCr and the wiring OL[ j] is in a conductive state. For example, the second data z i (k-1) If is "0", The currents output by the circuits MC and MCr are connected to the wiring OL[j] and wiring OLB[j]. In order to prevent current from flowing to either of the circuits, the circuit MP is connected between the circuit MC and the wiring OL[j], And, the circuit MC and the wiring OLB[j] are brought into a non-conductive state, and the circuit MCr and the wiring OL[j ] and between the circuit MCr and the wiring OLB[j].

[0129] An example of the above operations is shown below. i (k-1) j (k) is "1" In this case, a current is output from the circuit MC, and the first data w i (k-1) j (k) is "-1" In this case, a current is output from the circuit MCr. i (k-1) is "1" In this case, the connection between the circuit MC and the wiring OL[j] and between the circuit MCr and the wiring OLB[j] The second data z i (k-1) If is "-1", then the circuit MC and Conduction occurs between the wiring OLB[j] and the circuit MCr and the wiring OL[j]. From the above, the first data i (k-1) j (k) and the second data z i (k-1) product of When the first data w is a positive value, a current is output to the wiring OL[j]. i (k-1) j (k) and the second data z i (k-1) If the product is negative, the current flows through the wiring OLB[j]. The first data w is output. i (k-1) j (k) and the second data z i (k-1) The product of is zero When the value is , no current is output to either wire.

[0130] To take the above example as a specific example, the first data w i (k-1) j (k) is "1" And the second data z i (k-1) is "1", for example, from the circuit MC to the wiring OL A current I1[i,j] with a first current value flows through the wiring OLB[j] from the circuit MCr. A current I2[i,j] having a second current value flows through the first current I2[i,j]. At this time, the magnitude of the second current value is For example, it is zero. In other words, strictly speaking, the current from the circuit MCr to the wiring OLB[j] is It doesn't flow. First data i (k-1) j (k) is "-1", and the second data z i (k -1) If is "1", for example, a current having a second current value is sent from the circuit MC to the wiring OL[j]. A current I1[i,j] flows, and a current I2 with a first current value flows from the circuit MCr to the wiring OLB[j]. [i, j] flows. At this time, the magnitude of the second current value is, for example, zero. In other words, strictly speaking, no current flows from the circuit MC to the wiring OL[j]. i (k- 1) j (k) is "0", and the second data z i (k-1) If is "1", the circuit M A current I1[i, j] having a second current value flows from C to the wiring OL[j], and a current I2[i, j] flows from the circuit MCr to the wiring OL[j]. A current I2[i, j] having a second current value flows through the line OLB[j]. At this time, the second current value For example, the magnitude of is zero. In other words, strictly speaking, from the circuit MC to the wiring OL[j ], and no current flows from circuit MCr to wiring OLB[j].

[0131] Also, the first data i (k-1) j (k) is "1", and the second data z i (k-1 )is "-1", a current I1[ i, j] flows from the circuit MCr to the wiring OL[j], and a current I2[i, j] with a second current value flows At this time, the magnitude of the second current value is, for example, zero. In this case, no current flows from the circuit MCr to the wiring OL[j]. i (k-1) j ( k) is "-1", and the second data z i (k-1) If is "-1", the circuit MC A current I1[i, j] with a second current value flows from the circuit MCr to the wiring OLB[j]. A current I2[i, j] with a first current value flows through OL[j]. At this time, a current I2[i, j] with a second current value flows through OL[j]. For example, the magnitude is zero. In other words, strictly speaking, the wiring OLB[j] from the circuit MC No current flows through the first data i (k-1) j (k) is "0", and the second data z i (k-1) If is "-1", the second current value flows from the circuit MC to the wiring OLB[j]. Current I1[i, j] flows, and current I2 with a second current value flows from circuit MCr to wiring OL[j]. [i, j] flows. At this time, the magnitude of the second current value is, for example, zero. Strictly speaking, no current flows from the circuit MC to the wiring OLB[j], and no current flows from the circuit MCr to the wiring O No current flows through L[j].

[0132] Also, the second data z i (k-1) When is "0", for example, the circuit MC and the wiring OL[j] and between the circuit MC and the wiring OLB[j]. , between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OLB[j] Therefore, the first data w i (k-1) j (k) Whatever the value of No current is output from the circuit MC and the circuit MCr to the wiring OL[j] and the wiring OLB[j]. stomach.

[0133] In this way, as an example, the first data w i (k-1) j (k) and the second data z i (k -1) If the product of is positive, the wiring is A current flows through OL[j]. At this time, the first data w i (k-1) j (k) If is a positive value In this case, a current flows from the circuit MC to the wiring OL[j], and the first data w i (k-1) j (k) When the value of is negative, a current flows from the circuit MCr to the wiring OL[j]. w i (k-1) j (k) and the second data z i (k-1) If the product of is negative, A current flows through the wiring OLB[j] from either the circuit MC or the circuit MCr. First data w i (k-1) j (k) If is a positive value, the wiring OLB[j] from the circuit MC A current flows through the first data w i (k-1) j (k)If is negative, then from the circuit MCr Current flows through the wiring OLB[j]. Therefore, multiple circuits M connected to the wiring OL[j] The sum of the currents output from C or the circuit MCr flows through the wiring OL[j]. In other words, a current that is the sum of positive values ​​flows through the wiring OL[j]. On the other hand, the current output from multiple circuits MC or MCr connected to wiring OLB[j] The sum of the negative current flows to the wiring OLB[j]. As a result of the above operation, a current equal to the sum of the values ​​flows through the wiring OL[ The total current value flowing through wiring OLB[j], that is, the sum of the positive values, and the total current value flowing through wiring OLB[j], In other words, by using the sum of negative values, it is possible to perform product-sum calculations. For example, the total current value flowing through wiring OL[j] is greater than the total current value flowing through wiring OLB[j]. If it is larger, it can be determined that the result of the multiplication and accumulation operation will be a positive value. If the total current value flowing through OL[j] is smaller than the total current value flowing through wiring OLB[j], In this case, it can be determined that the result of the sum-of-products operation is a negative value. ] and the total current value flowing through wiring OLB[j] are approximately the same value. It can be determined that the result of the multiplication and accumulation operation is zero.

[0134] In addition, the second data z i (k-1) is one of two values: "-1", "0", or "1" For example, the binary values ​​"-1" and "1" or the binary values ​​"0" and "1" are also the same. Similarly, the first data w i (k-1) j (k) is "-1", In the case of two values, for example, "-1" and "1", Alternatively, the same operation can be performed in the case of two values, "0" and "1".

[0135] In addition, the first data i (k-1) j (k) is an analog value or multi-bit (multi-valued) A specific example is to use "negative analog" instead of "-1". value” and “1” can be replaced by “positive analog value”. In this case, the circuit M The magnitude of the current flowing from C or the circuit MCr is also, for example, the first data w i (k-1 ) j (k) It becomes an analog value according to the absolute value of the value.

[0136] Next, an example of modifying the circuit MP[i,j] in FIG. 5A will be described. Regarding the modified example of [i,j], the difference from the circuit MP[i,j] of FIG. 5A will be mainly explained. , the description of the parts common to the circuit MP[i,j] in FIG. 5A may be omitted.

[0137] The circuit MP[i,j] shown in FIG. 5B is a modified example of the circuit MP[i,j] in FIG. 5A. The circuit MP[i,j] of FIG. 5B is the same as the circuit MP[i,j] of FIG. 5A, but is composed of a circuit MC and a circuit However, the circuit MP[i,j] in FIG. 5B includes a holding unit HCr in the circuit MCr. 5A in that it does not include

[0138] Also, since the circuit MCr does not have a holding unit HCr, the circuit MP[i,j] in FIG. The applied arithmetic circuit uses the wiring ILB[j] to supply the potential to be held in the holding unit HCr. In addition, the circuit MCr may not be electrically connected to the wiring WL[i]. Good too.

[0139] In the circuit MP[i,j] of FIG. 5B, the holding unit HC included in the circuit MC is That is, the circuit MP[i,j] in FIG. 5B is electrically connected to the circuit MCr and the circuit MC and the holding unit HC are configured to share each other. The inverted signal of the signal held in C is supplied from the holding unit HC to the circuit MCr. This allows the circuits MC and MCr to operate differently. Alternatively, the internal circuit configurations of the circuits MC and MCr may be different. The voltages output by the circuits MC and MCr for the same signal held by the holding unit HC are It is also possible to make the magnitude of the flow different. i (k-1) j (k) and holds the potential according to the second data z i (k-1) Apply a potential according to By supplying the line X1L[i] and the wiring X2L[i], the circuit MP[i,j] is The first data w i (k-1) j (k) and Day 2 Taz i (k-1) It is possible to output a current according to the product of

[0140] The arithmetic circuit 110 to which the circuit MP of FIG. 5B is applied is the same as the circuit of the arithmetic circuit 120 shown in FIG. The arithmetic circuit 120 can be changed to a wiring configuration from the arithmetic circuit 110 in FIG. The configuration excludes wiring B[1] to wiring ILB[m].

[0141] The circuit MP[i,j] shown in FIG. 5C is a modified example of the circuit MP[i,j] in FIG. 5A. Specifically, this is an example of the configuration of the circuit MP[i,j] that can be applied to the arithmetic circuit 120 in FIG. The circuit MP[i,j] of C is the same as the circuit MP[i,j] of FIG. 5A, and is composed of the circuit MC and the circuit M Cr. However, the circuit MP[i,j] in FIG. 5C and the circuit MP[i,j] in FIG. 5A have , the configuration of the electrically connected wiring is different.

[0142] The wiring W1L[i] and the wiring W2L[i] shown in FIG. 5C are the wiring WLS The wiring W1L[i] is electrically connected to the holding unit HC, and the wiring W2L[i ] is electrically connected to the holding part HCr.

[0143] The wiring IL[j] is electrically connected to the holding portion HC and the holding portion HCr. .

[0144] In the circuit MP[i,j] of FIG. 5C, different When holding the potential, the holding operation of the potential to the holding part HC and the holding part HCr is not simultaneous, For example, the first data w of the circuit MP[i,j] i (k-1) j (k ) can be expressed by holding the first potential in the holding part HC and the second potential in the holding part HCr. First, a predetermined voltage is applied to each of the wiring W1L[i] and the wiring W2L[i]. By applying a potential, the holding unit HC and the wiring IL[j] are brought into a conductive state, and the holding unit HCr and the wiring IL[j] are brought into a conductive state. Next, a first potential is supplied to the wiring IL[j]. Then, the first potential can be applied to the holding unit HC. A predetermined potential is applied to each of the lines W2L[i], and a potential is applied between the holding unit HC and the wiring IL[j]. The holding unit HCr and the wiring IL[j] are brought into a non-conductive state, and the holding unit HCr and the wiring IL[j] are brought into a conductive state. By supplying the second potential to the wiring IL[j], the second potential can be applied to the holding unit HCr. As a result, the circuit MP[i,j] receives w as the first data. i (k-1) j (k) of It can be set.

[0145] In addition, when the holding section HC and the holding section HCr are held at approximately the same potential (circuit M The first data w of P[i,j] i (k-1) j (k) However, the holding part HC and the holding part HCr (When the voltage is set by holding the voltage at the holding section HC and the wiring IL and the holding unit HCr and the wiring IL[j] are in a conductive state. In this way, a predetermined potential is applied to each of the wiring W1L[i] and the wiring W2L[i]. After that, the potential is supplied to the wiring IL[j].

[0146] The circuit MP[i,j] in FIG. 5C stores first data w in the holding unit HC and the holding unit HCr. i (k -1) j (k) and holds the potential according to the second data z i (k-1) Wire X with a potential according to 1L[i] and wiring X2L[i], the circuit MP[i,j] in FIG. 5A Similarly, the first data w i (k-1) j (k) and the second data z i (k-1) It is possible to output a current according to the product of

[0147] The circuit MP[i,j] shown in FIG. 5D is a modified version of the circuit MP[i,j] in FIG. 5A. The circuit MP[i,j] of FIG. 5D is composed of a circuit MC and a circuit MCr, where the circuit MP[i,j] in FIG. 5D and the circuit MP[i,j] in FIG. 5A The configuration of the electrically connected wiring is different.

[0148] The wiring IOL[j] in FIG. 5D is a combination of the wiring IL[j] and the wiring OL[j] in FIG. 5A. The wire IOLB[j] in Figure 5D functions as a bundled wire. LB[j] and wiring OLB[j] function as a single wiring. The IOL[j] is electrically connected to the holding portion HC, the circuit MC, and the circuit MCr, and is connected to the wiring The IOLB[j] is electrically connected to the holding unit HCr, the circuit MC, and the circuit MCr. There are.

[0149] The circuit MP[i,j] in FIG. 5D is i (k-1) j (k) When holding Therefore, between the circuit MC and the wiring IOL[j], and between the circuit MC and the wiring IOLB[j] becomes non-conductive, and the circuit MCr and the wiring IOL[j] and the circuit MCr and the wiring IOL[j] become non-conductive. The wiring X1L[i] and the wiring X2L[ A predetermined potential is input to the wiring WL[i]. Then, a predetermined potential is input to the wiring WL[i] and maintained. The holding unit HC and the wiring IOL[j] are electrically connected, and the holding unit HCr and the wiring IOLB[j ] and the wiring IOL[j] and the wiring IOLB[j] are connected to each other. 1 data w i (k-1) j (k) By supplying each potential according to Each potential can be input to the holding unit HC and the holding unit HCr. The connection between the holding part HCr and the wiring IOL[j] is non-conductive, and the connection between the holding part HCr and the wiring IOLB[j] is non-conductive. By inputting a predetermined potential to the wiring WL[i], the connection between the wirings is made non-conductive. The first data w is stored in each of the holding unit HC and the holding unit HCr. i (k-1) j (k) According to each The potential can be maintained.

[0150] The first data w is stored in each of the holding unit HC and the holding unit HCr. i (k-1) j (k) Depending on After the potential is maintained, the second data z i (k-1) The potential according to the wiring X1L[i] and By supplying the signal to the wiring X2L[i], the wiring is connected in the same manner as the circuit MP[i,j] in FIG. 5A. OL[j] and wiring OLB[j], the first data w i (k-1) j (k) and the second data z i (k-1) It is possible to output a current according to the product of

[0151] The arithmetic circuit 110 to which the circuit MP of FIG. 5D is applied is the same as the circuit of the arithmetic circuit 130 shown in FIG. The arithmetic circuit 130 can be changed to the circuit configuration in the arithmetic circuit 110 of FIG. The lines IL[1] to IL[n] and the lines OL[1] to OL[n] are connected to the wiring IO L[1] to IOL[n] are grouped together, and wiring ILB[1] to ILB[n] are grouped together. , wiring OLB[1] to wiring OLB[n], and wiring IOLB[1] to wiring IOLB[n] n]. In the arithmetic circuit 130, the wiring IOL[1 ] to wiring IOL[n], wiring IOLB[1] to wiring IOLB[n] are connected to the circuit ILD. In other words, the wiring IOL[j] and the wiring IOLB[j] are electrically connected to the circuit MP For [i,j], the first data w i (k-1) j (k) A signal line for transmitting the In this case, the circuit MP [i,j] is the first data w i (k-1) j (k) When transmitting, the circuit ILD The connection between LD and wiring IOL[j] and between circuit ILD and wiring IOLB[j] are established. The circuit ACTF[j] is connected between the circuit ACTF[j] and the wiring IOL[j] and between the circuit AC It is preferable to make the connection between TF[i] and the wiring IOLB[j] non-conductive. When supplying current to the circuit ACTF[j], the circuit ILD is connected to the wiring IOL[j ] and between the circuit ILD and the wiring IOLB[j] are made non-conductive, and the circuit ACTF[ j] is the connection between the circuit ACTF[j] and the wiring IOL[j], and between the circuit ACTF[j] and the wiring I It is preferable to establish a conductive state between OLB[j] and OLB[j].

[0152] The circuit MP[i,j] shown in FIG. 5E is a modified example of the circuit MP[i,j] in FIG. 5A. Specifically, this is an example of the configuration of the circuit MP[i,j] that can be applied to the arithmetic circuit 110 in FIG. The circuit MP[i,j] of E is the same as the circuit MP[i,j] of FIG. 5A, and is composed of the circuit MC and the circuit M However, the circuit MP[i,j] in FIG. 5E has a circuit MC connected to the wiring OLB[j]. The circuit MCr is electrically connected to the wiring OL[j]. 5A and the circuit MP[i,j] in FIG.

[0153] The wiring WL[i] shown in FIG. 5E corresponds to the wiring WLS[i] in FIG. 2. L[i] is electrically connected to the holding unit HC and the holding unit HCr.

[0154] 2. The wiring XL[i] shown in FIG. 5E corresponds to the wiring XLS[i] in FIG. The wiring XL[i] is electrically connected to the circuit MC and the circuit MCr.

[0155] As described above, the circuit MP[i,j] in FIG. 5E is electrically connected to the wiring OLB[j] by the circuit MC. , and the circuit MCr is not electrically connected to the wiring OL[j]. 5A to 5D, the circuit MP[i,j] in FIG. 5E is different from the circuit MP[i,j] in FIG. The current output from the circuit MC does not flow to the wiring OLB[j], and the current output from the circuit MCr is configured so that it does not flow into wiring OL[j].

[0156] Therefore, the circuit MP[i,j] of FIG. 5E receives the second data z i (k-1) is "0", or For example, when the second data z i (k-1) When the value is "1", the circuit MP establishes a conductive state between the circuit MC and the wiring OL[j]. In this state, the circuit MCr and the wiring OLB[j] are electrically connected. Data z i (k-1) When is "0", the voltages output by the circuits MC and MCr are In order to prevent current from flowing to either wiring OL[j] or OLB[j], the circuit MP The circuit between MC and wiring OL[j] is in a non-conductive state, and the circuit between MCr and wiring OLB[j] is in a non-conductive state. Put into a non-conducting state.

[0157] The circuit MP[i,j] in FIG. 5E can be applied to the arithmetic circuit 110 to obtain, for example: is the first data w i (k-1) j (k) can take one of three values: "-1", "0", or "1". Take the second data z i (k-1) When the value is "0" or "1", the calculation is performed. The circuit MP[i,j] in FIG. 5E stores the first data w i (k-1) j ( k) is one of two values, "-1", "0", "1", for example, "-1" and "1". It can also operate in the case of two values, or two values ​​of "0" and "1". First data w i (k-1) j (k) is an analog value or a multi-bit (multi-value) digital value. For example, instead of "-1" you can use "negative analog value" and In addition, instead of "1" a "positive analog value" may be used. In this case, the circuit MC or The magnitude of the current flowing from the circuit MCr can also be calculated using the first data w i (k-1) j (k ) It becomes an analog value according to the absolute value of the value.

[0158] The circuit MP[i,j] shown in FIG. 5F includes the wiring OL[j] and the wiring OLB[i,j] in the same manner as in FIG. 5A. [j], the first data w i (k-1) j (k) and the second data z i (k-1) Depending on the product of The circuit MP[i,j] in FIG. 5F is a circuit that can output a current. For example, it can be applied to the arithmetic circuit 110 in FIG.

[0159] The circuit MP[i,j] of FIG. 5F includes a circuit MC and a circuit MCr, as well as a transistor Has MZ.

[0160] The first terminal of the transistor MZ is connected to the first terminal of the circuit MC and the first terminal of the circuit MCr. The second terminal of the transistor MZ is electrically connected to the wiring VL. The gate of the transistor MZ is electrically connected to the wiring XL[i].

[0161] For example, the wiring VL functions as a wiring that applies a constant voltage. It is preferable to determine this by the configuration of MP[i,j] and the arithmetic circuit 110. For example, VDD is a high level potential, VSS is a low level potential, and the ground potential. This can be done.

[0162] 5F is the same as the wiring WLS[i] in the arithmetic circuit 110 in FIG. The wiring WL[i] is electrically connected to the holding part HC and the holding part HCr. It is being done.

[0163] The wiring OL[j] is electrically connected to the second terminal of the circuit MC. OLB[j] is electrically connected to the second terminal of the circuit MCr.

[0164] The wiring IL[j] is electrically connected to the holding unit HC, and the wiring ILB[j] is electrically connected to the holding unit HC. It is electrically connected to the HCr part.

[0165] In the circuit MP[i,j] of FIG. 5F, the first data is stored in each of the holding unit HC and the holding unit HCr. Regarding the operation when maintaining a potential according to the data, the circuit MP[i,j] in FIG. 5A is Please refer to the description of the operation of holding the potential according to the first data.

[0166] In the circuit MP[i,j] of FIG. 5F, the circuit MC has a first terminal connected to a wiring VL. When a constant voltage is applied, a current corresponding to the potential held in the holding section HC is generated. The circuit MCr has a function of passing current between the first terminal and the second terminal of the circuit MC. When a constant voltage is applied to the first terminal of the The circuit MCr has a function of passing a current corresponding to the potential between the first and second terminals of the circuit MCr. The first data w is stored in the holding unit HC and the holding unit HCr of the circuit MP[i,j]. i (k -1) j (k) By maintaining a potential according to Determine the amount of current flowing between the first and second terminals of the circuit MCr. It should be noted that a constant voltage is applied to the first terminal of the circuit MC (circuit MCr) through the wiring VL. If not supplied, the circuit MC (circuit MCr) may, for example, It is also possible that no current flows between the first terminal and the second terminal.

[0167] For example, if the first data w of "1" is stored in each of the storage units HC and HCr, i (k-1) j (k) When the potential according to is maintained, a constant voltage is applied to the circuit MC from the wiring VL. By this, the circuit MC flows a predetermined current between the first terminal and the second terminal of the circuit MC. Therefore, a current flows between the circuit MC and the wiring OL. does not allow current to flow between the first and second terminals of the circuit MCr. No current flows between MCr and the wiring OLB. The first data w of "-1" for each of r i (k-1) j (k) The potential is maintained according to When the constant voltage given by the wiring VL is applied to the circuit MC, the circuit MCr , a predetermined current flows between the first terminal and the second terminal of the circuit MCr. At this time, the current flows between the first terminal of the circuit MC and the wiring OLB. Therefore, no current flows between the circuit MC and the wiring OL. For example, if the first data of "0" is stored in each of the holding parts HC and HCr, Ta w i (k-1) j (k)When the potential according to the circuit MC and the circuit MCr is maintained, Regardless of whether a constant voltage is applied to the wiring VL, the circuit MC is connected to the first terminal of the circuit MC. No current flows between the first and second terminals of the circuit MCr. In other words, no current flows between the circuit MC and the wiring OL, and no current flows between the circuit MCr and the wiring OL. No current flows between the lines OLB.

[0168] In the circuit MP[i,j] of FIG. 5F, the data stored in the storage units HC and HCr are , the first data w i (k-1) j (k) For a specific example of the potential according to P[i,j]. Also, in the circuit MP[i,j] of FIG. 5F, the holding unit H C, the holding unit HCr, like the circuit MP[i,j] in Fig. 5A, does not store potential but current and resistance values. The circuit MC and the circuit MCr have the function of storing information such as It may have a function.

[0169] The wiring XL[i] shown in FIG. 5F corresponds to the wiring XLS[i] in the arithmetic circuit 110 in FIG. The second data z input to the circuit MP[i,j] corresponds to i (k-1) is an example The potential and current of the wiring XL[i] are determined. The gate of MZ is connected to the second data z via the wiring XL[i]. i (k-1) Depending on The potential is input.

[0170] For example, the second data z i (k-1) Consider the case where takes either of the two values ​​"0" or "1". For example, the second data zi (k-1) If is "1", the wire XL[i] has a high level. At this time, the transistor MZ is turned on, so The circuit MP brings the wiring VL and the first terminal of the circuit MC into a conductive state, and the wiring VL and the circuit MC r and the first terminal of the second data z i (k-1) is "1" When this occurs, a constant voltage is applied to the circuit MC and the circuit MCr from the wiring VL. For example, the second data z i (k-1) When is "0", the wire XL[i] has a low level potential. In this case, the circuit MP is a non-transitory circuit between the circuit MC and the wiring OLB[j]. The second device is in a conductive state, and the second device is in a non-conductive state. Data z i (k-1) When is "0", the circuit MC and the circuit MCr are connected to the wiring VL. No constant voltage is given by these.

[0171] Here, for example, the first data w i (k-1) j (k) is "1", and the second data z i (k-1) When is "1", current flows between the circuit MC and the wiring OL, and the circuit MC As a result, no current flows between r and the wiring BLB. i ( k-1) j (k) is "-1", and the second data z i (k-1) If is "1", No current flows between circuit MC and wiring OL, and current flows between circuit MCr and wiring OLB. For example, the first data w i (k-1) j (k) is "0" , second data z i (k-1) is "1", the line between the circuit MC and the wiring OL, and the line between the circuit MC and the wiring OL As a result, no current flows between MCr and the wiring OLB. i (k-1) is "0", the first data w i (k-1) j (k) is "-1", "0 " or "1", the circuit MC and the wiring OL, and the circuit MCr and the wiring O As a result, no current flows between LB.

[0172] That is, the circuit MP[i,j] in FIG. 5F is, for example, As the first data w i (k-1) j (k) can take one of the three values ​​"-1", "0", or "1" and the second data z i (k-1) When takes two values, "0" and "1", In addition, similar to the circuit MP[i,j] in FIG. 5E, the circuit MP[ i,j] is the first data w i (k-1) j (k) is "-1", "0", or "1", Any two values, for example, "-1" and "1", or "0" and "1" It can also be operated in the case of the first data w i (k-1) j (k) Yes, Anna It may take a logarithmic value or a multi-bit (multi-value) digital value. "Negative analog value" instead of "-1" and "Positive analog value" instead of "1" In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr can be, for example, As for the first data, i (k-1) j (k) It becomes an analog value according to the absolute value of the value.

[0173] <Example of operation of an arithmetic circuit> Next, an example of the operation of the arithmetic circuit 110 in Fig. 2 will be described. As an example, the arithmetic circuit 110 shown in FIG. 8 is used.

[0174] The arithmetic circuit 110 in FIG. 8 is illustrated by focusing on the circuit located in the j-th column of the arithmetic circuit 110 in FIG. That is, the arithmetic circuit 110 of FIG. 8 is the same as the neural network shown in FIG. 1A. Neuron N in Network 100 j (k) neuron N1 (k-1 ) Neuron N m (k-1) Signal z1 from (k-1) ~z m (k-1) and weight Coefficient w1 (k-1) j (k) Or even w m (k-1) j (k) and the sum of products operation The calculation circuit 11 in FIG. The circuit MP included in the array unit ALP of 0 is assumed to be the circuit MP of FIG. 5A. do.

[0175] First, in the arithmetic circuit 110, the first Data w1 (k-1) j (k) Or even w m (k-1) j (k) The first data w is set. i (k-1) j (k) As a method of setting, the wiring WLS[1] A predetermined potential is input to the wiring WLS[m] in order, and the circuits MP[1,j] to MP[m , j] in order, and the holding part HC of the circuit MC included in the selected circuit MP, For the holding part HCr of the circuit MCr, from the circuit ILD, the wiring IL[j], the wiring ILB After the supply of the potential, the circuit W Deselecting each of the circuits MP[1,j] to MP[m,j] by LD By this, the holding of the circuit MC that each of the circuits MP[1,j] to MP[m,j] has The first data w1 is stored in the storage unit HC and the storage unit HCr of the circuit MCr. (k-1) j (k) Or even w m ( k-1) j (k) As an example, the potential corresponding to the first data w1 (k-1) j (k) Or even w m (k-1) j (k) When each of the values ​​is positive, In the hold part HC, enter a value corresponding to the positive value, and in the hold part HCr, enter a value corresponding to zero. On the other hand, the first data w1 (k-1)j (k) Or even w m (k-1) j (k ) If each of these takes a negative value, the value equivalent to zero is entered in the holding section HC. The holding unit HCr receives a value corresponding to the absolute value of the negative value.

[0176] Next, the wirings X1L[1] to X1L[m] and X2L[1 ] to wiring X2L[m], (k-1) ~z m (k-1) of As a specific example, the second data is supplied to the wiring X1L[i] and the wiring X2L[i]. z1 (k-1) The wiring X1L[i] and wiring X2L[i] are shown in FIG. This corresponds to the wiring XLS[i] of the arithmetic circuit 110.

[0177] Second data z1 input to each of the circuits MP[1,j] to MP[m,j] ( k-1) ~z m (k-1) According to the circuit MP[1,j] to the circuit MP[m,j], The conduction state between the circuit MC and the circuit MCr and the wiring OL[j] and the circuit OLB[j] is As a specific example, the circuit MP[i,j] determines the state of the second data z i (k-1) to In response, "the circuit MC and the wiring OL[j] become conductive, and the circuit MCr and the wiring OLB[j ] and "conduction occurs between the circuit MC and the wiring OLB[j], and The state in which the circuit MCr and the wiring OL[j] are electrically connected is shown. The state of each of the wirings OL[j] and OLB[j] is non-conductive. As an example, the second data z1 (k-1) If the value is positive, then wire X1L In [1], the circuit MC and the wiring OL[j] are in a conductive state, and the circuit MCr and the wiring Enter a value that allows the connection between the wire OLB[j] and the wire X2L. In [1], the circuit MC and the wiring OLB[j] are in a non-conductive state, and the circuit MCr A value that can cause a non-conduction state between the second data line and the wiring OL[j] is input. Data z1 (k-1) If the value is negative, the wiring X1L[1] has a circuit MC and wiring OLB[j] are in a conductive state, and Then, input a value that allows the circuit MC and the wiring OL[j] are in a non-conductive state, and the circuit MCr and the wiring OLB[j] are in a non-conductive state. The second data z1 is input as a value that allows the connection between the first and second data z1 to be in a non-conductive state. (k-1) to When the value of zero is taken, the wiring X1L[1] has the circuit MC and the wiring OLB[j]. and the circuit MCr and the wiring OL[j] are in a non-conductive state. Then, for the wiring X2L[1], input the value that can be used to connect the circuit MC and the wiring OL[j ] and the circuit MCr and the wiring OLB[j] are in a non-conductive state. Enter the value that can be.

[0178] The second data z input to the circuit MP[i,j] i (k-1) Depending on the circuit MP[i, the circuit MC and the circuit MCr included in the wiring OL[j] and the circuit OLB[j] By determining the conductive state or non-conductive state between the circuit MC and the circuit MCr, Current is input and output between the wiring OL[j] and the wiring OLB[j]. The amount of flow is the first data w set in the circuit MP[i,j]. i (k-1) j (k) and / or is the second data z i (k-1) It depends on:

[0179] For example, in the circuit MP[i,j], the wiring OL[j] is connected to the circuit MC or the circuit MCr. Let I[i,j] be the current flowing through the wiring OLB[j] to the circuit MC or the circuit MCr. The current flowing through the B [i,j]. Then, the current flows from the circuit ACTF[j] to the wiring OL[j]. The current flowing through the out [j], and the current flowing from wiring OLB[j] to circuit ACTF[j] I Bout If [j], then I out [j] and I Bout [j] can be expressed by the following formula: This can be done.

[0180]

number

[0181] In the circuit MP[i,j], as an example, the first data w i (k-1) j (k) "+ 1", the circuit MC outputs I(+1) and the circuit MCr outputs I(-1). The first data w i (k-1) j (k) When is "-1", the circuit MC is I(-1 ) and the circuit MCr outputs I(+1), and the first data w i (k-1) j (k) When is "0", the circuit MC emits I(-1) and the circuit MCr emits I(-1). shall be discharged.

[0182] Furthermore, the circuit MP[i,j] receives the second data z i (k-1) When is "+1", Conduction occurs between the circuit MC and the wiring OL[j], and conduction occurs between the circuit MCr and the wiring OLB[j]. Conduction occurs, and there is no conduction between the circuit MC and the wiring OLB[j], and there is no conduction between the circuit MCr and the wiring OL [j] is in a non-conductive state, and the second data z i (k-1) is "-1" When this happens, "there is conduction between the circuit MC and the wiring OLB[j], and the circuit MCr and the wiring OL[j ] becomes conductive, and the circuit MC and the wiring OL[j] become non-conductive, and the circuit MCr and The second data z i (k-1) is "0 "When ", "between circuit MC and wiring OL[j], and between circuit MC and wiring OLB[j] and there is no conduction between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OL[j]. B[j] and the circuit MCr and the wiring OL[j], and the circuit MC The state between r and OLB[j] is assumed to be "non-conductive."

[0183] At this time, in the circuit MP[i,j], the wiring OL[j] is connected to the circuit MC or the circuit MC The current I[i,j] flowing through r and the current I[i,j] flowing from wiring OLB[j] to circuit MC or circuit MCr The current I B[i,j] is as shown in the table below. In some cases, I(- The circuit MP[i,j] may be configured so that the current amount of 1) is 0. i,j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OL[j]. Similarly, the current I B [i,j] flows from the circuit MC or the circuit MCr to the wiring OLB[j]. It may also be an electric current.

[0184] [Table 1]

[0185] Then, I flowing from each of the wiring OL[j] and wiring OLB[j] out [ j] and I Bout [j] is input to the circuit ACTF[j]. , Circuit ACTF[j] is, for example, I out [j] and I Bout [j] comparison The circuit ACTF[j] performs, for example, the following operations depending on the result of the comparison: N j (k) is the signal z sent to the (k+1)th layer neuron. j (k) Output.

[0186] As an example, the arithmetic circuit 110 of FIG. j (k) is entered into Neuron N1 (k-1) Neuron N m (k-1) Signal z1 from (k-1) ~ z m (k-1) and weighting factor w1 (k-1) j (k) Or even w m (k-1)j (k) And, It is possible to perform a product-sum operation and a calculation of an activation function using the result of the product-sum operation. In addition, in the array part ALP of the arithmetic circuit of FIG. 8, by providing n columns of circuits MP, the arithmetic circuit of FIG. In other words, the arithmetic circuit 110 of FIG. Ron N1 (k) Neuron N n (k) and the sum of products in each of the The activation function can be calculated using the result of the calculation at the same time.

[0187] <<Example of changing circuits included in the arithmetic circuit>> The above-mentioned array part ALP, circuit ILD, circuit WLD, circuit XLD, circuit AFP, circuit Some or all of the transistors included in each of the MP, etc., are, for example, For example, it is desirable to have a low off-state current. For example, in the case of such a transistor, the function of holding the charge stored in the capacitance element is The transistor having the above structure is preferably an OS transistor. When an OS transistor is used as a transistor, the OS transistor may be the same as that described in the third embodiment. However, one embodiment of the present invention is a transistor structure in which Not limited to.

[0188] Also, the array part ALP, the circuit ILD, the circuit WLD, the circuit XLD, the circuit AFP, the circuit MP The transistors included in the above are, in addition to OS transistors, for example, channel-type It can also be used as a transistor containing silicon in the compound region (hereinafter referred to as a Si transistor). As the silicon, for example, single crystal silicon or hydrogenated amorphous silicon can be used. The OS transistor may be made of silicon, microcrystalline silicon, polycrystalline silicon, or the like. As for transistors other than Si transistors, for example, semiconductors such as Ge are used. Layered transistors, ZnSe, CdS, GaAs, InP, GaN, SiGe, etc. Transistors with compound semiconductor active layers, transistors with carbon nanotubes active layers A transistor having an organic semiconductor as an active layer, or the like can be used.

[0189] In the metal oxide semiconductor layer of the OS transistor, a metal oxide containing indium In oxides containing zinc (e.g., In oxide), Although n-type semiconductors have been successfully fabricated, p-type semiconductors are difficult to fabricate due to mobility and reliability issues. Therefore, the arithmetic circuit 110, the arithmetic circuit 120, and the arithmetic circuit 130 are n circuits included in LP, circuit ILD, circuit WLD, circuit XLD, circuit AFP, circuit MP, etc. An OS transistor is used as a p-channel transistor. A configuration using Si transistors may also be used.

[0190] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0191] (Embodiment 2) In this embodiment, a specific configuration example of the circuit MP described in the first embodiment will be described. do.

[0192] In the first embodiment, the reference numerals of the circuits MP are denoted by [1,1 ], [i,j], [m,n], etc. are added, but in this embodiment, unless otherwise specified, The notation [1,1], [i,j], [m,n], etc. is omitted for the symbols of the MP.

[0193] <Configuration example 1> First, an example of a circuit configuration that can be applied to the circuit MP of FIG. 5A will be described. The circuit MP is an example of the configuration of the circuit MP of FIG. 5A, and is a circuit included in the circuit MP of FIG. 9A. The circuit MC includes, for example, transistors M1 to M4, a capacitance element C1, For example, the holding unit HC is formed by the transistor M1 and the capacitance element C1. It is composed of:

[0194] The transistors M1 to M4 shown in FIG. 9A are, for example, It is an n-channel transistor with a multi-gate structure that has gates above and below the panel. Each of the transistors M1 to M4 has a first gate and a second gate. However, in this specification and the like, for the sake of convenience, the first gate will be referred to as the gate (front gate) as an example. The first gate is sometimes referred to as the "first gate." The second gate is sometimes referred to as the "back gate." However, the first gate and the second gate can be interchanged. In the above, the term "gate" is replaced with the term "back gate." Similarly, the term "backgate" can be interchanged with the term "gate." A specific example is "the gate is electrically connected to the first wiring, and the The connection configuration in which "the back gate is electrically connected to the second wiring" is The gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring. can be replaced as a configuration.

[0195] Furthermore, the semiconductor device of one embodiment of the present invention can be used without depending on the connection structure of the back gate of the transistor. In each of the transistors M1 to M4 shown in FIG. The back gate is shown, but the connection configuration of the back gate is not shown. The electrical connection destination of the back gate can be determined at the design stage. In a transistor having a gate, in order to increase the on-current of the transistor, The gate and the back gate may be electrically connected. In each of the transistors M1 to M4, the gate and the back gate are electrically connected to each other. For example, in a transistor having a back gate, the transistor In order to change the threshold voltage of the transistor or to reduce the off-state current of the transistor, For this purpose, wiring electrically connected to an external circuit or the like is provided, and the external circuit or the like is used to A potential may be applied to the back gate of the transistor. rather than transistors described elsewhere in the specification or illustrated in other drawings. The same applies to the transistors.

[0196] In addition, a semiconductor device according to one embodiment of the present invention may include a transistor having a structure For example, the transistors M1 to M4 shown in FIG. As shown in FIG. 9C, the transistors M1r to M4r do not have back gates. In other words, a transistor with a single gate structure may be used. Some of the transistors have a back gate, and some of the transistors have a back gate. It is also possible to have a configuration without a lock gate. as well as transistors described elsewhere in the specification or illustrated in other drawings. The same applies to the transistors.

[0197] In this specification and the like, transistors having various structures are used as transistors. Therefore, there is no limitation on the type of transistor to be used. Examples include transistors with single crystal silicon, or transistors with amorphous silicon, polycrystalline silicon, etc. Silicon, microcrystalline (also called microcrystal, nanocrystal, or semi-amorphous) A transistor having a non-single-crystal semiconductor film, such as a silicon nitride film, can be used. Alternatively, thin film transistors (TFTs) made from these semiconductors can be used. There are various advantages to using TFTs. For example, it is Since it can be manufactured at a very low temperature, it is possible to reduce manufacturing costs and increase the size of manufacturing equipment. Since the manufacturing equipment can be made larger, it is possible to manufacture on large substrates. Since a large number of display devices can be manufactured, they can be manufactured at low cost. Therefore, a substrate having low heat resistance can be used. Alternatively, a transistor on a light-transmitting substrate can be used to manufacture a display element. It is possible to control the light transmission. Also, because the film thickness of the transistor is thin, A part of the film that forms the capacitor can transmit light, which improves the aperture ratio. It is possible.

[0198] An example of a transistor is a compound semiconductor (e.g., SiGe, GaAs, etc.). ), or oxide semiconductors (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, I n-Sn-O(ITO), Sn-O, Ti-O, Al-Zn-Sn-O(AZTO), I A transistor having a material such as n-Sn-Zn-O can be used. These compound semiconductors or thin film transistors made by thinning these oxide semiconductors These can be used to lower the manufacturing temperature, for example, As a result, it is possible to manufacture a resistor on a substrate with low heat resistance, such as a plastic The transistor can be formed directly on a substrate or a film substrate. Compound semiconductors or oxide semiconductors are used not only for the channel portion of transistors but also for For example, these compound semiconductors or oxide semiconductors can be used for other purposes. It can be used as a wiring, a resistor element, a pixel electrode, or a light-transmitting electrode. These can be deposited or formed simultaneously with the transistor, thereby reducing costs.

[0199] An example of a transistor is a transistor formed by an ink-jet method or a printing method. These can be used for manufacturing at room temperature, manufacturing at low vacuum, or can be manufactured on a large substrate. Therefore, it can be manufactured without using a mask (reticle). This allows the transistor layout to be easily changed. Alternatively, it can be manufactured without using resist, which reduces material costs and the number of processes. Or, since it is possible to apply the film only to the necessary parts, after forming the film on the entire surface, This method wastes less material and is less costly than the conventional etching method.

[0200] An example of a transistor is a transistor having an organic semiconductor or a carbon nanotube. This allows transistors to be mounted on a flexible substrate. Transistors using organic semiconductors and carbon nanotubes can be formed. The device using this can be made shock resistant.

[0201] Note that transistors with various other structures can also be used. For example, transistors include MOS transistors, junction transistors, and bipolar transistors. A MOS transistor can be used as the transistor. By using this, the size of the transistor can be reduced. It is possible to mount a bipolar transistor as a transistor. This allows a large current to flow, making it possible to operate the circuit at high speed. It is also possible to combine MOS transistors and bipolar transistors on the same substrate. This can achieve low power consumption, miniaturization, high-speed operation, etc. can.

[0202] An example of a transistor is a structure in which gate electrodes are arranged above and below an active layer. The transistor can be applied to a structure in which gate electrodes are arranged above and below the active layer. This results in a circuit configuration in which multiple transistors are connected in parallel. Since the channel forming region increases, the current value can be increased. The structure in which gate electrodes are arranged above and below makes it easier for a depletion layer to form. , the S value can be improved.

[0203] An example of a transistor is a structure in which a gate electrode is disposed on an active layer. A structure in which a gate electrode is placed under an active layer, a normal staggered structure, an inverted staggered structure, a channel A structure in which the region is divided into multiple regions, a structure in which the active layers are connected in parallel, or a structure in which the active layers are connected in series Alternatively, a transistor having a structure such as a pre-transistor may be used. NA type, FIN type, TRI-GATE type, top gate type, bottom gate type, double gate type (gates are placed above and below the channel), etc. A variety of configurations can be used.

[0204] An example of a transistor is a transistor in which a source electrode or a drain electrode is formed in the active layer (or a part thereof). A transistor with an overlapping active layer (or its equivalent) can be used. By using a structure in which the source electrode and drain electrode overlap with part of the active layer, This can prevent the operation from becoming unstable due to accumulation of electric charges.

[0205] As an example of a transistor, a structure provided with an LDD region can be applied. By providing a region, the off-state current can be reduced or the withstand voltage of the transistor can be improved (reliability can be improved). Alternatively, by providing an LDD region, it is possible to , even if the voltage between the drain and source changes, the drain current does not change much, and the slope is A flat voltage-current characteristic can be obtained.

[0206] For example, in this specification and the like, transistors can be formed using various substrates. The type of substrate is not limited to a specific one. Conductor substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrate, sapphire glass substrate, metal substrate, stainless steel substrate, stainless Substrate with less steel foil, tungsten substrate, tungsten foil Substrates, flexible substrates, laminated films, paper containing fibrous materials, base film, etc. Examples of glass substrates include barium borosilicate glass and aluminoborosilicate glass. Glass or soda lime glass. Flexible substrates, laminating films, base film Examples of films include polyethylene terephthalate. Polyethylene naphthalate (PET), Polyethersulfone (PES) ), and polytetrafluoroethylene (PTFE) are typical plastics. For example, synthetic resin such as acrylic resin is used. Examples include polyethylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and the like. In particular, transistors are manufactured using semiconductor substrates, single crystal substrates, or SOI substrates. By manufacturing the capacitors, there is little variation in characteristics, size, or shape, and current capacity is This allows for the production of high-power, small-sized transistors. By configuring a circuit using a capacitor, it is possible to reduce the power consumption of the circuit or to increase the integration density of the circuit. Cut.

[0207] In addition, a flexible substrate is used as the substrate, and a transistor is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate and the transistor. After a semiconductor device is partially or completely completed, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be formed of an inorganic film such as a tungsten film and a silicon oxide film. It uses a laminated film structure or a structure in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0208] That is, a transistor is formed using one substrate, and then a transistor is formed on another substrate. The transistor may be transposed and placed on another substrate. For example, in addition to the substrate on which the above-mentioned transistors can be formed, a paper substrate, a cellophane substrate, etc. Fan board, aramid film board, polyimide film board, stone board, wood board, cloth Substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), There are leather substrates, rubber substrates, etc. By using these substrates, Formation of transistors, formation of low power consumption transistors, manufacturing of durable devices, heat resistance It is possible to provide a lighter, thinner, or more flexible device.

[0209] All circuits required to realize a given function are mounted on the same substrate (e.g., glass It can be formed on a substrate such as a silicon substrate, a plastic substrate, a single crystal substrate, or an SOI substrate. This reduces the cost by reducing the number of components, or reduces the number of connections to circuit components. This can improve reliability.

[0210] It is possible that not all of the circuits required to realize a given function are formed on the same substrate. In other words, part of the circuitry required to achieve a given function can be formed on a certain substrate. Another part of the circuitry required to realize a given function is formed on a different substrate. For example, some of the circuits required to realize a given function can be Another part of the circuitry required to realize a specific function is formed on the single crystal substrate. It can be formed on a substrate (or SOI substrate) and realizes a predetermined function. The single crystal substrate (also called an IC chip) on which another part of the circuitry required for (Chip On Glass) connects to the glass substrate and Alternatively, the IC chip can be mounted on a TAB (Tape Au tomated Bonding), COF(Chip On Film), SMT(S Surface Mount Technology) or a printed circuit board. In this way, part of the circuit is formed on the same substrate as the pixel section. This reduces the number of components, thereby reducing costs, and This reduces the number of circuits, which improves reliability. Also, circuits with high drive frequencies often consume a lot of power. Therefore, such a circuit is formed on a substrate (for example, a single crystal substrate) separate from the pixel section, and By using this IC chip, it is possible to prevent an increase in power consumption. Cut.

[0211] In the circuit MP of FIG. 9A, the first terminal of the transistor M1 is electrically connected to the line IL. The second terminal of the transistor M1 is connected to the first terminal of the capacitance element C1 and the second terminal of the transistor M2. The gate of the transistor M1 is electrically connected to the wiring WL. The first terminal of the transistor M2 is connected to the second terminal of the capacitance element C1 and the line VL The second terminal of the transistor M2 is electrically connected to the first terminal of the transistor M3. The first terminal of the transistor M3 is electrically connected to the first terminal of the transistor M4. The second terminal of the transistor M3 is electrically connected to the wiring OL. The second terminal of the transistor M4 is electrically connected to the wiring OLB. The gate of the transistor M4 is electrically connected to the wiring X2L. As shown, the second terminal of the capacitance element C1 is electrically connected to another wiring VLm, not to the wiring VL. Similarly, the second terminal of the capacitance element C1r may be connected to the line VLr instead of the line VLr. 9A and other wirings. In the circuit diagram of the drawing, the second terminal of the capacitance element C1 is connected to another wiring VL instead of the wiring VL. 9B, for example, the wiring VL and the wiring VLr are regarded as one and the same wiring, and the wiring VLm and the wiring VLmr are regarded as one and the same wiring. Alternatively, a single wiring may be used (not shown).

[0212] In the holding unit HC shown in FIG. 9A, the second terminal of the transistor M1 and the capacitance element C The electrical connection point between the first terminal of transistor M1 and the gate of transistor M2 is referred to as node nd1. do.

[0213] As described in the first embodiment, the holding unit HC holds, for example, The circuit MC shown in FIG. 9A has a function of holding the potential. When the transistor M1 is turned on, the potential is input from the wiring IL. , is written to the capacitance element C1, and then the transistor M1 is turned off. This allows the potential of the node nd1 to be maintained as a potential corresponding to the first data. can.

[0214] In addition, the transistor M1 holds the potential of the node nd1 for a long time, and therefore the off-state current is small. It is preferable to use a transistor that does not have a low off-state current. For example, an OS transistor can be used. A transistor having a gate is applied, and a low level potential is applied to the back gate to obtain a threshold voltage. Alternatively, the voltage may be shifted to the positive side to reduce the off-state current.

[0215] The circuit MCr has almost the same circuit configuration as the circuit MC. The circuit elements that have the same characteristics are marked with "r" to distinguish them from the circuit elements that have the same characteristics as the circuit MC. are.

[0216] The circuit MCr has a different connection configuration from the circuit MC. The second terminal of the transistor M4r is electrically connected to the wiring OLB instead of the wiring OL. The second terminal of the transistor M is electrically connected to the wiring OL, not to the wiring OLB. The first terminal of No. 2 is electrically connected to the wiring VLr.

[0217] In the operation example described later, in order to simply explain the current flowing in and out of the circuit MP, The ends of the wiring OL shown in 9A are the nodes ina and outa, and the ends of the wiring OLB are the nodes Let node inb and node outb.

[0218] The wiring VL functions as a wiring for supplying a constant voltage, for example. The transistor M2 or the transistor M2r is an n-channel transistor. In this case, for example, VSS, which is a low-level potential, ground potential, or other low-level potentials may be used. The wiring VLr is a wiring for supplying a constant voltage, similar to the wiring VL. The constant voltage may be VSS, which is a low level potential, or ground potential. In this case, the circuits ACT of the arithmetic circuits 110, 120, and 130 can be 3A to 3E, 4A to 4D, and 4F as circuits F[1] to ACTF[n]. If applied, it is electrically connected to the circuits ACTF[1] to ACTF[n]. The constant voltage given by the wiring VAL is a potential higher than the potential given by the wiring VL and the wiring VLr. , for example, VDD.

[0219] Furthermore, the constant voltage supplied by the line VLr may be different from the constant voltage supplied by the line VL. For example, when the constant voltages applied by the wiring VL and the wiring VLr are approximately equal, As shown in the circuit MP of FIG. 10A, the wiring VLr can be the same wiring as the wiring VL. .

[0220] The configuration of the circuit MP in FIG. 9A can be changed depending on the situation. For example, 10B, the transistor M2, the transistor M2r, and the transistor M3 of the circuit MP of FIG. 9A are Transistor M3, transistor M3r, transistor M4, and transistor M4r, respectively. The transistors M2p, M2pr, and M2p are p-channel transistors. The transistors M3p, M3pr, M4p, and M4pr are In particular, the transistors M2 and M2r may be replaced with p-channel transistors. When replacing it with a resistor, the constant voltage given by the wiring VL is set to VDD, which is the high level potential. In addition to this case, the arithmetic circuit 110, the arithmetic circuit 120, and the arithmetic circuit 130 are preferably 3A to 3E, 4A to 4E, and 4F. D, when applying FIG. 4F, the circuits ACTF[1] to ACTF[n] are electrically The constant voltage provided by the connected wiring VAL is preferably the ground potential or VSS. In this way, when the potential of the wiring is changed, the direction of the current flow also changes. do.

[0221] Similarly, the transistor M1 is replaced with a p-channel transistor. 10B, the transistor M2 and the transistor M2 r, transistor M3, transistor M3r, transistor M4, transistor M4r The transistors M2p and M2pr are p-channel transistors, respectively. , transistor M3p, transistor M3pr, transistor M4p, transistor M4 pr, but the transistors M2, M2r, and M3 of the circuit MP in FIG. The transistor M3, the transistor M3r, the transistor M4, and the transistor M4r are selected from the group consisting of One or more of the transistors may be replaced with a p-channel transistor.

[0222] 11A, for example, the transistors M3 and M3r in the circuit MP of FIG. , transistor M4, and transistor M4r are connected to analog switches A3 and A4, respectively. The switch A4 may be replaced with an analog switch A3r or an analog switch A4r. In addition, in FIG. 11A, analog switches A3, A4, and A5 are shown. Wiring X1LB and wiring X2LB are also shown to operate A3r and analog switch A4r. The wire X1LB is electrically connected to the analog switch A3 and analog switch A3r. The wire X2LB is electrically connected to the analog switch A4 and analog switch A4r. The inverted signal of the signal input to the wire X1L is input to the wire X1LB. The inverted signal of the signal input to the line X2L is input to the line X2LB. As shown in FIG. 1B, the wires X1L and X2L are designated as wires XL, and the wires X1LB and X2L are designated as wires XL. B may be grouped together as wiring XLB. Analog switch A4, analog switch A3r, and analog switch A4r are n-channel Alternatively, a CMOS configuration using a n-channel transistor and a p-channel transistor may be used.

[0223] 12A, for example, the transistor M4 of the circuit MP of FIG. 9A, The transistors M4r and M4p are p-channel transistors, respectively. In the circuit MP of FIG. 12A, the transistor M3 may be replaced by the transistor M4pr. The gate is electrically connected to the gate of the transistor M4p and the wiring XL. L corresponds to the two wirings X1L and X2L in FIG. 9A combined into one wiring. The polarities of the transistors M3 and M4p are opposite to each other. The gates of the transistors M3 and M4p are electrically connected to the wiring XL. Therefore, by applying a predetermined potential to the wiring XL, the transistors M3 and M4 are turned on. One of the transistors M4p is turned on, and the other of the transistors M3 and M4p is turned on. It can be turned off.

[0224] 12B, for example, the circuit MP of FIG. 9A may include a transistor M2m and a transistor The first transistor M2mr is added, and the first transistor M4 and the first transistor M4r are added. The electrical connection destination of the terminal may be changed. The first terminal of the capacitor C1, the first terminal of the transistor M2, and the wiring V L, and the second terminal of the transistor M2m is electrically connected to the first terminal of the transistor M4. In the circuit MP of FIG. 9A, the second terminal of the transistor M2 is electrically connected to the The terminal was electrically connected to the first terminal of transistor M4, but the circuit MP In this example, the second terminal of transistor M2 is electrically connected to the first terminal of transistor M4. In the circuit MP shown in FIG. 12B, the currents flowing through the transistors M3 and M4 are This is determined by the potential of the gates of the transistors M2 and M2m. For example, the size of the transistor M2 and the transistor M2m, e.g., the channel length or It is preferable that the channel widths are equal to each other. In addition, the current flowing through transistors M3 and M4 can be reduced. It may be possible to align the currents that are being transmitted.

[0225] <<Example of operation>> Next, an example of the operation of the circuit MP shown in FIG. 9A will be described.

[0226] 13A to 13C, 14A to 14C, and 15A to 15C are diagrams illustrating the circuit MP. 10 is a timing chart showing an example of operation, and shows wiring IL, wiring ILB, and wiring WL. , and fluctuations in the potentials of the wiring X1L, the wiring X2L, the node nd1, and the node nd1r. 13A to 13C, 14A to 14C, and 15A to 15C. The high indicates a high level potential, and the low indicates a low level potential. The amount of current output to node outa (or from node outa to wiring OL) is I OL Also, from wiring OLB to node outb (or from node outb to wiring The amount of current output to the OLB is I OLB 13A to 13C and 14A. In the timing charts shown in FIGS. 14A to 14C and 15A to 15C, the amount of current I OL , I O LB The change in the

[0227] In this example, the constant voltages applied by the lines VL and VLr are VSS (low level potential). In this case, current flows from the wiring VAL to the wiring VL via the wiring OL. Similarly, when a current flows from the wiring VAL to the wiring VLr via the wiring OLB, become.

[0228] In this specification and the like, the terms "low level potential" and "high level potential" are used in particular It does not mean a fixed potential, and the specific potential may be different for different wirings. For example, the low level potential and the high level potential held at the node nd1 and the node nd1r are These are potentials different from the low-level potential and high-level potential applied to the wiring X1L and wiring X2L. may be.

[0229] Before explaining the operation example, the weighting coefficients held by the circuit MP are defined as follows: A high level potential is held at the node nd1 of C, and a low level potential is held at the node nd1r of the holding unit HCr. When this is done, the circuit MP holds a weighting factor of "+1". A low level potential is held at the node nd1 of the HC, and a high level potential is held at the node nd1r of the holding unit HCr. When the weighting coefficient is held, the circuit MP is assumed to hold "-1". A low level potential is applied to the node nd1 of the holding unit HC, and a low level potential is applied to the node nd1r of the holding unit HCr. When this is held, the circuit MP holds "0" as the weighting coefficient. The high level potential held at the nodes nd1 and nd1r may be, for example, VDD or , the potential can be set to be slightly lower than VDD, and the potentials at the nodes nd1 and nd1r are maintained. The low level potential to be maintained can be, for example, VSS. It is also possible to use analog values. In that case, for example, a "positive analog" value can be used as a weighting coefficient. In the case of "value", a high level analog potential is applied to the node nd1 of the holding unit HC, and A low level potential is held at node nd1r. A weighting coefficient of "negative analog value" is used. In this case, for example, the node nd1 of the holding unit HC is at a low level potential, and the node n A high level analog potential is held in d1r. When the weighting coefficient is "0", For example, a low level potential is applied to the node nd1 of the holding unit HC, and a low level potential is applied to the node nd1r of the holding unit HCr. The level potential is maintained.

[0230] In addition, the neuron signal (calculated value) input to the circuit MP is, for example, as follows: When a high-level potential is applied to the wiring X1L and a low-level potential is applied to the wiring X2L, The circuit MP receives a neuron signal of "+1". When a high-level potential is applied to the wire X2L, the circuit MP has a neuron The signal "-1" is input to the wire X1L and the wire X2L. When the Bell potential is applied, the circuit MP receives a "0" as a neuron signal. It shall be possible.

[0231] In this specification and the like, the transistors M2 and M2r are If there is no such case, the on-state includes the case where the device finally operates in the saturated region. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are , including when it is properly biased to a voltage in the range in which it operates in the saturation region. However, one embodiment of the present invention is not limited to this. Therefore, the transistors M2 and M2r may operate in the linear region. When analog values ​​are used, the transistors M2, M2 r may operate in both the linear region and the saturation region.

[0232] In this specification and the like, the transistors M1, M3, and M 4. Transistor M1r, transistor M3r, transistor M4r, unless otherwise specified, In the case where the on-state is not reached, this includes the case where the device ultimately operates in the linear region. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are as follows: This includes the case where the device is properly biased to a voltage within the range in which it operates in the linear region.

[0233] Below, for each combination of the weighting coefficients and the neuron's signals, An example of the operation of the circuit MP will now be described.

[0234] [Condition 1] First, as an example, the weight coefficient w is "0" and the neuron input to the circuit MP is Consider the case where the signal (calculated value) of the circuit M is "+1". 1 is a timing chart of P.

[0235] Between time T1 and time T2, the wiring IL and the wiring ILB each have a holding The potential of the node nd1 of the holding unit HC and the potential of the node nd1r of the holding unit HCr are used to initialize the potential of the node nd1 of the holding unit HCr. Initialization potential V ini In FIG. 13A, V ini is a low level potential Although the potential is shown as higher than the high-level potential and lower than the high-level potential, V ini is a low level potential Alternatively, the potential may be set to a potential lower than the high-level potential or a potential higher than the high-level potential. i ni may be set to the same potential as the low level potential or the same potential as the high level potential. In addition, the initialization potential V given to each of the wiring IL and the wiring ILB ini are different from each other Note that the wirings IL and ILB may be supplied with an initialization potential V ini of In other words, there is no need to set a period between time T1 and time T2. .

[0236] In addition, a low level potential is input to the wiring WL between time T1 and time T2. Therefore, the transistor M1 and the transistor M1r are both in an off state. It is.

[0237] In addition, between time T1 and time T2, The potentials of the nodes nd1 and nd The potential of each of 1r is higher than the low level potential, V ini The potential is lower than .

[0238] A low-level potential is input to the wiring X1L and the wiring X2L. , transistor M3, transistor M4, transistor M3r, and transistor M4r are both in the off state.

[0239] Next, between time T2 and time T3, a high-level potential is input to the wiring WL. As a result, the transistors M1 and M1r are turned on. , the line IL and the node nd1 are in a conductive state, and the line ILB and the node nd1r are in a conductive state. Therefore, the potentials of the nodes nd1 and nd1r are V ini The potentials of the nodes nd1 and nd1r are set to the initialization potential V ini So In other words, there is no need to provide a period from time T2 to time T3.

[0240] Between time T3 and time T4, the wiring IL and the wiring ILB are at low levels. A bell potential is applied to the wiring WL, and "0" is input as the weighting coefficient w. Since a high level potential continues to be input from before and "0" is input as the weighting coefficient w, Therefore, the transistors M1 and M1r are in the ON state. The potentials of the node nd1 and the node nd1r are both at low level potential.

[0241] Between time T4 and time T5, a low level potential is input to the wiring WL. As a result, the transistors M1 and M1r are turned off, and the capacitance element The capacitance elements C1 and C1r of the nodes nd1 and nd1r are The respective potentials are maintained.

[0242] The operation from time T1 to time T5 sets the weighting coefficient of the circuit MP to "0". can be.

[0243] By the operations up to this point, the gates of the transistors M2 and M2r The potentials of the transistors M2 and M2r become low level potentials. The potential of the first terminal of the transistor M2 is VSS, so that of the transistor M2r Each is in the off state.

[0244] Between time T5 and time T6, for example, the wiring IL and the wiring ILB are initialized. Potential V ini is input. Note that this operation is not particularly necessary, so wiring I L and wiring ILB are initialized to a potential V ini In other words, from time T5 It is not necessary to provide a period until time T6. In this case, different potentials may be input.

[0245] After time T6, the signal “+1” of the neuron is input to the circuit MP via the wire X A high level potential is input to wiring X1L and a low level potential is input to wiring X2L. The transistors M3 and M3r are turned on, and the transistors M4 and M5 are turned on. The transistors M4r and M4r are turned off. Conduction is established between the wiring OL, and conduction is established between the circuit MCr and the wiring OLB.

[0246] At this time, in the circuit MC, the transistor M2 is in the off state, so that the wiring O No current flows from L to the wiring VL. In other words, the output from node outa of wiring OL The current I OL does not change before and after time T6. Since the transistor M2r is in the off state, a current flows from the wiring OLB to the wiring VLr. does not flow. In other words, the current I output from node outb of wiring OLB OLB Also, time There is no change before and after T6.

[0247] By the way, this condition is that the weight coefficient is set to "0" and the neuron signal input to the circuit MP is Since we set "+1", by using equation (1.1), the product of the weight coefficient and the neuron signal is The result of the product of the weight coefficient and the neuron signal being "0" is that the circuit MP In operation, from time T6 onwards, the current I OL and current I OLB If each of these does not change, This corresponds to the case.

[0248] Once the weighting coefficient w is input, the value is not updated and only the calculated value is changed. In this case, the weighting coefficient w does not need to be updated. Since it is necessary to update the weight coefficient w less, power consumption can be reduced. In order to do this, it is necessary to hold the weight coefficient w for a long period of time. By using a capacitor, it is possible to maintain the weighting factor w for a long period of time by taking advantage of the low off-state current. This becomes:

[0249] [Condition 2] Next, as an example, the weight coefficient w is "+1" and the neuron input to the circuit MP is Consider the case where the signal (calculated value) of the circuit M is "+1". 1 is a timing chart of P.

[0250] Regarding the operation from time T1 to time T3, from time T1 to time T3 under condition 1 Since the operation is the same as that between time T1 and time T3 in Condition 1, please refer to the explanation of the operation between time T1 and time T3 in Condition 1. To pour drinks.

[0251] Between time T3 and time T4, a high level potential is applied to the wiring IL and a low level potential is applied to the wiring ILB. A bell potential is applied, and a weighting coefficient w is set to "1." Since a high level potential continues to be input from before and "1" is input as the weighting coefficient w, Therefore, the transistor M1 and the transistor M1r are in the ON state. The potential of the node nd1 becomes a high level potential, and the potential of the node nd1r becomes a low level potential.

[0252] Between time T4 and time T5, a low level potential is input to the wiring WL. As a result, the transistors M1 and M1r are turned off, and The capacitance element C1 and the capacitance element C1r are connected to the node nd1 and the node nd1 The potential of each of the electrodes r is maintained.

[0253] The operation from time T1 to time T5 sets the weighting coefficient of circuit MP to "+1". will be done.

[0254] By the operation up to this point, the potential of the gate of transistor M2 is at a high level potential, The potential of the gate of transistor M2r is at a low level. The potential of the first terminal of each of the transistors M2r and M2r is VSS, so the transistor M2 is turned on. In the on state, the transistor M2r is in the off state.

[0255] Regarding the operation from time T5 to time T6, from time T5 to time T6 under condition 1 Since the operation is the same as that between time T5 and time T6 in Condition 1, please refer to the explanation of the operation between time T5 and time T6 in Condition 1. To pour drinks.

[0256] After time T6, the signal “+1” of the neuron is input to the circuit MP via the wire X A high level potential is input to wiring X1L and a low level potential is input to wiring X2L. The transistors M3 and M3r are turned on, and the transistors M4 and M5 are turned on. The transistors M4r and M4r are turned off. Conduction is established between the wiring OL, and conduction is established between the circuit MCr and the wiring OLB.

[0257] At this time, in the circuit MC, the transistor M2 is in the on state, so that the wiring O A current flows from L to the wiring VL. In other words, the current is output from the node outa of the wiring OL. The current I OL increases after time T6 (in FIG. 13B, the current I OL The increase in On the other hand, in the circuit MCr, the transistor M2r is in the off state. Therefore, no current flows between the wiring OLB and the wiring VLr. The current I output from node outb of LB OLB does not change before and after time T6.

[0258] By the way, this condition is that the weight coefficient w is set to "+1" and the neuron input to the circuit MP is Since the signal (calculated value) is set to "+1", when using formula (1.1), the weighting coefficient and the new The product of the weight coefficient and the neuron signal is "+1". As a result, in the operation of the circuit MP, the current I OL changes, and the current I OLB but This corresponds to the case where there is no change.

[0259] [Condition 3] Next, as an example, the weight coefficient w is "-1" and the neuron input to the circuit MP is Consider the case where the signal (calculated value) of the circuit M is "+1". 1 is a timing chart of P.

[0260] Regarding the operation from time T1 to time T3, from time T1 to time T3 under condition 1 Since the operation is the same as that between time T1 and time T3 in Condition 1, please refer to the explanation of the operation between time T1 and time T3 in Condition 1. To pour drinks.

[0261] Between time T3 and time T4, the wiring IL is at a low level potential and the wiring ILB is at a high level potential. A bell potential is applied, and "-1" is input as the weighting coefficient w. Since a high level potential has been input from before, the transistor M1 and the transistor The register M1r is in the ON state. Therefore, "-1" is input as the weighting coefficient w. The potential of the node nd1 becomes low level potential, and the potential of the node nd1r becomes high level potential. do.

[0262] Between time T4 and time T5, a low level potential is input to the wiring WL. As a result, the transistors M1 and M1r are turned off, and The capacitance element C1 and the capacitance element C1r are connected to the node nd1 and the node nd1 The potential of each of the electrodes r is maintained.

[0263] The operation from time T1 to time T5 sets the weighting coefficient of circuit MP to "-1". will be done.

[0264] By the operation up to this point, the potential of the gate of transistor M2 is at a low level potential, The potential of the gate of the transistor M2r becomes high level potential, and the potential of the gate of the transistor M2r becomes high level potential. Since the potential of the first terminals of the transistors M1 and M2 is VSS, the transistor M1 is in the off state, and the transistor M2 is in the The starter M2r is turned on.

[0265] Regarding the operation from time T5 to time T6, from time T5 to time T6 under condition 1 Since the operation is the same as that between time T5 and time T6 in Condition 1, please refer to the explanation of the operation between time T5 and time T6 in Condition 1. To pour drinks.

[0266] After time T6, the signal “+1” of the neuron is input to the circuit MP via the wire X A high level potential is input to wiring X1L and a low level potential is input to wiring X2L. The transistors M3 and M3r are turned on, and the transistors M4 and M5 are turned on. The transistors M4r and M4r are turned off. Conduction is established between the wiring OL, and conduction is established between the circuit MCr and the wiring OLB.

[0267] At this time, in the circuit MC, the transistor M2 is in the off state, so that the wiring O No current flows from L to the wiring VL. In other words, the output from node outa of wiring OL The current I OL does not change before and after time T6. Since the resistor M2r is in the ON state, a current flows from the wiring OLB to the wiring VLr. In other words, the current I output from node outb of wiring OLB OLB At time T6 (In FIG. 13C, the current I OLB The increase in this is described as ΔI.

[0268] By the way, this condition is that the weight coefficient w is set to "-1" and the neuron input to the circuit MP is Since the signal (calculated value) is set to "+1", when using formula (1.1), the weighting coefficient and the new The product of the signal of the neuron is "-1". The product of the weight coefficient and the signal of the neuron is "-1". The result is that in the operation of the circuit MP, the current I OL does not change, and the current I OL B This corresponds to the case where changes.

[0269] [Condition 4] In this condition, for example, the weight coefficient w is set to "0", and the neuron input to the circuit MP is Consider the operation of the circuit MP when the signal (calculated value) is set to "-1." 10 is a timing chart of the circuit MP in this case.

[0270] Regarding the operation from time T1 to time T6, from time T1 to time T6 under condition 1 Since the operation is the same as that between time T1 and time T6 in Condition 1, please refer to the explanation of the operation between time T1 and time T6 in Condition 1. To pour drinks.

[0271] After time T6, the neuron signal (calculated value) “-1” is input to the circuit MP. As a result, a low level potential is input to the wiring X1L and a high level potential is input to the wiring X2L. , transistor M3, and transistor M3r are turned off, and transistor M4 and transistor M4r are turned on. The circuit MC and the wiring OLB are in a conductive state, and the circuit MCr and the wiring OL are in a conductive state. becomes.

[0272] At this time, in the circuit MC, the transistor M2 is in the off state, so that the wiring O No current flows from LB to the wiring VL. In other words, from node outb of wiring OLB Output current I OLB does not change before and after time T6. Similarly, in the circuit MCr, , because the transistor M2r is in the off state, No current flows. In other words, the current I output from node outa of wiring OL OL Also, time There is no change before and after T6.

[0273] By the way, this condition is that the weight coefficient w is set to "0" and the signal of the neuron input to the circuit MP is Since the signal (calculated value) is set to "-1", when using formula (1.1), the weighting coefficient and The product of the weight coefficient and the neuron signal is "0". In the operation of the circuit MP, after time T6, the current I OL and current I OLB Each of This corresponds to the case where there is no change, which is consistent with the result of the circuit operation under condition 1.

[0274] [Condition 5] In this condition, for example, the weighting coefficient w is set to "+1", and the neuron input to the circuit MP is Consider the operation of the circuit MP when the signal (operation value) of the input is set to "-1". 10 is a timing chart of the circuit MP in the case where

[0275] Regarding the operation from time T1 to time T6, condition 2, from time T1 to time T6 Therefore, please refer to the explanation of the operation from time T1 to time T6 in Condition 2. To pour drinks.

[0276] After time T6, the neuron signal (calculated value) “-1” is input to the circuit MP. As a result, a low level potential is input to the wiring X1L and a high level potential is input to the wiring X2L. , transistor M3, and transistor M3r are turned off, and transistor M4 and transistor M4r are turned on. The circuit MC and wiring OLB are in a conductive state, and the circuit MCr and wiring OL are in a conductive state. becomes.

[0277] At this time, in the circuit MC, the transistor M2 is in the on state, so that the wiring O Current flows from LB to the wiring VL. In other words, the current flows from the node outb of the wiring OLB. Input current I OLB increases after time T6 (in FIG. 14B, the current IOLB of The increase is denoted as ΔI.) On the other hand, in the circuit MCr, when the transistor M2r is turned on, Since the line is in the off state, no current flows between the line OL and the line VLr. The current I output from node outa of wiring OL OL does not change before and after time T6.

[0278] By the way, this condition is that the weight coefficient w is set to "+1" and the neuron input to the circuit MP is Since the signal (calculated value) is set to "-1", when using formula (1.1), the weighting coefficient and The product of the signal of the neuron is "-1". The product of the weight coefficient and the signal of the neuron is "-1". The result is that in the operation of the circuit MP, the current I OL does not change, and the current I OL B This corresponds to the case where changes, which is consistent with the circuit operation result for condition 3.

[0279] [Condition 6] In this condition, for example, the weighting coefficient w is set to "-1", and the neural network input to the circuit MP is Consider the operation of the circuit MP when the signal (operation value) of the input is set to "-1". 10 is a timing chart of the circuit MP in the case where

[0280] Regarding the operation from time T1 to time T6, condition 3, from time T1 to time T6 Therefore, please refer to the explanation of the operation from time T1 to time T6 in Condition 3. To pour drinks.

[0281] After time T6, the neuron signal (calculated value) “-1” is input to the circuit MP. As a result, a low level potential is input to the wiring X1L and a high level potential is input to the wiring X2L. , transistor M3, and transistor M3r are turned off, and transistor M4 and transistor M4r are turned on. The circuit MC and the wiring OLB are in a conductive state, and the circuit MCr and the wiring OL are in a conductive state. becomes.

[0282] At this time, in the circuit MC, the transistor M2 is in the off state, so that the wiring O No current flows from LB to the wiring VL. In other words, from node outb of wiring OLB Output current I OLB does not change before and after time T6. On the other hand, in the circuit MCr, Since the transistor M2r is in the on state, a current flows between the wiring OL and the wiring VLr. In other words, the current I output from the node outa of the wiring OL OL At time T6 (In FIG. 14C, the current I OL The increase in this is described as ΔI.

[0283] By the way, this condition is that the weight coefficient w is set to "-1" and the neuron input to the circuit MP is Since the signal (calculated value) is set to "-1", when using formula (1.1), the weighting coefficient and The product of the signal of the neuron is "+1". The product of the weight coefficient and the signal of the neuron is "+1". The result is that in the operation of the circuit MP, the current I OL changes, and the current I OLB This corresponds to the case where there is no change, which is consistent with the circuit operation result for condition 2.

[0284] [Condition 7] In this condition, for example, the weighting coefficient w is "0" and the new Let us consider the operation of the circuit MP under condition 7, where the signal (calculated value) of the RON is "0". 15A is a timing chart of the circuit MP in this case.

[0285] Regarding the operation from time T1 to time T6, from time T1 to time T6 under condition 1 Since the operation is the same as that between time T1 and time T6 in Condition 1, please refer to the explanation of the operation between time T1 and time T6 in Condition 1. To pour drinks.

[0286] After time T6, as the input of the neuron signal (operation value) “0” to the circuit MP, A low level potential is input to the wiring X1L, and a low level potential is input to the wiring X2L. The transistors M3, M3r, M4, and M4r are In other words, this operation turns off the circuits MC and MCr. Each of these is in a non-conductive state whether it is between the wiring OL or the wiring OLB.

[0287] Therefore, in the circuit MC, between the wiring OL and either the wiring VL or the wiring VLr, No current flows. In other words, the current I output from node outb of wiring OLB OLB teeth, There is no change before and after time T6. Similarly, in the circuit MCr, In other words, no current flows from node outa of wiring OL to the other end of wiring VLr. The current I OL does not change before and after time T6.

[0288] By the way, this condition is that the weight coefficient w is "0" and the signal of the neuron input to the circuit MP is Since the signal (calculated value) is "0", when using equation (1.1), the weight coefficient and the neuron The product of the signal is "0". The result of the product of the weight coefficient and the neuron signal being "0" is In the operation of the MP, the current I OL and current IOLB Each of these changes This corresponds to the case where no such condition is applied, and is consistent with the results of the circuit operation under conditions 1 and 4.

[0289] [Condition 8] In this condition, for example, the weighting coefficient w is "+1" and the input to the circuit MP is The operation of the circuit MP is considered under the condition 8 where the signal (calculated value) of the LO is "0". FIG. 15B is a timing chart of the circuit MP in this case.

[0290] Regarding the operation from time T1 to time T6, condition 2, from time T1 to time T6 Therefore, please refer to the explanation of the operation from time T1 to time T6 in Condition 2. To pour drinks.

[0291] After time T6, as the input of the neuron signal (operation value) “0” to the circuit MP, , a low-level potential is input to the wiring X1L, and a low-level potential is input to the wiring X2L. This operation is the same as that after time T6 in the circuit MC. LB, the circuit MCr is in a non-conductive state. Therefore, from the wiring OL or the wiring OLB, Since no current flows between the wiring VL and the wiring VLr, the The current I output from the output OL , and the signal output from node outb of wiring OLB current I OLB do not change before and after time T6.

[0292] By the way, this condition is that the weight coefficient w is set to "+1" and the neuron input to the circuit MP is Since the signal (calculated value) is set to "0", when using equation (1.1), the weighting coefficient and the neuro The product of the weight coefficient and the neuron signal is "0". In the operation of the circuit MP, after time T6, the current I OL and current I OLB Each of This corresponds to the case where there is no change, which is consistent with the results of the circuit operation under conditions 1, 4, and 7. do.

[0293] [Condition 9] In this condition, for example, the weighting coefficient w is "-1" and the input to the circuit MP is The operation of the circuit MP is considered under the condition 9 where the signal (calculated value) of the LO is "0". FIG. 15C is a timing chart of the circuit MP in this case.

[0294] Regarding the operation from time T1 to time T6, condition 3, from time T1 to time T6 Therefore, please refer to the explanation of the operation from time T1 to time T6 in Condition 3. To pour drinks.

[0295] After time T6, as the input of the neuron signal (operation value) “0” to the circuit MP, , a low-level potential is input to the wiring X1L, and a low-level potential is input to the wiring X2L. This operation is the same as that after time T6. Therefore, by this operation, the circuit MC The circuit MCr is in a non-conductive state between the wiring OL and the wiring OLB. Therefore, the line OL or the line OLB is in a non-conductive state. Therefore, no current flows between the wiring VL and the wiring VLr. The current I output from node outa OL , and the output from node outb of wiring OLB The current I OLB do not change before and after time T6.

[0296] By the way, this condition is that the weight coefficient w is set to "-1" and the neuron input to the circuit MP is Since the signal (calculated value) is set to "0", when using equation (1.1), the weighting coefficient and the neuro The product of the weight coefficient and the neuron signal is "0". In the operation of the circuit MP, after time T6, the current I OL and current I OLB Each of This corresponds to the case where there is no change, and this is the result of the circuit operation under conditions 1, 4, 7, and 8. matches.

[0297] The results of the operation example under the above conditions 1 to 9 are summarized in the table below. The high level potential is described as high, and the low level potential is described as low.

[0298] [Table 2]

[0299] Here, one circuit MC and one circuit MCr are connected to the wiring OL and wiring OLB, respectively. This is an example of the case shown in Figures 2, 6, 7, and 8. A plurality of circuits MC and a plurality of circuits MCr are connected to the wiring OL and the wiring OLB. In this case, the current output from each circuit MC and circuit MCr is calculated based on Kirchhoff's current law. As a result, the sum is calculated. In the circuits MC and MCr, a multiplication operation is performed, and multiple circuits MC and MCr are used. The sum is calculated by adding up the currents. As a result, the sum-of-products calculation is performed. This will be the case.

[0300] By the way, in the operation of the circuit MP, the weighting coefficients are limited to two values, "+1" and "-1", By calculating neuron signals with only two values, "+1" and "-1", the circuit MP It can perform the same operation as an exclusive OR negation circuit (match circuit).

[0301] In addition, in the operation of the circuit MP, the weighting coefficient is limited to two values, "+1" and "0", and the By performing calculations with only two values ​​for the Ron signal, "+1" and "0", the circuit MP can It can perform the same operation as the circuit.

[0302] In this example of operation, the holding unit HC and the holding unit MCr of the circuit MP The potential held in the holding section HCr was set to a high level potential or a low level potential. The holding unit HCr may hold a potential indicating an analog value. In the case of a "positive analog value", a high-level analog potential is applied to the node nd1 of the holding unit HC. A low level potential is held at the node nd1r of the holding unit HCr. In the case of "analog value of HC", for example, a low level potential is applied to the node nd1 of the holding unit HC, A high-level analog potential is held at the node nd1r of HCr. Then, the current I O L and current I OLB The magnitude of the current is proportional to the analog potential. The HC and HCr sections hold potentials that indicate analog values, as shown in the circuit MP The present invention is not limited to the above example of operation, and may be applied to other circuits MP shown in this specification and the like.

[0303] <Configuration example 2> Next, an example of a circuit configuration that can be applied to the circuit MP shown in FIGS. 5C and 5D will be described. do.

[0304] The circuit MP shown in FIG. 16A shows a configuration example of the circuit MP of FIG. 5C, and is the same as the circuit M of FIG. 9A. The difference from P is that the wiring IL and wiring ILB are combined into one, and the wiring WL in Figure 9A is The point is that it has wiring W1L and wiring W2L.

[0305] In the circuit MP of FIG. 16A, the first terminal of the transistor M1 and the second terminal of the transistor M1r The first terminal is electrically connected to the wiring IL. The gate of the transistor M1r is electrically connected to the wiring W2L. The circuit MP in FIG. 16A has the same connection configuration as the circuit MP in FIG. 9A. The explanation of the parts that are omitted will be omitted.

[0306] When setting weighting coefficients for the circuit MP of FIG. 16A, first, By changing the voltage supplied to the transistor M1, the transistor M1r is turned on and the transistor M1r is turned off. Then, a potential for holding is supplied from the wiring IL to the holding section HC, and the transistor After that, the potentials supplied to the wirings W1L and W2L are changed. This turns off the transistor M1 and turns on the transistor M1r. A potential for holding is supplied from the line IL to the holding unit HCr, and the transistor M1r is turned off. In this way, in the case of the circuit MP of FIG. 16A, the wiring IL is connected to the holding unit HC, the holding unit HC By sequentially supplying potentials to the holding units HC and HCr, the weighting coefficients corresponding to the weighting coefficients are applied to the holding units HC and HCr. The potential can be maintained.

[0307] The circuit MP shown in FIG. 16B is a configuration example of the circuit MP of FIG. 5D, and is the same as the circuit MP of FIG. 9A. The difference with P is that the wiring IL and wiring OL are combined into wiring IOL, and the wiring ILB and wiring OLB are combined into wiring IOL. The key point is that these are all integrated into the wiring IOLB.

[0308] In the circuit MP of FIG. 16B, the first terminal of the transistor M1 is electrically connected to the line IOL. A first terminal of the transistor M1r is electrically connected to the wiring IOLB. In addition, the second terminal of the transistor M3 is electrically connected to the line IOL, and the transistor The second terminal of M4 is electrically connected to the wiring IOLB, and the second terminal of the transistor M3r is The second terminal of the transistor M4r is electrically connected to the wiring IOLB. 16B and the circuit MP of FIG. 9A. The explanation of the parts that are composed of the above will be omitted.

[0309] In the circuit MP of FIG. 16B, the wiring IOL is electrically connected to the holding part HC, and the holding part HCr is The wiring IOLB is electrically connected to the wiring WL. Since the gates are electrically connected, the holding unit H C, a potential corresponding to a weighting coefficient can be simultaneously written to the holding unit HCr.

[0310] <Configuration example 3> The circuit MP shown in FIG. 17 differs from the circuit MP shown in FIG. 9A in that only the holding unit HC and the holding unit HCr HCs and HCsr.

[0311] The circuit MC included in the circuit MP of FIG. 17 is added to the circuit elements included in the circuit MP of FIG. 9A. Eh, transistor M1s, transistor M2s, transistor M5, transistor M5s , and a capacitance element C1s. The circuit MCr included in the circuit MP of FIG. Since the circuit has the same circuit elements as MC, the transistors M1s and M2 s, transistor M5, transistor M5s, and capacitance element C1s, Transistor M1sr, transistor M2sr, transistor M5r, transistor M5s r, and has a capacitance element C1sr.

[0312] In this specification, the transistors M5, M5s, and Unless otherwise specified, when the transistor M5r and transistor M5sr are in the on state, they are ultimately connected to the line. This includes the case where the transistors operate in the MOSFET region. The gate voltage, source voltage, and drain voltage are appropriate for the voltage range in which the device operates in the linear region. This includes cases where the information is biased towards

[0313] Next, the configuration of the circuit MP in Fig. 17 will be described. In the circuit MP in Fig. 17, Portions having the same configuration as the circuit MP in FIG. 9A are omitted.

[0314] The gate of the transistor M1 is electrically connected to the wiring W1L. The first terminal of transistor M5 is electrically connected to the second terminal of transistor M2, and the The second terminal is electrically connected to the first terminal of the transistor M3 and the first terminal of the transistor M4. , and the gate of the transistor M5 is electrically connected to the wiring S1L.

[0315] The first terminal of the transistor M1s is electrically connected to the wiring IL. The second terminal of the capacitor C1s is electrically connected to the first terminal of the capacitor C1s and the gate of the transistor M2s. The gate of the transistor M1s is electrically connected to the wiring W2L. The first terminal of the transistor M2s is electrically connected to the second terminal of the capacitance element C1s and the wiring VLs. The second terminal of the transistor M2s is electrically connected to the first terminal of the transistor M5s. The second terminal of the transistor M5s is connected to the first terminal of the transistor M3. The first terminal of the transistor M4 is electrically connected to the gate of the transistor M5s. Electrically connected to S2L.

[0316] In the circuit MP of FIG. 17, the circuit MCr has almost the same circuit configuration as the circuit MC. Therefore, the circuit elements of the circuit MCr are distinguished from the circuit elements of the circuit MC. Therefore, the symbol is prefixed with "r."

[0317] The wiring VLs functions as a wiring for supplying a constant voltage, and the constant voltage is a low-level voltage. The potential may be VSS, which is a high potential, a low level potential other than VSS, or the ground potential. The constant voltage may be a high-level potential VDD. The constant voltage supplied by the line VL may be different from or the same as the constant voltage supplied by the line VL. When the constant voltages VL and VLs are approximately equal, the wiring VLs is the same wiring as the wiring VL. It can be a line.

[0318] The line VLsr functions as a line that supplies a constant voltage, and the constant voltage is a low level The potential may be VSS, a low-level potential other than VSS, or the ground potential. The constant voltage may be a high-level potential VDD. The constant voltage supplied may be different from or the same as the constant voltage supplied by the line VLr. If the constant voltages applied by the wiring VLr and the wiring VLsr are approximately equal, the wiring VLsr is It can be wired the same as Lr.

[0319] In addition, the constant voltages given by the wiring VL, wiring VLs, wiring VLr, and wiring VLsr are The voltages may be different from each other or may be the same. The constant voltages applied by two or three wires selected from the line VLr and the wiring VLsr are equal to each other. It's okay.

[0320] The wiring S1L turns the transistor M5 and the transistor M5r on or off. The wiring S2L serves as a wiring for supplying a potential to the transistors M5s and The wiring functions as a wiring for supplying a potential to turn on or off the transistor M5sr. It works.

[0321] The circuit MP shown in FIGS. 5C and 5D can be realized by applying the configuration shown in the circuit MP of FIG. Specifically, the circuit MP in FIG. The potential corresponding to the weighting coefficient is stored in the holding section HC of the circuit MC and the holding section HCr of the circuit MCr. , and the potential according to the second weighting coefficient is stored in the storage unit HCs of the circuit MC and the storage unit HCs of the circuit MC. The circuit MP in FIG. The weighting coefficients used in the calculation can be switched by the potential applied from the wiring S2L. For example, the circuits MP[1,j] to MP[m,j] included in the arithmetic circuit 110 The weighting coefficient w1 is assigned to each of the holding parts HC and HCr. (k-1) j (k) Or even w m (k-1 ) j (k) and the circuits MP[1,j] to MP Each holding part HCs, HCsr included in [m,j] is weighted by a weighting coefficient w1 (k-1) h ( k) Or even w m (k-1) h (k) (Here, h is an integer greater than or equal to 1 and not equal to j.) The wirings XLS[1] to XLS[m] (in the circuit MP in FIG. 17) are held at a potential corresponding to the Connect the signal z1 to the wires X1L and X2L. (k-1) ~z m (k-1) Enter the potential according to At this time, a high level potential is applied to the wiring S1L, and the transistors M5 and The transistor M5r is turned on, and a low-level potential is applied to the wiring S2L, By turning off the transistor M5sr, the circuit MP[1,j] of the arithmetic circuit 110 The circuit MP[m,j] has a weighting coefficient w1 (k-1) j (k) Or even w m (k-1) j (k) and signal z1 (k-1) ~z m (k-1) It is possible to calculate the sum of products and activation functions with In addition, a low-level potential is applied to the wiring S1L, and the transistors M5 and M5 r is turned off, a high level potential is applied to the wiring S2L, and the transistors M5s and By turning on the register M5sr, the circuits MP[1,j] to MP[1,j] of the arithmetic circuit 110 are MP[m,j] is the weighting coefficient w1 (k-1) h (k) Or even wm (k-1) h (k) and traffic lights z1 (k-1) ~z m (k-1) It is possible to perform product sum and activation function calculations.

[0322] As described above, by applying the circuit MP of FIG. 17 to the arithmetic circuit 110, the weight coefficients are It is possible to hold two weight coefficients and switch between them to perform product sum and activation function calculations. The arithmetic circuit 110 constituting the circuit MP of FIG. 17 can, for example, When the number of nodes is greater than n, when performing calculations in a hidden layer other than the kth layer, etc. In the circuit MP of FIG. 17, the holding unit of the circuit MC and the circuit MCr However, depending on the situation, the number of circuits MC and MCr may be increased to three. The above holding portions may be provided.

[0323] <Configuration Example 4> The circuit MP shown in FIG. 18A is a circuit that can be applied to the circuit MP of FIG. 5A, and includes a holding unit HC, and the holding unit HCr are connected to the load circuit LC instead of the capacitance element C1 and the capacitance element C1r. 9A in that it has a load circuit LCr.

[0324] In the circuit MC of the circuit MP of FIG. 18A, the first terminal of the load circuit LC is connected to the transistor M A second terminal of transistor M1, a first terminal of transistor M3, and a first terminal of transistor M4 are connected to the second terminal of transistor M1, the first terminal of transistor M3, and the first terminal of transistor M4. The second terminal of the load circuit LC is electrically connected to the wiring VL.

[0325] The circuit MCr of the circuit MP in FIG. 18A has almost the same circuit configuration as the circuit MC. Therefore, the circuit elements of the circuit MCr are distinguished from the circuit elements of the circuit MC. Therefore, the symbol is prefixed with "r."

[0326] The wiring VL and wiring VLr function as wirings that supply a constant voltage VCNS. CNS can be, for example, the ground potential (GND), or the load circuit LC and the load circuit LCr. It can be set to a low potential within the range in which it is always operated.

[0327] The load circuit LC and the load circuit LCr are, for example, the resistance between the first terminal and the second terminal. The first and second terminals of the load circuit LC and the load circuit LCr are By changing the resistance between the first and third terminals of the load circuit LC and the load circuit LCr, The amount of current flowing between the two terminals can be changed.

[0328] In the circuit MP of FIG. 18A, the first terminal and the second terminal of the load circuit LC and the load circuit LCr are The method for changing the resistance between the two terminals will be explained. First, let us consider the wiring X1L and the wiring X2. A low-level potential is input to each of the transistors M3, M3r, and L. Next, a high-level potential is applied to the wiring WL. This input turns on the transistors M1 and M1r, changing the potential of the wiring IL (wiring ILB). By doing so, the resistance value between the first and second terminals of the load circuit LC (load circuit LCr) is For example, the first load circuit LC (load circuit LCr) is set to the wiring IL (wiring ILB). Input a potential to reset the resistance between the terminal and the second terminal, and then connect the wiring IL (Wiring ILB) is the resistor between the first and second terminals of the load circuit LC (load circuit LCr). There are methods to input a voltage that will make the value of the load circuit LC (load circuit LC After setting the resistance between the first and second terminals of the resistor (r) to the desired value, The bell potential is input to turn off the transistors M1 and M1r.

[0329] The load circuits LC and LCr may be, for example, resistor transformers as shown in FIG. 18B. The load circuit LC and the load circuit LCr can be, for example, For example, as shown in FIG. 18C, a circuit VC including an MTJ element MR can be used. In addition, as the load circuit LC and the load circuit LCr, for example, as shown in FIG. 18D, A resistive element (referred to as "phase change material" in this specification) containing a phase change material is used in a phase change memory (PCM) or the like. For convenience, a phase change memory (PCM) can be used.

[0330] Furthermore, the circuit MP using the load circuit LC and the load circuit LCr is not limited to the configuration shown in FIG. 18A. The configuration of the circuit MP in FIG. 18A can be changed depending on the situation. As an example of a modification of the circuit MP, the circuit MP of FIG. 18A is modified by adding wiring IL, wiring ILB, and a transistor. The circuit configuration can be such that the transistor M1 and the transistor M1r are not provided. 5D. This is a circuit diagram showing the circuit configuration, which is one of the configuration examples of the circuit MP of FIG. 5D.

[0331] In the circuit MP of Figure 19, setting the resistance value between the first and second terminals of the load circuit LC By inputting a high level potential to the wiring X1L and a low level potential to the wiring X2L, the transistor M 3 is turned on, transistor M4 is turned off, and the This can be done by applying a potential to the first terminal of the load circuit LC. , a potential is applied from the wiring IOLB to the first terminal of the load circuit LCr via the transistor M3r. Therefore, the first and second terminals of the load circuit LCr can be connected at the same time as the load circuit LC. The resistance value between these values ​​can also be set.

[0332] Also, the resistance between the first and second terminals of the load circuit LC is set by connecting a low level A high-level potential is input to the wiring X2L to turn off the transistor M3. The load circuit LC This can also be done by applying a potential to the first terminal of the wiring IOL. , a potential can be applied to the first terminal of the load circuit LCr via the transistor M4r. Therefore, the resistance between the first and second terminals of the load circuit LCr must be set at the same time as the load circuit LC. It is also possible to make a decision.

[0333] The first terminals of the load circuits LC and LCr shown in FIGS. 18A and 19 are The resistance value between the terminal and the second terminal may be two values, three values ​​or more, and may further be an analog value. You may do so.

[0334] <Configuration example 5> The circuit MP shown in FIG. 20A is applicable to the circuit MP of FIG. 5A, and includes a holding unit HC, Each of the holding units HCr is an inverter loop instead of the capacitance element C1 and the capacitance element C1r. 9A in that it has the circuit configuration shown below.

[0335] In the circuit MC of the circuit MP of FIG. 20A, the holding unit HC includes an inverter circuit INV1 and The input terminal of the inverter circuit INV1 is connected to an inverter circuit INV2. the output terminal of the inverter circuit INV2, the second terminal of the transistor M1, and the gate of the transistor M2. As in the description of FIG. 9A, the first 2 terminal, the gate of the transistor M2, the input terminal of the inverter circuit INV1, and the inverter The electrical connection point between the output terminal of the data circuit INV2 and the node nd1 is called the node nd2. The terminal nd1 is not the input terminal of the inverter circuit INV1, but the output terminal of the inverter circuit INV1. It may be connected to a power terminal.

[0336] The circuit MCr of the circuit MP in FIG. 20A has almost the same circuit configuration as the circuit MC. Therefore, the circuit elements of the circuit MCr are distinguished from the circuit elements of the circuit MC. Therefore, the symbol is prefixed with "r."

[0337] The holding unit HC included in the circuit MC is an inverter circuit INV1 and an inverter circuit I NV2 and NV3 form an inverter loop, and the holding unit H included in the circuit MCr Cr is an inverter circuit INV1r and an inverter circuit INV2r. That is, the circuit MP in FIG. 20A includes a holding unit HC and a holding unit H Each inverter loop of Cr can hold a potential corresponding to the weighting coefficient. can.

[0338] In the circuit MP of FIG. 20A, the inverter circuit INV1 and the inverter circuit INV1r , inverter circuit INV2, inverter circuit INV2r are shown, circuit INV1, inverter circuit INV1r, inverter circuit INV2, inverter circuit IN At least one of V2r is a logic circuit that receives an input signal and outputs an inverted signal of the input signal. The logic circuit may be replaced with a circuit, such as a NAND circuit, a NOR circuit, XOR circuits, and circuits combining these. Specifically, inverters When replacing the circuit with a NAND circuit, a fixed potential is applied to one of the two input terminals of the NAND circuit. By inputting a high-level potential, the NAND circuit can function as an inverter circuit. Also, when replacing the inverter circuit with a NOR circuit, the two input terminals of the NOR circuit By inputting a low-level potential as a fixed potential to one of the Also, if the inverter circuit is replaced with an XOR circuit, the XOR By inputting a high-level voltage as a fixed voltage to one of the two input terminals of the R circuit, an XOR circuit can function as an inverter circuit.

[0339] As described above, the inverter circuits described in this specification and the like are not limited to NAND circuits, NOR circuits, or the like. It can be replaced with a logic circuit such as a logic circuit, an XOR circuit, or a circuit that combines these. Therefore, in this specification and elsewhere, the term "inverter circuit" is used interchangeably with "logic circuit." It can be called as:

[0340] The circuit MP in Figure 20A can be reconfigured depending on the situation. A modified example of the circuit MP is shown in FIG. 20B. The circuit MP of FIG. 20B is the same as the circuit MP of FIG. 20A. The MP circuit MCr is configured by removing the holding unit HCr, and the holding unit HC of the circuit MC is configured by removing the holding unit HCr from the circuit MCr. It is electrically connected to the gate of the transistor M2r of the MCr.

[0341] In FIG. 20B, the output terminal of the inverter circuit INV1 and the input terminal of the inverter circuit INV2 The electrical connection point between the terminal and the node nd2 is the gate of the transistor M2r. The potential of the node nd2 is input to the output.

[0342] In the circuit MP shown in FIG. 20B, the holding unit HCr is not included in the circuit MCr, and the transistor The potential applied to the gate of M2r is held by the holding unit HC of the circuit MC. The section HC is an inverter loop consisting of an inverter circuit INV1 and an inverter circuit INV2. Since the node nd1 has a loop configuration, either a high level potential or a low level potential is held at the node nd1. The node nd2 is held at the other of the high level potential and the low level potential.

[0343] In addition, due to the configuration of the inverter loop, the holding unit HC is connected to the node nd1 and the node nd2. Therefore, in the circuit MP of FIG. , node nd1, and node nd2 are held at the same potential. Specifically, in the above example of operation, the transistor M 2. Since the low level potential cannot be maintained at the gate of each transistor M2r, The weighting factor "0" cannot be set for circuit MP of B.

[0344] <Configuration Example 6> The circuit MP shown in FIG. 21A is a circuit that can be applied to the circuit MP of FIG. 5A, and includes a holding unit HC, Each of the holding units HCr has two transistors and two capacitance elements. 9A.

[0345] In the circuit MC of the circuit MP shown in FIG. 21A, the holding unit HC includes a transistor M1, a transistor The first capacitor of the transistor M1 includes a first capacitor M1s, a second capacitor C2, and a third capacitor C2s. The first terminal of the transistor M1 is electrically connected to the wiring IL, and the second terminal of the transistor M1 is connected to the capacitance element C2. and the gate of the transistor M6. The gate of the transistor M1s is electrically connected to the wiring WL. IL, and the second terminal of the transistor M1s is electrically connected to the first terminal of the capacitive element C2s. and the gate of the transistor M7, and the gate of the transistor M1s is , and is electrically connected to the wiring WL. As in the description of FIG. 9A, the transistor M1 the second terminal of the transistor M6, the gate of the transistor M6, and the first terminal of the capacitive element C2. The point is called nd1, and the second terminal of the transistor M1s, the gate of the transistor M7, The electrical connection point with the first terminal of the capacitance element C2s is referred to as nd1s.

[0346] The second terminal of the capacitance element C2 is electrically connected to the wiring X1L, and the second terminal of the capacitance element C2s is The terminal is electrically connected to the wiring X2L.

[0347] The first terminal of the transistor M6 is electrically connected to the first terminal of the transistor M7 and the wiring VL. The second terminal of the transistor M6 is electrically connected to the wiring OL. The second terminal of the resistor M7 is electrically connected to the wiring OLB.

[0348] The circuit MCr of the circuit MP in FIG. 21A has almost the same circuit configuration as the circuit MC. Therefore, the circuit elements of the circuit MCr are distinguished from the circuit elements of the circuit MC. Therefore, the symbol is prefixed with "r."

[0349] The holding unit HC included in the circuit MC holds the potential by the capacitance elements C2 and C2s. Specifically, a high-level potential is input to the wiring WL, and the transistor After turning on the transistor M1 and the transistor M1s, a predetermined potential is input to the wiring IL. As a result, the potential is written to the first terminals of the capacitance elements C2 and C2s. After that, a low level potential is input to the wiring WL, and the transistors M1 and M2 are turned on. By turning off M1s, the nodes nd1 and nd1s of the holding unit HC are It is possible to write a predetermined potential to the holding unit HC and hold it. When the wiring X1L and the wiring X2L are connected, the potentials of the wiring X1L and the wiring X2L are set to, for example, a constant potential. It is preferable, and particularly preferable that the potential is higher than the low level potential and lower than the high level potential. For convenience, the constant potential is referred to as a reference potential.

[0350] In the circuit MP of FIG. 21A, the wiring WL is connected to the holding unit HC and the holding unit HCr. Since they are electrically connected to each other, the holding part HC and the holding part HCr each have a heavy When writing and holding a potential corresponding to the write coefficient, when the potential of the wiring WL is high level potential, At the same time, a predetermined potential is written to the holding unit HC and the holding unit HCr, and then the wiring WL The potential is set to a low level, and the transistors M1, M1s, and M1r , and the transistor M1sr are turned off simultaneously.

[0351] Here, the neuron signal input to the circuit MP is defined as follows: A voltage higher than the reference potential (hereafter referred to as high-level potential) is applied to wiring X1L, and the reference potential is applied to wiring X2L. When a voltage lower than the low level (hereinafter referred to as low level potential) is applied to the circuit MP, When a neuron receives a signal of "+1", the wire X1L is at a low potential and the wire X2 When a high level potential is applied to L, the circuit MP receives a neuron signal of "-1 " is input and a low-level potential is applied to the wires X1L and X2L. ,It is assumed that "0" is input to the circuit MP as a neuron signal.

[0352] For example, after the potential corresponding to the weighting coefficient is held in the holding unit HC and the holding unit HCr, When inputting "+1" as a neuron signal to MP, a high level potential is input to the wire X1L. Therefore, the potentials of the nodes nd1 and nd1r are respectively This increases due to the capacitive coupling of transistor M6 and transistor M6 The potential of the gates of transistors M6 and M6r becomes high. In addition, since a low-level potential is input to the wiring X2L, the nodes nd1s and The potentials of the nodes nd1sr and nd1sr are capacitively coupled by the capacitive elements C2s and C2sr. This causes the gates of the transistors M7 and M7r to Since the potential of the port becomes low, the transistors M7 and M7r are turned off. In other words, when a neuron inputs "+1" to the circuit MP, the circuit M There is a conductive state between C and wiring OL, and there is a conductive state between circuit MCr and wiring OLB. .

[0353] Also, for example, after holding potentials corresponding to weighting coefficients in the holding units HC and HCr, When "-1" is input as a neuron signal to the circuit MP, a low-level voltage is applied to the wire X1L. Since the potentials of the nodes nd1 and nd1r are input, the potentials of the nodes nd1 and nd1r are This is lowered by the capacitive coupling of the capacitive element C2r. The potential of the gates of the transistors M6 and M6r becomes low. Also, since a high-level potential is input to the wiring X2L, the node The potentials of the nodes nd1s and nd1sr are applied to the capacitors C2s and C2sr, respectively. This increases the capacitance of the transistors M7 and M7r. Since the potential of each gate becomes high, transistor M7 and transistor M7r are turned on. In other words, when "-1" is input to the circuit MP as a neuron signal, Therefore, the circuit MC and the wiring OLB are in a conductive state, and the circuit MCr and the wiring OL are in a conductive state. It will be in normal state.

[0354] Also, for example, after holding potentials corresponding to weighting coefficients in the holding units HC and HCr, When "0" is input as a neuron signal to the circuit MP, a low-level potential is applied to the wire X1L. Since the potentials of the nodes nd1 and nd1r are input, the potentials of the capacitors C2 and C3 are This is due to the capacitive coupling of the capacitance element C2r. The potential of the gate of each of the transistors M6 and M6r becomes low. The transistor M6r is turned off. Also, a low-level potential is input to the wiring X2L. The potentials of the nodes nd1s and nd1sr are respectively connected to the capacitors C2s and C2 This is due to the capacitive coupling of transistor M7 and transistor The potential of the gates of the transistors M7 and M7r becomes low. The neuron M7r is in the OFF state. In other words, "0" is input to the circuit MP as a neuron signal. As a result, the distance between the circuit MC and the wiring OL and the wiring OLB is , it becomes non-conductive.

[0355] The transistors M6, M6r, M7, and As an example, it is preferable that the on-state of M7r operates in the saturation region. The transistors M6, M6r, M7, and M7r The gate, source, and drain are appropriately connected so that the transistors operate in the saturation region when on. It is preferable that the transistor M6, the transistor M6r, and the transistor By operating the on-states of the transistors M7 and M7r in the saturation region, When the gate-source potential increases, the current that flows between the source and drain of the transistor increases. In other words, when the wiring X1L (wiring X2L) is at a high level potential, the transistor The source-drain of transistor M6, transistor M6r (transistor M7, transistor M7r) The current flowing between the drains is 1sr) is determined by the magnitude of the potential. However, one embodiment of the present invention is not limited to this. stomach.

[0356] Furthermore, the configuration of the circuit MP in Figure 21A can be changed depending on the situation. A modified example of the circuit MP is shown in FIG. 21B. The circuit MP of FIG. 21B is a modified version of the circuit MP of FIG. 21A. Transistor M6, transistor M6r, transistor M7, and transistor M7r form a bias Therefore, the transistors included in the circuit MP M6, transistor M6r, transistor M7, and transistor M7r are transistors. This can be determined at the design stage and is independent of the structure of the controller.

[0357] For example, transistor M6, transistor M6r, transistor M7, and The transistor M7r includes single-crystal silicon or non-single-crystal silicon in the active layer. The transistor M6 in FIG. 21B can be a Si transistor. The transistors M6r, M7, and M7r contain an oxide semiconductor in the active layer. The transistor M6 and the transistor M7 can be used as an OS transistor. M6r, transistor M7, and transistor M7r may be organic semiconductors, compound semiconductors, or the like. The transistor may have a body.

[0358] As described above, by applying the circuit MP of FIGS. 21A and 21B to the arithmetic circuit 110, , , ,like ,the ,circuit MP ,of ,Figure 9A, ,it ,can ,perform ,product-sum ,and ,activation ,function ,operations.

[0359] <Configuration Example 7> In the configuration examples 1 to 6, the weighting coefficients held by the circuit MP are "+1", "-1", and "0". " and the neuron signal according to the potential input from wire X1L and wire X2L is " This section explains the circuit MP, which can calculate the product of three values, +1, -1, and 0, and As explained above, in this configuration example, the weighting coefficients are assumed to have three values: "+1", "-1" and "0". The neuron's signal (calculated value) can be multiplied by two values, "+1" and "0". Next, we will explain the circuit MP.

[0360] The circuit MP shown in FIG. 22A is the circuit MP shown in FIG. 9A without the transistors M4 and M4r. In addition, since the transistors M4 and M4r are omitted, in FIG. 22A, , a transistor M4, and a transistor M4r. The wire X2L is also excluded. The wire corresponding to the wire X1L is marked as wire XL in FIG. 22A. It is listed.

[0361] The weighting coefficient set in the circuit MP of FIG. 22A is a weighting coefficient set in the node nd1 of the holding unit HC. When a low level potential is held at the node nd1r of the holding unit HCr, it is set to "+1". , a low level potential is applied to the node nd1 of the holding unit HC, and a high level potential is applied to the node nd1r of the holding unit HCr. When the potential is held, it is set to "-1" and a low level potential is applied to the node nd1 of the holding unit HC. When a low level potential is held at the node nd1r of the holding unit HCr, it is set to "0".

[0362] In addition, the neuron signal input to the circuit MP in FIG. 22A is a high-level potential on the wire XL. When a low level potential is applied to the wiring XL, it is set to "+1". Let it be “0”.

[0363] For the operation of the circuit MP in FIG. 22A, please refer to the explanation of the operation example of the first configuration example.

[0364] In the circuit MP of FIG. 22A, as described above, the weight coefficients and the input neuron signals When we define the weight coefficients, the signal of the neuron is input to the circuit MP. As a result, the current I OL The effect of change Current I output from node outb of wiring OLB OLB The presence or absence of change is as follows: In the table below, high level potential is written as "high" and low level potential is written as "low". is described as low.

[0365] [Table 3]

[0366] As shown in the table above, the circuit MP in FIG. 22A has three weighting coefficients: "+1", "-1", and "0". The product of this and the binary value of the neuron signal, "+1" or "0", can be calculated. The weighting coefficient may be two values ​​or more than three values ​​instead of three values. For example, It may be a binary value of "1" or "0", or a binary value of "+1" or "-1". Alternatively, a weighting coefficient may be an analog value or a multi-bit (multi-valued) digital value.

[0367] In this example of operation, the holding units HC The potential held in the holding unit HCr is set to a high level potential or a low level potential. The weighting coefficient HC and the holding coefficient HCr may hold a potential indicating an analog value. In the case of a "positive analog value" as a number, a high-level analog signal is output to node nd1 of the holding unit HC. A low level potential is held at the node nd1r of the holding unit HCr. In the case of a "negative analog value", for example, a low level potential is applied to the node nd1 of the holding unit HC, A high level analog potential is held at the node nd1r of the holding unit HCr. Flow I OL and current I OLB The magnitude of the current is in accordance with the analog potential.

[0368] The circuit MP of FIG. 22A is similar to the circuit MP of FIG. 16A in that the wiring IL and the wiring ILB are connected in a single line. Alternatively, the wiring WL may be divided into wirings W1L and W2L. The configuration is shown in FIG. 22B. The circuit MP in FIG. 22B is applied to the arithmetic circuit 120 in FIG. 6 as an example. The operation method of the circuit MP in FIG. 22B can be explained by referring to the circuit M in FIG. Please refer to the description of how P works.

[0369] In addition, the circuit MP in FIG. 22A is configured by dividing the wiring XL into wiring X1L and wiring X2L. Such a circuit configuration is shown in FIG. 22C. When a high-level potential or a low-level potential is applied, the There are four combinations of the on and off states of the holding part HC and the holding part HC. The nodes nd1 and nd1r of HCr are connected to a high level potential or a low level potential. If the potentials held at the nodes nd1 and nd1r are There are four ways to do this.

[0370] Specifically, a high level potential is held at the node nd1, and a high level potential is applied to the wiring X1L. When the voltage is applied, the wiring OL and the wiring VL are electrically connected, so the current flows through the wiring OL. The amount of current I OL Also, a high level potential is held at the node nd1r, and the line X2 When a high-level potential is applied to L, the wiring OLB and the wiring VLr are electrically connected. Therefore, the amount of current I OLB In the circuit MP of FIG. The combination of the potentials held at the nodes nd1 and nd1r and the wiring X1L and X2L is given. The potentials output from the node outa of the wiring OL are determined by the combination of the potentials current I OLand the current I output from node outb of wiring OLB OLB The presence or absence of change is as shown in the table below. In the table below, high level potential is referred to as high. The low level potential is described as low.

[0371] [Table 4]

[0372] Next, a circuit having a different configuration from the circuit MP of FIGS. 22A to 22C will be described.

[0373] The circuit MP shown in FIG. 23A has weighting coefficients of "+1" and "- Calculate the product of the ternary values ​​"1" and "0" and the binary values ​​"+1" and "0" of the neuron signal The circuit MP of FIG. 21A includes a transistor M1s, a transistor M1sr, and a transistor M1sr. A circuit in which the transistor M7, the transistor M7r, the capacitance element C2s, and the capacitance element C2sr are not provided In addition, since the capacitance elements C2s and C2sr are omitted, the capacitance of the capacitor C2 is Then, to input a potential to the second terminal of each of the capacitance elements C2s and C2sr, Wiring X2L is also excluded. In addition, the wiring equivalent to wiring X1L is wiring XL in Figure 23A. It is stated.

[0374] For the operation of FIG. 23A, please refer to the description of Configuration Example 6.

[0375] As with the circuit MP of FIG. 22A, the weight coefficients and the neurons By defining the signal and the weighting coefficients as "+1", "-1", " The product of the ternary value of "0" and the binary value of the neuron signal "+1" and "0" can be calculated. The weighting coefficients may be two values ​​or more than three values ​​instead of three values. For example, it may be two values ​​of "+1" and "0", or two values ​​of "+1" and "-1". The weighting coefficients may be analog values ​​or multi-bit (multi-valued) digital values. For example, , the circuit MC of the circuit MP, the circuit MCr has a holding unit HC, the holding unit HCr has The potential was set to a high level potential or a low level potential, but the holding part HC and the holding part HCr were set to analog. For example, in the case of a "positive analog value" as the weighting coefficient, is a high-level analog potential at the node nd1 of the holding unit HC, and a high-level analog potential at the node nd1 of the holding unit HCr. r holds a low level potential. In the case of a "negative analog value" as the weighting coefficient, e.g. For example, a low level potential is applied to the node nd1 of the holding unit HC, and a high level potential is applied to the node nd1r of the holding unit HCr. The analog potential of the bell is maintained. And the current I OL and current I OLB Large current The magnitude corresponds to the analog potential.

[0376] The circuit MP of FIG. 23A is similar to the circuit MP of FIG. 16A in that the wiring IL and the wiring ILB are connected in a single line. Alternatively, the wiring WL may be divided into wiring W1L and wiring W2L. The circuit configuration is shown in FIG. 23B. The circuit MP in FIG. 23B corresponds to the arithmetic circuit 120 in FIG. 6, for example. It should be noted that the operation method of the circuit MP in FIG. 23B can be applied to the circuit in FIG. Please refer to the description of the MP operation method.

[0377] 22C, the circuit MP of FIG. 23A is similar to the circuit MP of FIG. 22C in that the wiring XL is connected to the wiring X1L, The wiring X1 may be divided into two parts, namely, wiring X2L. Such a circuit configuration is shown in FIG. If a high level potential or a low level potential is applied to each of the wirings X1L and X2L, Combinations of the on and off states of the transistors M6 and M6r There are four ways. In addition, the nodes nd1 and n of the holding unit HC and the holding unit HCr are If a high level potential or a low level potential is held at node nd1, There are four combinations of potentials held at the node nd1r. The potentials held in the holding units HC and HCr of the circuits MC and MCr are Although it is set to a level potential or a low level potential, the holding part HC and the holding part HCr show analog values. For example, if the weighting coefficient is a "positive analog value," the holding unit A high level analog potential is applied to the node nd1 of the HC, and a low level is applied to the node nd1r of the holding unit HCr. In the case of a "negative analog value" as the weighting coefficient, for example, The node nd1 of the HC section is at a low level potential, and the node nd1r of the HCr section is at a high level potential. A logarithmic potential is maintained. Then, the current I OL and current I OLB The magnitude of the current is The magnitude depends on the analog potential.

[0378] In the circuit MP of FIG. 23C, the change in the current flowing through the wiring OL and wiring OLB is Therefore, in the circuit MP of FIG. 23C, The combination of the potentials held at the nodes nd1 and nd1r and the wiring X1L and X2L is given. The potentials output from the node outa of the wiring OL are determined by the combination of the potentials current I OL and the current I output from node outb of wiring OLB OLB The presence or absence of change is as shown in the above table explained for the circuit MP in FIG. 22C.

[0379] <Configuration Example 8> The circuit MP shown in FIG. 24A is an example of a circuit that can be applied to the circuit MP of FIG. 5F.

[0380] The circuit MP in FIG. 24A includes a circuit MC, a circuit MCr, and a transistor MZ.

[0381] The circuit MCr of the circuit MP in FIG. 24A has almost the same circuit configuration as the circuit MC. Therefore, the circuit elements of the circuit MCr are distinguished from the circuit elements of the circuit MC. Therefore, the symbol is prefixed with "r."

[0382] The circuit MC also includes a holding unit HC and a transistor M8. The circuit has a section HCr and a transistor M8r.

[0383] The holding unit HC included in the circuit MC of the circuit MP of FIG. 24A is, for example, Circuit MP of Figs. 9C, 10A, 10B, 11A, 11B, 12A, 12B, etc. The holding unit HC can have the same configuration as that of the holding unit HC included in the circuit MC.

[0384] The first terminal of the transistor M8 is electrically connected to the first terminal of the transistor MZ. The gate of the transistor M8 is connected to the second terminal of the transistor M1 and the first terminal of the capacitance element C1. , and the second terminal of the transistor M8 is electrically connected to the wiring OL. A second terminal of the capacitor C1 is electrically connected to the wiring CVL. A first terminal of M1 is electrically connected to the wiring IL.

[0385] The first terminal of the transistor M8r is electrically connected to the first terminal of the transistor MZ. The gate of the transistor M8r is connected to the second terminal of the transistor M1r and the capacitance element C1 The first terminal of the transistor M8r is electrically connected to the wiring OLB. The second terminal of the capacitance element C1r is electrically connected to the wiring CVL. A first terminal of the transistor M1 is electrically connected to the wiring ILB.

[0386] The wiring CVL functions as a wiring that applies a constant voltage, for example. , for example, a high-level potential, a low-level potential, a ground potential, etc.

[0387] The holding units HC and HCr included in the circuit MP of FIG. 24A are the same as those shown in FIG. 9A etc. Similarly to the holding units HC and HCr included in the circuit MP, the potential according to the weighting coefficient Specifically, for example, a predetermined potential is applied to the wiring WL, and the transistor The first transistor M1 and the second transistor M1r are turned on, and the first capacitor C1 is connected to the wiring IL. A potential is supplied to the first terminal of the capacitor C1r from the wiring ILB. After that, a predetermined potential is applied to the wiring WL to turn on the transistor M1 and the transistor M1. Just turn r off.

[0388] Here, for example, the weighting coefficient set in the circuit MP of FIG. 24A is When a high level potential is held at d1 and a low level potential is held at node nd1r of the holding unit HCr, When the node nd1 of the holding unit HC is set to a low level potential, the node n of the holding unit HCr is set to a low level potential. When a high level potential is held at node nd1r, the value is set to "-1" and the node nd1 of the holding unit HC is set to "-1". When a low level potential is held at node nd1r of the holding unit HCr, and a low level potential is held at node nd1r of the holding unit HCr, Let it be “0”.

[0389] The potentials corresponding to the weighting coefficients are held in the holding units HC and HCr, respectively. Therefore, the potentials of the gates of the transistors M8 and M8r are determined. Here, by applying a potential to the wire XL according to the value of the neuron signal, , the current flowing from the circuit MP to the wiring IL and / or the wiring ILB is determined. When a high-level potential is applied to L as the second data of "1", the constant voltage applied by the wiring VL is applied to a first terminal of the transistor M8 and a first terminal of the transistor M8r. When the potential of the gate of the transistor M8 is at a high level potential, the transistor M8 A current flows between the first and second terminals of the transistor M8, and the potential of the gate of the transistor M8 becomes low. When the potential is at the same level, no current flows between the first and second terminals of transistor M8. When the potential of the gate of the transistor M8r is at a high level potential, A current flows between the first and second terminals of the transistor M8r, and the potential at the gate of the transistor M8r becomes low. When the transistor M8r is at the ground potential, no current flows between the first and second terminals of the transistor M8r. Also, for example, when a low level potential is applied to the wiring XL as the second data "0", A wiring VL is provided between the first terminal of the transistor M8 and the first terminal of the transistor M8r. Since no constant voltage is applied, the current between the first and second terminals of each transistor is It doesn't flow.

[0390] In other words, to summarize the above, the product of the weight coefficient and the neuron signal value is "+1". When the voltage is high, a predetermined current flows from the circuit MC to the wiring OL, and a predetermined current flows from the circuit MCr to the wiring OLB. When the product of the weight coefficient and the neuron signal value is "-1", the A specified current flows from circuit MCr to wiring OLB, and a specified current flows from circuit MC to wiring OL. Also, when the product of the weight coefficient and the value of the neuron signal is "0", No current flows through the wiring OL, and the predetermined current does not flow from the circuit MCr to the wiring OLB.

[0391] As described above, the circuit MP of FIG. 24A has the same weighting coefficient as the circuit MP described in the seventh configuration example. The three values ​​are "+1", "-1", and "0", and the neuron signal (calculated value) is "+1" and "0". The circuit MP of FIG. 24A can calculate the product of the two values ​​of and . As with the MP circuit, the weighting coefficients can be analog values ​​or multi-bit (multi-valued) digital values. That's fine.

[0392] 24A, which can be applied to an arithmetic circuit that is a semiconductor device of one embodiment of the present invention. may be changed as appropriate depending on the situation.

[0393] For example, when the circuit MP of FIG. 24A is applied to the arithmetic circuit 130 of FIG. 7, the circuit MP of FIG. The MP circuit can be changed to the circuit MP shown in FIG. In the circuit MP of A, the wiring OL and the wiring IL are combined into a single wiring IOL. In addition, the wiring OLB and wiring ILB are combined into a single wiring called wiring IOLB. The wiring XL shown in FIG. 24B corresponds to the wiring XLS[1] to the wiring XLS[2] shown in FIG. XLS[m], and the wiring WL shown in FIG. 24B corresponds to the wiring WLS shown in FIG. It corresponds to any one of wirings [1] to WLS[m].

[0394] Furthermore, circuits that can be applied to the circuit MP of FIG. 5A are not limited to the circuit MP of FIG. 24A.

[0395] For example, the circuit MP of FIG. 18A described in the configuration example 4 can be applied to the circuit MP of FIG. 5A. The circuit MP shown in FIG. 25A can be applied to the circuit MP of FIG. 18A, and a load circuit LCr. The operation of FIG. 25A is the same as that of the circuit MP in FIG. 24A. Please refer to the explanation of the operation example of the circuit MP etc. in FIG. 18A.

[0396] For example, when the circuit MP of FIG. 25A is applied to the arithmetic circuit 130 of FIG. 7, The circuit MP shown in FIG. 25B can be configured as follows: In the circuit MP of FIG. 25A, the wiring OL and the wiring IL are connected as a single wiring IOL. The wiring OLB and the wiring ILB are combined into a single wiring called wiring IOLB. Furthermore, the transistor M1 and the transistor M1r are not provided. The wiring XL shown in FIG. 25B is any one of the wirings XLS[1] to XLS[m] shown in FIG. 7. The wiring WL shown in FIG. 25B corresponds to one of the wirings WLS[1] to WL shown in FIG. It corresponds to one of S[m].

[0397] Also, for example, the circuit MP of FIG. 20A described in the configuration example 5 can be applied to the circuit MP of FIG. 5A. The circuit MP shown in FIG. 26A can be modified to a circuit that can be applied to the circuit MP of FIG. 20A, the inverter circuit INV1 and the inverter circuit IN V2, and inverter circuits INV1r and INV2r. The circuit MP in FIG. 26A includes a transistor M3, a transistor The transistor M3r, the transistor M4, and the transistor M4r are not provided. For the operation of the circuit MP, please refer to the explanation of the operation examples of the circuit MP in FIG. 24A and the circuit MP in FIG. 20A. do.

[0398] Also, for example, the circuit MP of FIG. 20B described in the configuration example 5 can be applied to the circuit MP of FIG. 5A. The circuit MP shown in FIG. 26B can be modified to a circuit that can be applied to the circuit MP of FIG. 5A. 20B, the inverter circuit INV1 and the inverter circuit IN The circuit MP in FIG. 26B includes a transistor M3, a transistor The transistors M3r, M4, and M4r are not provided. For the operation of B, please refer to the explanation of the operation examples of the circuit MP of FIG. 24A, the circuit MP of FIG. 20B, etc. To pour drinks.

[0399] Also, for example, the circuit MP of FIG. 22A described in the configuration example 7 can be applied to the circuit MP of FIG. 5A. The circuit MP shown in FIG. 27A can be applied to the circuit MP of FIG. 5A. This circuit is a modification of the circuit MP of FIG. 22A. The second terminal of the capacitance element C1 is electrically connected to the wiring VL, and the third terminal of the capacitance element C1r is electrically connected to the wiring VL. The first terminal of transistor M2 is electrically connected to the wiring VL. The first terminal of the transistor M2 is electrically connected to the first terminal of the transistor MZ. This circuit differs from the circuit MP of FIG. 22A in that it does not include the transistor M3 and the transistor M3r. The operation of FIG. 27A is the same as that of the circuit MP of FIG. 24A, the circuit MP of FIG. 22A, etc. Please refer to the explanation of the operation example.

[0400] For example, when the circuit MP of FIG. 27A is applied to the arithmetic circuit 120 of FIG. 6, The circuit MP shown in FIG. 27B can be modified to have the following configuration: In the circuit MP of FIG. 27A, the wiring IL and the wiring ILB are connected as a single wiring IL. The wiring XL shown in FIG. 27B is the wiring XLS shown in FIG. The wiring WL shown in FIG. 27B corresponds to any one of the wirings XLS[1] to XLS[m]. 1 corresponds to any one of the wirings WLS[1] to WLS[m] shown.

[0401] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0402] (Embodiment 3) In this embodiment mode, an OS transistor applicable to the semiconductor device described in the above embodiment mode will be described. An example of the configuration of the data will be described below.

[0403] <Configuration example of semiconductor device> The semiconductor device shown in FIG. 28 includes a transistor 300, a transistor 500, and a capacitor element 30A is a cross-sectional view of the transistor 500 in the channel length direction. 30B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 30C is a cross-sectional view of the transistor 500 in the channel width direction. 1 is a cross-sectional view of a transistor 300 in the channel width direction.

[0404] The transistor 500 is a transistor having a metal oxide in a channel formation region (OS transistor). Since the off-state current of the transistor 500 is small, it is , in particular, the transistors M1 and M3 of the circuit MP included in the arithmetic circuit 110, By using it in transistor M4, etc., it is possible to retain written data for a long period of time. In other words, it is possible to perform refresh operations less frequently or Since no operation is required, the power consumption of the semiconductor device can be reduced.

[0405] The transistor 500 is provided above the transistor 300, and the capacitance element 600 is provided above the transistor 300. The capacitor 600 is provided above the transistor 300 and the transistor 500. can be the capacitive element C1, the capacitive element C1r, etc. in the circuit MP.

[0406] The transistor 300 is disposed on a substrate 311, and includes a conductor 316, an insulator 315, and a substrate a semiconductor region 313 formed of a part of the semiconductor region 311; The transistor 300 has a resistive region 314a and a low resistive region 314b. For example, the present invention can be applied to the transistors in the above embodiments.

[0407] The transistor 300 is formed by forming a semiconductor region 313 on the upper surface thereof and a channel region thereof as shown in FIG. 30C. The side surfaces in the width direction are covered with the conductor 316 via the insulator 315. By making the resistor 300 a fin type, the effective channel width is increased, and This can improve the on-characteristics of the transistor 300. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300. .

[0408] The transistor 300 may be either a p-channel type or an n-channel type. .

[0409] The region where the channel of the semiconductor region 313 is formed, the region nearby, the source region, or the drain region In the low resistance region 314a and the low resistance region 314b, which are to be the drain region, silicon It is preferable that the material contains a semiconductor such as a silicon-based semiconductor, and it is preferable that the material contains single crystal silicon. are Ge (germanium), SiGe (silicon germanium), and GaAs (gallium arsenide). Alternatively, the insulating layer 12 may be formed of a material containing gallium aluminum arsenide (GaAlAs), GaAlAs (gallium aluminum arsenide), or the like. It uses silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 30 may be formed by using GaAs and GaAlAs. 0 stands for HEMT (High Electron Mobility Transistor) ) can also be used.

[0410] The low resistance region 314a and the low resistance region 314b are semiconductor regions applied to the semiconductor region 313. In addition to the material, elements that give n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. It contains an element that provides electrical conductivity.

[0411] The conductor 316, which functions as a gate electrode, is made of arsenic, phosphorus, or the like, which provides n-type conductivity. Semiconductor materials such as silicon that contain elements or elements that give them p-type conductivity, such as boron Conductive materials such as aluminum, metal, alloy, or metal oxide materials can be used.

[0412] Since the work function is determined by the material of the conductor, it is necessary to select the material of the conductor. Specifically, the conductor is made of nitride silicon, and the threshold voltage of the transistor can be adjusted. It is preferable to use materials such as tantalum or tantalum nitride. To achieve this, metal materials such as tungsten and aluminum are used as layers for the conductor. It is preferable to use tungsten, in particular, in terms of heat resistance.

[0413] The transistor 300 shown in FIG. 28 is an example, and the structure is not limited to this. An appropriate transistor may be used depending on the structure and driving method. In the case of a unipolar circuit using only transistors, the structure of transistor 300 is as shown in FIG. The structure of the transistor 500 may be similar to that of the transistor 500 including an oxide semiconductor. The transistor 500 will be described in detail below.

[0414] Over the transistor 300 are insulators 320, 322, 324, and The bodies 326 are stacked one on top of the other.

[0415] The insulators 320, 322, 324, and 326 may be, for example, oxide. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxide Aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0416] In this specification, silicon oxynitride refers to a material having a higher content of oxygen than nitrogen in its composition. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen. In this specification, aluminum oxynitride refers to a material with a high content. Aluminum oxide nitride is a material that has a higher oxygen content than nitrogen. It refers to a material that contains more nitrogen than oxygen as a constituent.

[0417] The insulator 322 serves to eliminate a step caused by the transistor 300 and other components disposed below it. For example, the top surface of the insulator 322 may have a function as a planarizing film. To improve flatness, the surface is flattened by a planarization process using chemical mechanical polishing (CMP) or other methods. It may be possible.

[0418] The insulator 324 is also provided with a substrate 311 or a transistor 300, etc. A film having a barrier property that prevents hydrogen and impurities from diffusing is used in the area where the capacitor 500 is provided. It is preferable that

[0419] An example of a film having a barrier property against hydrogen is silicon nitride formed by CVD. Here, a semiconductor having an oxide semiconductor such as the transistor 500 can be used. The diffusion of hydrogen into semiconductor elements can cause a deterioration in the characteristics of the semiconductor elements. Therefore, a film that suppresses hydrogen diffusion is provided between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film that reduces the amount of hydrogen desorption. The membrane is thin.

[0420] The amount of hydrogen desorption can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorbed from the insulator 324 can be determined by TDS analysis as follows: In the range of 50°C to 500°C, the amount of desorption converted to hydrogen atoms is Converted to a hit, it's 10 x 10 15 atoms / cm 2 Less than or equal to 5 x 10 15 a toms / cm 2 The following is fine.

[0421] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, The dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the insulator 326 is preferably 0.7 times or less than the relative dielectric constant of the insulator 324, and more preferably 0.6 times or less. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. can be reduced.

[0422] The insulators 320, 322, 324, and 326 are connected to the capacitance element 6. 00, or the conductor 328 and the conductor 330 connected to the transistor 500 are embedded. The conductors 328 and 330 function as plugs or wiring. In addition, the conductors that function as plugs or wiring are grouped together to form the same structure. In addition, in this specification and the like, a wiring and a plug connected to the wiring may be In other words, when a part of the conductor functions as a wiring, In some cases, a portion of the conductor functions as a plug.

[0423] The materials for each plug and wiring (conductor 328, conductor 330, etc.) include metal materials, alloys, and the like. Conductive materials such as gold, metal nitride, or metal oxide materials are used in a single layer or laminated layers. High-melting-point materials such as tungsten and molybdenum, which are both heat-resistant and conductive, can be used. It is preferable to use a material such as tungsten, or aluminum. It is preferable to form the wiring board from a low-resistance conductive material such as copper. This can reduce the wiring resistance.

[0424] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring that connects to the transistor 300. The conductor 356 is made of the same material as the conductors 328 and 330. It is possible.

[0425] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 350 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0426] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the overall conductivity. In this case, the tantalum nitride layer having a barrier property against hydrogen is It is preferable that the insulating body 350 has a structure in which the insulating body 350 is in contact with the insulating body 350.

[0427] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. An insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed on the insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0428] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 360 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0429] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. An insulator 370, an insulator 372, and an insulator 374 are stacked in this order. In addition, a conductor 376 is formed on the insulators 370, 372, and 374. The conductor 376 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0430] For example, the insulator 370 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. In particular, an insulator 370 having a barrier property against hydrogen is useful. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0431] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. An insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed on the insulators 380, 382, ​​and 384. The conductor 386 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0432] For example, the insulator 380 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulator 380 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0433] In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the conductor 376 The wiring layer including the conductor 386 has been described above. The semiconductor device is not limited to this. Alternatively, the number of wiring layers may be three or less, or five or more wiring layers similar to the wiring layer including the conductor 356 may be provided. Good too.

[0434] On the insulator 384, an insulator 510, an insulator 512, an insulator 514, and an insulator 516 are formed. , are stacked in this order. It is preferable that any of the bodies 516 is made of a material that has a barrier property against oxygen and hydrogen. .

[0435] For example, the insulator 510 and the insulator 514 may include, for example, the substrate 311 or the transistor. Hydrogen and impurities diffuse from the region where the capacitor 300 is provided to the region where the transistor 500 is provided. It is preferable to use a film having a barrier property that prevents the diffusion of the insulator 324. The same materials as those mentioned above can be used.

[0436] As an example of a film with barrier properties against hydrogen, silicon nitride formed by CVD is used. Here, a semiconductor element including an oxide semiconductor, such as the transistor 500, However, the diffusion of hydrogen may deteriorate the characteristics of the semiconductor element. A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen. do.

[0437] In addition, as a film having a barrier property against hydrogen, for example, an insulator 510 and an insulator 5 14 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable.

[0438] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. Therefore, it has a high blocking effect that prevents impurities such as acid and moisture from passing through the membrane. Aluminum oxide is a material that can absorb impurities such as hydrogen and moisture during and after the transistor manufacturing process. This can prevent impurities from being mixed into the transistor 500. Therefore, the release of oxygen from the oxide constituting the transistor 5 can be suppressed. Suitable for use as a protective film against 00.

[0439] For example, the insulators 512 and 516 may be made of the same material as the insulator 320. In addition, by using materials with a relatively low dielectric constant for these insulators, , the parasitic capacitance occurring between the wirings can be reduced. A silicon oxide film, a silicon oxynitride film, or the like can be used as the film 516 .

[0440] In addition, the insulators 510, 512, 514, and 516 are provided with conductors 5 18, and conductors (for example, conductor 503) that constitute the transistor 500 are embedded. Note that the conductor 518 is connected to the capacitor 600 or the transistor 300. The conductor 518 functions as a plug or a wiring. It can be provided using the same material as 30.

[0441] In particular, the insulator 510 and the conductor 518 in the area in contact with the insulator 514 are free of oxygen, hydrogen, It is preferable that the conductive material has a barrier property against water. The transistor 300 and the transistor 500 have barrier properties against oxygen, hydrogen, and water. The layer can be separated, and hydrogen diffusion from transistor 300 to transistor 500 can be suppressed.

[0442] Above the insulator 516 is the transistor 500 .

[0443] As shown in FIGS. 30A and 30B, the transistor 500 includes an insulator 514 and an insulator 516. The conductor 503 is disposed so as to be embedded in the insulator 516, and the insulator 516 and the conductor 50 3, an insulator 520 disposed on the insulator 520, and an insulator 522 disposed on the insulator 520. An insulator 524 is disposed on the insulator 522, and an oxide 53 is disposed on the insulator 524. 530a, oxide 530b disposed on oxide 530a, and oxide 530b disposed on oxide 530b. Conductor 542a and conductor 542b are spaced apart, and conductor 542a and conductor 54 2b, and an opening is formed between the conductors 542a and 542b. The edge 580, the oxide 530c disposed on the bottom and side surfaces of the opening, and the shape of the oxide 530c an insulator 550 disposed on the forming surface; and a conductor 560 disposed on the forming surface of the insulator 550; It has.

[0444] As shown in FIGS. 30A and 30B, the oxide 530a, the oxide 530b, and the conductive The insulator 544 is disposed between the conductor 542a and the insulator 580, and the conductor 542b. As shown in FIGS. 30A and 30B, the conductor 560 is preferably made of an insulator 560. 50, and a conductor 560a provided inside the conductor 560a. It is preferable that the conductive material 560b is provided. As shown, an insulator 574 is disposed over an insulator 580, a conductor 560, and an insulator 550. It is preferable that the

[0445] In the following, the oxide 530a, the oxide 530b, and the oxide 530c will be collectively referred to as oxides 530a, 530b, and 530c. It is sometimes called oxide 530.

[0446] In the transistor 500, an oxide is formed in the region where the channel is formed and in the vicinity thereof. 5 shows a structure in which three layers of oxide 530a, oxide 530b, and oxide 530c are stacked. However, the present invention is not limited to this. For example, a single layer of oxide 530b, an oxide a two-layer structure of oxide 530b and oxide 530a; a two-layer structure of oxide 530b and oxide 530c; Alternatively, a stacked structure of four or more layers may be provided. Although the conductive body 560 is shown as a two-layer laminated structure, the present invention is not limited to this. For example, the conductor 560 may have a single layer structure or a laminated structure of three or more layers. 28 and 30A is an example, and the structure of the transistor 500 is not limited to this example. It is only necessary to use an appropriate transistor depending on the circuit configuration and driving method.

[0447] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and The conductor 542b functions as a source electrode and a drain electrode, respectively. The conductor 560 is sandwiched between the opening of the insulator 580 and the conductors 542a and 542b. The conductor 560, the conductor 542a, and the conductor 542b are formed so as to be embedded in the region. The placement of 42b is selected to be self-aligned with the opening of the insulator 580. In the transistor 500, the gate electrode is self-aligned between the source electrode and the drain electrode. Therefore, the conductor 560 can be positioned with a margin for alignment. Since the transistor 500 can be formed without any additional wiring, the area occupied by the transistor 500 can be reduced. This allows for miniaturization and high integration of semiconductor devices.

[0448] Furthermore, the conductor 560 is self-aligned in the region between the conductors 542a and 542b. Since the conductor 560 is formed, the conductor 560 has an overlapping region with the conductor 542a or the conductor 542b. As a result, the gap formed between the conductor 560 and the conductors 542a and 542b is Therefore, the switching speed of the transistor 500 can be improved. This improves the sound quality and provides high frequency characteristics.

[0449] Conductor 560 may function as a first gate (also called a top gate) electrode. The conductor 503 also functions as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor 503 may be different from the potential applied to the conductor 560. The threshold voltage of the transistor 500 is controlled by changing them independently without linking them together. In particular, applying a negative potential to the conductor 503 can turn on the transistor 5 It is possible to increase the threshold voltage of 00 to be higher than 0V and reduce the off-current. Therefore, when a negative potential is applied to the conductor 503, the conductor 560 This can reduce the drain current when the potential applied to is 0V.

[0450] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, The electric field and the electric field generated by the conductor 503 are connected, and a channel is formed in the oxide 530. In this specification and the like, the first gate electrode and the second gate electrode can cover the region where the first gate electrode and the second gate electrode are formed. The structure of a transistor in which the electric field of the gate electrode electrically surrounds the channel formation region is called This is called a surrounded channel (S-channel) structure.

[0451] The conductor 503 has the same structure as the conductor 518, and the insulators 514 and 5 Conductor 503a is formed in contact with the inner wall of opening 16, and conductor 503b is formed further inside. In the transistor 500, the conductor 503a and the conductor 503b are stacked. However, the present invention is not limited to this. The body 503 may be configured as a single layer or a laminated structure of three or more layers.

[0452] Here, the conductor 503a is a diffusion layer for impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has the function of suppressing the impurities (i.e., the impurities are less likely to permeate). Alternatively, the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is suppressed. It is preferable to use a conductive material that has the function of being difficult to permeate by the above oxygen. In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of the above impurities or the above The function is to suppress the diffusion of any one or all of the oxygen.

[0453] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503 This can prevent b from being oxidized and the electrical conductivity from decreasing.

[0454] When the conductor 503 also functions as a wiring, the conductor 503b is made of tungsten, copper, or the like. It is preferable to use a conductive material having high conductivity, such as aluminum or aluminum-based material. Although the conductor 503b is illustrated as a single layer, it may have a laminated structure. It may also be a laminate of titanium dioxide and the above conductive material.

[0455] Insulator 520, insulator 522, insulator 524, and insulator 550 form a second gate insulator. It functions as a membrane.

[0456] Here, the insulator 524 in contact with the oxide 530 has more oxygen than the stoichiometric composition. It is preferable to use an insulator that contains a large amount of oxygen. That is, the insulator 524 has an excess oxygen region. It is preferable that the insulator containing such excess oxygen is formed in the oxide 530. By providing the oxide 530 in contact with the oxide 530, oxygen vacancies in the oxide 530 are reduced, and the signal quality of the transistor 500 is improved. The reliability can be improved.

[0457] As an insulator having an excess oxygen region, specifically, an oxide in which a part of oxygen is released by heating is used. It is preferable to use oxide materials. Oxides that release oxygen when heated are called TDS (Th Thermal Desorption Spectroscopy (DSS) analysis revealed that the oxygen atoms The converted amount of oxygen desorption is 1.0 x 10 18 atoms / cm 3 or more, preferably 1.0 x10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / c m 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is 100°C or higher and 700°C or lower. The temperature range is preferably from 0°C to 400°C.

[0458] In addition, the insulator having the excess oxygen region and the oxide 530 are brought into contact with each other and subjected to heat treatment. One or more of microwave treatment and RF treatment may be performed. By performing this, water or hydrogen in the oxide 530 can be removed. At 530, a reaction occurs in which the VoH bond is broken, in other words, "V O H→V O + The reaction "H" occurs, and some of the hydrogen generated at this time is It combines with oxygen to form H2O, which is then removed from the oxide 530 or the insulators adjacent to the oxide 530. In addition, some of the hydrogen may be transferred to the conductor 542 (the conductor 542a and the conductor 542b) or may be captured (also called gettered).

[0459] The microwave treatment may be carried out using, for example, an apparatus having a power source that generates high-density plasma. Alternatively, it is preferable to use a device having a power source that applies RF to the substrate side. By using a gas containing oxygen and high density plasma, high density oxygen radicals are generated. By applying RF to the substrate side, the high density plasma generated Oxygen radicals are efficiently introduced into the oxide 530 or into the insulator near the oxide 530. The microwave treatment can be carried out at a pressure of 133 Pa or more, preferably 200 The microwave treatment may be performed at a pressure of 400 Pa or more, more preferably 400 Pa or more. The gases introduced into the device are, for example, oxygen and argon, with an oxygen flow rate ratio (O / (O2+Ar)) is set to 50% or less, preferably 10% or more and 30% or less.

[0460] In addition, during the manufacturing process of the transistor 500, the surface of the oxide 530 is exposed. The heat treatment is preferably carried out at a temperature of, for example, 100° C. or higher and 450° C. or lower. The heat treatment is preferably performed at a temperature of 350° C. or higher and 400° C. or lower. Or in an inert gas atmosphere, or oxidizing gas is 10 ppm or more, 1% or more, or For example, it is preferable to carry out the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 530, and oxygen vacancies (V O ) can be reduced. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out under nitrogen gas or nitrogen gas. After heat treatment in an active gas atmosphere, oxidizing gas was added at 10p to compensate for the oxygen that was released. The treatment may be carried out in an atmosphere containing at least pm, at least 1%, or at least 10% of an oxidizing gas. After heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more, Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0461] In addition, by performing an oxygen addition treatment on the oxide 530, oxygen vacancies in the oxide 530 are filled with oxygen. In other words, "V O +O→null” reaction. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530. This allows the hydrogen to be removed as H2O (dehydration). The hydrogen remaining in the substance 530 recombines with the oxygen vacancy to form V. O inhibits the formation of H It is possible.

[0462] Also, if the insulator 524 has an excess oxygen region, the insulator 522 may be oxygen-rich (e.g., It has the function of suppressing the diffusion of oxygen atoms, oxygen molecules, etc. (the oxygen is less likely to permeate) It is preferable that:

[0463] The insulator 522 has a function of suppressing the diffusion of oxygen and impurities, and the oxide 530 The oxygen contained in the conductor 503 is preferably not diffused to the insulator 520 side. This can prevent the insulator 524 and the oxide 530 from reacting with oxygen.

[0464] The insulator 522 may be, for example, aluminum oxide, hafnium oxide, aluminum and hafnium oxide. oxides containing ammonium (hafnium aluminate), tantalum oxide, zirconium oxide, titanium Lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba Insulators containing so-called high-k materials such as (Sr, Sr)TiO3 (BST) are used as single layers or laminated layers. As transistors become smaller and more highly integrated, the gate insulating layer Thinning the film can cause problems such as leakage current. Functions as a gate insulating film By using a high-k material as the insulator, the transistor behavior can be improved while maintaining the physical thickness. This makes it possible to reduce the gate potential during operation.

[0465] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the oxygen is difficult to penetrate) ) Use an insulator containing oxide of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an oxide of aluminum or hafnium as an insulator. Aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium It is preferable to use a material such as aluminum aluminate. When formed, the insulator 522 prevents oxygen from being released from the oxide 530 and prevents the transistor 500 from being damaged. The layer functions as a layer that suppresses the intrusion of impurities such as hydrogen from the surrounding area into the oxide 530.

[0466] Alternatively, for example, aluminum oxide, bismuth oxide, or germanium oxide may be added to these insulators. Niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Alternatively, zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the edge.

[0467] The insulator 520 is preferably thermally stable. For example, silicon oxide and Silicon oxide nitride and silicon oxynitride are suitable because they are thermally stable. By combining an insulator with silicon oxide or silicon oxynitride, it is possible to obtain a thermally stable Furthermore, it is possible to obtain the insulator 520 having a laminated structure with a high relative dielectric constant.

[0468] 30A and 30B, the transistor 500 has a three-layer stack structure. As the second gate insulating film, an insulator 520, an insulator 522, and an insulator 524 are illustrated. However, the second gate insulating film may have a single layer, two layers, or a laminated structure of four or more layers. In this case, it is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials. Good too.

[0469] The transistor 500 includes an oxide 530 including a channel formation region, and an oxide semiconductor It is preferable to use a functional metal oxide. For example, the oxide 530 is In-M- Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryl Sodium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, la tantalum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium It is preferable to use a metal oxide such as one or more selected from the following. Examples of the In-M-Zn oxide that can be used as the In-Zn oxide include CAAC-OS, The oxide 530 is preferably an In—Ga oxide, an I n-Zn oxide may also be used.

[0470] Furthermore, it is preferable to use a metal oxide with a low carrier concentration for the transistor 500. When the carrier concentration of the metal oxide is reduced, the impurity concentration in the metal oxide is reduced. In this specification and the like, the impurity concentration is low and the defect level density is low. A low level density is called high purity intrinsic or substantially high purity intrinsic. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, Examples include rubber and silicon.

[0471] In particular, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. In this case, oxygen vacancies may be formed in the metal oxide. When an oxygen atom is introduced, the oxygen vacancy and hydrogen bond to form V O May form H. V O H is for Donna It functions as a carrier and electrons are generated. It may combine with oxygen to produce electrons, which are carriers. Transistors using metal oxides containing a large amount of silicon tend to be normally on. In addition, hydrogen in metal oxides is easily moved by stresses such as heat and electric fields. If the metal oxide contains a large amount of hydrogen, the reliability of the transistor may be reduced. In one aspect of the invention, V in oxide 530 O Reduce H as much as possible and use high purity intrinsic or It is preferable that V is substantially intrinsic with high purity. O Metal with sufficiently reduced H To obtain the oxide, impurities such as water and hydrogen must be removed from the metal oxide (dehydration, This is sometimes referred to as oxidation treatment.) and oxygen deficiency is compensated for by supplying oxygen to the metal oxide. It is important to note that this is sometimes referred to as oxygenation treatment. O Impurities such as H are not enough By using a metal oxide that has been reduced to a low level in the channel formation region of a transistor, stable current can be obtained. It can be given a special characteristic.

[0472] The defect where hydrogen has entered the oxygen vacancy can function as a donor for the metal oxide. However, it is difficult to quantitatively evaluate the defects. Therefore, in this specification, metal As a parameter of the oxide, instead of donor concentration, we use the capacitance assuming a state where no electric field is applied. In other words, the "carrier concentration" described in this specification and the like is This can sometimes be rephrased as "energy concentration."

[0473] Therefore, when a metal oxide is used for the oxide 530, the hydrogen in the metal oxide should be as low as possible. Specifically, in the case of metal oxides, secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) The resulting hydrogen concentration is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 Less than, more Preferably 1 x 10 18 atoms / cm 3 Less than 100%. Impurities such as hydrogen are sufficiently reduced. By using this metal oxide in the channel formation region of a transistor, stable electrical characteristics can be achieved. can be granted.

[0474] In addition, when a metal oxide is used for the oxide 530, the capacitance of the metal oxide in the channel formation region is Rear density is 1 x 10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 Not yet It is more preferable that the 16 cm -3 more preferably less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 Less than It is more preferable that the lower limit of the carrier concentration of the metal oxide in the channel formation region is There is no particular limitation on the -9 cm -3 It can be said that:

[0475] When a metal oxide is used for the oxide 530, the conductor 542 (the conductor 542a and When the oxide 530 comes into contact with the conductor 542b, the oxygen in the oxide 530 is transferred to the conductor 542. The conductor 542 may be oxidized by the oxidation of the conductor 542. It is highly likely that the conductivity of the conductor 542 will decrease. The diffusion of the conductor 542 into the oxide 530 can be expressed as the absorption of oxygen from the oxide 530 by the conductor 542. This can be done.

[0476] In addition, oxygen in the oxide 530 is converted into conductor 542 (conductor 542a and conductor 542b ) at and near the interface between the conductor 542a and the oxide 530b, and The insulating region at the interface between the conductor 542b and the oxide 530b and in the vicinity of the interface The region contains more oxygen than the conductor 542, so the region It is estimated that the region has a higher electrical resistance than the conductors 542a and 542b. The three-layer structure of the conductor 542, the region, and the oxide 530b is a metal-insulator-semiconductor. It can be considered as a three-layer structure consisting of MIS (Metal-Insulator-Se A diode junction structure called a MIS structure, or a diode junction structure mainly based on the MIS structure It is sometimes called.

[0477] The insulating region is formed between the conductor 542 and the oxide 530b. For example, the insulating region may be a conductor 542 and an oxide 530c. conductor 542 and oxide 530b, and between conductor 542 and oxide 530c. Oxide 530c may be formed between the oxide 530c.

[0478] In addition, the metal oxide that functions as a channel formation region in the oxide 530 is a band gap. It is preferable to use a material with a gap of 2 eV or more, preferably 2.5 eV or more. As shown in Fig. 1, by using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. can be reduced.

[0479] The oxide 530 has an oxide 530a under the oxide 530b, so that the oxide 530a The diffusion of impurities from structures formed below the oxide 530b can be suppressed. In addition, by having the oxide 530c on the oxide 530b, the oxide 530c can be formed. Therefore, the diffusion of impurities from the structure formed above into the oxide 530b can be suppressed. do.

[0480] The oxide 530 has a layered structure made of oxides with different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 530a, the constituent elements are preferably The atomic ratio of element M in the oxide 530b is It is preferable that the atomic ratio of the metal oxide used for the oxide 530a is larger than that of the element M. In the oxide 530b, the atomic ratio of the element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element M. In the metal oxide used, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In to the element M in the metal oxide is larger than that of In. The oxide 530c is a metal oxide that can be used for the oxide 530a or the oxide 530b. can be used.

[0481] The energy of the conduction band minimum of the oxide 530a and the oxide 530c is It is preferable that the energy of the oxide is higher than the energy of the bottom of the conduction band of oxide b. The electron affinity of oxide 530a and oxide 530c is smaller than that of oxide 530b. It is preferable that:

[0482] Here, at the junctions of the oxide 530a, the oxide 530b, and the oxide 530c, The energy level of the lower conduction band edge changes gradually. The energy levels of the conduction band minimum at the junction of 530b and oxide 530c are continuous. In order to achieve this, the oxide 530 The interface between oxide 530a and oxide 530b, and the interface between oxide 530b and oxide 530c are It is preferable to lower the defect level density of the resulting mixed layer.

[0483] Specifically, oxide 530a and oxide 530b, and oxide 530b and oxide 530c are By having a common element other than oxygen (as the main component), a mixed layer with low defect level density is formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a and oxide 530c are In-Ga-Zn oxide, Ga-Zn oxide, oxide Gallium or the like may be used.

[0484] At this time, the main path of the carriers is the oxide 530b. By configuring the oxide 530c as described above, the interface between the oxide 530a and the oxide 530b and the oxide The defect state density at the interface between the substrate 530b and the oxide 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 has a high On-current can be obtained.

[0485] On the oxide 530b, a conductor 542a is formed, which functions as a source electrode and a drain electrode. The conductors 542a and 542b are provided. Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, ungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium , beryllium, indium, ruthenium, iridium, strontium, and lanthanum The metal elements mentioned above, or alloys containing the above metal elements, or combinations of the above metal elements It is preferable to use an alloy of tantalum nitride, titanium nitride, tungsten nitride, ...

Claims

1. A semiconductor device having a first circuit and a second circuit, the first circuit includes first to fourth transistors and a first capacitor; the second circuit includes fifth to eighth transistors and a second capacitor; one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the first transistor is electrically connected to a first electrode of the first capacitor; one of a source and a drain of the second transistor is electrically connected to a second electrode of the first capacitor; the other of the source and the drain of the second transistor is electrically connected to the one of the source and the drain of the third transistor; the other of the source and the drain of the second transistor is electrically connected to the one of the source and the drain of the fourth transistor; the other of the source and the drain of the third transistor is electrically connected to a first wiring; a gate of the third transistor electrically connected to a first input wiring; the other of the source and the drain of the fourth transistor is electrically connected to a second wiring; a gate of the third transistor is electrically connected to the first input wiring; one of the source and the drain of the fifth transistor is electrically connected to the gate of the sixth transistor; one of a source and a drain of the fifth transistor is electrically connected to a first electrode of the second capacitor; one of a source and a drain of the sixth transistor is electrically connected to a second electrode of the second capacitor; the other of the source and the drain of the sixth transistor is electrically connected to the one of the source and the drain of the seventh transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the eighth transistor; the other of the source and the drain of the seventh transistor is electrically connected to the second wiring; a gate of the seventh transistor is electrically connected to the first input wiring; the other of the source and the drain of the eighth transistor is electrically connected to the first wiring; a gate of the seventh transistor electrically connected to the first input wiring; Semiconductor device.

2. A semiconductor device according to claim 1, The semiconductor device performs neural network calculations. electronic equipment.

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