Semiconductor Devices

Abstract

To provide a transistor that is excellent in electric characteristics (e.g., on-state current, electron field-effect mobility, frequency characteristics, and the like).SOLUTION: A transistor has: an oxide semiconductor layer having a channel formation region; first and second gate electrodes; and a source electrode and a drain electrode. The first and second gate electrodes are provided while interposing the oxide semiconductor layer therebetween. The oxide semiconductor layer has a pair of lateral faces in contact with the source electrode and the drain electrode, and has a region surrounded by the first and second gate electrodes without interposing the source and drain electrodes.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, relating to the manufacture or composition of matter, especially One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, or any of these devices. The present invention relates to a driving method or a manufacturing method thereof.

[0002] In this specification, a semiconductor device refers to a semiconductor element (transistor, diode, etc.). It also refers to a circuit that includes a semiconductor, and a device that has the circuit. For example, integrated circuits, chips equipped with integrated circuits, display devices, light-emitting devices, Lighting devices, electronic devices, and the like may include semiconductor devices. [Background technology]

[0003] Transistors are used in various electronic devices such as integrated circuits (ICs) and image display devices (display devices). Silicon-based semiconductor materials are widely used as semiconductors that can be applied to transistors. Although it is well known that oxide semiconductors are used for semiconductors, oxide semiconductors are attracting attention as other materials.

[0004] For example, amorphous oxides containing indium (In), gallium (Ga), and zinc (Zn) Patent Document 1 discloses a transistor using a compound semiconductor layer.

[0005] In addition, a technique for improving carrier mobility by forming an oxide semiconductor layer into a stacked structure has been developed. This is disclosed in Patent Document 2 and Patent Document 3.

[0006] In addition, as one of the means for reducing the size and narrowing the frame of active matrix display devices, It is known to fabricate the driver circuit together with the pixel circuit on the same substrate. The transistors are either n-channel or p-channel. Therefore, it is possible to reduce the number of manufacturing steps, reduce manufacturing costs, and shorten the bezel width. To create a narrow display, a single-conductivity transistor is used instead of a CMOS circuit. It is preferable to design the driver in

[0007] The main circuit of the driver circuit of the display device is a shift register. In the above and 5, a shift register composed of transistors using an oxide semiconductor layer is developed. is shown. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-138934 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-124360 [Patent Document 4] Japanese Patent Application Laid-Open No. 2011-090761 [Patent Document 5] Japanese Patent Application Laid-Open No. 2011-209714 Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to provide a semiconductor device whose threshold voltage can be controlled. and / or semiconductors with excellent electrical properties (e.g., on-state current, field-effect mobility, frequency characteristics, etc.). The present invention provides a conductor device.

[0010] An object of one embodiment of the present invention is to improve the reliability of a semiconductor device including transistors having the same conductivity type. Or, the driving frequency of the driving circuit is improved. The object is to provide a novel semiconductor device.

[0011] It should be noted that the description of multiple problems does not preclude the existence of each problem. The embodiment does not necessarily solve all of these problems. These problems are also clearly evident from the description of the present invention, such as drawings and claims. This could be a form of challenge for Ming. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer having a channel formation region, first and second gate electrodes, and a gate insulating film. a first gate electrode, a first insulating layer, a second insulating layer, a source electrode, and a drain electrode; The first electrode faces the oxide semiconductor layer via the first insulating layer, and the second gate electrode faces the second insulating layer. At least one of the first and second insulating layers is provided opposite to the oxide semiconductor layer via the insulating layer. the oxide semiconductor layer is in contact with the first gate electrode at the first opening, and the oxide semiconductor layer is in contact with the source electrode, The first and second side surfaces in contact with the drain electrode and the region surrounded by the first and second gate electrodes The transistor has the following characteristics.

[0013] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer having a channel formation region and first and second gate electrodes. a first insulating layer, a second insulating layer, a source electrode, and a drain electrode; The first and second gate electrodes are provided with an oxide semiconductor layer sandwiched therebetween, and the first gate electrode is a first gate electrode and a first insulating layer disposed below the oxide semiconductor layer through the first insulating layer; the layer, the oxide semiconductor layer, the source electrode, and the drain electrode are covered with a second insulating layer; The second gate electrode is formed in at least one first opening provided in the first and second insulating layers. The oxide semiconductor layer is in contact with the first gate electrode, and the oxide semiconductor layer is in contact with the source electrode and the drain electrode. The oxide semiconductor layer has first and second side surfaces that sandwich a source electrode and a drain electrode. a semiconductor including a transistor having a region surrounded by first and second gate electrodes without It is a body device. [Effects of the Invention]

[0014] According to one embodiment of the present invention, there is provided a semiconductor device capable of controlling a threshold voltage. However, semiconductor devices with excellent electrical characteristics (for example, on-current, field-effect mobility, frequency characteristics, etc.) or a semiconductor device having high reliability, or an oxide To provide a semiconductor device in which a driver circuit and a pixel section are fabricated on the same substrate from a semiconductor film. According to one embodiment of the present invention, a novel semiconductor device can be provided. becomes.

[0015] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. , the specification, drawings, claims, etc., and It is possible to extract other effects from the claims and other descriptions. [Brief explanation of the drawings]

[0016] [Figure 1]A diagram showing an example of a transistor configuration. A: Circuit symbol. B: Plan view. C: Cross-sectional view taken along line A1-A2 in Figure B. D: Cross-sectional view taken along line B1-B2 in Figure B. [Figure 2] A diagram showing an example of a transistor configuration. A: Circuit symbol. B: Plan view. C: Cross-sectional view taken along line A1-A2 in Figure B. D: Cross-sectional view taken along line B1-B2 in Figure B. [Figure 3] A diagram showing an example of a transistor configuration. A: Circuit symbol. B: Plan view. C: Cross-sectional view taken along line A1-A2 in Figure B. D: Cross-sectional view taken along line B1-B2 in Figure B. [Figure 4] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 5] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 6] 1A and 1B are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 7] 1A and 1B are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 8] Circuit symbol diagram of an inverter circuit. [Figure 9] A: Circuit diagram showing an example of the configuration of an inverter circuit. B: Truth table for the inverter circuit. [Figure 10] A and B are circuit diagrams showing an example of the configuration of an inverter circuit. [Figure 11] A: Circuit symbol diagram of a clocked inverter circuit. B, C: Circuit diagrams showing an example of the configuration of a clocked inverter circuit. [Figure 12] A: Circuit symbol diagram of a latch circuit. B: Circuit diagram showing an example of the configuration of a latch circuit. [Figure 13] FIG. 1 is a circuit diagram showing an example of the configuration of a shift register. [Figure 14] FIG. 1 is a block diagram showing an example of the configuration of an active matrix display device. [Figure 15] 1A-1C are plan views showing an example of the configuration of a display panel. [Figure 16] FIG. 1 is an exploded perspective view showing an example of the configuration of an active matrix display device. [Figure 17]A and B are circuit diagrams showing an example of a pixel configuration. [Figure 18] FIG. 2 is a plan view showing an example of the configuration of a pixel portion. [Figure 19] FIG. 2 is a cross-sectional view showing an example of the configuration of a pixel portion. [Figure 20] AF: A diagram showing an example of the configuration of an electronic device. [Figure 21] AF: A diagram illustrating an example of how to use an RFID tag. [Figure 22] A, B: Nanobeam electron diffraction patterns of the oxide semiconductor film. [Figure 23] A and B: Schematics showing an example of a transmission electron diffraction measurement device. [Figure 24] 1 is a graph showing an example of a structural analysis by transmission electron diffraction measurement. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications may be made without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments.

[0018] In addition, several embodiments of the present invention will be described below, and the embodiments may be combined appropriately. It goes without saying that it is possible to provide several configuration examples in one embodiment. In the case where the above configurations are shown, the configuration examples can be appropriately combined.

[0019] In addition, in the drawings used to explain the embodiments of the invention, the same parts or similar functions are shown. The same reference numerals are used to denote the same parts, and repeated explanations may be omitted.

[0020] A transistor is a device that has three terminals called a gate, a source, and a drain. The two terminals that function as the source or drain are the channel type and Depending on the level of the voltage applied to each terminal, one becomes the source and the other becomes the drain. Generally, in an n-channel transistor, the terminal to which a low voltage is applied is called the source. The terminal to which high voltage is applied is called the drain. Conversely, in a p-channel transistor, The terminal to which a low voltage is applied is called the drain, and the terminal to which a high voltage is applied is called the source. In the following, in order to make it easier to understand the circuit configuration and its operation, we will use the In some cases, the explanation will be limited to one terminal being the source and the other being the drain. Depending on the method, the magnitude relationship of the voltages applied to each terminal of the transistor changes, and the The drains may be interchanged.

[0021] The transistor further includes a second gate for applying a voltage to the back channel. In that case, in order to distinguish between the two gates, The exposed terminal will be called the "front gate" and the other the "back gate."

[0022] (Embodiment 1) In this embodiment, a transistor will be described as an example of a semiconductor device. The front gate is located closer to the substrate than the semiconductor layer where the channel is formed. A gate-type transistor will now be described.

[0023] <Configuration Example 1: FET-1> FIG. 1A is a circuit symbol of a transistor according to Configuration Example 1. The transistor has a front gate. The facility has two gates, a front gate and a back gate, and the back gate is connected to the front gate. Here, the transistor represented by the circuit symbol in Figure 1A is called FET-1. Boo.

[0024] The circuit symbol in FIG. 1A indicates that the transistor (FET-1) has a width in the channel length direction of The back gate is longer than the front gate, and the back gate is formed in the semiconductor layer. The device structure is shown as follows: 1B-1D illustrate the device structure of FET-1.

[0025] Figures 1B-1D show an example of the device structure of FET-1. 1C is a cross-sectional view taken along the line A1-A2 in FIG. 1B, and FIG. 1D is a cross-sectional view taken along the line A1-A2 in FIG. FIG. 1C is a cross-sectional view taken along line B1-B2. 1D is a cross-sectional view of the transistor in the channel length direction.

[0026] The transistor 11 is formed on a substrate 100, and includes an insulating layer 101, an insulating layer 102, and a front surface. a source gate electrode 121, an oxide semiconductor (OS) layer 130, a source electrode 140S, a drain electrode 140S, a The insulating layer 10 1 and 102 are formed with openings 172 and 173. The back gate electrode 150 is in contact with the front gate electrode 121. The pole 150 is connected to the front gate electrode 121 .

[0027] The insulating layer 101 constitutes a gate insulating layer for the front gate electrode 121. 2 constitutes a gate insulating layer for the back gate electrode 150.

[0028] A transistor whose channel formation region is made of Si (hereinafter referred to as a Si transistor) is By adding impurities to the i-layer, the resistance of the Si layer can be partially reduced, resulting in a source region On the other hand, the channel forming region is made of an oxide semiconductor. An OS transistor has a source electrode or a drain electrode in an oxide semiconductor layer. By directly joining the drain electrode, a device with the electrical properties of a transistor can be created. can be obtained.

[0029] Therefore, in the transistor 11, the source electrode 140S and the drain electrode 140D are Each of the gate electrodes is provided in contact with the OS layer 130. In the transistor 11, the channel length is shortened. Therefore, in the OS layer 130, the source electrode 140S and the drain electrode 140D are in contact with each other. The regions are present on the top surface as well, but mainly on the side surfaces. The area in contact with the source electrode 140S and the drain electrode 140D exists because of the common conductive film ( 141, 142) are etched to form the source electrode 140S and the drain electrode 140D. This is because the size variations of these elements are suppressed and the elements are formed with a high yield. In addition, the source electrode 140S and the drain electrode 140S are formed on the side surfaces of the OS layer 130. This is to make the area in contact with the pole 140D as large as possible.

[0030] Here, the length L1 of the OS layer 130 shown in FIG. 1D is set to the channel length of the transistor 11. The channel length L1 is the distance between the source electrode 140S and the drain electrode 140S on the top surface of the OS layer 130. 140D. The length L2 corresponds to the length of the OS layer 130 in the channel length direction. Therefore, the region in contact with the source electrode 140S and the drain electrode 140D is the OS layer. By having the MOSFET on the side of 130, the channel length L1 can be shortened while L2 can also be shortened as much as possible. As a result, the on-current characteristics of the transistor 11 can be The frequency characteristics can be improved while ensuring the same.

[0031] The channel length L1 may be set to 0.5 μm or more. Preferably, L1 is set to 0.5 μm to 2 μm. The thickness of the OS layer 130 is preferably 0.5 μm to 1 μm. The thickness may be 150 nm or more, for example, 150 nm to 1.5 μm. The thickness of the OS layer 130 is more preferably 250 nm to 1.5 μm. However, when the OS layer 130 is composed of two metal oxide films 131 and 132, the first metal oxide film The thickness of the film 131 may be 100 nm or more, for example, 100 nm to 1000 nm. The thickness m of the second metal oxide film is preferably 200 nm to 1000 nm. The thickness of 132 may be 50 nm or more, and may be 50 nm to 500 nm, or 10 It may be set to 0 nm to 300 nm.

[0032] The OS layer 130 is sandwiched between the front gate electrode 121 and the back gate electrode 150. The channel length and the channel width of the back gate electrode 150 are The OS layer 130 is longer than the S layer 130, and the entire OS layer 130 is connected to the back gate electrode via the insulating layer 102. In the planar layout of FIG. 1B, the OS layer 130 is covered with a back gate. It is located inside the electrode 150.

[0033] In the channel width direction, openings 172 and 173 are formed in the insulating layers 101 and 102. In the openings 172 and 173, the back gate electrode 150 is in contact with the front gate electrode 12. 1 and is connected to the front gate electrode 121. Not only is the gate electrode 150 at the same potential as the front gate electrode 121, This contributes to improving the electrical characteristics of the transistor 11.

[0034] As shown in FIG. 1C, the OS layer 130 is formed on the source electrode 140S and the drain electrode 140D. The area surrounded by the front gate electrode 121 and the back gate electrode 150 without any intervening With such a device structure, the front gate electrode 121 and the back gate electrode 122 are The electric field of the gate electrode 150 can electrically surround the OS layer 130. As in the case of the gate electrode 11, the OS layer where the channel is formed is in the electric field of the gate electrode (121, 150). The device structure of a transistor is electrically surrounded by This can be called a channel (s-channel) structure.

[0035] Since the transistor 11 has an s-channel structure, the front gate electrode 121 Therefore, an electric field for inducing a channel can be effectively applied to the OS layer 130. The current driving capability of the transistor 11 is improved, and high on-current characteristics are obtained. Since the thickness can be increased, the transistor 11 can be miniaturized.

[0036] The transistor 11 is surrounded by a front gate electrode 121 and a back gate electrode 150. This allows the mechanical strength of the transistor 11 to be increased.

[0037] In FIG. 1C, the direction perpendicular to the paper surface is the direction of current flow. In order to more effectively apply the electric field of the gate electrode 121 to the OS layer 130, openings 172 and 173 are formed. The length Wc1 in the channel length direction is preferably longer than the length L2 of the OS layer 130. As a result, the portions of the back gate electrode 150 present in the openings 172 and 173 To make the electric field act efficiently on the entire side surface of the OS layer 130 in the channel width direction. can be done.

[0038] The films and other components that make up the transistor 11 will be described below.

[0039] (substrate) There is no particular limitation on the material of the substrate 100. If the substrate is a support substrate at the time of manufacturing, it will at least be able to withstand the heat treatment in the process of forming the transistor 11. For example, glass substrates, ceramic substrates, and quartz substrates are used. A substrate such as a silicon substrate or a sapphire substrate may be used as the substrate 100. Single crystal semiconductor substrates, polycrystalline semiconductor substrates, silicon germanium substrates, etc. It is also possible to apply compound semiconductor substrates, SOI substrates, etc., on these substrates. The backplane substrate on which devices such as transistors and capacitors are fabricated is called substrate 1. It can be set to 00.

[0040] In addition, when the substrate 100 is a substrate that is not a support substrate when the transistor 11 is manufactured, In this case, the heat resistance of the substrate 100 may be low, and rigidity is not particularly required. Therefore, in addition to the above-mentioned substrates, flexible substrates such as resin substrates may also be used. When the transistor 11 is fabricated, a peeling layer (tungsten oxide, a layer containing molybdenum oxide or the like) and a base insulating layer. Then, the support substrate including the release layer is separated, and the base insulating layer is formed using a resin material. The substrate 100 may be fixed to the edge layer.

[0041] (front gate electrode, back gate electrode) The front gate electrode 121 and the back gate electrode 150 may have a single layer structure or a laminated structure of two or more layers. The conductor may be a metal, an alloy, or a metal compound (e.g., , metal oxides, metal nitrides, silicides, etc.), silicon containing phosphorus, etc. Conductors containing these metals may also be those to which other elements or compounds are added.

[0042] Metals used for conductors include aluminum, chromium, copper, tantalum, titanium, and molybdenum. Examples of suitable metals include zinc, tungsten, manganese, and zirconium.

[0043] Metal oxides include, for example, indium oxide, In-Sn oxide (ITO), and In-Z n-oxides. In addition, tungsten oxide and silicon oxide are also included in these metal oxides. Metal oxides can be used as light-transmitting conductors.

[0044] For example, when the front gate electrode 121 and the back gate electrode 150 have a two-layer structure, A film in which an aluminum film is laminated on a titanium film, a film in which a titanium film is laminated on a titanium nitride film, a film in which a titanium film is laminated on a titanium nitride film, A film in which a tungsten film is laminated on a titanium film, a tantalum nitride film or a tungsten nitride film The insulating film may be formed by laminating a tungsten film on a titanium film, or a copper film on a titanium film. In addition, when a three-layer structure is used, for example, a titanium film, an aluminum film, and a titanium film are laminated in this order. The film may be formed by the above process.

[0045] Here, the front gate electrode 121 is formed of a single layer of conductor. The gate electrode 121 can be formed of a tungsten film having a thickness of 80 nm to 200 nm. The back gate electrode 150 is formed of a single layer of conductor. For example, the thickness is 80 n It can be formed of In-Sn oxide (ITO) with a thickness of m-200 nm.

[0046] (source electrode, drain electrode) The source electrode 140S and the drain electrode 140D are also formed by a single layer, similar to the front gate electrode 121. The conductive material can be formed of a layer structure or a laminated structure of two or more layers. and alloys, metal compounds (e.g., metal oxides, metal nitrides, silicides, etc.), and phosphorus-containing Silicon and other metals are used as conductors. It may also be a conductor.

[0047] Metals used for conductors include aluminum, chromium, copper, silver, tantalum, titanium, molybdenum, and Examples include iridium, tungsten, manganese, and zirconium.

[0048] When the source electrode 140S and the drain electrode 140D have a two-layer structure, the second layer is made thicker and The first layer is made of a low-resistance metal such as aluminum or copper, and is in direct contact with the OS layer 130. The characteristics of the conductor or OS layer 130 that acts as a barrier layer for the second conductor layer are It is preferable to form the front gate electrode 121 from a conductor that does not deteriorate. The same applies when the gate electrode 150 is formed of a three-layered conductor. The holes are preferably formed of a conductive material that acts as a barrier layer against the second conductive layer. .

[0049] When the source electrode 140S and the drain electrode 140D have a two-layer structure, aluminum is formed on a titanium film. a film with a tungsten film and a copper film; a film with an aluminum film and a tungsten film; a film laminated with a magnesium film, a film laminated with a copper film on a copper-magnesium-aluminum alloy film In the case of a three-layer structure, the first and second layers may be made of titanium and copper. The third layer is made of titanium, titanium nitride, molybdenum, or molybdenum nitride. The first layer is made of aluminum and copper, and the second layer is made of a low-resistance film.

[0050] (insulating layer) The insulating layers 101 and 102 can be formed of a single insulating layer or two or more insulating layers. Such insulating films include aluminum oxide, magnesium oxide, and silicon oxide. , silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide Yttrium oxide, Zirconium oxide, Lanthanum oxide, Neodymium oxide, Hafnium oxide Examples of the film include films made of titanium, tantalum oxide, Ga-Zn oxide, and the like.

[0051] Hafnium silicate (HfSiO x ), nitrogen-containing hafnium silicate (HfSi x O y N z ), nitrogen-containing hafnium aluminate (HfAl x O y N z ), hafnium oxide, By using high-k materials such as yttrium oxide, the back gate of the transistor 11 can be These insulating films can reduce gate and front gate leakage. The film can be formed by using a deposition method, a CVD method, an MBE method, an ALD method, or a PLD method.

[0052] In this specification, the term "oxynitride" refers to a compound containing more oxygen than nitrogen. The term "nitride oxide" refers to a compound that contains more nitrogen than oxygen.

[0053] When the insulating layer 101 has a multilayer structure, the insulating film in contact with the OS layer 130 is an insulator containing oxygen. (oxide, oxynitride, etc.) is preferable. Here, the insulating layer 101 is insulated from the insulating film 111. The insulating film 111 is a silicon nitride film, and the insulating film 112 is an oxide film. It is a silicon nitride film.

[0054] When the insulating layer 102 has a multilayer structure, the insulating film in contact with the OS layer 130 is an insulator containing oxygen. The insulating layer 102 is preferably a stoichiometric material (such as an oxide or an oxynitride). It is preferable to have an oxide insulating film containing more oxygen than the oxygen that satisfies the chemical composition. When an oxide insulating film contains more oxygen than the stoichiometric composition, some of the oxygen is removed by heating. The oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition is called T DS (Thermal Desorption Spectrometry) analysis revealed that The amount of oxygen released in terms of oxygen atoms is 1.0 × 10 18 atoms / cm 3 That's all, I prefer 3.0 x 10 20 atoms / cm 3 The oxide insulating film is the above-mentioned T The surface temperature of the film during DS analysis is 100°C or higher and 700°C or lower, or 100°C or lower. The temperature is preferably in the range of 500°C or higher.

[0055] Here, the insulating layer 102 has a laminated structure of insulating films 113-115. Reference numeral 14 denotes a silicon oxynitride film, and insulating film 115 is a silicon nitride film.

[0056] The thickness of the insulating film 114 is set to 30 nm to 500 nm, preferably 50 nm to 400 nm. Alternatively, a silicon oxide film may be used as the insulating film 114 instead of a silicon oxynitride film. etc. may be formed.

[0057] The second insulating film 114 is formed as an oxide insulating film that supplies oxygen to the OS layer 130. That is, the insulating film 114 contains more oxygen than the oxygen required for the stoichiometric composition. It is preferable that the number of defects is small. Typically, g= The spin density calculated from the signal appearing around 2.001 is 1.5 × 10 18 spi ns / cm 3 Less than or even 1×10 18 spins / cm 3 It is preferable that: A typical example of electron spin with a g value of 2.001 comes from the dangling bond of silicon. It is something.

[0058] The insulating film 113 serves as a path for oxygen released from the insulating film 114 to move to the OS layer 130. Therefore, it is preferable to form the insulating film by an insulating film that is permeable to oxygen and contains oxygen. The insulating film 113 serves as a barrier layer for the OS layer 130 when the insulating films 114 and 115 are formed. It still works.

[0059] In the insulating film 113, all the oxygen that has entered the insulating film 113 from the outside is transferred to the outside. When the insulating film 113 moves, or when part of the oxygen that has entered the insulating film 113 from the outside remains in the insulating film 113, When oxygen enters the insulating film 113 from the outside, the insulating film 113 When oxygen moves to the outside of the insulating film 113, oxygen moves in the insulating film 113. There are cases like this.

[0060] The insulating film 113 has fewer defects than the insulating film 114 because it is in contact with the OS layer 130. The insulating film 113 is preferably a film having a thickness calculated from an ESR signal near g=2.001. The spin density is 3×10 17 spins / cm 3 The following silicon oxide or oxynitride films: It is preferable that the film is a silicon film. Also, the film has a g value of about 1.93 (for example, 1.89 to 1.9 6) The spin density calculated from the ESR signal is 1×10 17 spins / cm 3 below , and more preferably below the lower limit of detection.

[0061] The thickness of the insulating film 113 is 5 nm to 150 nm, preferably 5 nm to 50 nm. be.

[0062] The top layer of the insulating layer 102 is formed of an insulating film 115 having a blocking effect against hydrogen and oxygen. It is more preferable to use oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. It is preferable that the insulating film has a blocking effect against metalloids, etc. The purpose of this is to prevent impurities such as hydrogen from entering the OS layer 130 and to prevent oxygen from being released from the OS layer 130. Here, a silicon nitride film is formed as the insulating film 115.

[0063] The thickness of the insulating film 115 is 50 nm to 300 nm, preferably 100 nm to 200 nm. The insulating film 115 may be formed of silicon nitride, silicon nitride oxide, aluminum nitride, or the like. Aluminum, aluminum oxide nitride, aluminum oxide, aluminum oxynitride, gallium oxide, Gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, oxynitride A film made of hafnium chloride or the like can be formed.

[0064] (Oxide semiconductor (OS) layer) The OS layer 130 has a single layer or a multilayer structure made of a metal oxide. At least one semiconductor film (oxide semiconductor film) made of metal oxide in which a panel formation region is provided is formed. The metal oxide forming the OS layer 130 may be indium oxide, Tin, zinc oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg Oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide oxide (also written as IGZO), In-Al-Zn oxide, In-Sn-Zn oxide, S n-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf -Zn oxide, In-Zr-Zn oxide, In-Ti-Zn oxide, In-Sc-Zn oxide oxide, In-Y-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In -Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu- Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In -Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide, In- Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide can be used. do.

[0065] The oxide semiconductor serving as a channel formation region of the OS layer 130 contains at least indium (In). Alternatively, those containing zinc (Zn) are preferred. Examples of such oxide semiconductors include In-G Typical examples are α-Zn oxide and In-Sn-Zn oxide. It may also contain an element that acts as a stabilizer to reduce variations in mechanical properties. Examples of suitable elements include Ga, Sn, Hf, Al, and Zr.

[0066] Here, the In-Ga-Zn oxide refers to an oxide having In, Ga, and Zn as the main components. The ratio of In, Ga, and Zn is not important. Group elements may be included.

[0067] When a large amount of hydrogen is contained in the oxide semiconductor film, the hydrogen is bonded to the oxide semiconductor. Some of the electrons become donors and generate electron carriers. The threshold voltage of the transistor is shifted in the negative direction.

[0068] In the OS layer 130 (at least in the region where the channel is formed), oxygen vacancies and hydrogen are generated. Specifically, in the OS layer 130, the secondary ion mass is preferably reduced as much as possible. Secondary Ion Mass Spectrometer (SIMS) The hydrogen concentration obtained by y) is 2 × 10 20 atoms / cm 3 Below 5x, preferably 1019 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 below , more preferably 5 × 10 18 atoms / cm 3 Less than or equal to 1×10 18 a toms / cm 3 Less than or equal to 5 × 10 17 atoms / cm 3 Below are some more good ones: Preferably 1 x 10 16 atoms / cm 3 The following applies.

[0069] When the OS layer 130 contains silicon or carbon, which is one of the group 14 elements, the OS layer As a result, oxygen vacancies increase in the OS layer 130, resulting in a low resistance. The concentration of silicon and carbon (obtained by SIMS) was 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0070] In the OS layer 130, alkali metal or alkaline earth metal The concentration is 1 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / c m 3 Alkali metals and alkaline earth metals form capacitive couplings when bonded to oxide semiconductors. This may cause a rear to be generated, which may increase the off-state current of the transistor. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the OS layer 130. It's nice.

[0071] In addition, when nitrogen is contained in an oxide semiconductor, electrons that act as carriers are generated, and the carrier density Therefore, the nitrogen concentration in the OS layer 130 is reduced as much as possible. For example, the nitrogen concentration obtained by SIMS is preferably 5×10 18 at oms / cm 3 It is preferable to do the following:

[0072] The channel formation region of the OS layer 130 is a CAAC-OS (C Axis Aligned Array) Consists of ned Crystalline Oxide Semiconductor It is preferable that the CAAC-OS has a polycrystalline structure, a microcrystalline structure, or This is because it is an oxide semiconductor with the lowest defect level density compared to an amorphous structure. The crystal structure of the metal oxide constituting the S layer 130 will be described in the fourth embodiment. .

[0073] The metal oxide constituting the OS layer 130 may have a microcrystalline structure, a polycrystalline structure, a CAAC-OS structure, or a single crystal structure. The OS layer 130 may have two or more types of crystal structures, for example, a microcrystalline structure. two or more of the following: a region of a polycrystalline structure, a region of a CAAC-OS structure, and a region of a single crystal structure The OS layer 130 may also have regions with a microcrystalline structure, a polycrystalline structure, or the like. The product of two or more of the following regions: a crystal structure region, a CAAC-OS region, and a single crystal structure region. It may have a layer structure.

[0074] The OS layer 130 may be a single layer of metal oxide or a laminate of two or more metal oxide films. When the OS layer 130 has a stacked structure, the layers constituting the OS layer 130 can be It is preferable that the metal oxide film contains at least one of the same metal. When formed as a stacked film of Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd) The atomic ratio of In, M, and Zn in each layer may be appropriately set. The common metal element is In, and the films are In-M-Zn oxide, In-M oxide, and In-Zn oxide. A suitable combination of oxide films may also be used.

[0075] For example, when the metal oxide film 131 is an In—Ga—Zn oxide film, the metal oxide film 132 is , an In-Ga-Zn oxide film containing more Ga than the metal oxide film 131, or an In-Ga a oxide film.

[0076] Here, the OS layer 130 has a two-layer structure of a metal oxide film 131 and a metal oxide film 132. The metal oxide film 131 on the front gate electrode 121 side has a channel forming region. The metal oxide film 132 is an oxide semiconductor film that is present on the source electrode 140S and the drain electrode 140S. In the process of forming the electrode 140D, the process of forming the conductive film (141, 142) and the process of forming the conductive film (14 1, 142) to suppress damage to the metal oxide film 131 during the etching process. It is preferable that the metal oxide film 131 functions as a metal oxide layer, and that the metal oxide film 131 is formed of a denser film. It is preferable that:

[0077] The metal oxide film 132 provides a barrier between the insulating layer 102 (gate insulating layer) and the OS layer 130. Therefore, the channel forming region (metal oxide film 131) can be separated from the surface. Even if trap levels are formed on the surface, the charges flowing through the channel are not captured by the trap levels. Therefore, the on-current of the transistor 11 can be increased, and the field effect This can increase the fruit mobility.

[0078] As described above, in the transistor 11, a channel is formed in the metal oxide film 131. Therefore, the source electrode 140S and the drain electrode 140D are formed on the side surfaces of the metal oxide film 131. Therefore, the metal oxide film 132 is formed as a source region and a drain region. Therefore, the metal oxide film 132 is not an oxide semiconductor. The metal oxide film 132 may be a film having a high resistance. The contact resistance with the electrode 140D is very high, and the electrode 140D may be made of an insulator with infinite resistance. Therefore, the options for films that can be used as the metal oxide film 132 are increased.

[0079] Therefore, it is possible to form a thick metal oxide film 132. The film 132 functions as a protective film for the metal oxide film (oxide semiconductor film) 131. Therefore, the diffusion of copper into the OS layer 130 (metal oxide film 131) can be prevented by the metal oxide film 131. 132, so that the so-called channel etch type bottom gate transistor In the transistor 11, which is a transistor, the source electrode 140S and the drain electrode 140D are extended. This makes it easier to use copper materials that tend to dissipate.

[0080] In the OS layer 130, the thickness of the metal oxide film 131 may be 100 nm or more. For example, it may be 100 nm to 1000 nm, and preferably 200 nm to 1000 nm. The thickness of the metal oxide film 132 may be 50 nm or more, for example, 50 nm to It may be 500 nm, and preferably 100 nm to 300 nm.

[0081] For example, the metal oxide film 131 and the metal oxide film 132 are formed by sputtering In-G When forming a α-Zn oxide film, the sputtering target for the metal oxide film 131 is In-Ga-, in which the atomic ratio of In:Ga:Zn is 1:1:1 or 1:3:2 A Zn oxide target can be used, and the sputtering target of the metal oxide film 132 The ratio of In:Ga:Zn (atomic ratio) is 1:3:2, or 1:3:4, or A 1:3:6 In-Ga-Zn oxide target can be used. The metal oxide film 132 is an In-Ga-Zn oxide film that is richer in Ga than the metal oxide film 131. A film can be formed.

[0082] For example, the metal oxide film 131 may be formed of an In-Ga-Zn oxide film by sputtering. In the case where the metal oxide film 132 is formed by a sputtering method using an In-Ga oxide film, In this case, the sputtering target for the metal oxide film 131 is In:Ga:Zn (atomic number Use an In-Ga-Zn oxide target with a ratio of 1:1:1 or 1:3:2. As a sputtering target for the metal oxide film 132, In:Ga (atomic An In-Ga oxide target with a 7:93 ratio of In to Ga can be used. As the metal oxide film 132, an In-Ga oxide film richer in Ga than In is formed. Such a Ga-rich In-Ga oxide film is suitable as a Cu diffusion barrier film. It is a membrane.

[0083] <Configuration Example 2: FET-2> The transistor according to the second configuration example is a modified example of the transistor according to the first configuration example, and has a back gate. The potential or signal can be input to the front gate independently. The circuit symbol for such a transistor is shown below. The transistor has a front gate and a back gate. The back gate is not connected to the front gate. Here, the transistor represented by the circuit symbol in Figure 2A is called FET-2.

[0084] Figures 2B-2D show an example of the device structure of FET-2. 2C is a cross-sectional view taken along the line A1-A2 in FIG. 2B, and FIG. 2D is a cross-sectional view taken along the line A1-A2 in FIG. 2C is a cross-sectional view taken along line B1-B2. 2D is a cross-sectional view of the transistor in the channel length direction.

[0085] The transistor 12 is formed on a substrate 100, and includes an insulating layer 101, an insulating layer 102, a front surface of the insulating layer 103, and a gate insulating layer 104. the gate electrode 121, the OS layer 130, the source electrode 140S, the drain electrode 140D, The gate electrode 151, the electrode 152, and the electrode 153 are arranged in the channel width direction. The insulating layers 101 and 102 are provided with openings 172 and 173. In 173, the electrode 152 and the electrode 153 are in contact with the front gate electrode 121. In the transistor 12, the back gate electrode 151 is connected to the front gate electrode 121. not present.

[0086] The transistor 12 is formed by connecting the back gate electrode 150 of the transistor 11 to three electrodes (151 The transistor 12 also has a device structure divided into transistors 11 and 153. Similarly, it is an s-channel structure transistor, and similarly, the frequency characteristics and on-current characteristics Sexuality has been improved.

[0087] In transistor 12, as shown in FIG. 2C, OS layer 130 is connected to source electrode 140S. The front gate electrode 121 and the back gate electrode 140D are connected to each other without the drain electrode 140D. The electrode 151 is surrounded by the electrode 152 and the electrode 153. By connecting the port electrode 121 and the electrodes 152 and 153 as shown in the figure, These electrodes can surround the bottom surface, two opposing side surfaces, and top surface of the OS layer 130. The OS layer 130 can be electrically surrounded by the electric field of the front gate electrode 121. The electrodes 152 and 153 form a part of the front gate, and as shown in FIG. Since the gate electrode faces the side surface of the OS layer 130, it can be called a side gate electrode.

[0088] The back gate electrode 150 of the transistor 11 has a pair of side gate electrodes. This can be called a back gate electrode (Figure 1C).

[0089] As shown in FIG. 2C , electrodes 152 and 153 are connected to OS layer 130 with insulating layer 102 interposed therebetween. In other words, in the channel width direction, the electrodes 152 and 153 The widths SGov2 and SGov3 of the regions facing the top surface of the OS layer 130 have values ​​greater than 0. tsu.

[0090] The back gate electrode 151 is configured to receive a potential or signal different from that of the front gate electrode 121. Therefore, the input signal or input potential of the back gate electrode 151 can change the state of the transistor 1. The threshold voltage of 2 (hereinafter referred to as Vth or threshold) is increased in the positive voltage direction, Alternatively, the voltage can be shifted in the negative direction. This allows transistor 12 to be configured as an enhancement or depletion mode transistor during operation. It is possible to change it as appropriate.

[0091] <Configuration Example 3: FET-3> The transistor according to the third example is a modified example of the transistor according to the second example. FIG. 3A is a circuit diagram of a transistor according to Configuration Example 3. Here, the transistor represented by the circuit symbol in Figure 3A is called FET-3.

[0092] Figures 3B-3D show an example of the device structure of FET-3. 3C is a cross-sectional view taken along the line A1-A2 in FIG. 3B, and FIG. 3D is a cross-sectional view taken along the line A1-A2 in FIG. 3C is a cross-sectional view taken along line B1-B2. 3D is a cross-sectional view of the transistor in the channel length direction.

[0093] The transistor 13 is formed on a substrate 100, and includes an insulating layer 101, an insulating layer 102, a front surface of the insulating layer 103, and a gate insulating layer 104. the source gate electrode 121, the OS layer 130, the source electrode 140S, the drain electrode 140D, The insulating layers 101 and 102 are provided with a first electrode 152 and a second electrode 153 in the channel width direction. In the openings 172 and 173, the electrode 15 2. The electrode 153 is in contact with the front gate electrode 121.

[0094] The transistor 13 is different from the transistor 12 in that it does not have a back gate electrode 151. In the transistor 13, as shown in FIG. 3C, the OS layer 130 is The front gate electrode 121 and the electrode 140S and the drain electrode 140D are not connected via the front gate electrode 121 and the electrode 140S. The area surrounded by the conductive film consisting of the electrode 152 and the electrode 153 (the bottom surface, the two opposing Thus, the transistor 13 also has a side surface and a top surface. As with 2, the frequency and on-current characteristics are excellent due to the s-channel structure. It will be improved.

[0095] As shown in FIG. 3C, the electrodes 152 and 153 are connected to the OS layer 102 via the insulating layer 102. The circuit symbol in FIG. 3A shows that FET-3 has such a size. 15. The gate electrodes (151, 152) are shown.

[0096] <Modification> Modified examples of the transistor will be described below.

[0097] In the transistor 11, either an opening 172 or an opening 173 is formed to The gate electrode 150 may be connected to the front gate electrode 121. In the transistors 12 and 13, a device that forms either the electrode 152 or the electrode 153 It may be a silicon structure.

[0098] The transistors 11-13 each have one of a side gate electrode and a back gate electrode, or It is a transistor with an S-Channel structure that has both a side gate electrode and It is also possible to provide a device structure in which no back gate electrode is provided. The transistor does not have an S-Channel structure, but like the transistor 11, it is The device structure is such that the source electrode 140S and the drain electrode 140D are in contact with the side surface of the semiconductor substrate 130. Therefore, it is necessary to shorten the channel length L1 and also to make L2 as short as possible (close to L1). As a result, it is possible to improve the frequency characteristics while maintaining the on-current characteristics. can.

[0099] <<Unipolar transistor circuit>> The transistors (FET-1-FET-3) have a channel formation region made of oxide semiconductor. Therefore, it is an n-channel transistor. Below is an example of a circuit configuration using unipolar transistors. The transistors used in the circuit are FET-1-3.

[0100] <Inverter circuit> From unipolar transistors, for example, basic logic circuits (buffer circuits, inverter circuits, It is possible to configure a circuit such as a locked inverter circuit, a NAND circuit, or a NOR circuit. Here, we will explain the inverter circuit. Figure 8 shows the circuit symbol for the inverter circuit.

[0101] The inverter circuits (INV-1, INV-2, INV- 3) each have a transistor M1 and a transistor M2 connected in series. Transistor M1 has the device structure of FET-1, and transistor M2 has the device structure of FET-2. In this way, the transistor with improved on-current characteristics and frequency characteristics is By using transistors (FET-1, FET-2), power consumption is reduced and the operating frequency is It is possible to provide a high-number inverter circuit.

[0102] In the following description, the inverter circuit (INV-1) is abbreviated to INV-1. This also applies to other circuits, elements, voltages, signals, etc.

[0103] (INV-1) Figure 9A is the circuit diagram of INV-1, and Figure 9B is its truth table. Instead of data values, potential levels are used, with "H" representing high-level potential. It has a size that turns on the transistor M1. Also, "L" indicates a low level potential. represents a potential that is large enough to turn off transistor M1.

[0104] INV-1 has an input terminal (IN) and an output terminal (OUT), and uses VDD as the power supply voltage. VSS is supplied to the drain of transistor M2. VDD is the high power supply voltage. VSS is a low power supply voltage and is input to the source of transistor M1.

[0105] The back gate of the transistor M1 is connected to the front gate, and the front gate is connected to the terminal The input terminal (IN) is connected to the transistor M, and the drain terminal is connected to the terminal (OUT). 2, the front gate and source are connected, the source is connected to the terminal (OUT), and the back A signal φ1 is input to the gate.

[0106] The signal φ1 may be a signal whose potential level fluctuates or a signal whose potential level is constant. For example, as shown in FIG. 9B, the signal φ1 changes in potential depending on the signal input from the terminal (IN). It can be a signal whose level fluctuates. When the terminal (IN) becomes high level, The potential of the signal φ1 becomes VH1, and when the terminal (IN) becomes low level, the potential of the signal φ1 becomes Make it VL1.

[0107] In this case, for example, when the transistor M1 is in an on state, the current flowing through the transistor M2 is When transistor M1 is in the off state, the current flowing through transistor M2 is increased. A signal φ1 that increases the voltage of the transistor M2 may be supplied to the transistor M2. A voltage higher than the source (positive bias voltage) is applied to the back gate of transistor M2. This makes it possible to achieve a higher transistor potential than when no voltage is applied to the back gate. On the other hand, VL1 can reduce the threshold voltage of transistor M2. The back gate of the transistor is biased to a potential that is lower than the source voltage (negative bias voltage). This allows the transistor M2 to operate more efficiently than when no voltage is applied to the back gate. The threshold voltage of the transistor can be increased.

[0108] When transistor M1 is on, node NA is discharged slowly, and transistor M1 When the MOSFET is off, the node NA is charged at high speed, allowing for low power consumption and high speed operation. Possible INV-1.

[0109] (INV-2) The inverter circuit (INV-2) in FIG. 10A is a modification of INV-1, and includes a transistor The circuit has a configuration in which the back gate of M2 is connected to the drain.

[0110] In INV-2, VDD is applied to the back gate of transistor M2, A positive bias voltage is applied to the back gate of the transistor M2.

[0111] (INV-3) The inverter circuit (INV-3) in FIG. 10B is a modification of INV-2, and includes a transistor This corresponds to a circuit in which the front gate and back gate connections of M2 are swapped. M2 has its front gate connected to the drain and its back gate connected to the source. .

[0112] Here, the inverter circuit is configured with FET-1 and FET-2. For example, the transistors in INV-1-INV-3 can be used. In this case, the transistor M1 may be configured with the FET-3. The transistor may be configured without a back gate electrode and a side gate electrode. It is possible.

[0113] <Clocked inverter circuit> Explains clocked inverter circuits (CINV) composed of unipolar transistors do.

[0114] FIG. 11A shows the circuit symbol of a clocked inverter circuit. 1 shows an example of the configuration of a clocked inverter circuit.

[0115] The clock inverter circuits (CINV-1, CINV-2) shown in FIGS. 11B and 11C are Each has three transistors M11, M12, and M13 connected in series. The transistors M11 and M12 have the device structure of FET-1, and the transistor M13 has the device structure of F It has the same device structure as ET-2. As a result, the on-current characteristics and frequency characteristics are improved. By using the transistors (FET-1, FET-2), power consumption is reduced. It is possible to provide a clocked inverter circuit with a high operating frequency.

[0116] (CINV-1) As shown in FIG. 11B, CINV-1 is connected to transistors M1 and V of INV-1 (FIG. 9A). This corresponds to a circuit in which a transistor M11 is connected between the SS input terminals. The clock signal (CLK1) is input to the front gate, and the back gate is The front gate of transistor M12 is connected to the terminal (IN) and the The gate of the transistor M1 is connected to the terminal (OUT) and the drain of the transistor M2 is connected to the terminal (OUT). 3 is the front gate connected to the source, the source connected to the terminal (OUT), and the back A clock signal (CLK2) is input to the gate.

[0117] CINV-1 functions as an inverter circuit when CLK1 is at a high level. When it is at a low level, the terminal (OUT) is in a high impedance state. It is used as a signal to control the Vth of transistor M13, and is trans- formed by CLK2. The Zister M13 can be switched between enhanced and depletion modes.

[0118] For example, the same signal as CLK1 can be input as CLK2. In this case, CL When K1 becomes high level, M11 turns on and M13 shifts Vth to the negative voltage side. When CLK1 goes low, M11 is turned off and M13 is turned on at Vt h is shifted to the positive voltage side.

[0119] (CINV-2) As shown in Figure 11C, CINV-2 binds to the front gate and back gate of M13 of CINV-1. It corresponds to a circuit with the connections of the gates swapped, and operates in the same way as CINV-1.

[0120] <Latch circuit> FIG. 12A shows an example of the configuration of a latch circuit as an example of a sequential circuit. 12A is a block diagram showing the same, and FIG. 12B is a circuit diagram of the same.

[0121] The latch circuit (LAT) 200 includes clocked inverter circuits 201 and 202 and an inverter. The inverter circuit 203 and the clocked inverter circuit 202 are A loop circuit consisting of two inverter stages is configured. The input terminal of this loop circuit is It is connected to the input terminal (D) via a clocked inverter circuit 201 .

[0122] Here, INV-1-INV-3 are used for the inverter circuit 203, and a clocked inverter By using CINV-1 and CINV-2 in the transistor circuits 201 and 202, Therefore, a latch circuit with a fast rise time can be obtained.

[0123] The clock signals CLK1 and CLK3 are inverted phases. CLK2 controls the Vth of the transistor M13 of the clocked inverter circuit 201. CLK4 is a signal that is output from the VOUT terminal of the transistor M13 in the clocked inverter circuit 202. This is a signal that controls th.

[0124] <Shift register> As an example of a sequential circuit, a shift register is shown. As shown in FIG. 13, a shift register is configured by multiple LAs. By connecting T in series, a shift register 210 can be configured. In the register 210, the clock signals CLK and CLKB are in opposite phases. The output terminal of the LAT is connected to the input terminal of the LAT in the next stage. A start pulse signal SP is input to the input terminal D of the first stage LAT. The rising edge of the clock signal CLK or CLKB causes the start signal input to the first stage LAT to The output pulse signal is transferred to the next LAT in sequence, and the signal SROUT1- It is extracted as SROUT4.

[0125] For example, the shift register 210 may be a gate driver for an active matrix display device. In the third embodiment, the active layer can be used in a circuit and a source driver circuit. A description will now be given of a display device of a passive matrix type.

[0126] (Embodiment 2) In this embodiment, a manufacturing method of the transistor according to Embodiment 1 will be described. Now, the manufacturing method will be explained using the transistor 11 (FET-1) as an example.

[0127] 4A to 7B are cross-sectional views illustrating an example of a method for manufacturing the transistor 11. In the plane, the left side shows a cross section in the channel length direction (B1-B2), and the right side shows a cross section in the channel width direction. A cross-sectional view in the direction (A1-A2) is shown.

[0128] The films constituting the transistor 11 (insulating film, semiconductor film, oxide semiconductor film, metal oxide film, conductive film, The conductive film, etc., can be deposited by sputtering, chemical vapor deposition (CVD), vacuum deposition, pulse laser, etc. It can be formed using the laser deposition (PLD) method. Alternatively, it can be formed by coating or printing methods. The film formation method can be sputtering, plasma chemical vapor deposition (PE The most common method is MOCVD, but thermal CVD is also acceptable. (Metal Organic Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) may also be used.

[0129] In the thermal CVD method, the chamber is kept at atmospheric pressure or reduced pressure, and the source gas and oxidant are simultaneously mixed in the chamber. The film is formed by sending the gas into the chamber, reacting it near or on the substrate, and depositing it on the substrate. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0130] In the ALD method, the chamber is kept at atmospheric pressure or reduced pressure, and the source gases for the reaction are sequentially introduced. Next, the gas is introduced into the chamber, and the film is formed by repeating this gas introduction sequence. By switching each switching valve (also called high-speed valve), two or more types of raw material gas can be The first and second source gases are supplied to the chamber in order to prevent the multiple source gases from mixing. At the same time or afterwards, an inert gas (argon, nitrogen, etc.) is introduced to If an inert gas is introduced at the same time, the inert gas is introduced as a carrier gas. In addition, an inert gas may be introduced at the same time as the second source gas is introduced. Instead of introducing an inert gas, the first source gas is discharged by evacuation, and then the second source gas is introduced. A source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first monoatomic layer. The second monolayer is formed on the first monolayer by reacting with the second source gas introduced later. The thin film is formed by stacking the layers.

[0131] By controlling the gas introduction order and repeating this process multiple times until the desired thickness is achieved, the step coverage is improved. The thickness of the thin film can be increased by repeating the gas introduction sequence. This allows precise film thickness control, making it possible to fabricate minute transistors. Hereinafter, an example of a method for manufacturing the transistor 11 will be described with reference to the drawings. explain.

[0132] Here, a glass substrate is used as the substrate 100. First, as shown in FIG. A conductive film 120 constituting a front gate electrode 121 is formed on the insulating film 100. As the film 120, a tungsten film having a thickness of 100 nm is formed by sputtering.

[0133] Furthermore, a tungsten film can be formed using a film formation device that utilizes ALD. In this case, WF6 gas and B2H6 gas are introduced repeatedly in sequence to form the initial tungsten film. Then, WF6 gas and H2 gas are introduced simultaneously to form a tungsten film. SiH4 gas may be used in place of 2H6 gas.

[0134] A photoresist mask is formed on the conductive film 120 by a photolithography process using a first photoresist mask. A resist mask RM1 (not shown) is formed. The film is etched to form the front gate electrode 121 (FIG. 4B). Remove dystomask RM1.

[0135] The etching process in the manufacturing process of the transistor 11 includes wet etching and dry etching. etching, or both.

[0136] The front gate electrode 121 is formed by electrolytic plating, printing, inkjet printing, or the like. It is also possible.

[0137] Next, as shown in FIG. 4C, an insulating layer 101 is formed to cover the front gate electrode 121. The insulating layer 101 can be formed by a sputtering method, a CVD method, a vapor deposition method, or the like. Here, a silicon nitride film having a thickness of 400 nm is formed as the insulating film 111 by the PECVD method. As the insulating film 112, a silicon oxynitride film having a thickness of 50 nm is formed.

[0138] Alternatively, the film constituting the insulating layer 101 may be formed by thermal CVD. For example, hafnium oxide When forming a hafnium film, a liquid containing a solvent and a hafnium precursor compound (hafnium alcohol) is used. oxide solution, typically tetrakisdimethylamidohafnium (TDMAH), is vaporized. Two types of gases are used: the source gas and ozone (O3) as an oxidizing agent. The chemical formula for dimethylamidohafnium is Hf[N(CH3)2]4. The liquid material may be tetrakis(ethylmethylamido)hafnium.

[0139] For example, when forming an aluminum oxide film, a solvent and an aluminum precursor compound are used. Two types of gases are used: a raw material gas made by vaporizing a liquid containing methyl methacrylate (TMA, etc.), and H2O as an oxidizing agent. The chemical formula for trimethylaluminum is Al(CH3)3. The solution includes tris(dimethylamido)aluminum, triisobutylaluminum, Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate) There are some.

[0140] For example, when forming a silicon oxide film, hexachlorodisilane is adsorbed on the surface to be formed. This removes the chlorine contained in the adsorbed material and provides radicals of oxidizing gases (O2, nitrous oxide). is fed to react with the adsorbate.

[0141] Next, as shown in FIG. 5A, a metal oxide film 13 constituting an OS layer 130 is formed on the insulating layer 101. 1, 132 laminated films are formed.

[0142] The metal oxide films 131 and 132 can be formed by a film formation apparatus that uses ALD. For example, when forming an In-Ga-Zn oxide film, In(CH3)3 gas and O3 gas are used. The InO2 layer is formed by repeatedly introducing gases, and then Ga(CH3)3 gas and O3 gas are introduced. The GaO layer was formed by simultaneously introducing Zn(CH3)2 and O3 gases. The order of these layers is not limited to this example. These gases are mixed to form InGaO2 layer, InZnO2 layer, GaInO layer, ZnInO layer, Ga A mixed compound layer such as a ZnO layer may be formed. Note that an inert gas such as Ar may be used instead of O3 gas. Although H2O gas bubbled with gas may be used, it is better to use O3 gas that does not contain H. It is also preferable to use In(C2H5)3 gas instead of In(CH3)3 gas. Also, Ga(C2H5)3 gas may be used instead of Ga(CH3)3 gas. Alternatively, Zn(CH3)2 gas may be used.

[0143] When the metal oxide films 131 and 132 are formed by sputtering, plasma is generated. The power supply for this purpose can be an RF power supply, an AC power supply, a DC power supply, or the like. Cut.

[0144] The sputtering gas is a rare gas (typically argon), oxygen, or a mixture of rare gas and oxygen. In the case of a mixture of rare gas and oxygen, the gas ratio of oxygen to rare gas is It is preferable to increase the target of the metal oxide films 131 and 132 to be formed. It may be selected appropriately according to the composition.

[0145] In order to obtain a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film, a chamber Not only is it necessary to evacuate the inside of the chamber to a high vacuum, but it is also necessary to highly purify the sputtering gas. The oxygen gas and argon gas used in this process have a dew point of -40°C or less, preferably -80°C or less, and Preferably, the gas is purified to a temperature of -100°C or lower, more preferably -120°C or lower. By using this, it is possible to prevent moisture and the like from being absorbed into the metal oxide films 131 and 132 as much as possible. It is possible.

[0146] Here, an In-Ga-Zn oxide target (In:Ga:Zn=3:1:2) was used. The metal oxide film 131 was formed by sputtering with a thickness of 300 nm. The metal oxide film 131 is formed as an oxide semiconductor film. The sputtering method was performed using an In-Ga oxide target (In:Ga=7:93). As a result, an In-Ga oxide film having a thickness of 50 nm is formed as the metal oxide film 132. The semiconductor film 132 is formed as an oxide semiconductor film or an insulating film.

[0147] Next, a photolithography process using a second photoresist mask is performed on the metal oxide film 132. After forming a resist mask RM2 (not shown) by a photolithography process, The laminated film of the metal oxide film 131 and the metal oxide film 132 is then wet-etched to form a device. The resist mask RM2 is then removed (FIG. 5B). ).

[0148] For example, after the OS layer 130 is formed, the substrate is heated at a temperature of 150° C. or higher and lower than the substrate strain point, preferably 200° C. or higher. Heat treatment may be carried out at 450°C or less, more preferably at 300°C or more and 450°C or less. The heat treatment is one of the purification treatments for an oxide semiconductor, and hydrogen contained in the OS layer 130 is removed. , water, etc. can be reduced.

[0149] A laminated film including conductive films 141 and 142 is formed to cover the OS layer 130 and the insulating layer 101. (Figure 5C). Here, a 50 nm thick tungsten film ( 141) and a copper film (142) having a thickness of 300 nm are formed.

[0150] Alternatively, the conductive film 141 may be formed by an ALD method. The conductive film 141 can be formed without causing damage.

[0151] The front gate electrode 121 (including the electrode formed in the same layer as this) and the source electrode The electrode 140S and the drain electrode 140D (including the electrode formed in the same layer) are connected to each other. In this case, openings for this connection are formed in the insulating layer 101 before the formation of the conductive films 141 and 142. In this case, the resist is formed by a photolithography process using a third photoresist mask. A resist mask RM3 is formed on insulating layer 101 and OS layer 130. By etching, openings are formed in the insulating layer 101. The resist mask RM3 is removed. After that, conductive films 141 and 142 are formed.

[0152] Next, a photolithography process using a fourth photoresist mask is performed on the conductive film 142. A resist mask RM4 (not shown) is formed by this. The layer films (141, 142) are etched to form the source electrode 140S and the drain electrode 140D. (Figure 6A).

[0153] For example, the copper film (142) is etched by wet etching, and the tungsten film (142) is etched by wet etching. When (141) etching is performed by dry etching using SF6, the surface of the copper film Fluorides are formed, which cause copper from the copper film to diffuse into OS layer 130. In addition, the metal oxide film 132 of the OS layer 130 is prevented from being damaged by the metal oxide film 131. The conductive film 141 and the conductive film 142 function as an etching protection film against metal diffusing from the conductive film 141 and the conductive film 142. Therefore, the deterioration of the electrical characteristics of the transistor 11 and the decrease in reliability are prevented. You can suppress the bottom.

[0154] After removing the resist mask RM4, the insulating layer 101, the OS layer 130, and the source electrode 140S are Then, an insulating layer 102 is formed to cover the drain electrode 140D (FIG. 6B).

[0155] Here, the insulating film 113 and the insulating film 114 are successively formed. This is a film formation method in which, after forming the first layer, the second and subsequent layers are formed without exposing the processed substrate to the atmosphere. By forming films continuously, it is possible to reduce the concentration of impurities originating from atmospheric components at the interface of the laminated film. do.

[0156] The insulating film 113 and the insulating film 114 are made of a silicon oxynitride film having a thickness of 50 nm and a silicon nitride film having a thickness of 400 nm. By changing the film formation conditions in the PECVD equipment, The source gas for the silicon oxynitride film is silicon. It is preferable to use a deposition gas containing silicon and an oxidizing gas. Typical examples of gases include silane, disilane, trisilane, and fluorinated silane. The gases include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0157] When a PECVD apparatus is used, the insulating film 113 can be formed under the following conditions: The gases were silane and nitrous oxide, and the flow rates were 30 sccm for silane and 30 sccm for nitrous oxide. The pressure in the processing chamber was 200 Pa, and the substrate temperature was 22 0°C. In the PECVD device, a high frequency power supply of 27.12 MHz was used to heat the The high frequency power of 1000 W is supplied to the parallel plate electrodes. A silicon film can be formed.

[0158] Furthermore, in the same processing chamber, the insulating film 114 is formed without being exposed to the atmosphere. The process can be carried out under the following conditions: the source gas is the same as that for the insulating film 113; The run is 200sccm and the nitrous oxide is 4000sccm. The pressure in the processing chamber is The pressure was 200 Pa and the substrate temperature was 220°C. A 1500 W high frequency power is supplied to the parallel plate electrodes using a 1000 Hz high frequency power supply.

[0159] Here, the PECVD device shown as an example has an electrode area of ​​6000 cm 2 Parallel plate PEC The power supplied during the formation of the insulating film 114 is expressed as the power per unit area (power density). This is converted to 0.25W / cm 2 is.

[0160] The insulating film 113 is formed by the PECVD apparatus at a substrate temperature of 280° C. to 400° C. and a pressure of 1000 kJ / cm. The pressure is set to 20 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 250 Pa or less. It is preferable to carry out the treatment under the condition that high frequency power is supplied to an electrode provided in the treatment chamber. By appropriately selecting the listed source gases, a silicon oxide film can also be formed under these conditions. It is possible.

[0161] By forming the insulating film 113 under such conditions, the silicon oxynitride film which transmits oxygen can be obtained. Alternatively, a silicon oxide film can be formed. By setting the temperature below 100°C, the bonding strength between silicon and oxygen is strengthened. As a result, oxygen can penetrate and the density is increased. A dense and hard silicon oxynitride film or silicon oxide film can be formed. Typically, the etching rate when using 0.5% by weight of hydrofluoric acid at 25°C is 1 Silicon oxynitride film or silicon oxide film with a rate of 0 nm / min or less, preferably 8 nm / min or less can be formed.

[0162] Furthermore, since the insulating film 113 is formed while heating, the OS layer 130 contains hydrogen, water, and the like. In this case, hydrogen, water, and the like contained in the OS layer 130 can be released in this step. The hydrogen contained in the OS layer 130 combines with oxygen radicals generated in the plasma to form water. Since the substrate is heated, the water generated by the bond between oxygen and hydrogen flows into the OS layer 13. That is, by forming the insulating film 113 by the PECVD method, the OS layer 130 The water and hydrogen content can be reduced.

[0163] Furthermore, since the OS layer 130 is heated during the formation of the insulating film 113, the OS layer 130 is exposed. The heating time in the heated state is short, and oxygen desorption from the OS layer 130 due to the heat treatment is suppressed. By setting the pressure in the processing chamber to 100 Pa or more and 250 Pa or less, the insulating film 113 Since the water content can be reduced, the variation in the electrical characteristics of the transistor 11 can be reduced. Therefore, the fluctuation of the threshold voltage can be suppressed.

[0164] It is preferable to minimize damage to the OS layer 130 during the formation of the insulating film 113. This is because, when the insulating film 114 is formed under conditions that reduce defects, the oxygen in the insulating film 114 Therefore, the amount of desorption is reduced. This is because it may be difficult to sufficiently reduce defects. By setting the pressure to 100 Pa or more and 250 Pa or less, the insulating film 113 can be formed on the OS layer 130. It is possible to reduce the damage caused by the

[0165] In addition, by increasing the amount of oxidizing gas to 100 times or more the amount of deposition gas containing silicon, It is possible to reduce the hydrogen content in the insulating film 113. As a result, the OS layer 130 This reduces the amount of hydrogen that gets mixed into the transistor, thereby suppressing the negative shift in the threshold voltage of the transistor. It can be controlled.

[0166] When a PECVD apparatus is used, the insulating film 114 can be formed under the following conditions: The temperature is 180°C or higher and 280°C or lower, and more preferably 200°C or higher and 240°C or lower. The pressure in the processing chamber is 100 Pa or more and 250 Pa or less, and more preferably 100 Pa or more and 250 Pa or less. The high frequency power supplied to the electrode of the PECVD device is 0.17 W / cm 2 More than 0.5W / cm 2 or less, more preferably 0.25 W / cm 2 More than 0.35W / c m 2 The following is the result.

[0167] By supplying high frequency power with the above power density to the reaction chamber under the above pressure, The decomposition efficiency of the source gas increases, oxygen radicals increase, and oxidation of the source gas progresses, resulting in an insulating The oxygen content in the film 114 becomes higher than the stoichiometric ratio. In the film formed at this temperature, the bonding strength between silicon and oxygen is weak, so the film is easily broken down by the heat treatment in the subsequent process. A portion of the oxygen in the film is desorbed. As a result, more oxygen than the stoichiometric composition is obtained. A silicon oxynitride film containing the compound can be formed, from which part of the oxygen is released by heating.

[0168] The insulating film 113 is provided on the OS layer 130. In this case, the insulating film 113 serves as a protective film for the OS layer 130. The insulating film 114 can be formed using high frequency power with high power density while reducing the size. can.

[0169] After the insulating films 113 and 114 are formed, a heat treatment is performed. A part of the oxygen contained in 4 is transferred to the OS layer 130, and the amount of oxygen vacancies in the OS layer 130 is reduced. After the heat treatment, the insulating film 115 is formed.

[0170] The insulating film 113 and the insulating film 114 contain water, hydrogen, etc., and have a function of blocking water, hydrogen, etc. When the insulating film 115 having the insulating property is formed, heat treatment is performed after the insulating film 115 is formed. Water, hydrogen, and the like contained in the insulating film 113 and the insulating film 114 move to the OS layer 130, and the OS layer 13 By performing heat treatment before forming the insulating film 115, defects are generated in the insulating film 113. In addition, water and hydrogen contained in the insulating film 114 can be effectively reduced.

[0171] By forming the insulating film 114 over the insulating film 113 while heating, oxygen is introduced into the OS layer 130. This heating can reduce oxygen vacancies in the OS layer 130. There are cases where no processing is necessary.

[0172] The temperature of this heat treatment is typically 150°C or higher and 400°C or lower, preferably 300°C or higher. The temperature is set to 400°C or lower, preferably 320°C or higher and 370°C or lower. , ultra-dry air (water content is 20 ppm or less, preferably 1 ppm or less, preferably 10 The reaction may be carried out under an atmosphere of air (ppb or less) or a rare gas (argon, helium, etc.). It is preferable that the nitrogen, oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, etc. For the heat treatment, an electric furnace, an RTA device, etc. can be used. By doing so, it is possible to perform heat treatment at a temperature above the distortion point of the substrate for a short period of time. Therefore, the heat treatment time can be shortened.

[0173] Here, heat treatment is performed in a nitrogen and oxygen atmosphere at 350°C for 1 hour. Form 115.

[0174] When the insulating film 115 is formed by the PECVD method, the substrate temperature is set to 300° C. or more and 400° C. or less. Preferably, the temperature is 320°C or higher and 370°C or lower, since a dense film can be formed. .

[0175] When a silicon nitride film is formed as the insulating film 115 by the PECVD method, the insulating film 115 contains silicon. The deposition gases nitrogen and ammonia are preferably used as source gases. By using a small amount of ammonia, the ammonia dissociates in the plasma and active species are generated. The active species react with the silicon and hydrogen contained in the silicon-containing deposition gas, This breaks the triple bond of silicon and nitrogen, promoting the bonding of silicon and nitrogen. Therefore, a dense silicon nitride film can be formed with fewer hydrogen bonds and fewer defects. On the other hand, if the amount of ammonia relative to nitrogen is high, the decomposition of silicon-containing deposition gases and nitrogen The silicon nitride layer is not etched well, and silicon and hydrogen bonds remain, resulting in an increase in defects and a coarse silicon nitride layer. For these reasons, the nitrogen content of the raw material gas is low compared to that of ammonia. It is preferable that the flow rate ratio is 5 or more and 50 or less, or 10 or more and 50 or less.

[0176] Here, the insulating film 115 is formed by using a PECVD apparatus and a CVD method using silane, nitrogen, and ammonia. A silicon nitride film with a thickness of 50 nm is formed from the source gas of silane. ccm, nitrogen 5000sccm, and ammonia 100sccm. The pressure was 100 Pa, the substrate temperature was 350°C, and a 27.12 MHz high frequency power source was used. The PECVD device is designed to supply high-frequency power of 6000 W to parallel plate electrodes. cm 2 The power supplied is expressed as the power per unit area. (power density) is 1.7 x 10 -1 W / cm 2 is.

[0177] Through the above steps, the insulating films 113, 114, and 115 can be formed. Cut.

[0178] After the insulating film 115 is formed, heat treatment may be performed. The temperature of the heat treatment is typically 150°C or higher and 400°C or lower, preferably 300°C or higher and 400°C or lower, preferably 320°C During this heat treatment, the insulating film 113 and the insulating film 114 are heated to a temperature of 370° C. or lower. Since the amount of oxygen and water is reduced, the occurrence of defects in the OS layer 130 as described above is suppressed. are.

[0179] Next, a photolithography process is performed on the insulating layer 102 using a fifth photoresist mask. A resist mask RM5 (not shown) is formed by this. Etching the edge layer 102 and the insulating layer 101 to form openings 172 and 173 (Figure 7A).

[0180] After removing the resist mask RM5, a conductive film is formed on the insulating layer 102. A resist mask R is formed by a photolithography process using a sixth photoresist mask. M6 (not shown) is formed. The conductive film is etched using the resist mask RM6. The back gate electrode 150 is formed, and then the resist mask is removed.

[0181] Through the above steps, the transistor 11 is formed using the first to sixth photoresist masks. The other transistors according to the first embodiment can also be fabricated as transistors. It can be fabricated in the same manner as the heater 11.

[0182] As described above, in this embodiment, in the manufacturing process of an OS transistor, forming a film that supplies oxygen to the OS layer to reduce defects in the OS layer including the formed region; The process also includes a step of supplying oxygen from the film to the OS layer, thereby achieving highly reliable OS transistors. It is possible to create a

[0183] (Embodiment 3) In this embodiment, the OS transistor according to the first embodiment is used as an example of a semiconductor device. The active matrix display device will now be described.

[0184] <Example of display device configuration> An active matrix display device is a semiconductor device that includes a display panel, a controller, a power supply circuit, etc. FIG. 14 shows the structure of an active matrix liquid crystal display (LCD). 15A, 15B, and 15C are block diagrams showing an example of a display that configures an LCD. 1 shows an example of the configuration of a liquid crystal panel (LC panel).

[0185] As shown in FIG. 14, the display device 400 includes a controller 401, a power management unit (PMU), 402, a power supply circuit 403, a pixel section 411, a gate driver circuit 412, a source driver circuit It has a path 413.

[0186] The controller 401 controls the display device 400. The controller 401 includes a video The input signals include a signal, a synchronization signal for controlling the rewriting of the screen, etc. For example, there are horizontal sync signals, vertical sync signals, and reference clock signals. The controller 401 generates control signals for the driver circuits (412, 413). The PMU 402 is controlled based on a control signal from the controller 401 or an external device. The PMU 402 then controls the power supply circuit 403 .

[0187] The pixel section 411 includes a plurality of pixels 421 arranged in an array, a plurality of gate lines 422, and The pixels 421 in the same row are connected to the gate lines 422 in each row. The pixels 421 in the same column are connected to the source line 423 of each column. It has a transistor that controls conduction with the source line 423. The gate of this transistor is , which is connected to a gate line 422 and is controlled to be turned on or off by a signal input to the gate line. do.

[0188] The source line 423 is connected to the source driver circuit 413. 3 generates a data signal from the video signal input from the controller 401, and The gate driver circuit 412 has a function of outputting the signal from the controller 401 to the gate driver circuit 423. It has a function of outputting a gate signal to the gate line 422 according to the input control signal. The gate signal is a signal for selecting a pixel 421 to which a data signal is input. 2 is connected to the gate driver circuit 412.

[0189] When the pixel portion 411 is configured with an OS transistor, both the driver circuits (412, 413) Shift register 210 (FIG. 13) made of unipolar transistors shown in Embodiment 1. By using this, the pixel section 411 and the driver circuits (412, 413) can be integrated on the same substrate. It is possible.

[0190] <Display panel configuration example> In FIG. 15A, a pixel section 411 and a driver circuit (412, 413) are integrated on the same substrate. The display panel 471 has a substrate 501 and a substrate 502. The substrate 501 includes a pixel section 411 and driver circuits (412, 413), and In the example of FIG. 15A, the gate driver circuit 412 has two The gate driver circuit 412R and the gate driver circuit 412L are formed separately. There are.

[0191] The terminal section 415 is a section for connecting the pixel section 411 and the driver circuit (412, 413) to an external circuit. A plurality of terminals for connection are formed on the terminal portion 415. The terminal portion 415 is connected to the FPC 416. (FPC: Flexible printed circuits). A device having a structure in which the FPC 416 is not connected to the terminal portion 415 is also included in the display panel. It shall be.

[0192] The sealing member 503 maintains a gap (cell gap) between the substrate 501 and the substrate 502. For example, in the case of a display panel (liquid crystal panel) of a liquid crystal display device, the substrate A liquid crystal layer is sealed between the substrate 501 and the substrate 502. A liquid crystal layer is sealed between the substrate 501 and the substrate 502. As shown in FIG. By providing a seal member 503 so as to overlap the display circuit (412, 413), The frame that does not contribute to the display of panel 471 can be narrowed.

[0193] In the display panel 471, for example, the pixel portion 411 is configured with a circuit made of OS transistors. In this case, the driver circuits (412, 413) are also configured with circuits made of OS transistors. These driver circuits (412, 413) are connected to FET-1-FET-3 (Fig. 1-Fig. 3). By using this, it is possible to provide a circuit with a high driving frequency and low power consumption.

[0194] The display panel 471 has circuits (411-413) formed on the substrate 501, so that the This reduces the number of IC chips and other components installed in the unit, thereby reducing costs. In addition, if the circuit is not integrated on the same substrate as the pixel section 411, it becomes necessary to extend the wiring. If a driver circuit is provided on the same substrate 501, the number of connections between the wirings will increase. This reduces the number of connections between the components, improving reliability and yield. .

[0195] It should be noted that part or all of the source driver circuit 413 may be implemented as a CMOS circuit using Si transistors. In this case, a part of the source driver circuit 413 may be configured as This can be incorporated into an IC chip, which can then be mounted on substrate 501.

[0196] An example of such a display panel is shown in Figures 15B and 15C. In 472, TCP 418 is an IC chip that constitutes part of the source driver circuit 413. is implemented (TCP; Tape Carrier Package). In the display panel 473 shown in FIG. 1, the TCP 418 IC chip is provided with a source driver circuit 413. All circuits are built in. TCP418 also includes an FP connected to the IC chip. In this case, the substrate 501 has a terminal portion 41 connected to the TCP 418. 7 is fabricated. The terminal section 417 is connected to the source line of the pixel section 411 and the TCP 418. There are multiple terminals for connecting the TCP418 to the UPS. This embodiment is also regarded as one example of the configuration of the display panel of this embodiment.

[0197] In addition, a part of the source driver circuit 413 is connected to the pixel section 411 and the gate driver circuit 4 If the circuit can be fabricated using transistors of the same conductivity type as 12, the circuit can be integrated on the substrate 501. Other circuits may be incorporated into the IC chip.

[0198] The method for mounting the IC chip is not particularly limited. Also, instead of TCP, The IC chip is incorporated into the SOF (System on Film), and the SOF is mounted on the substrate 501. It may also be attached to.

[0199] <Display device structure> As an example of the display device 400, the structure of the display device will be described with reference to FIG. 16 is an exploded perspective view of the display device.

[0200] As shown in FIG. 16, the display device 400 has an upper cover 481 and a lower cover 482 between them. , touch panel unit 484 connected to FPC483, table connected to FPC485 display panel 471, backlight unit 487, frame 489, printed circuit board 490, The backlight unit 487, the battery 491, the The touch panel unit 484 may not be provided. In the case of a reflective liquid crystal display or electroluminescence (EL) display, The light unit 487 is an unnecessary part.

[0201] The upper cover 481 and the lower cover 482 are connected to the touch panel unit 484 and the display panel The shape and dimensions can be changed as needed to fit the size of the 471.

[0202] The touch panel unit 484 is a resistive or capacitive touch panel. The display panel 471 can be used by overlapping it with the opposing substrate (sealing substrate). It is also possible to provide a touch panel function to the display panel. It is also possible to provide an optical sensor in each pixel of 471 to make it an optical touch panel. Alternatively, a touch sensor electrode is provided in each pixel of the display panel 471, and a capacitive touch panel is formed. It is also possible to use

[0203] The backlight unit 487 includes a light source 488. Alternatively, a light diffusing plate may be used as the light diffusing plate.

[0204] The frame 489 has a function of protecting the display panel 471 and also functions as a protective element for the printed circuit board 490. It also functions as an electromagnetic shield to block the electromagnetic waves generated. 9 may also function as a heat sink.

[0205] The printed circuit board 490 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. The power supply that supplies power to the power supply circuit may be an external commercial power supply. Alternatively, the power source may be a separately provided battery 491. This can be omitted if a power supply is used.

[0206] The display device 400 is also equipped with additional components such as a polarizing plate, a retardation plate, and a prism sheet. In the example of FIG. 16, the display panel 471 of FIG. 15A is used. Display panels of other configurations (eg, display panels 472, 473) may also be used.

[0207] <Liquid crystal display (LCD) pixel> FIG. 17A is a circuit diagram showing an example of the configuration of pixels of an LCD. Pixel 430 has a transistor 431, a liquid crystal element 432, and a capacitive element 433.

[0208] The liquid crystal element 432 has two electrodes and a liquid crystal layer sandwiched between the two electrodes. One electrode is composed of a pixel electrode formed on a substrate 501, and the pixel electrode is connected to the transistor 43 1. Also, a voltage VLC is input to the other electrode of the liquid crystal element 432. The transistor 431 functions as a switch for controlling the conduction state between the liquid crystal element 432 (pixel electrode) and the source line 423, and its gate is connected to the gate line 422. Here, the transistor 431 applies FET-1 (FIG. 1). The capacitive element 433 has a function of a holding capacitor for holding the voltage between the two electrodes of the liquid crystal element [[ID=1�]]432. When the transistor 431 is in the on state, the liquid crystal element 432

[0209] <000156۵> and the capacitive element 433 are discharged or charged by the potential of the source line 423. Due to the voltage held by the liquid crystal element 432 and the capacitive element 433, the alignment state of the liquid crystal layer changes, and the transmittance of the liquid crystal element 432 changes

[0210] . Note that by changing the circuit configuration of the pixel, a display device other than an LCD can be obtained. For example

[0211] , when making an electronic paper, in FIG. 17A, instead of the liquid crystal element 432, a display element for controlling gradation by an electrophoretic method or the like may be provided. <Pixels of an EL Display Device> Also, when the display device 400 is an EL display device, pixel 440 in FIG. 17B may be provided in pixel portion 411

[0212] Pixel 440 has a transistor 441, a transistor 442, an EL element 4 43 and a capacitor 444. Here, the transistors 441 and 442 are the same It is a conductivity type transistor.

[0212] The transistor 441 is a switch transistor that controls conduction between the pixel 440 and the source line 423. The transistor 442 is a transistor called a driving transistor. It has the device structure of FET-1.

[0213] The EL element 443 has two electrodes (anode and cathode) and an organic layer sandwiched between the two electrodes. The light-emitting element has a light-emitting layer containing a compound. One electrode is applied with a constant potential. The light-emitting layer is connected to a wiring 425. The light-emitting layer contains at least a light-emitting substance. The luminescence of the light-emitting layer can be a singlet luminescence (EL) material. Luminescence (fluorescence) when returning from an excited state to the ground state, and when returning from a triplet excited state to the ground state It emits light (phosphorescence).

[0214] The EL element 443 is capable of changing the light emission intensity by changing the current flowing between the two electrodes. Here, the light emitted by the EL element 443 is determined by the current value flowing through the transistor 442. The intensity of the EL element 443 is adjusted by the voltage at the gate of the transistor 442. The light emission intensity is adjusted.

[0215] A capacitor 444 is connected between the gate of the transistor 442 and the wiring 425. The capacitor 444 functions as a storage capacitor that holds the voltage of the gate of the transistor 442. When the transistor 441 is turned on, the source signal input to the source line 423 A current of a magnitude corresponding to the potential of the transistor 441 flows through the transistor 441. The gate of the transistor 442 is charged or discharged to adjust its potential.

[0216] The circuit configuration of the pixel is not limited to the example shown in Fig. 17. For example, A switch, a resistive element, a capacitive element, a sensor, a transistor, a logic circuit, or the like may be added.

[0217] For example, in this specification and the like, the term "display element," "display device having a display element," "light emitting element," "light emitting device," "light emitting element ... A light-emitting device, which is a device having a light-emitting element and a light-emitting element, can be formed in various forms or in various forms. Examples of a display element, a display device, a light-emitting element, or a light-emitting device include , EL (electroluminescence) elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc. ), transistors (transistors that emit light according to the current), electron-emitting devices, liquid crystal devices, Dye ink, electrophoretic element, grating light valve (GLV), plasma display PDP, MEMS (Micro-Electro-Mechanical Systems), Digital Micromirror Device (DMD), DMS (Digital Micro Shutter), MIR ASOL (registered trademark), IMOD (Interference Modulation) element, Electrowetting elements, piezoelectric ceramic displays, carbon nanotubes, etc. A display medium whose contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic effects. An example of a display device using an EL element is an EL display. An example of a display device using electron-emitting elements is a field emission display. Flat panel display (FED) or SED (Surface-co Induction Electron-emitter Display). An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display). , Transflective LCD, Reflective LCD, Direct-view LCD, Projection Examples of display devices using electronic ink or electrophoretic elements include: Examples include electronic paper.

[0218] <Device structure of pixel in display device> Hereinafter, with reference to FIGS. 18 and 19, the device structure of a pixel of an active matrix display device will be described. Here, the device structure of the pixel section 411 will be explained as an example. Here, the structure of the pixel section 411 will be described using the pixel 430 in FIG. 17A as an example.

[0219] FIG. 18 is a top view of the pixel portion 411 (pixel 430), and shows the plan view of the transistor 431 and the like. FIG. 19 is a cross-sectional view taken along the line B3-B4 in FIG. It also corresponds to a cross-sectional view of the display panel 471.

[0220] The pixel 430 includes circuits (411, 412, and 413) formed from an oxide semiconductor film. The backplane includes a substrate and a color filter substrate. The substrate 501 is a support substrate for the color filter substrate, and the substrate 502 is a support substrate for the color filter substrate. A substrate that transmits visible light is used, such as a glass substrate or a flexible substrate made of resin. When a flexible substrate is used, after the backplane is formed, the substrate used in the manufacturing After the support substrate is separated, the flexible substrate may be fixed.

[0221] FIG. 18 shows a planar layout of a pixel 430 on the backplane side. The lanes are formed by the OS process using the first to sixth photoresist masks described in the second embodiment. It is manufactured using the same process as the transistor manufacturing process. The method is the same as that of the second embodiment. Driver circuits (412, 413) are formed using the compound semiconductor film.

[0222] A liquid crystal layer 520 is sealed between the substrate 501 and the substrate 502 by a sealing member 503 (FIG. 15A). On the substrate 502, a shielding film 541 that has the function of blocking visible light and a specific wavelength are provided. The shielding film 541 and the colored layer 542 are provided to transmit long-range visible light. A resin film 543 is provided on the substrate 42, and an electrode 652 is provided on the resin film 543. The electrode 652 is called a common electrode and constitutes an electrode of the liquid crystal element 432. An alignment film 532 is formed to cover the film 52 .

[0223] The pixel section 411 includes a wiring (GL) 621, a wiring (SL) 645, an electrode (ME) 646, a barrier The gate electrode (BG) 650 and the oxide semiconductor layer (OS) 630 are included. The wiring (GL) 621 is connected to the gate line 422. The wiring (SL) 645 includes a region that will become the front gate electrode of the transistor 431. corresponds to the source line 423 and includes a region that becomes the source electrode of the transistor 431. ME) 646 constitutes the drain electrode of the transistor 431. The cross-sectional structure of the transistor 431 in the channel length direction is shown.

[0224] The pixel portion 411 is formed with a metal oxide layer (OC) 635 and a pixel electrode (PIX) 651. The metal oxide layer 635 and the pixel electrode 651 constitute a pair of electrodes of the capacitor element 433. The pixel electrode 651 constitutes an electrode of the liquid crystal element 432. The area where the pixel electrode 651 and the electrode 652 face each other functions as the liquid crystal element 432 (see FIG. 19).

[0225] As shown in FIG. 19, an insulating layer 601 is formed to cover the wiring 621, and An oxide semiconductor layer 630 and a metal oxide layer 635 are formed. The insulating film 611 and the insulating film 612 are stacked together. The oxide semiconductor layer 63 is a laminated film of a metal oxide film 631 and a metal oxide film 632. In FIG. 0, the metal oxide film 631 is an oxide semiconductor film in which a channel is formed. The semiconductor layer 630 has a pair of opposing side surfaces to which a wiring (SL) 645 is in contact, and the other side surface is in contact with the wiring (SL) 645. An electrode (ME) 646 is in contact with it.

[0226] The oxide semiconductor layer 630, the metal oxide layer 635, the wiring 645, and the electrode 646 are covered with an insulating film. An insulating layer 602 is formed on the insulating layer 602. A back gate electrode 650 and a pixel electrode The back gate electrode 650 and the pixel electrode 651 are covered with an alignment film. A film 531 is formed.

[0227] The insulating layer 602 has a laminated structure made up of insulating films 613-615. An opening 671 is formed to reach the electrode 646, and the electrode 646 and the pixel The insulating layer 602 and the insulating layer 601 are in contact with the electrode 651. An opening 672 (FIG. 18) is formed, and the back gate electrode 650 is It is in contact with the wiring 621. As shown in FIG. 1A, the back gate electrode 650 and the wiring 621 Two openings may be provided to connect the

[0228] The opening 673 is formed in the laminated film of the insulating film 613 and the insulating film 614 of the insulating layer 602. In the opening 673, the metal oxide layer 635 and the pixel electrode 65 are disposed with the insulating film 615 interposed therebetween. The region where the insulating films 613 and 611 face each other functions as a capacitor element 433. After successively forming the insulating film 615 made of a nitride insulating material, an opening 673 is formed. The metal oxide layer 635 can be used as an electrode of the capacitor 433 because For example, when the opening 673 is formed or when the insulating film (nitride insulating film) 615 is formed, a metal oxide film is formed. Oxygen vacancies are formed in the oxide layer 635, and hydrogen diffused from the insulating film 615 enters the oxygen vacancies. This is thought to be because the donor is generated by bonding to the metal oxide layer 6. The resistivity of 35 is typically 1×10 -3 Ωcm or more 1×10 4 Less than Ωcm, more preferred Or, the resistivity is 1×10 -3 Ωcm or more 1×10 -1 It is preferable that the resistivity is less than Ωcm.

[0229] The metal oxide layer 635 preferably has a higher hydrogen concentration than the oxide semiconductor layer 630. In the oxide layer 635, the hydrogen concentration obtained by SIMS is 8×10 19 atoms / cm 3 or more, preferably 1 × 10 20 atoms / cm 3More than 5x1, preferably 0 20 atoms / cm 3 The oxide semiconductor layer 630 was subjected to SIMS. The resulting hydrogen concentration is 5 x 10 19 atoms / cm 3 Less than 5 x 10 18 a toms / cm 3 Less than 1 x 10 18 atoms / cm 3 The following is more preferable: is 5 x 10 17 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / c m 3 The following is the result.

[0230] In Figures 18 and 19, the LCD is driven in Twisted Nematic (TN) mode. The pixel configuration is shown as an example, but is not limited to this. Twisting mode, STN (Super Twisted Nematic) mode Mode, VA (Vertical Alignment) mode, MVA (Multi-d Main Vertical Alignment mode, IPS (In-Plane Switching) mode, OCB (Optically Compensated d Birefringence mode, Blue phase mode, TBA (Transverse Birefringence) mode, se Bend Alignment) mode, VA-IPS mode, ECB (Electronic Control Board) mode Electrically Controlled Birefringence mode, FL C (Ferroelectric Liquid Crystal) mode, AFLC ( AntiFerroelectric Liquid Crystal) mode, PDL C (Polymer Dispersed Liquid Crystal) mode, P NLC (Polymer Network Liquid Crystal) mode, Host mode, ASV (Advanced Super View) mode, etc. It is also possible to use a pixel structure driven by a voltage.

[0231] The liquid crystal layer 520 may be made of, for example, a thermotropic liquid crystal or a lyotropic liquid crystal. Alternatively, the liquid crystal layer 520 may be made of, for example, nematic Liquid crystals are classified as smectic, cholesteric, or discotic liquid crystals. Alternatively, the liquid crystal layer 520 may be made of, for example, a ferroelectric liquid crystal. Alternatively, a liquid crystal material classified as an antiferroelectric liquid crystal can be used. 20 may be, for example, a main chain type polymer liquid crystal, a side chain type polymer liquid crystal, or a composite type polymer liquid crystal. Any liquid crystal material classified as a polymer liquid crystal or a low molecular weight liquid crystal can be used. The liquid crystal layer 520 is made of a liquid crystal material classified as a polymer dispersed liquid crystal (PDLC). You can be there.

[0232] Furthermore, when no alignment film is used, a liquid crystal exhibiting a blue phase may be used for the liquid crystal layer 520. The cholesteric phase is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, The blue phase appears just before the transition from the crystalline phase to the isotropic phase. Therefore, chiral agents and UV-curable resins are added to improve the temperature range. The liquid crystal composition containing the chiral agent has a short response time of 1 msec or less and is optically isotropic. Therefore, alignment treatment is not required, and the viewing angle dependency is small, which is preferable.

[0233] Here, a liquid crystal display device that displays a color image by using a color filter is also described. Although this is an example, the color display method is not limited to this. For example, The light source may be sequentially turned on to display a color image. .

[0234] (Fourth embodiment) In this embodiment, an oxide semiconductor film and the like which form an OS layer of an OS transistor will be described. do.

[0235] <Structure of oxide semiconductor film> The structure of the OS layer of the OS transistor is described below. In this context, "parallel" means that two straight lines are arranged at an angle of between -10° and 10°. Therefore, it also includes the case where the angle is between -5° and 5°. The angle between the two lines is between -30° and 30°. refers to the state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This includes cases where the angle is between 85° and 95°. Also, "almost perpendicular" means that the angle between two straight lines is less than 60°. This refers to a state in which the device is positioned at an angle of 120° or less.

[0236] The OS layer may be formed using a single-crystal oxide semiconductor film or a non-single-crystal oxide semiconductor film. The crystalline oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, and a polycrystalline oxide semiconductor film. Semiconductor film, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor films, etc.

[0237] An amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is disordered and has no crystal component. The entire film is completely amorphous and has no crystal part even in a minute region. A typical example is an oxide semiconductor film having no crystal part.

[0238] A microcrystalline oxide semiconductor film contains, for example, microcrystals (also referred to as nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, the microcrystalline oxide semiconductor film has a higher degree of order than the amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film is characterized in that the density of defect levels is lower than that of the amorphous oxide semiconductor film.

[0239] A CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts.

[0240] <CAAC-OS film> By observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS film with a transmission electron microscope (TEM: Transmission Electron Microscope), a plurality of crystal parts can be confirmed. On the other hand, even with a high-resolution TEM image, it is impossible to confirm a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary). Therefore, it can be said that in a CAAC-OS film, a decrease in electron mobility due to grain boundaries is unlikely to occur.

[0241] When observing a high-resolution TEM image of a cross section of a CAAC-OS film from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms reflects the unevenness of the surface (also referred to as the film formation surface) or the upper surface of the CAAC-OS film. The CAAC-OS film has a shape and is aligned parallel to the surface on which the film is formed or the upper surface.

[0242] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction approximately perpendicular to the sample surface. It was confirmed that the metal atoms in the crystals were arranged in a triangular or hexagonal shape. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0243] When electron diffraction is performed on the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, a potential difference of 1 nm to 30 nm is measured on the top surface of the CAAC-OS film. When electron diffraction using a sagittal beam (also called nanobeam electron diffraction) is performed, spots are observed. (Figure 22A).

[0244] The high-resolution TEM images of the cross section and the plane show that the crystalline part of the CAAC-OS film It can be seen that the film has orientation.

[0245] Most of the crystals in the CAAC-OS film are cubes with sides of less than 100 nm. Therefore, the crystal part included in the CAAC-OS film has a side length of 10n This also includes cases where the size fits within a cube of less than 100 mm, less than 5 nm, or less than 3 nm. In addition, multiple crystals in the CAAC-OS film are connected to form a single large crystal region. For example, in a high-resolution TEM image of a plane, 2 End , 5 μm 2 More than or equal to 1000 μm 2 Crystal regions with more than this size may be observed.

[0246] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was found by structural analysis using the device. In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. You can see that it is oriented vertically.

[0247] On the other hand, in-pla, X-rays are incident on the CAAC-OS film from a direction almost perpendicular to the c-axis. In the analysis by the NE method, a peak may appear at 2θ around 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. InGaZnO4 single crystal oxide In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is obtained. In contrast, in the case of the CAAC-OS film, the 2θ is set to 56 Even when φ is fixed at around 10° and scanned, no clear peak appears.

[0248] From the above, it is concluded that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. Although it is regular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. Therefore, it is clear that the orientation of the crystals is consistent with the previously mentioned high-resolution TEM observation of the cross section. Each layer of metal atoms arranged in layers is parallel to the ab plane of the crystal.

[0249] The crystalline part was formed when the CAAC-OS film was formed or after crystallization treatment such as heat treatment. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed or The orientation is parallel to the normal vector of the top surface. When the crystal c-axis is changed by etching, the CAAC-OS film is formed on the surface of the CAAC-OS film. may not be parallel to the normal vector of the top surface.

[0250] In addition, the distribution of c-axis oriented crystal parts in the CAAC-OS film may not be uniform. For example, the crystalline part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film. When the crystal is formed by the above method, the region near the top surface has more c-axis oriented crystals than the region near the surface on which the crystal is formed. In addition, when impurities are added to the CAAC-OS film, the impurities The added region is transformed, forming regions with different proportions of c-axis oriented crystals. This sometimes happens.

[0251] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ around 31°, a peak also appeared at 2θ around 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferable that the peak is exhibited at 2θ of around 36° and that the peak is not exhibited at 2θ of around 36°.

[0252] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. These are elements other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that constitute the oxide semiconductor film, such as fluorine, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius (or molecular radius) is large, and when it is contained inside the oxide semiconductor film, The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement and cause a decrease in crystallinity. Objects can act as carrier traps or carrier sources.

[0253] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a source of carrier generation.

[0254] Low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or The term "substantially highly purified intrinsic" refers to a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. A transistor using an oxide semiconductor film has electrical characteristics such as a negative threshold voltage ( It is also called marion.) It is rare for it to become high purity genuine or substantially high purity genuine. The oxide semiconductor film has few carrier traps. A transistor using such a material has little fluctuation in electrical characteristics and is highly reliable. Note that it takes a long time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time between the charges is long and the charge may behave as if it is a fixed charge. However, a transistor using an oxide semiconductor film with a high density of defect states has unstable electrical characteristics. There are cases where this happens.

[0255] The electrical characteristics of the OS transistor using the CAAC-OS film are changed by irradiation with visible light or ultraviolet light. The fluctuation is small and the reliability is high.

[0256] The CAAC-OS film is formed by sputtering, for example, using a polycrystalline metal oxide target. When ions collide with the target, the particles contained in the target are The crystal region is cleaved from the ab plane, and the crystal is formed into a flat or pellet-shaped strip with a plane parallel to the ab plane. In this case, the plate-shaped or pellet-shaped particles may peel off as puttering particles. The sputtered particles reach the substrate while maintaining their crystalline state, resulting in CAAC-OS A film can be formed.

[0257] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the impurity concentration (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the processing chamber can be In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas at a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0258] In addition, by increasing the substrate heating temperature during film formation, it is possible to deposit flat or pellet-shaped sputtering. When the particles reach the substrate, migration occurs on the substrate, and the sputtered particles The flat surface is attached to the substrate. For example, the substrate heating temperature is preferably 100°C or more and 740°C or less. Alternatively, the temperature may be set to 200°C or higher and 500°C or lower.

[0259] In addition, increasing the oxygen ratio in the deposition gas and optimizing the power reduces plasma damage during deposition. For example, the ratio of oxygen in the deposition gas is preferably 30% by volume or more. It can be 100% by volume.

[0260] <Microcrystalline oxide semiconductor film> Next, a microcrystalline oxide semiconductor film will be described.

[0261] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a crystal region and a crystal region where no clear crystal part can be identified. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fine particles are often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In addition, the nc-OS film has clearly defined grain boundaries in high-resolution TEM images. It may not be possible to recognize it.

[0262] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS film may be indistinguishable from an amorphous oxide semiconductor film. For example, an XRD apparatus using X-rays with a diameter larger than that of the crystals is used for nc-OS films. When structural analysis is performed using the out-of-plane method, the crystal plane is shown. In addition, the probe diameter ( For example, electron diffraction (also called selected area electron diffraction) is performed using an electron beam of 50 nm or more. On the other hand, for the nc-OS film, Nanobeam electron diffraction using an electron beam with a probe diameter close to or smaller than the size of the crystal part Furthermore, nanobeam electron diffraction was performed on the nc-OS film. When the nc When nanobeam electron diffraction was performed on the -OS film, multiple spots were observed within the ring-shaped region. This may be the case (Figure 22B).

[0263] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher defect state density than the CAAC-OS film.

[0264] <Amorphous oxide semiconductor film> The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and is an oxide film that does not have a crystalline portion. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0265] In the amorphous oxide semiconductor film, no crystalline portion can be confirmed in a high-resolution TEM image.

[0266] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the analysis by the Lane method, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. It is observed.

[0267] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a CA The AC-OS film may be a laminated film having two or more kinds of films.

[0268] When an oxide semiconductor film has multiple structures, the structure can be analyzed using nanobeam electron diffraction. may be possible.

[0269] FIG. 23 shows an example of a transmission electron diffraction measurement device. FIG. 23A shows the outside of the transmission electron diffraction measurement device. The view is shown in FIG. 23B, and its internal structure is shown in FIG.

[0270] The transmission electron diffraction measurement device 9000 comprises an electron gun chamber 9010, an optical system 9012, a sample chamber 9014, and a , an optical system 9016, an observation chamber 9020, and a film chamber 9022. 0, a camera 9018 and a fluorescent screen 9032 are installed. The film chamber 9022 is not necessarily provided.

[0271] Inside the transmission electron diffraction measurement device 9000, an electron gun installed in the electron gun chamber 9010 emits The electrons emitted from the sample enter the material 9028 placed in the sample chamber 9014 via the optical system 9012. The electrons that have passed through the substance 9028 are projected onto a fluorescent screen 9032 via an optical system 9016. On the fluorescent screen 9032, a pattern appears according to the intensity of the incident electrons. A transmission electron diffraction pattern can be measured.

[0272] The camera 9018 is installed facing the fluorescent screen 9032 and captures the patterns that appear on the fluorescent screen 9032. The center of the lens of the camera 9018 and the fluorescent screen 90 The angle between the line passing through the center of the fluorescent screen 9032 and the upper surface of the fluorescent screen 9032 is, for example, 15° or more and 80° or less. 30° or more and 75° or less, or 45° or more and 70° or less. However, the transmission electron diffraction pattern captured by the camera 9018 is distorted. If the angle is known in advance, distortions in the obtained transmission electron diffraction pattern can be corrected. is also possible.

[0273] In some cases, the camera 9018 may be installed in the film chamber 9022. For example, The camera 9018 is installed in the film chamber 9022 so as to face the direction of incidence of the electrons 9024. In this case, a transmission electron diffraction pattern with little distortion can be obtained from the rear surface of the fluorescent screen 9032. You can take pictures.

[0274] The sample chamber 9014 is provided with a holder for fixing a sample substance 9028. The holder is structured to be transparent to electrons passing through the substance 9028. For example, it may have a function to move the substance 9028 in the X-axis, Y-axis, Z-axis, etc. The movement function of the ruler is, for example, 1 nm to 10 nm, 5 nm to 50 nm, 10 nm m or more and 100 nm or less, 50 nm or more and 500 nm or less, 100 nm or more and 1 μm or less The accuracy of the movement within the range is sufficient. These ranges are determined by the structure of the substance 9028. The optimum range can be set by using the above method.

[0275] Next, the transmission electron diffraction pattern of the material is measured using a transmission electron diffraction measurement device 9000. The method will be explained.

[0276] For example, as shown in FIG. 23B, the irradiation of electrons 9024 in a nanobeam on a material 9028 By changing the irradiation position (scanning), the structure of material 9028 changes. In this case, if the substance 9028 is a CAAC-OS film, the If the material 9028 is an nc-OS film, the diffraction pattern shown in , a diffraction pattern such as that shown in Figure 22B is observed.

[0277] By the way, even if the material 9028 is a CAAC-OS film, it may be partially an nc-OS film. Therefore, the quality of the CAAC-OS film can be evaluated. is the ratio of the area where the diffraction pattern of the CAAC-OS film is observed in a certain range (CA It can be expressed as follows: For example, a high-quality CAAC-OS film can be If so, the CAAC conversion rate is 60% or more, preferably 80% or more, and more preferably 90% or more. % or more, and more preferably 95% or more. The area measured is referred to as the non-CAAC rate.

[0278] As an example, immediately after film formation (denoted as as-depo), after heat treatment at 350°C or after heat treatment at 450°C Three types of samples with heat-treated CAAC-OS films were prepared. Transmission electron diffraction patterns were acquired by scanning the top surface at a rate of 5 nm / sec. The diffraction pattern was observed while scanning at a speed of 0.5 s for 60 s, and the observed diffraction pattern was recorded as 0. The CAAC conversion rate was calculated by converting the image into a still image every 5 seconds. A nano-beam electron beam with a diameter of 1 nm was used.

[0279] The CAAC conversion rate for each sample is shown in Figure 24. The CAAC conversion rate was compared immediately after film formation and after heat treatment at 350°C. It can be seen that the CAAC conversion rate is high after heat treatment at 450°C. Heat treatment at high temperatures (e.g., 400°C or higher) reduces the non-CAAC ratio (CA (The AC conversion rate increases.)

[0280] Here, most of the diffraction patterns different from those of the CAAC-OS film are similar to those of the nc-OS film. Therefore, the heat treatment resulted in a film with a similar structure to the nc-OS film. It is suggested that the CAAC structure is influenced by the structure of the adjacent region. By using such a measurement method, it becomes possible to analyze the structure of oxide semiconductor films with multiple structures. There are cases where this happens.

[0281] (Embodiment 5) A variety of electronic devices can be configured using a transistor according to one embodiment of the present invention. For example, electronic devices include display devices, personal computers, and image reproducing devices equipped with recording media. (typically DVD: Digital Versatile Disc) It can be used in a device that has a display that can reproduce and display the image. Other examples of electronic devices in which a transistor according to one embodiment of the present invention can be used include a mobile phone. Phones, game consoles including portable ones, personal digital assistants, e-books, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation audio systems, audio playback devices (car audio, digital audio players, etc.), Copiers, fax machines, printers, multi-function printers, automated teller machines (AT) M), vending machines, etc. Specific examples of these electronic devices are shown in Figure 20.

[0282] FIG. 20A shows a portable game machine, which includes a housing 5001, a housing 5002, a display unit 5003, and a display part 5004, microphone 5005, speaker 5006, operation key 5007, stylus The display unit 5003 or the display unit 5004 and other integrated circuits include A transistor according to one embodiment of the present invention can be used. The portable game machine has two display units 5003 and 5004. The number of display units that the device has is not limited to this.

[0283] FIG. 20B shows a portable information terminal, which includes a first housing 5601, a second housing 5602, and a first display unit 56 03, a second display unit 5604, a connection unit 5605, operation keys 5606, etc. 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected by a connection portion 5605. The angle between the first housing 5601 and the second housing 5602 is The image on the first display unit 5603 can be changed by the connection unit 560 5, the first housing 5601 and the second housing 5602 are switched according to the angle between them. The first display unit 5603 or the second display unit 5604 or other integrated circuits may include this A transistor according to one embodiment of the present invention can be used.

[0284] FIG. 20C shows a notebook personal computer, which includes a housing 5401, a display unit 5402, The computer includes a keyboard 5403, a pointing device 5404, and the like. The transistor according to one embodiment of the present invention can be used in other integrated circuits.

[0285] FIG. 20D shows a wristwatch, which includes a housing 5201, a display unit 5202, operation buttons 5203, and a band. The display portion 5202 and other integrated circuits may include a display unit 5204 and other integrated circuits. A transistor can be used.

[0286] FIG. 20E shows a video camera, which includes a first housing 5801, a second housing 5802, and a display unit 5803. The operation keys 5804, the lens 5805, the connection part 5806, etc. The lens 5805 is provided in the first housing 5801, and the display unit 5803 is provided in the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connection portion 58 5806, and the angle between the first housing 5801 and the second housing 5802 is The video on the display unit 5803 can be changed by connecting The structure is performed according to the angle between the first housing 5801 and the second housing 5802 in the connection portion 5806. The transistor according to one embodiment of the present invention may be used in the display portion 5803 or other integrated circuits. A star can be used.

[0287] FIG. 20F shows a mobile phone, which includes a housing 5901, a display unit 5902, a microphone 5907, a speaker, and the like. A car 5904, a camera 5903, an external connection part 5906, and operation buttons 5905 are provided. The display portion 5902 and other integrated circuits include a transistor according to one embodiment of the present invention. Further, a transistor according to one embodiment of the present invention can be formed on a flexible substrate. When the display device is formed in this manner, a display portion 5902 having a curved surface as shown in FIG. 20F is formed in accordance with one embodiment of the present invention. Such a transistor can be applied.

[0288] A transistor according to one aspect of the present invention is a Si transistor formed on a single crystal silicon wafer. By combining it with a memory, various types of semiconductor devices can be constructed. programmable devices such as CPUs, microcontrollers, FPGAs, and RFID Here we will explain an example of how to use RFID tags.

[0289] RFID tags have a wide range of uses, including banknotes, coins, securities, etc. , bearer bonds, certificates (driver's licenses, resident registration cards, etc., Figure 21A), packaging containers (wrapping paper, Bottles, etc. (Fig. 21C), recording media (DVD software, video tapes, etc. (Fig. 21B)), vehicles (bicycles, etc., Figure 21D), personal belongings (bags, glasses, etc.), food, plants, animals, human body , clothing, daily necessities, medicines and medical supplies, or electronic devices (liquid crystal displays, EL displays) display devices, smartphones, mobile phones, clocks, watches, etc., or attached to each item The tag (FIGS. 21E and 21F) can be used.

[0290] The RFID tag 4000 is fixed to an item by being attached to the surface or embedded therein. For example, if it is a book, it is embedded in the paper, and if it is a package made of organic resin, it is embedded in the organic resin. The RFID tag 4000 is embedded inside and fixed to each item. It is small, thin, and lightweight. Therefore, even after being fixed to an item, the design of the item itself is not impaired. RFID tags 4000 are attached to banknotes, coins, securities, bearer bonds, certificates, etc. By using this authentication function, it is possible to prevent counterfeiting. In addition, packaging containers, recording media, personal belongings, food, clothing, and daily necessities can be stopped. By attaching RFID tags 4000 to goods or electronic devices, etc., inspection systems can be This will improve the efficiency of systems such as inventory management systems. Security can be increased by attaching ID tag 4000. [Explanation of symbols]

[0291] 11 Transistor 12 transistors 13 Transistor 100 boards 101 Insulating layer 102 Insulating layer 111 insulating film 112 insulating film 113 Insulating film 114 insulating film 115 insulating film 120 Conductive film 121 Front gate electrode 130 Oxide semiconductor (OS) layer 131 Metal oxide film (oxide semiconductor film) 132 Metal oxide film 140D Drain electrode 140S Source Electrode 141 Conductive film 142 Conductive film 150 back gate electrode 151 Back gate electrode 152 Electrode 153 Electrode 172 Aperture 173 Aperture

Claims

1. a first conductive film; a first gate insulating film on the first conductive film; an oxide semiconductor film having a region overlapping with the first conductive film with the first gate insulating film interposed therebetween; a second conductive film electrically connected to the oxide semiconductor film; a third conductive film electrically connected to the oxide semiconductor film; a second gate insulating film on the oxide semiconductor film; a fourth conductive film having a region overlapping with the oxide semiconductor film with the second gate insulating film interposed therebetween; the first conductive film has a region that functions as a first gate electrode of a transistor, the oxide semiconductor film has a region that functions as a channel formation region of the transistor, the second conductive film has a region functioning as one of a source electrode and a drain electrode of the transistor, the third conductive film has a region functioning as the other of the source electrode and the drain electrode of the transistor, the fourth conductive film has a region that functions as a second gate electrode of the transistor, the first gate insulating film has a region overlapping an end of the first conductive film in a cross section seen in a channel width direction; an end portion of the fourth conductive film has a region located outside an end portion of the oxide semiconductor film in a cross-sectional view in a channel width direction; an end portion of the fourth conductive film has a region located outside an end portion of the oxide semiconductor film in a cross-sectional view in a channel length direction; a second conductive film formed on the first insulating film and having a first insulating layer formed on the second insulating layer; a second conductive film formed on the second insulating layer and having a second insulating layer formed on the second insulating layer;

2. a first conductive film; a first gate insulating film on the first conductive film; an oxide semiconductor film having a region overlapping with the first conductive film with the first gate insulating film interposed therebetween; a second conductive film electrically connected to the oxide semiconductor film; a third conductive film electrically connected to the oxide semiconductor film; a second gate insulating film on the oxide semiconductor film; a fourth conductive film having a region overlapping with the oxide semiconductor film with the second gate insulating film interposed therebetween; the first conductive film has a region that functions as a first gate electrode of a transistor, the oxide semiconductor film has a region that functions as a channel formation region of the transistor, the second conductive film has a region functioning as one of a source electrode and a drain electrode of the transistor, the third conductive film has a region functioning as the other of the source electrode and the drain electrode of the transistor, the fourth conductive film has a region that functions as a second gate electrode of the transistor, the first gate insulating film has a region overlapping an end of the first conductive film in a cross section seen in a channel width direction; an end portion of the fourth conductive film has a region located outside an end portion of the oxide semiconductor film in a cross-sectional view in a channel width direction; an end portion of the fourth conductive film has a region located outside an end portion of the oxide semiconductor film in a cross-sectional view in a channel length direction; a lower surface of the fourth conductive film has a region located closer to the first conductive film than a lower surface of the oxide semiconductor film in a cross-sectional view in a channel width direction; The semiconductor device is configured such that the fourth conductive film is supplied with the same potential as that of the first conductive film.

3. a first conductive film; a first gate insulating film on the first conductive film; an oxide semiconductor film having a region overlapping with the first conductive film with the first gate insulating film interposed therebetween; a second conductive film electrically connected to the oxide semiconductor film; a third conductive film electrically connected to the oxide semiconductor film; a second gate insulating film on the oxide semiconductor film; a fourth conductive film having a region overlapping with the oxide semiconductor film with the second gate insulating film interposed therebetween; the first conductive film has a region that functions as a first gate electrode of a transistor, the oxide semiconductor film has a region that functions as a channel formation region of the transistor, the second conductive film has a region functioning as one of a source electrode and a drain electrode of the transistor, the third conductive film has a region functioning as the other of the source electrode and the drain electrode of the transistor, the fourth conductive film has a region that functions as a second gate electrode of the transistor, the first gate insulating film has a region overlapping an end of the first conductive film in a cross section seen in a channel width direction; the fourth conductive film has a first region that does not overlap with the oxide semiconductor film in a cross-sectional view in a channel width direction; an end portion of the fourth conductive film has a region located outside an end portion of the oxide semiconductor film in a cross-sectional view in a channel length direction; In the first region, a lower surface of the fourth conductive film is located closer to the first conductive film than a lower surface of the oxide semiconductor film.

4. a first conductive film; a first gate insulating film on the first conductive film; an oxide semiconductor film having a region overlapping with the first conductive film with the first gate insulating film interposed therebetween; a second conductive film electrically connected to the oxide semiconductor film; a third conductive film electrically connected to the oxide semiconductor film; a second gate insulating film on the oxide semiconductor film; a fourth conductive film having a region overlapping with the oxide semiconductor film with the second gate insulating film interposed therebetween; the first conductive film has a region that functions as a first gate electrode of a transistor, the oxide semiconductor film has a region that functions as a channel formation region of the transistor, the second conductive film has a region functioning as one of a source electrode and a drain electrode of the transistor, the third conductive film has a region functioning as the other of the source electrode and the drain electrode of the transistor, the fourth conductive film has a region that functions as a second gate electrode of the transistor, the first gate insulating film has a region overlapping an end of the first conductive film in a cross section seen in a channel width direction; the fourth conductive film has a first region that does not overlap with the oxide semiconductor film in a cross-sectional view in a channel width direction; an end portion of the fourth conductive film has a region located outside an end portion of the oxide semiconductor film in a cross-sectional view in a channel length direction; in the first region, a lower surface of the fourth conductive film is located closer to the first conductive film than a lower surface of the oxide semiconductor film; The semiconductor device is configured such that the fourth conductive film is supplied with the same potential as that of the first conductive film.

5. a first conductive film; a first gate insulating film on the first conductive film; an oxide semiconductor film having a region overlapping with the first conductive film with the first gate insulating film interposed therebetween; a second conductive film electrically connected to the oxide semiconductor film; a third conductive film electrically connected to the oxide semiconductor film; a second gate insulating film on the oxide semiconductor film; a fourth conductive film having a region overlapping with the oxide semiconductor film with the second gate insulating film interposed therebetween; the first conductive film has a region that functions as a first gate electrode of a transistor, the oxide semiconductor film has a region that functions as a channel formation region of the transistor, the second conductive film has a region functioning as one of a source electrode and a drain electrode of the transistor, the third conductive film has a region functioning as the other of the source electrode and the drain electrode of the transistor, the fourth conductive film has a region that functions as a second gate electrode of the transistor, the first gate insulating film has a region overlapping an end of the first conductive film in a cross section seen in a channel width direction; an end portion of the first conductive film has a region located outside an end portion of the oxide semiconductor film in a cross-sectional view in a channel width direction; an end portion of the fourth conductive film has a region located outside an end portion of the oxide semiconductor film in a cross-sectional view in a channel width direction; an end portion of the fourth conductive film has a region located outside an end portion of the oxide semiconductor film in a cross-sectional view in a channel length direction; a second conductive film formed on the first insulating film and having a first insulating layer formed on the second insulating layer; a second conductive film formed on the second insulating layer and having a second insulating layer formed on the second insulating layer;

6. a first conductive film; a first gate insulating film on the first conductive film; an oxide semiconductor film having a region overlapping with the first conductive film with the first gate insulating film interposed therebetween; a second conductive film electrically connected to the oxide semiconductor film; a third conductive film electrically connected to the oxide semiconductor film; a second gate insulating film on the oxide semiconductor film; a fourth conductive film having a region overlapping with the oxide semiconductor film with the second gate insulating film interposed therebetween; the first conductive film has a region that functions as a first gate electrode of a transistor, the oxide semiconductor film has a region that functions as a channel formation region of the transistor, the second conductive film has a region functioning as one of a source electrode and a drain electrode of the transistor, the third conductive film has a region functioning as the other of the source electrode and the drain electrode of the transistor, the fourth conductive film has a region that functions as a second gate electrode of the transistor, the first gate insulating film has a region overlapping an end of the first conductive film in a cross section seen in a channel width direction; an end portion of the first conductive film has a region located outside an end portion of the oxide semiconductor film in a cross-sectional view in a channel width direction; an end portion of the fourth conductive film has a region located outside an end portion of the oxide semiconductor film in a cross-sectional view in a channel width direction; an end portion of the fourth conductive film has a region located outside an end portion of the oxide semiconductor film in a cross-sectional view in a channel length direction; a lower surface of the fourth conductive film has a region located closer to the first conductive film than a lower surface of the oxide semiconductor film in a cross-sectional view in a channel width direction; The semiconductor device is configured such that the fourth conductive film is supplied with the same potential as that of the first conductive film.

7. a first conductive film; a first gate insulating film on the first conductive film; an oxide semiconductor film having a region overlapping with the first conductive film with the first gate insulating film interposed therebetween; a second conductive film electrically connected to the oxide semiconductor film; a third conductive film electrically connected to the oxide semiconductor film; a second gate insulating film on the oxide semiconductor film; a fourth conductive film having a region overlapping with the oxide semiconductor film with the second gate insulating film interposed therebetween; the first conductive film has a region that functions as a first gate electrode of a transistor, the oxide semiconductor film has a region that functions as a channel formation region of the transistor, the second conductive film has a region functioning as one of a source electrode and a drain electrode of the transistor, the third conductive film has a region functioning as the other of the source electrode and the drain electrode of the transistor, the fourth conductive film has a region that functions as a second gate electrode of the transistor, the first gate insulating film has a region overlapping an end of the first conductive film in a cross section seen in a channel width direction; an end portion of the first conductive film has a region located outside an end portion of the oxide semiconductor film in a cross-sectional view in a channel width direction; the fourth conductive film has a first region that does not overlap with the oxide semiconductor film in a cross-sectional view in a channel width direction; an end portion of the fourth conductive film has a region located outside an end portion of the oxide semiconductor film in a cross-sectional view in a channel length direction; In the first region, a lower surface of the fourth conductive film is located closer to the first conductive film than a lower surface of the oxide semiconductor film.

8. a first conductive film; a first gate insulating film on the first conductive film; an oxide semiconductor film having a region overlapping with the first conductive film with the first gate insulating film interposed therebetween; a second conductive film electrically connected to the oxide semiconductor film; a third conductive film electrically connected to the oxide semiconductor film; a second gate insulating film on the oxide semiconductor film; a fourth conductive film having a region overlapping with the oxide semiconductor film with the second gate insulating film interposed therebetween; the first conductive film has a region that functions as a first gate electrode of a transistor, the oxide semiconductor film has a region that functions as a channel formation region of the transistor, the second conductive film has a region functioning as one of a source electrode and a drain electrode of the transistor, the third conductive film has a region functioning as the other of the source electrode and the drain electrode of the transistor, the fourth conductive film has a region that functions as a second gate electrode of the transistor, the first gate insulating film has a region overlapping an end of the first conductive film in a cross section seen in a channel width direction; an end portion of the first conductive film has a region located outside an end portion of the oxide semiconductor film in a cross-sectional view in a channel width direction; the fourth conductive film has a first region that does not overlap with the oxide semiconductor film in a cross-sectional view in a channel width direction; an end portion of the fourth conductive film has a region located outside an end portion of the oxide semiconductor film in a cross-sectional view in a channel length direction; in the first region, a lower surface of the fourth conductive film is located closer to the first conductive film than a lower surface of the oxide semiconductor film; The semiconductor device is configured such that the fourth conductive film is supplied with the same potential as that of the first conductive film.

9. In any one of claims 1 to 8, The semiconductor device, wherein the oxide semiconductor film contains In, M (M is Ga, Y, Zr, La, Ce, or Nd), and Zn.

10. In any one of claims 1 to 9, The fourth conductive film includes titanium and molybdenum.

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