Memory System

Abstract

To provide a semiconductor storage device and a memory system for suppressing peak current.SOLUTION: A semiconductor storage device of the embodiment includes: a first pad; a clock generation circuit for generating a first clock; an output circuit for outputting the first clock from the first pad; a designation circuit for designating one of a plurality of time slots generated based on the first clock as a specific time slot; and a peak control circuit for executing a partial operation in which the current peak occurs at a timing corresponding to the specific time slot when an operation is instructed.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] An embodiment of the present invention comprises: M Regarding Mori system. [Background technology]

[0002] In recent years, NAND type memories have become widespread as semiconductor storage devices.

[0003] In such semiconductor memory devices, there is a demand for suppressing peak current. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-58860 Summary of the Invention [Problem to be solved by the invention]

[0005] This embodiment can suppress the peak current. M We provide a Mori system. [Means for solving the problem]

[0006] The semiconductor memory device of the embodiment includes a first pad, a clock generation circuit that generates a first clock, an output circuit that outputs the first clock from the first pad, a designation circuit that designates one of a plurality of time slots generated based on the first clock as a specific time slot, and a peak control circuit that, when an operation is instructed, executes a partial operation that generates a current peak at a timing corresponding to the specific time slot. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a memory system according to an embodiment. [Figure 2]2 is a schematic cross-sectional view illustrating a structural example of a memory device in which memory chips 2 are stacked. FIG. [Figure 3] FIG. 1 is a block diagram showing an example of the configuration of a memory system having a plurality of packages. [Figure 4] FIG. 1 is an explanatory diagram showing an example of the configuration of one package. [Figure 5] FIG. 2 is a block diagram showing an example of the configuration of a nonvolatile memory according to the embodiment; [Figure 6] FIG. 3 is a circuit diagram showing a part of the configuration of an input / output circuit 22. [Figure 7] FIG. 2 is a circuit diagram showing a part of the configuration of a logic control circuit 21. [Figure 8] FIG. 4 is an explanatory diagram for explaining generation of a peak enable signal. [Figure 9] FIG. 4 is an explanatory diagram for explaining generation of a peak enable signal. [Figure 10] FIG. 10 is an explanatory diagram for explaining peak operation control. [Figure 11] FIG. 10 is an explanatory diagram for explaining a current generated during peak operation. [Figure 12] FIG. 10 is an explanatory diagram for explaining a current generated during peak operation. [Figure 13] FIG. 10 is an explanatory diagram for explaining peak operation control in a specific memory chip 2. [Figure 14] FIG. 10 is an explanatory diagram showing another embodiment of the present invention. [Figure 15] 10 is a timing chart showing a SetFeature sequence. [Figure 16] 10 is a timing chart showing a SetFeature sequence. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0009] (First embodiment) In this embodiment, in a multi-chip semiconductor memory device, a specific chip is designated as a leader and the other chips are designated as followers, and the clock generated by the leader is used by all chips to control the operation of each chip, thereby suppressing peak current.

[0010] (Memory system configuration) FIG. 1 is a block diagram showing an example of the configuration of a memory system according to an embodiment. The memory system of this embodiment includes a memory controller 1 and one or more NAND-type nonvolatile memories. FIG. 1 shows an example including four NAND-type nonvolatile memories 2A to 2D. Hereinafter, when there is no need to distinguish between the four NAND-type nonvolatile memories 2A to 2D, they will be collectively referred to as the NAND-type nonvolatile memory 2. The NAND-type nonvolatile memory will also be simply referred to as the nonvolatile memory. The memory system can be connected to a host (not shown). The host is, for example, an electronic device such as a personal computer or a mobile terminal. Each nonvolatile memory 2 is formed into a chip. In the following description, the nonvolatile memory 2 will also be referred to as a memory chip 2. Such memory chips 2 may be stacked within a memory device.

[0011] 2 is a schematic cross-sectional view for explaining a structural example of a memory device in which memory chips 2 are stacked. n 2 are stacked on the wiring board 7. n When there is no need to distinguish between them, they are referred to as memory chips 2. The memory device 5 achieves high storage density and large storage capacity by using multiple memory chips 2.

[0012] In order to reduce the size (area) of the package, multiple memory chips 2 are stacked on a substrate. The stacked memory chips 2 are connected to each other using bonding wires 6 or through electrodes.

[0013] For example, as shown in FIG. 2, the upper memory chip 2 is connected to the upper memory chip 2 by bonding wires 6. n and the lower memory chip 2 n-1 When the upper memory chip 2 is connected to the n However, the lower memory chip 2 n-1 The memory chips 2 in the lower layer are stacked at a fixed interval. n-1 The pad 4A on the upper layer memory chip 2 n It is exposed without being covered by anything.

[0014] For example, pads 4A of each memory chip 2 are connected to a common bonding wire 6, which is then connected to terminals 5 of wiring board 7. In this way, multiple memory chips 2 share wiring for inputting and outputting signals. For this reason, multiple memory chips 2 cannot drive data lines individually. Therefore, of multiple nonvolatile memories (and controllers) that share data lines, only one chip can output data.

[0015] (peak current) When a multi-chip configuration such as that shown in Figure 2 is adopted, the timing of cell operations of multiple memory chips 2 may coincide. In this case, current peaks generated in each memory chip 2 due to cell operations may occur simultaneously, resulting in a higher-than-expected peak current overall. Therefore, TDPPM (Time Division Peak Power Management) may be adopted to manage the period during which current peaks are allowed to occur for each memory chip 2.

[0016] However, this management method requires that a common clock be provided to all memory chips 2 to manage cell operation. Conventionally, in TDPPM, a common clock is supplied from the controller to all memory chips 2. This has the drawback of increasing the number of terminals and wiring required for clock supply, which increases the load on the controller.

[0017] One possible solution is to manage the peak generation period using an internal clock generated within each memory chip 2. However, in this case, it is necessary to synchronize each internal clock at a predetermined interval, and moreover, it is not possible to reliably manage the peak current during long-term operation.

[0018] (Leader and Follower) Therefore, in this embodiment, a clock is generated in a specific memory chip (hereinafter also referred to as the leader) among all memory chips 2, and the clock generated by the leader is supplied to all other memory chips (hereinafter also referred to as the followers) using a terminal commonly connected to all memory chips 2, thereby enabling TDPPM to stably manage the period during which peak currents are generated.

[0019] In FIG. 1, nonvolatile memories (memory chips) 2 are semiconductor storage devices that store data nonvolatilely. As shown in FIG. 1, a memory controller 1 and each nonvolatile memory 2 are connected via a NAND bus. The memory controller 1 controls writing of data to the nonvolatile memory 2 in accordance with a write request from the host. The memory controller 1 also controls reading of data from the nonvolatile memory 2 in accordance with a read request from the host. The memory controller 1 includes a RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correct) circuit 14, and a memory interface 15. The RAM 11, the processor 12, the host interface 13, the ECC circuit 14, and the memory interface 15 are connected to one another via an internal bus 16.

[0020] The host interface 13 outputs requests received from the host, write data which is user data, and the like to the internal bus 16. The host interface 13 also transmits user data read from the nonvolatile memory 2, responses from the processor 12, and the like to the host.

[0021] The memory interface 15 controls the process of writing user data and the like to the nonvolatile memory 2 and the process of reading user data and the like from the nonvolatile memory 2 based on instructions from the processor 12 .

[0022] The processor 12 performs overall control of the memory controller 1. The processor 12 is, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). When the processor 12 receives a request from the host via the host interface 13, it performs control in accordance with the request. For example, the processor 12 instructs the memory interface 15 to write user data and parity to the nonvolatile memory 2 in accordance with the request from the host. Furthermore, the processor 12 instructs the memory interface 15 to read user data and parity from the nonvolatile memory 2 in accordance with the request from the host.

[0023] The processor 12 determines a storage area (hereinafter referred to as a memory area) on the nonvolatile memory 2 for user data to be accumulated in the RAM 11. The user data is stored in the RAM 11 via the internal bus 16. The processor 12 determines the memory area for data in units of pages, which are writing units, i.e., page data. In this specification, user data stored in one page of the nonvolatile memory 2 is defined as unit data. The unit data is, for example, encoded and stored in the nonvolatile memory 2 as a code word.

[0024] Note that encoding is not essential. The memory controller 1 may store the unit data in the nonvolatile memory 2 without encoding it, but FIG. 1 shows a configuration in which encoding is performed as an example. When the memory controller 1 does not perform encoding, the page data matches the unit data. Also, one code word may be generated based on one unit data, or one code word may be generated based on divided data into which the unit data is divided. Also, one code word may be generated using multiple unit data.

[0025] The processor 12 determines the memory area in the nonvolatile memory 2 to which the unit data is to be written for each unit data. A physical address is assigned to the memory area in the nonvolatile memory 2. The processor 12 manages the memory area to which the unit data is to be written using the physical address. The processor 12 instructs the memory interface 15 to write the user data to the nonvolatile memory 2 by specifying the physical address of the determined memory area. The processor 12 manages the correspondence between the logical address of the user data (logical address managed by the host) and the physical address. When the processor 12 receives a read request including a logical address from the host, it identifies the physical address corresponding to the logical address and instructs the memory interface 15 to read the user data by specifying the physical address.

[0026] The ECC circuit 14 generates code words by encoding the user data stored in the RAM 11. The ECC circuit 14 also decodes code words read from the nonvolatile memory 2. The RAM 11 temporarily stores user data received from the host before storing it in the nonvolatile memory 2, and temporarily stores data read from the nonvolatile memory 2 before transmitting it to the host. The RAM 11 is, for example, a general-purpose memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory).

[0027] 1 shows an example of a configuration in which the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 may be built into the memory interface 15. Alternatively, the ECC circuit 14 may be built into the nonvolatile memory 2.

[0028] When a write request is received from the host, the memory controller 1 operates as follows: The processor 12 temporarily stores write data in the RAM 11. The processor 12 reads the data stored in the RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and provides the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the non-volatile memory 2.

[0029] When a read request is received from the host, the memory controller 1 operates as follows: The memory interface 15 provides the code word read from the nonvolatile memory 2 to the ECC circuit 14. The ECC circuit 14 decodes the input code word and stores the decoded data in the RAM 11. The processor 12 transmits the data stored in the RAM 11 to the host via the host interface 13.

[0030] The processor 12 of the memory controller 1 controls the memory interface 15 to transmit the signal DQ<7:0> and the data strobe signals DQS and / DQS to the nonvolatile memory 2. The signal DQ<7:0> transmitted from the memory controller 1 to the nonvolatile memory 2 includes a command, an address, and data. This data includes SetFeature data, which is a setting value for various operation modes of the nonvolatile memory 2, and write data, which is the target of a write operation to the memory cell array 23, which will be described later. The data strobe signals DQS and / DQS are synchronous control signals that indicate the read and write timings that occur in synchronization with data transfer.

[0031] The processor 12 controls the memory interface 15 to send chip enable signals / CE, CLE, ALE, / WE, and read enable signals RE and / RE to the nonvolatile memories 2. The signal / CE is a signal for putting each nonvolatile memory 2 into an operating state. The write enable signal / WE is a signal that enables writing, and the nonvolatile memory 2 receives this signal / WE to acquire a command and an address. In other words, the signal / WE may be called an acquisition signal. The command latch enable signal CLE is a signal that enables latching of a command, and the address latch enable signal ALE is a signal that enables latching of an address.

[0032] Signals preceded by the symbol " / " indicate that they are active low or non-logical. That is, signals without a leading symbol " / " are active when they are at a "H" level, while signals preceded by a " / " are active when they are at a "L" level.

[0033] Meanwhile, the nonvolatile memory 2 receives various signals from the memory controller 1 by an input / output circuit 22, which will be described later, and transmits signals DQ<7:0> and data strobe signals DQS and / DQS to the memory controller 1. The nonvolatile memory 2 also transmits a signal R / B to the memory controller 1. The ready / busy signal R / B indicates whether the memory is in a ready state in which it can accept an external command, or in a busy state in which it cannot accept an external command.

[0034] Although the memory controller 1 is capable of outputting a write protect signal / WP, in this embodiment, the terminals (pads) / WP used to transmit the write protect signal / WP are commonly connected to each other in each memory chip 2, so the write protect signal / WP is not received in each memory chip 2.

[0035] Four memory chips 2 may be packaged. In the example of Fig. 1, one memory controller 1 controls four memory chips 2 included in one package. Also, one memory controller 1 may control memory chips 2 included in multiple packages.

[0036] Fig. 3 is a block diagram showing an example of this case, and Fig. 4 is an explanatory diagram showing an example of the configuration of one package.

[0037] As shown in Figure 3, the memory controller 1 and each package P0 to PN-1 (hereinafter referred to as package P when there is no need to distinguish between these packages) are connected by a NAND bus, and each signal except for the write protect signal / WP is transmitted between the memory controller 1 and each memory chip 2 in the package P. In addition, wiring is provided between the memory controller 1 and each package P to individually supply a chip enable signal / CE. A power supply voltage is supplied to each package P from a predetermined power supply.

[0038] In this embodiment, the terminal / WP for receiving the write protect signal / WP is used to connect the memory chips 2 in each package P together, as described above.

[0039] As shown in FIG. 4, each package P has multiple memory chips 2 (LUN0 to LUN3). Note that while FIG. 4 shows an example in which the package P is configured with four memory chips 2, the number of memory chips 2 included in the package P is not limited. As shown in FIG. 4, various wirings for supplying various signals and power, except for the write protect signal / WP, are shared by each memory chip 2 in the package P. That is, in the package P, signals ALE, CLE, DQ, DQS, / DQS, / WE, / RE, RE, etc. are shared, and a group to which these signal lines are supplied is also called a channel. That is, in the example of FIG. 4, a channel is configured by one package P. In the example of FIG. 4, only one chip enable signal / CE is supplied in the package P, but one package P may have groups driven by multiple chip enable signals / CE.

[0040] A chip address is used to select each memory chip 2 in a group driven by one chip enable signal / CE. In the example of FIG. 4, four memory chips 2 are selected by the chip enable signal / CE, so each memory chip 2 can be identified by a 2-bit chip address. The memory chip 2 identified by the chip address is called an LUN. The example of FIG. 4 shows an example in which four LUNs, LUN0 to LUN3, exist in one package P.

[0041] (Non-volatile memory configuration) 5 is a block diagram showing an example of the configuration of the nonvolatile memory of this embodiment. The nonvolatile memory (memory chip) 2 includes a logic control circuit 21, an input / output circuit 22, a memory cell array 23, a sense amplifier 24, a row decoder 25, an address register 26a, a command register 26b, a control circuit 27, a voltage generation circuit 28, an R / B signal generation circuit 30, an input / output pad group 32, and a logic control pad group 33.

[0042] The memory cell array 23 includes a plurality of blocks (memory blocks). Each of the plurality of blocks BLK includes a plurality of memory cell transistors (memory cells). The memory cell array 23 includes a plurality of bit lines, a plurality of word lines, a source line, and the like, for controlling the voltage applied to the memory cell transistors.

[0043] The input / output pad group 32 has a plurality of terminals (pads) corresponding to the signals DQ<7:0> and data strobe signals DQS and / DQS in order to transmit and receive signals including data to and from the memory controller 1.

[0044] The logic control pad group 33 has a plurality of terminals (pads) corresponding to the chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, and read enable signals RE and / RE to transmit and receive various signals to and from the memory controller 1.

[0045] In this embodiment, the terminal (pad) / WP corresponding to the write protect signal / WP is used to transmit the clock CK between the leader and follower.

[0046] The logic control circuit 21 and the input / output circuit 22 are connected to the memory controller 1 via a NAND bus. The logic control circuit 21 receives external control signals (e.g., a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, and a read enable signal RE, / RE) from the memory controller 1 via the NAND bus. In addition, the R / B signal generation circuit 30 transmits a ready / busy signal R / B to the memory controller 1 via the NAND bus.

[0047] The address register 26a holds an address, and the command register 26b holds a command. The address registers 26a and 26b are configured by, for example, an SRAM.

[0048] The nonvolatile memory 2 is supplied with various operating power supplies, power supply voltages Vcc, VccQ, and Vpp, and a ground voltage Vss, from the outside. The power supply voltage Vcc is a circuit power supply voltage generally provided from the outside as an operating power supply, and is, for example, a voltage of about 2.5 V. The power supply voltage VccQ is, for example, a voltage of 1.2 V. The power supply voltage VccQ is used when transmitting and receiving signals between the memory controller 1 and the nonvolatile memory 2. The power supply voltage Vpp is a power supply voltage that is higher than the power supply voltage Vcc, and is, for example, a voltage of 12 V.

[0049] The control circuit 27 receives a command from the command register 26b and controls each part of the nonvolatile memory 2 in accordance with a sequence based on this command.

[0050] The voltage generation circuit 28 is controlled by the control circuit 27 to receive a power supply voltage from outside the nonvolatile memory 2 and generate a plurality of voltages required for write, read, and erase operations using this power supply voltage. The voltage generation circuit 28 supplies the generated voltages to the memory cell array 23, the sense amplifier 24, the row decoder 25, etc.

[0051] The row decoder 25 receives a row address from the register 26a and decodes the row address. The row decoder 25 selects a word line based on the decoded row address. The row decoder 25 then transfers multiple voltages required for write, read, and erase operations to the selected block.

[0052] The sense amplifier unit group 24A of the sense amplifier 24 receives a column address from the register 26a and decodes this column address. The sense amplifier unit group 24A selects one of the bit lines based on the decoded column address. When reading data, the sense amplifier unit group 24A detects and amplifies data read from the memory cell transistors onto the bit lines. When writing data, the sense amplifier unit group 24A transfers write data to the bit lines.

[0053] The sense amplifier 24 has a data register 24B, and when reading data, the data register 24B holds the data detected by the sense amplifier unit group 24A and transfers it serially to the input / output circuit 22. When writing data, the data register 24B holds the data transferred serially from the input / output circuit 22 and transfers it to the sense amplifier unit group 24A. The data register 24B is configured with an SRAM or the like.

[0054] The input / output circuit 22 is controlled by the logic control circuit 21, and transmits and receives signals DQ (for example, DQ0 to DQ7) and signals DQS and / DQS to and from the memory controller 1 via the NAND bus.

[0055] Fig. 6 is a circuit diagram showing a part of the configuration of the input / output circuit 22. As shown in Fig. 6, the input / output circuit 22 has an input receiver 22a and an output driver 22b for each terminal of the input / output pad group 32. The input receiver 22a receives a signal input via each terminal, and the output driver 22b transmits a signal to be output via each terminal.

[0056] When the input / output circuit 22 is supplied with the signal DQ together with the signals DQS and / DQS, the input / output circuit 22 is configured to receive the signal DQ as data in synchronization with the signals DQS and / DQS. In addition, the input / output circuit 22 transmits data read from the memory cell array 23 as the signal DQ to the memory controller 1 together with the signals DQS and / DQS in response to the signal RE supplied to the logic control circuit 21.

[0057] The input / output circuit 22 is controlled by the logic control circuit 21 to enable signal transfer corresponding to the signal / WE and signal transfer corresponding to the signals DQS and / DQS. The input / output circuit 22 is controlled by the logic control circuit 21 to output the various signals it receives to the address register 26 a or the command register 26 b.

[0058] The logic control circuit 21 determines, based on the address Cadd, whether or not signal transfer between itself and its nonvolatile memory 2 is specified by the memory controller 1. The logic control circuit 21 controls the input / output circuit 22 in response to the signal CLE to enable output of the command received as the signal DQ to the command register 26b. The logic control circuit 21 controls the input / output circuit 22 in response to the signal ALE to enable output of the address received as the signal DQ to the address register 26a. The logic control circuit 21 outputs the signal received by the input / output circuit 22 to each unit in synchronization with the signal / WE to enable writing.

[0059] When a command is given from the command register 26b, the control circuit 27 analyzes the command and controls the logic control circuit 21 based on the analysis result.

[0060] (Peak operation control) In this embodiment, when a peak control start command is input, the control circuit 27 executes peak management using TDPPM.

[0061] The memory cell array 23 is provided with an area (hereinafter referred to as the ROM area) for storing system information for setting the system operation. In this embodiment, the ROM area also stores peak management information for TDPPM. In TDPPM, time slots (hereinafter simply referred to as slots) synchronized with the clock CK are set, and numbers (hereinafter referred to as slot numbers) specifying the slots are set in a cycle of a predetermined number of slots (hereinafter referred to as the total number of slots). Peak current management (peak operation control) is performed by identifying slots in which peak currents can be generated for each memory chip 2.

[0062] The peak management information stored in the ROM area includes information on the division period for setting the clock frequency used to control the TDPPM, information on the total number of slots indicating the period in which the slot numbers complete a cycle, information on slot allocation numbers that specify slots that are allowed to generate current peaks, and leader-follower information that indicates whether a slot is a leader or a follower. Note that the slot allocation number information and leader-follower information are set for each memory chip 2.

[0063] The system information including the peak management information is read by a power-on read that is executed immediately after starting up the memory system or memory chip 2. The memory chip 2 controls the write and read operations of user data using the system information and peak management information read from the ROM area by the power-on read.

[0064] The control circuit 27 includes a peak control circuit 27a and a ROM register 27b. The ROM register 27b stores system information and peak management information read by power-on read. The peak control circuit 27a controls the timing of peak currents flowing through the memory chip 2. That is, the peak control circuit 27a suspends a peak operation until a peak enable signal is input, which allows the execution of a partial operation (hereinafter referred to as a peak operation) that generates a current peak among the operations of the memory chip 2. For example, in a read operation, a channel clean operation is one of the partial operations (peak operations) that are subject to current peak control. The peak control circuit 27a controls peak operations such as the channel clean operation by waiting for the input of a peak enable signal (peak operation control), thereby preventing the peak current from increasing more than expected. Note that the peak control circuit 27a may be configured to execute the peak operation at a timing corresponding to the input of the peak enable signal by appropriate timing adjustment.

[0065] The control circuit 27 outputs the peak management information stored in the ROM register 27b to the logic control circuit 21 in order to generate a peak enable signal.

[0066] (Configuration of logic control circuit for peak operation control) 7 is a circuit diagram showing a portion of the configuration of the logic control circuit 21. The logic control circuit 21 has an input receiver 21a for each terminal of the logic control pad group 33. The input receiver 21a receives signals input via each terminal. The logic control circuit 21 also has an output driver 21b corresponding to the terminal / WP in the logic control pad group 33. The input receiver 21a receives signals input via each terminal. As will be described later, the input receiver 21a corresponding to the terminal / WP receives a clock CK transmitted from the terminal / WP of another memory chip 2, and the output driver 21b transmits the clock CK to be provided to the other memory chip 2 via the terminal / WP.

[0067] As shown in FIG. 5, the logic control circuit 21 includes a circuit section for controlling the input / output circuit 22, as well as a control section 41, a clock (CLK) oscillator 42, a frequency divider 43, an output circuit 44, an input circuit 45, a multiplexer 46, and a peak operation permission circuit 47. The input circuit 45 corresponds to the input receiver 21a in FIG. 7, and the output circuit 44 corresponds to the output driver 21b in FIG. 7. The control section 41 controls the entire logic control circuit 21. The control section 41 may be configured with a processor using a CPU, an FPGA (Field Programmable Gate Array), or the like. The control section 41 may operate according to a program stored in a memory (not shown) to control each section, or may realize some or all of its functions using a hardware electronic circuit. The control section 41 controls each section based on peak management information.

[0068] The clock oscillator 42 generates a clock of a predetermined frequency and outputs it to the frequency divider 43. The frequency divider 43 is specified by the control unit 41 with a division number based on the information on the frequency division period in the peak management information, and divides the output clock of the clock oscillator 42 to generate a clock CK. The frequency divider 43 outputs the clock CK obtained by dividing the frequency to the output circuit 44 and the multiplexer 46. The clock oscillator 42 and the frequency divider 43 form a clock generation circuit.

[0069] The output circuit 44 is controlled by the control unit 41 to output the clock CK from the frequency divider 43 to the terminal / WP. The input circuit 45 is controlled by the control unit 41 to receive the clock CK input via the terminal / WP. The input circuit 45 outputs the received clock CK to the multiplexer 46.

[0070] The multiplexer 46 is controlled by the control unit 41 to select either the clock CK from the frequency divider 43 or the clock CK received by the input circuit 45 and output it to the peak operation permission circuit 47 .

[0071] In this embodiment, the control unit 41 determines whether it has been designated as a leader or a follower based on the leader / follower information in the peak management information stored in the ROM register 27b. The control unit 41 of the memory chip designated as the leader operates the clock oscillator 42, the frequency divider 43, the output circuit 44, the multiplexer 46, and the permitted operation permission circuit 47. The control unit 41 of the memory chip designated as the follower operates the input circuit 45, the multiplexer 46, and the peak operation permission circuit 47.

[0072] That is, in the logic control circuit 21 of the memory chip designated as the leader, the output circuit 44 outputs the clock CK via the terminal / WP to each memory chip 2 connected to the terminal / WP. Also, in the logic control circuit 21 of the memory chip designated as the follower, the input circuit 45 receives the clock CK output from the other memory chips 2 via the terminal / WP. The control unit 41 of the memory chip designated as the leader causes the multiplexer 46 to select the clock CK output by the frequency divider 43 and provides it to the peak operation permission circuit 47, and the control unit 41 of the memory chip designated as the follower causes the multiplexer 46 to select the clock CK output by the frequency divider 43 and provides it to the peak operation permission circuit 47.

[0073] In this embodiment, the peak operation permission circuit 47, which serves as a designation circuit, is controlled by the control unit 41 to generate a peak enable signal for controlling the timing at which a peak current is generated. For example, the peak operation permission circuit 47 may be configured with a shift register. The peak operation permission circuit 47 recognizes the current slot number by counting the clock CK input via the multiplexer 46 while resetting a count value based on information about the total number of slots. The peak operation permission circuit 47 is given a slot assignment number by the control unit 41, and generates a peak enable signal in synchronization with the timing at which the current slot number reaches the slot assignment number. The peak operation permission circuit 47 outputs the generated peak enable signal to the peak control circuit 27a.

[0074] 8 and 9 are explanatory diagrams for explaining generation of the peak enable signal.

[0075] The example in FIG. 8 is an example where the total number of slots is 4 and the slot assignment number set for a specific memory chip 2 is 0. The example in FIG. 9 is an example where the total number of slots is 8 and the slot assignment number set for a specific memory chip 2 is 2.

[0076] As described above, the peak operation permission circuit 47 counts the clock CK while resetting the count value by the total number of slots, thereby obtaining the current slot number. That is, in the example of FIG. 8, the slot numbers 0, 1, 2, 3, 0, 1, ... are obtained. The peak operation permission circuit 47 generates a peak enable signal when the current slot number reaches the slot assignment number. In the example of FIG. 8, since the slot assignment number is 0, a peak enable signal that goes high is obtained each time the count value reaches 0.

[0077] 9, the slot numbers obtained are 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, .... In the example of Fig. 9, since the slot allocation number is 2, a peak enable signal that goes high every time the count value reaches 2 is obtained.

[0078] (operation) Next, the operation of the embodiment configured as above will be described with reference to Figures 10 to 13. Figure 10 is an explanatory diagram for explaining peak operation control. Figures 11 and 12 are explanatory diagrams for explaining currents generated during peak operation, and Figure 13 is an explanatory diagram for explaining peak operation control in a specific memory chip 2.

[0079] 10, the horizontal axis represents time, and shows the periods of peak operation due to commands from the memory controller 1 and peak operation control of each of the N+1 memory chips 2 (memory chips Die0 to DieN in FIG. 10). Note that in the example of FIG. 10, the peak management information stored in the ROM area of ​​the memory cell array 23 includes the division period, the total number of slots N, the slot allocation number for each of the memory chips Die0 to DieN, and information indicating that the memory chip Die0 is the leader and the other memory chips Die1 to DieN are followers.

[0080] After power-on, each memory chip Die0 to DieN receives a power-on read command FFh sent from the memory controller 1. The power-on read command FFh does not include a chip address Cadd. That is, when each memory chip Die0 to DieN receives the command FFh, it executes a power-on read operation regardless of the chip address of each memory chip Die0 to DieN. When each memory chip Die0 to DieN receives the command FFh, it reads system information and peak management information from the ROM area of ​​its respective memory cell array 23 and stores them in the ROM register 27b of the control circuit 27. A command that does not include a chip address Cadd, such as the power-on read command FFh, is also called a broadcast command. In contrast, a command that includes a chip address Cadd is also called an individual command.

[0081] In the example of Figure 10, by power-on-read (POR), memory chip Die0 is set as the leader and 0 is set as its slot allocation number. Also, memory chips Die1 to DieN are set as followers and 1 to N are set as their slot allocation numbers, respectively. Also, information about the clock period and the total number of slots is set in memory chips Die0 to DieN.

[0082] The control circuit 27 of each memory chip Die0 to DieN waits for a peak control start command XXh transmitted from the memory controller 1. This peak control start command XXh also does not include a chip address Cadd. That is, upon receiving the command XXh, each memory chip Die0 to DieN initiates peak control regardless of the chip address of each memory chip Die0 to DieN. That is, in this embodiment, each memory chip 2 initiates peak operation control upon receiving the peak control start command. That is, the peak control start command XXh is a broadcast command. When peak operation control is required, the memory controller 1 transmits the peak control start command. Conversely, when peak operation control is not required, the transmission of the peak control start command from the memory controller 1 can be suspended to prevent peak operation control from being implemented. Note that, when the start of peak operation control via the peak control start command is not required, peak operation control may be initiated a predetermined time after the start of power-on read. When the control circuit 27 of each of Die0 to DieN receives the peak control start command, it provides peak management information to the control unit 41 of the logic control circuit 21 to start peak operation control.

[0083] The control unit 41 of the memory chip Die0 designated as the leader operates the clock oscillator 42, frequency divider 43, output circuit 44, multiplexer 46, and peak operation permission circuit 47. The clock oscillator 42 generates a clock, and the frequency divider 43 divides the oscillation clock of the clock oscillator 42 by the division number designated by the frequency division period, and outputs the clock CK. As shown in FIG. 10, the output circuit 44 outputs the clock CK via the terminal / WP. The terminals / WP of the memory chips Die0 to DieN are connected to each other, and the clock CK from the leader memory chip Die0 is supplied to the terminals / WP of each of the follower memory chips Die1 to DieN. The multiplexer 46 of the leader memory chip Die0 outputs the clock CK from the frequency divider 43 to the peak operation permission circuit 47.

[0084] The control unit 41 of each of the memory chips Die1 to DieN set as followers operates the frequency divider 43, the multiplexer 46, and the peak operation permission circuit 47. In each of the memory chips Die1 to DieN, the input circuit 45 receives the clock CK input via the terminal / WP and provides it to the multiplexer 46. The multiplexer 46 of each of the memory chips Die1 to DieN outputs the clock CK received by the input circuit 45 to the peak operation permission circuit 47.

[0085] In this way, a common clock CK is input to each peak operation permission circuit 47 of the memory chips Die0 to DieN. The peak operation permission circuit 47 counts the clock CK while resetting the count value by the total number of slots. As a result, slots 0 to N are set in synchronization with the clock CK, as shown in FIG. 10. When the slot number matches the slot allocation number, the peak operation permission circuit 47 generates a peak enable signal.

[0086] 10 indicates the period during which the peak enable signal is active, and the peak operation permission circuit 47 of each of Die0 to DieN generates a peak enable signal at the timing corresponding to the slot indicated by slot number 0, 1, 2, ..., N and provides it to the peak control circuit 27a. In this way, the peak control circuit 27a of each of Die0 to DieN performs peak operation control to generate a peak current in the slot period corresponding to the slot allocation number assigned to it.

[0087] 11 and 12 show examples of voltage changes in the wirings that make up the memory cell array 23. Fig. 11 shows the occurrence of peak currents resulting from voltage changes in a program operation, and Fig. 12 shows the occurrence of peak currents resulting from voltage changes in a read operation.

[0088] The memory cell array 23 includes wiring such as word lines WL, bit lines BL, and select gate lines SGD and SGS. Figure 11 shows the voltage changes of these wirings during a program operation. Specifically, for the block BLK to be written (selected block BLK), a channel precharge period is provided from time t11 to t12 before the application of the program voltage Vpgm. During this period, the select gate line SGD is set to, for example, 5V. After the channel precharge period ends, a relatively high voltage Vpass is applied to unselected word lines (unselected WL), and a high voltage Vpgm is applied to the word line to be written (selected WL). During this program operation, current peaks occur at the start of the channel precharge period, the start of application of voltage Vpass, and the start of application of voltage Vpgm.

[0089] As shown in FIG. 12, during a read operation (verify operation), a disturbance prevention period (USTRDIS period) is set from time t21 to t22, and during this period, a read voltage Vr is applied to the selected word line WL (hereinafter also referred to as WL_sel) of the selected block. After the disturbance prevention period ends, a read period (from time t22 onwards) is set, and during the read period, a voltage VSG (e.g., 5 V) is applied to the select gate lines SGD_sel, SGD_usel, and SGS of the selected block. Furthermore, a sufficiently high voltage VREAD (e.g., 8 V) is applied to the selected word line WL_sel of the selected block and the unselected word lines WL_usel of the selected block. During such a read operation, a current peak occurs at the start of the disturbance prevention period, corresponding to the start of application of the voltage Vpass, and also at a certain timing during the read period.

[0090] In this embodiment, the peak operation that generates such a current peak is performed in the slots with slot assignment numbers assigned to the memory chips Die0 to DieN, respectively. Fig. 13 shows the period during which the peak operation is performed in the programming period performed in a specific memory chip 2. In the example of Fig. 13, in the specific memory chip 2, the peak operation is performed in the slot with slot number 0.

[0091] The example in FIG. 13 shows an example of a memory chip 2 assigned with slot allocation number 0. The peak control circuit 27a of this memory chip 2 starts channel precharge during the period of slot number 0. As a result, a current peak occurs during the period of slot number 0. This memory chip 2 does not perform peak operation until the next slot number becomes 0. Therefore, even if the channel precharge period ends during the period of slot number 2, for example, the program operation is suspended until the next slot with slot number 0 arrives. When the slot with slot number 0 arrives, the program operation, which becomes the peak operation, is resumed.

[0092] Each memory chip 2 performs peak operation in a different slot from the others, and the timing of the current peak is shifted, so that the peak current of the entire memory system can be suppressed.

[0093] As described above, in this embodiment, in a semiconductor memory device having a multi-chip configuration, a specific chip is designated as a leader and the other chips are designated as followers, and the clock generated by the leader is used by all chips to perform peak operation control for each chip, thereby making it possible to suppress peak current. Also, peak management information for peak operation control is stored in the memory cell array in advance, so there is no need to supply peak management information from the memory controller 1 to the memory chip 2. Also, peak operation control can be started by a peak control start command, and peak operation control can be performed when necessary.

[0094] In the above description, the terminals / WP of each memory chip 2 are commonly connected to transmit the clock CK for peak operation control, but the clock CK may be transmitted using another terminal of the memory chip 2. For example, the clock CK may be transmitted using a terminal that transmits the ready / busy signal R / B.

[0095] (Second embodiment) Fig. 14 is an explanatory diagram showing another embodiment of the present invention. The hardware configuration of this embodiment is the same as that of the first embodiment. Fig. 15 and Fig. 16 are timing charts showing SetFeature sequences. Fig. 15 shows the overall SetFeature sequence, and Fig. 16 shows an individual SetFeature sequence.

[0096] In the first embodiment, an example was described in which peak management information is stored in advance in the memory cell array 23. In contrast to this, in this embodiment, peak management information is set in each memory chip 2 by a command from the memory controller 1. In Fig. 14, the horizontal axis represents time, and the period of peak operation by the command from the memory controller 1 and the peak operation control of each of the N+1 memory chips 2 (memory chips Die0 to DieN in Fig. 14) is shown.

[0097] After power-on, the processor 12 of the memory controller 1 transmits a power-on read command FFh to all memory chips Die0 to DieN. When each memory chip Die0 to DieN receives the command FFh, it reads system information from the ROM area of ​​its respective memory cell array 23 and stores the information in the ROM register 27b of the control circuit 27. At this stage, no peak management information is stored in the ROM register 27b of the memory chips Die0 to DieN. Next, the processor 12 of the memory controller 1 generates a SetFeature command EFh for all memory chips Die0 to DieN, and transmits peak management information common to all memory chips Die0 to DieN. The SetFeature command EFh is a broadcast command because it does not include a chip address Cadd.

[0098] 15 shows the SetFeature sequence in this case. At the start of the SetFeature sequence, the processor 12 of the memory controller 1 activates the signal CLE to generate a SetFeature command EFh, and activates the signal / WE to cause the memory chips Die0 to DieN to retrieve the SetFeature command EFh. Next, the processor 12 activates the signal ALE to generate a feature address Fadd, thereby causing the memory chips Die0 to DieN to retrieve the feature address Fadd.

[0099] Next, the processor 12 activates the signal DQS multiple times to transmit the SetFeature data D0-D3 (feature data Fdata). As a result, the SetFeature data D0-D3 are captured in the memory chips Die0-DieN. The SetFeature data D0-D3 transmits the clock cycle and the total number of slots in the peak management information to the memory chips Die0-DieN and stores them in the ROM register 27b.

[0100] Next, the processor 12 of the memory controller 1 transmits peak management information individually to each of the memory chips Die0 to DieN. In this case, the processor 12 transmits peak management information sequentially to each of the memory chips Die0 to DieN according to the sequence of FIG. 16. The transmitted peak management information in this case includes leader-follower information and slot allocation number information. The processor 12 generates an individual SetFeature command D5h and activates the signal / WE. Furthermore, the processor 12 activates the signal ALE to continuously generate a chip address Cadd and a feature address Fadd. Then, the processor 12 activates the signal DQS multiple times to transmit the leader-follower information and slot allocation number information as SetFeature data D0 to D3 (feature data Fdata). The SetFeature command D5h is an individual command because it includes the chip address Cadd.

[0101] In the example of FIG. 14, information indicating that the memory chip Die0 is the leader and information indicating that the slot allocation number is 0 are transmitted to the memory chip Die0. The control circuit 27 of the memory chip Die0 stores the received peak management information in the ROM register 27b. Next, the memory chips Die1, Die2, ..., DieN sequentially receive the leader-follower information and the slot allocation number information. Note that the memory chips Die1, Die2, ..., DieN are given information indicating that they are followers and information indicating that the slot allocation numbers are 1, 2, ..., N, respectively. The control circuits 27 of the memory chips Die1, Die2, ..., DieN store the received follower information and slot allocation numbers in the ROM register 27b. In this way, all peak management information is stored in the ROM registers 27b of the memory chips Die0 to DieN.

[0102] In Fig. 14, the SetFeature sequence is shown as D5h-Cadd-Fadd-Fdata, but the SetFeature sequence for the memory chips Die1 to DieN is omitted. Note that followers and slot allocation numbers may be set in all memory chips Die0 to DieN by initial setting. In this case, it is sufficient to provide leader information to one memory chip among the memory chips Die0 to DieN, and individual SetFeature sequences can be omitted to one time.

[0103] The processor 12 of the memory controller 1 transmits a peak control start command XXh. Upon receiving the peak control start command XXh transmitted from the memory controller 1, the control circuit 27 of each of the memory chips Die0 to DieN provides peak management information to the control unit 41 of the logic control circuit 21 to start peak operation control.

[0104] If the memory system has 16 memory chips, the commands that the memory controller 1 needs to output are as follows: Power-on read (broadcast command) FFh x 1 Set Feature (Broadcast Command) -- Division Period x 1 Set Feature (Broadcast Command) -- Total number of slots x 1 Set Feature (individual command) -- slot allocation number x 16 Set Feature (individual command) -- Leader information × 1 Set Feature (individual command) -- Follower information x 15 Peak control start (broadcast command) --×1 Other operations are the same as those in FIG.

[0105] In the embodiment configured in this manner, it is possible to obtain the same effects as in the first embodiment. Furthermore, since peak management information can be set by a command from the memory controller, it is possible to improve the flexibility of peak operation control.

[0106] The present invention is not limited to the above-described embodiments, and various modifications can be made in the implementation stage without departing from the spirit of the invention. Furthermore, the above-described embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed multiple constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiments, if the problem described in the "Problem to be Solved by the Invention" section can be solved and the effect described in the "Effect of the Invention" section can be obtained, the configuration from which these constituent elements are deleted can be extracted as an invention. [Explanation of symbols]

[0107] 1...memory controller, 2...memory chip, 11...RAM, 12...processor, 13...host interface, 14...ECC circuit, 15...memory interface, 16...internal bus, 21...logic control circuit, 21a...input receiver, 21b...output driver, 22...input / output circuit, 22a...input driver, 22b...output driver, 23...memory cell array, 24...sense amplifier, 25...row decoder, 26a...address register, 26b...ROM register, 26b...command register, 27...control circuit, 27a...peak control circuit, 27b...ROM register, 28...voltage generation circuit, 30...R / B signal generation circuit, 32...input / output pad group, 33...logic control pad group, 41...control unit, 42...clock oscillator, 43...divider, 44...output circuit, 45...input circuit, 46...multiplexer, 47...peak operation enable circuit

Claims

1. A first pad; a clock generation circuit including an oscillator and a frequency divider that divides the frequency of an output of the oscillator, and that generates a first clock; an output circuit that outputs the first clock from the first pad; a designation circuit that designates one of a plurality of time slots generated based on the first clock as a specific time slot; a peak control circuit that, when instructed to perform an operation, executes a partial operation that generates a current peak at a timing corresponding to the specific time slot; a plurality of semiconductor memory devices each comprising: a memory controller that controls the plurality of semiconductor memory devices; Including, the memory controller transmits at least one of information for designating a leader semiconductor memory device among the plurality of semiconductor memory devices, information on the frequency division period of the frequency divider, information on the total number of the plurality of time slots, and information on the specific time slot to the semiconductor memory device; In the semiconductor memory device, the information on the frequency division period and the information on the total number of the plurality of time slots is received as a broadcast command; The information for designating a leader or follower and the information for the specific time slot are received as separate commands. Memory system.

2. A first pad; a clock generation circuit including an oscillator and a frequency divider that divides the frequency of an output of the oscillator, and that generates a first clock; an output circuit that outputs the first clock from the first pad; a designation circuit that designates one of a plurality of time slots generated based on the first clock as a specific time slot; a peak control circuit that, when instructed to perform an operation, executes a partial operation that generates a current peak at a timing corresponding to the specific time slot; a plurality of semiconductor memory devices each comprising: a memory controller that controls the plurality of semiconductor memory devices; Including, the memory controller transmits at least one of information for designating a leader semiconductor memory device among the plurality of semiconductor memory devices, information on the frequency division period of the frequency divider, information on the total number of the plurality of time slots, and information on the specific time slot to the semiconductor memory device; the memory controller transmits information about the division period of the divider and information about the total number of the plurality of time slots by a broadcast command; transmitting information for designating the leader or follower and information about the specific time slot to each of the plurality of semiconductor storage devices individually; Memory system.

3. the peak control circuit delays execution of the partial operation that generates the current peak until a timing corresponding to the specific time slot.

3. The memory system according to claim 1.

4. the clock generation circuit, the output circuit, the designation circuit, and the peak control circuit start operating upon receiving a first command; 3. The memory system according to claim 1.

5. the frequency divider generates the first clock based on information about a frequency division period; the designation circuit designates the specific time slot based on information on the total number of the plurality of time slots and information on the specific time slot.

3. The memory system according to claim 1.

6. the output circuit operates when designated as a leader, and does not operate when designated as a follower regardless of receipt of the first command; 5. The memory system of claim 4.

7. a memory for recording at least one of information for designating a leader or follower, information on the frequency division period, information on the total number of the plurality of time slots, and information on the specific time slot; 6. The memory system of claim 5, further comprising:

8. receiving at least one of information for designating a leader or a follower according to a specific transmission format, information on the frequency division period, information on the total number of the plurality of time slots, and information on the specific time slot; 6. The memory system of claim 5.

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