Information processing device, control method, and control program

Abstract

To suppress performance decrease when a counter value of route information is updated.SOLUTION: An information processing apparatus comprises: a storage part 110 which stores route information of flow control in a memory and also stores flows having the same ROW address in the memory as access destinations in a group when a counter value managed with the route information is updated; and an update processing part 112 which accesses the memory successively for the plurality of flows having the same ROW address as access destinations while changing the order of the plurality of flows so as to update the counter value.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to an information processing device, a control method, and a control program. [Background technology]

[0002] Virtual routers are known that use software to perform the functions of a network router. Just as routers connect servers and resolve packet destinations, virtual routers connect virtual machines (VMs) and resolve destinations. Virtual routers generally search multiple tables to resolve destinations.

[0003] The virtual router is implemented by a Software Defined Network (SDN) and comprises a control plane and a data plane. The control plane manages flows, and for example, sets a combination of an Internet Protocol (IP) address, a port number, and a destination as a flow.

[0004] The data plane is responsible for forwarding packets; it analyzes the contents of the input packet and performs the same hash calculation as the control plane to access the relevant entry and identify the destination.

[0005] In the data plane, a flow table is referenced based on the IP address and port number of the destination of the input packet, and the destination of the packet is determined.

[0006] Conventional software-implemented virtual routers require a large amount of CPU (Central Processing Unit) power for packet routing itself, wasting computing resources that should be provided to applications, making it difficult to meet the performance requirements of Network Functions Virtualization (NFV).

[0007] Therefore, the data plane functions that require heavy processing in virtual relay devices are offloaded to hardware such as FPGAs (Field Programmable Gate Arrays) and smart NICs (Network Interface Cards). Offloading part of the functions realized by software to hardware can also be called hardware offloading.

[0008] The flow table is updated every time the virtual router forwards a packet.

[0009] FIG. 28 is a diagram illustrating a flow table provided in the virtual relay device.

[0010] The flow table manages the address, 5tuple, action, and counter for each packet. This information set of address, 5tuple, action, and counter is used as route information that indicates the route along which the packet will be forwarded.

[0011] The 5tuple consists of the source IP address, the packet's destination IP address, the source port, the destination port, and the protocol. The action indicates the process to be performed on the packet, such as forwarding, blocking, or address change.

[0012] The address is the address of the entry in the flow table, and is a value obtained by hashing the 5 tuples using CRC32 or the like. CRC is an abbreviation for Cyclic Redundancy Check. The address of an entry in a flow table may be referred to as a flow table address.

[0013] Counter is a value that indicates how many times a packet has arrived. This counter value is used for flow aging, which deletes unused entries, and when users debug the network. Hereinafter, counter may be referred to as counter, and the value of this counter may be referred to as counter value.

[0014] Fig. 29 is a diagram showing a typical function for updating a counter in a flow table in a conventional virtual relay device, and Fig. 30 is a diagram showing the timing of each process shown in Fig. 29.

[0015] A packet input to the virtual relay device is input to a classifier (not shown), which extracts 5 tuples from the input packet.

[0016] The 5 tuples are hashed and input to the memory controller (see symbol P1 in Figure 29). The memory controller issues a read request (read) to the flow table using the hashed value (address) of this 5 tuple (see symbol P2 in Figures 29 and 30). In response to this read request, the flow table returns the data of the corresponding entry (response: see symbol P3 in Figures 29 and 30). The counter value indicates the number of times a packet with the same route information has arrived.

[0017] The virtual relay device has two caches (caches A and B) for updating the counters of the flow table. One of these two caches (for example, cache A) is used as a count side that stores values ​​for updating the counters of the flow table. The other (for example, cache B) is used as an update side that updates the counters of the flow table using the values ​​for updating the counters. The roles of the count side and update side are periodically alternated between caches A and B.

[0018] The count-up circuit generates a counter update value for the flow table by adding a count value corresponding to the packet to be processed to a count value read from the flow table. The count-up circuit stores the generated counter update value in the count-side cache (cache A in the example shown in FIG. 29) (see symbol P4 in FIG. 29). Then, the counter update value in the update-side cache (cache B in the example shown in FIG. 29) is written to the flow table at a predetermined timing (see symbol P5 in FIGS. 29 and 30).

[0019] Furthermore, in the flow table, in order to ensure consistency of counter values, the entry for a subsequent packet cannot be read until the counter update (write) for the preceding packet is completed.

[0020] FIG. 31 is a diagram for explaining the update process of the counters in the flow table in a conventional virtual router.

[0021] FIG. 31 shows an example in which three flows are processed in the order flow2, flow1, and flow1.

[0022] Based on the processing of these flows, the count value cnt1 of flow1 and the count value cnt2 of flow1 are stored in cache A on the count side. Meanwhile, the count value cnt3 of flow3 and the count value cnt2 of flow2 stored in cache B on the update side are written to the flow table, and the counts in the flow table are updated. [Prior art documents] [Patent documents]

[0023] [Patent Document 1] International Publication No. 2012 / 128282 [Patent Document 2] Japanese Patent Application Publication No. 2018-137616 [Patent Document 3] US Patent Application Publication No. 2003 / 0058873 Summary of the Invention [Problem to be solved by the invention]

[0024] However, in such a conventional virtual router, it may take longer to update the count value of the flow table than to register the count value in the cache on the count side for updating the flow table. As a result, it may take longer to update the flow table than the cache on the count side overflows, and it may not be able to keep up.

[0025] For example, if the number of entries in caches A and B is 1000, there is a risk that the count-side cache will overflow in 1000 cycles, but in the flow table, it may not be possible to update 1000 entries in 1000 cycles.

[0026] This problem occurs due to a structural problem in the DRAM (Dynamic Random Access Memory) used for the flow table.

[0027] FIG. 32 is a diagram illustrating the relationship between a flow table address and a row address and a column address in a DRAM.

[0028] The flow table address "xxxxyy" shown in Fig. 32 is a hash value of 5 tuples. Of the six digits "xxxxyy" that make up this flow table address, the first four digits "xxxx" are the ROW address, and the last two digits "yy" are the COL address.

[0029] FIG. 33 is a diagram showing a schematic structure of a DRAM.

[0030] A DRAM is formed by stacking multiple cell arrays, each of which has a plurality of memory cells arranged in the vertical and horizontal directions, in layers.

[0031] In Figure 33, symbol A indicates the configuration of a DRAM configured by stacking cell arrays in layers, and symbol B indicates a cell array in which multiple memory cells are arranged vertically and horizontally. In the diagram indicated by symbol B, symbol D indicates the memory cell corresponding to the flow table address "xxxxyy." Also, in Figure 33, symbol C indicates the configuration of one memory cell.

[0032] A memory cell has a transistor and a capacitor, with the capacitor being arranged in series with the transistor.

[0033] The COL is connected to the gate of the transistor and has a small capacitance, which allows it to be switched on and off quickly, allowing for fast changes to the COL during memory access.

[0034] On the other hand, the ROW is connected to the source power supply of the transistor and has a large capacitance. This means that it takes time to switch on / off, and changing the ROW address during memory access is slower. This slower memory access can be considered a penalty.

[0035] That is, in a DRAM, if a change in the access address causes a change in the row address, a delay (penalty) occurs in the access.

[0036] In one aspect, the present invention aims to suppress a performance degradation when a counter value of route information is updated. [Means for solving the problem]

[0037] For this reason, this information processing device is an information processing device that has a processor, a memory, and an FPGA (Field Programmable Gate Array) and has a packet relay function, and is equipped with a memory unit that stores route information for flow control in the memory, and when updating the counter value managed in the route information, stores flows that access the same ROW address in the memory as a group, and an update processing unit that rearranges the order of multiple flows and accesses the memory consecutively for multiple flows that access the same ROW address to update the counter value. [Effects of the Invention]

[0038] According to one embodiment, it is possible to suppress a decrease in performance when updating the counter value of the route information. [Brief explanation of the drawings]

[0039] [Figure 1] FIG. 1 is a diagram illustrating a hardware configuration of an information processing device that realizes a function of a virtual router as an example of an embodiment. [Figure 2] FIG. 2 illustrates a functional configuration of a virtual router according to an embodiment. [Figure 3] FIG. 1 illustrates a configuration example of a burst control circuit in a virtual router according to an embodiment; [Figure 4] FIG. 10 is a diagram illustrating a function of a new registration check circuit in a virtual router according to an example of an embodiment. [Figure 5] 10 is a flowchart illustrating a function of an update circuit in a virtual router according to an example of an embodiment. [Figure 6] 10 is a flowchart illustrating a function of an update circuit in a virtual router according to an example of an embodiment. [Figure 7] 10 is a flowchart illustrating a function of an update circuit in a virtual router according to an example of an embodiment. [Figure 8]10A and 10B are diagrams illustrating processing by a new registration check circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 9] 10A and 10B are diagrams illustrating processing by a new registration check circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 10] 10A and 10B are diagrams illustrating processing by a new registration check circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 11] 10A and 10B are diagrams illustrating processing by a new registration check circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 12] 10A and 10B are diagrams illustrating processing by a new registration check circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 13] 10A and 10B are diagrams illustrating processing by a new registration check circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 14] 10A and 10B are diagrams illustrating processing by a new registration check circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 15] 10A and 10B are diagrams illustrating processing by an update circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 16] 10A and 10B are diagrams illustrating processing by an update circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 17] 10A and 10B are diagrams illustrating processing by an update circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 18] 10A and 10B are diagrams illustrating processing by an update circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 19] 10A and 10B are diagrams illustrating processing by an update circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 20] 10A and 10B are diagrams illustrating processing by an update circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 21] 10A and 10B are diagrams illustrating processing by an update circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 22] 10A and 10B are diagrams illustrating processing by an update circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 23] 10A and 10B are diagrams illustrating processing by an update circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 24] 10A and 10B are diagrams illustrating processing by an update circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 25] 10A and 10B are diagrams illustrating processing by an update circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 26] 10A and 10B are diagrams illustrating processing by an update circuit of a burst control circuit in a virtual router as an example of an embodiment. [Figure 27] 10A and 10B are diagrams illustrating memory access in an onboard memory when a counter value of a flow table is updated in a virtual router as an example of an embodiment, in comparison with memory access in a conventional method. [Figure 28] FIG. 10 is a diagram illustrating a flow table provided in a virtual router. [Figure 29] FIG. 10 is a diagram illustrating a function for updating a counter in a flow table in a conventional virtual router. [Figure 30] FIG. 30 is a diagram showing the timing of each process shown in FIG. 29. [Figure 31] FIG. 10 is a diagram illustrating a process of updating a counter in a flow table in a conventional virtual router. [Figure 32] FIG. 10 is a diagram illustrating the relationship between a flow table address and a row address and a column address in a DRAM. [Figure 33] FIG. 1 is a diagram schematically illustrating the structure of a DRAM. DETAILED DESCRIPTION OF THE INVENTION

[0040] Hereinafter, embodiments of the present information processing device, control method, and control program will be described with reference to the drawings. However, the embodiments shown below are merely examples, and are not intended to exclude the application of various modifications and techniques not explicitly stated in the embodiments. In other words, the present embodiment can be implemented with various modifications within the scope of its purpose. Furthermore, each figure does not intend to include only the components shown in the figure, but can also include other functions, etc.

[0041] (A) Configuration FIG. 1 is a diagram illustrating a hardware configuration of an information processing device 20 that realizes the functions of a virtual router 1 as an example of an embodiment.

[0042] The information processing device 20 may be, for example, a computer having a server function. The information processing device 20 realizes the function of the virtual router 1.

[0043] The virtual router 1 realizes a packet relay function for transmitting and receiving (transferring) packets between virtual machines (not shown) and between a virtual machine and another device (not shown). A virtual machine may be represented as VM.

[0044] A virtual machine is a virtual computer created on an application program such as a hypervisor, and executes various processes in the same way as a computer implemented by physical hardware.

[0045] A virtual machine has a virtual port (not shown) through which it sends and receives packets. A virtual port is identified by a port number.

[0046] As shown in FIG. 1, the information processing device 20 includes a CPU 2, a system memory 3, and a PCI (Peripheral Component Interconnect) card 4.

[0047] The CPU 2 is a processing device that performs various controls and calculations, and realizes various functions by executing the OS and programs stored in the system memory 3. In other words, the CPU 2 realizes the function of a virtual router.

[0048] The system memory 3 is a storage memory including a ROM (Read Only Memory) and a RAM (Random Access Memory). The ROM of the system memory 3 stores software programs related to virtual router control and data for these programs. The software programs in the system memory 3 are read and executed by the CPU 2 as appropriate. The RAM of the system memory 3 is used as a primary storage memory or working memory.

[0049] The information processing device 20 may also include a storage device (not shown). The storage device is a storage device such as a hard disk drive (HDD), a solid state drive (SSD), or a storage class memory (SCM), and stores various data.

[0050] The PCI card 4 is an expansion card that expands the functions of the information processing device 20, and is attached to, for example, a main board (motherboard) (not shown) of the information processing device 20. The PCI card 4 communicates with the main board of the information processing device 20 via a PCI bus.

[0051] 1, the PCI card 4 includes an on-board memory 5 and an FPGA 10. The on-board memory 5 stores a program (configuration data) that forms the basis of the logic circuit in the FPGA 10. The on-board memory 5 is, for example, a DRAM.

[0052] The FPGA 10 is a device that can electrically change the circuit design of a digital circuit. The FPGA 10 is an LSI (Large Scale Integration circuit) that has a large number of logic gates. The FPGA 10 functions as a predetermined logic circuit by writing configuration data that describes the logical relationships and connection relationships between the logic gates to a configuration RAM (not shown) provided in the FPGA 10.

[0053] The FPGA 10 includes a BRAM (Block Random Access Memory) 11 and a plurality of registers 12. When the FPGA 10 is powered on, a program file (bitstream data) is loaded from the on-board memory 5 into the BRAM 11 in the FPGA 10.

[0054] Each bit of the bitstream data loaded into the BRAM 11 becomes the source of information for a user circuit to be realized on the FPGA 10, and a predetermined circuit is realized by customizing the resources equipped in the FPGA 10. In this information processing device 20, the FPGA 10 realizes at least a part of the functions of the data plane in the virtual router 1.

[0055] The register 12 temporarily stores various data and the like generated when the FPGA 10 functions as a data plane.

[0056] FIG. 2 is a diagram illustrating a functional configuration of the virtual router 1 as an example of an embodiment.

[0057] The virtual router 1a illustrated in FIG. 2 includes a flow table 101, a memory controller 102, a count-up unit 103, a packet processing unit 104, caches 105a and 105b, and burst control circuits 106a and 106b.

[0058] The flow table 101 manages, for example, an address, a 5tuple, an action, and a counter (counter value) for packets processed by the virtual router 1. The address, 5tuple, action, and counter managed in the flow table 101 are used as route information for specifying a packet forwarding route in flow control. In the virtual router 1, the information that makes up the flow table 101 is stored in the onboard memory 5.

[0059] The address of the flow table 101 is a flow table address, and is a value obtained by hashing the 5 tuples of the flow using CRC32 or the like. This address is configured as a combination of a row address and a column address in the DRAM that configures the on-board memory 5 (see FIG. 32).

[0060] The caches 105a and 105b each store a value (counter update value) for updating the counter of the flow table 101. Hereinafter, the cache 105a may be referred to as cache A. The cache 105b may be referred to as cache B. Hereinafter, when there is no need to distinguish between the caches 105a and 105b, they will be referred to as cache 105.

[0061] Of these two caches 105a and 105b, one cache 105 (for example, cache 105a) is used to store values ​​for updating counters in the flow table 101. The cache 105 used to store values ​​for updating counters in the flow table 101 may be called the count side.

[0062] The other cache 105 (for example, cache 105b) is used to update the counter values ​​of the flow table 101 using the counter update value. The cache 105 used to update the counter values ​​of the flow table 101 may be called the update side.

[0063] The role of the count side and the role of the update side are alternated between the caches 105a and 105b at a predetermined timing (for example, periodically).

[0064] The memory controller 102 requests the flow table to read data from an entry whose address is a hashed value of the 5 tuples of the input packet.

[0065] The memory controller 102 receives the data of the corresponding entry returned from the flow table in response to this read request.

[0066] The memory controller 102 extracts the count value from the received entry information and passes it to the count-up unit 103 .

[0067] Furthermore, the memory controller 102 passes the input packet (packet body) to the packet processing unit 104 .

[0068] The packet processor 104 processes the input packet according to the action of the entry whose address matches in the flow table. For example, if the action in the flow table is set to "forward," the packet processor 104 sends the input packet to a destination specified by the 5-tuple of the destination IP address and destination port.

[0069] The count-up unit 103 generates a counter update value by adding a count value corresponding to the packet to be processed to a count value read from the flow table. The count-up unit 103 stores the generated counter update value in the count-side cache 105 (cache 105a in the example shown in FIG. 2). Then, the counter update value in the update-side cache 105 (cache 105b in the example shown in FIG. 2) is written to the flow table 101 at a predetermined timing.

[0070] The burst control circuits 106a and 106b each manage flows having the same row address in the flow table address. The burst control circuit 106a is provided corresponding to the cache 105a, and the burst control circuit 106b is provided corresponding to the cache 105b.

[0071] Hereinafter, when there is no need to distinguish between the burst control circuits 106a and 106b, they will be referred to as the burst control circuit 106. The burst control circuit 106 may be provided in the FPGA 10.

[0072] FIG. 3 is a diagram illustrating the configuration of the burst control circuit 106 in the virtual router 1 as an example of an embodiment.

[0073] As shown in FIG. 3, the burst control circuit 106 includes a new registration check circuit 111, a row address management table 110, and an update circuit 112.

[0074] The ROW address management table 110 illustrated in FIG. 3 associates hash values ​​with flows.

[0075] The hash value (hash) is the ROW address extracted from the value (flow table address) obtained by hashing the 5 tuples of the flow. Also, the flow (flow) is information that identifies the flow.

[0076] The ROW address management table 110 corresponds to a storage unit that stores, as a group, flows that access the same ROW address in the on-board memory 5 .

[0077] In the ROW address management table 110 illustrated in FIG. 3, for example, the ROW address of flow2 is "dddd."

[0078] Furthermore, the ROW addresses of flow1 and flow3 are both "aaaa." In this way, flows with the same ROW address are managed as the same group in the ROW address management table 110. It can be said that the ROW address management table 110 manages flows with the same ROW address.

[0079] In this way, by referring to the ROW address management table 110, flows with the same ROW address can be easily identified.

[0080] The new registration check circuit 111 performs processing to register a flow in the ROW address management table 110. For example, when a new flow that has not been registered in the ROW address management table 110 is input, the new registration check circuit 111 registers the flow in the ROW address management table 110.

[0081] Furthermore, at this time, if another flow has already been registered in the ROW address management table 110 at the same ROW address as the ROW address of the flow to be newly registered, the new registration check circuit 111 adds the new flow in association with this same ROW address. That is, the new registration check circuit 111 registers flows with the same ROW address in the ROW address management table 110 as the same group.

[0082] FIG. 4 is a diagram for explaining the function of the new registration check circuit 111 in the virtual router 1 as an example of an embodiment.

[0083] In FIG. 4, the processing (function) of the new registration check circuit 111 is shown in the form of a flowchart (steps A1 to A5).

[0084] The new registration check circuit 111 receives a flow (flow input) and also receives a hashed value (hash) of the 5 tuples of the flow (see step A1).

[0085] The new registration check circuit 111 checks whether the input flow is a new flow that has not been registered in the ROW address management table 110 (a registration check is performed; step A2). That is, the new registration check circuit 111 checks whether the flow should be registered in the ROW address management table 110.

[0086] If the result of the registration check shows that the flow is a new flow (see the YES route in step A3), information identifying the flow and its ROW address are registered in the ROW address management table 110 (step A4). On the other hand, if the flow is not a new flow (see the NO route in step A3), the flow is discarded (or may be discarded) (step A5). The new registration check circuit 111 in the burst control circuit 106 may be called a count up side.

[0087] The update circuit 112 refers to the row address management table 110 and performs processing to update the count value of the flow table 101 .

[0088] The update circuit 112 receives a hashed value (hash) of the 5 tuples of the flow and the count value (cnt) of the flow read from the flow table 101. Furthermore, when updating the counter of the flow table 101, the update circuit 112 realizes a function of controlling the processing order of a plurality of input flows to be processed so that flows with the same ROW address in the flow table address are consecutive.

[0089] Therefore, the update circuit 112 manages the number of consecutive flows using the count value Outstand. The count value Outstand may be stored in a predetermined storage area such as the register 12. Alternatively, the count value Outstand may be stored in a predetermined storage area such as a memory (not shown) mounted in the update circuit 112.

[0090] The update circuit 112 also manages the ROW addresses of the input flows by storing them in a predetermined storage area such as the register 12. This allows the update circuit 112 to grasp the ROW addresses of the previously processed flows and the ROW addresses of the newly input flows. The ROW addresses of the input flows may also be stored in a predetermined storage area such as a memory (not shown) mounted in the update circuit 112.

[0091] The ROW address of the flow processed last time may be called the previous ROW address.

[0092] Furthermore, the update circuit 112 has a function of updating the counter value of the flow table 101. Therefore, the update circuit 112 may read the count value of a specific flow from the cache 105 and store the read count value in a predetermined storage area such as the register 12. Alternatively, the count value may be stored in a predetermined storage area such as a memory (not shown) mounted in the update circuit 112.

[0093] The update circuit 112 also stores the count value of the flow returned from the flow table 101 and the flow table address of the flow in a predetermined storage area such as the register 12. The count value of the flow returned from the flow table 101 and the flow table address of the flow may also be stored in a predetermined storage area such as a memory (not shown) mounted in the update circuit 112.

[0094] 5 to 7 are diagrams for explaining the function of the update circuit 112 in the virtual router 1 as one example of an embodiment.

[0095] 5 to 7, the processing (functions) of the update circuit 112 are shown in the form of a flowchart (steps B1 to B8, B11 to B12, B21 to B22).

[0096] First, the function of updating the counters in the flow table 101 by the update circuit 112 will be described with reference to the flowchart shown in FIG.

[0097] The update circuit 112 receives input of a hash value (hash) generated by hashing 5 tuples of a flow and a count value (cnt) of the flow read from the flow table 101 (step B1).

[0098] The update circuit 112 compares the ROW address of the newly input flow with the ROW address of the previously processed flow to check whether the ROW address has changed (step B2).

[0099] If there is no change in the ROW address (see NO route in step B2), the process proceeds to step B5.

[0100] In step B5, the update circuit 112 issues a request to read the count value of an entry specified by a hash value to the flow table 101. This read request to the flow table 101 is equivalent to issuing a request to the onboard memory 5 (DRAM) that stores the information that configures the flow table 101 to read the count value of an entry specified by a hash value.

[0101] The update circuit 112 waits for a response of the count value from the flow table 101 (step B6).

[0102] The update circuit 112 sums the count value returned from the flow table 101 and the count value (cnt) of the flow to be processed, to create (calculate) an update count value (step B7).

[0103] The update circuit 112 uses the created update count value to rewrite (update: step B8) the count value of the corresponding entry in the flow table 101. Writing this count value to the flow table 101 is equivalent to writing the count value of the entry specified by the hash value to the onboard memory 5 (DRAM) that stores the information that configures the flow table 101.

[0104] Furthermore, if the result of the check in step B2 is that the ROW address is to be changed (see the YES route in step B2), the process proceeds to step B3.

[0105] In step B3, the update circuit 112 checks whether the count value outstand is 0. If the count value outstand is not 0 (see the NO route in step B3), the update circuit 112 stops processing the input flow (step B4) and then returns to step B3.

[0106] On the other hand, if the count value outstand is 0 (see the YES route from step B3), the process proceeds to step B5.

[0107] Next, the function of updating the count value outstanding in update circuit 112 will be described with reference to the flowcharts shown in FIGS.

[0108] The flowchart shown in FIG. 6 (steps B11 to B12) shows the process of counting up the count value outstanding, which is carried out when a flow is input to the virtual router 1.

[0109] The update circuit 112 receives a hash value (hash) generated by hashing 5 tuples of a flow to be newly processed and the count value (cnt) of the flow read from the flow table 101.

[0110] The update circuit 112 compares the row address of the newly processed flow with the row address of the previously processed flow to check whether they match (last req row = input row?) (step B11).

[0111] If the ROW address of the newly processed flow does not match the ROW address of the previously processed flow (see the NO route in step B11), the process ends.

[0112] On the other hand, if the ROW address of the newly processed flow matches the ROW address of the previously processed flow (see the YES route in step B11), the update circuit 112 adds (increments) "1" to the count value outstanding (step B12), and then terminates the processing.

[0113] The flowchart shown in FIG. 7 (steps B21 to B22) shows the process of counting down the value of the count value outstanding, which is performed when a count value is returned from the flow table 101 in response to a count value read request made to the flow table 101.

[0114] The update circuit 112 compares the row address of the flow table address corresponding to the count value returned from the flow table 101 with the row address of the flow table address returned from the flow table 101 last time, and checks whether they match (last resp row = current resp row?) (step B21). If the ROW address of the flow table address corresponding to the count value returned from the flow table 101 does not match the ROW address of the flow table address returned from the flow table 101 last time (see NO route in step B21), the process ends.

[0115] On the other hand, if the ROW address of the flow table address corresponding to the count value returned from the flow table 101 matches the ROW address of the flow table address returned from the flow table 101 last time (see the YES route in step B21), proceed to step B22.

[0116] The update circuit 112 subtracts (decrements) "1" from the count value outstanding (step B22), and then ends the process.

[0117] (B) Operation The processing of the new registration check circuit 111 of the burst control circuit 106 in the virtual router 1 configured as above as an example of an embodiment will be described with reference to FIGS.

[0118] 8 to 14 are diagrams illustrating the transition of processing by new registration check circuit 111 in burst control circuit 106, with FIG. 8 showing the initial state (T=0) and FIGS. 9 to 14 showing states 1 to 5, respectively.

[0119] 8 to 14 show examples in which flow5, flow4, flow3, flow2, and flow1 are input to the virtual router 1 in this order. Also, the ROW address of flow5 is "aaac", the ROW address of flow4 is "bbbb", the ROW address of flow3 is "aaaa", the ROW address of flow2 is "dddd", and the ROW address of flow1 is "aaaa".

[0120] That is, among these flows 1 to 5, the row addresses of flow 1 and flow 3 are the same.

[0121] In the initial state (T=0), no flow is registered in the ROW address management table 110, as shown in FIG.

[0122] In state 1 (T=1), as shown in Fig. 9, flow5 is input to the new registration check circuit 111. The new registration check circuit 111 checks whether flow5 is a new flow that has not been registered in the ROW address management table 110 (see symbol P01 in Fig. 9).

[0123] In the example shown in FIG. 9, the new registration check circuit 111 receives a response indicating that flow5 has not been registered in the ROW address management table 110 (see reference symbol P02 in FIG. 9).

[0124] In state 2 (T=2), as shown in FIG. 10, the new registration check circuit 111 registers flow5 in the ROW address management table 110 in association with the ROW address "aaac" (see symbol P03 in FIG. 10).

[0125] In states 3 (T=3) to 5 (T=5), the new registration check circuit 111 sequentially checks whether flow4, flow3, and flow2 are not yet registered in the ROW address management table 110, and registers them in the ROW address management table 110, as in states 1 and 2 above.

[0126] In state 3 (T=3), the new registration check circuit 111 registers flow4 in the ROW address management table 110 in association with the ROW address "bbbb" as shown in FIG. 11 (see symbol P04 in FIG. 11).

[0127] In state 4 (T=4), the new registration check circuit 111 registers flow3 in the ROW address management table 110 in association with the ROW address "aaaa" as shown in FIG. 12 (see symbol P05 in FIG. 12).

[0128] In state 5 (T=5), the new registration check circuit 111 registers flow2 in the ROW address management table 110 in association with the ROW address "dddd" as shown in FIG. 13 (see symbol P06 in FIG. 13).

[0129] In state 6 (T=6), the new registration check circuit 111 registers flow1 in the ROW address management table 110 in association with its ROW address "aaaa" as shown in Fig. 14 (see reference symbol P07 in Fig. 17). At this time, since flow3 has been registered earlier in association with the ROW address "aaaa" in the ROW address management table 110, two flows, flow3 and flow1, are associated with the ROW address "aaaa". That is, in the ROW address management table 110, flow3 and flow1, which have the same ROW address "aaaa", are managed as a group.

[0130] Next, the processing of the update circuit 112 of the burst control circuit 106 in the virtual router 1 as an example of an embodiment will be described with reference to FIGS.

[0131] FIG. 15 illustrates memory accesses (flow table memory accesses) that occur when the flow update circuit 112 processes the flow table 101 for multiple types of flows (five types: flow1 to flow5 in the example shown in FIG. 15).

[0132] 15 to 26, the update circuit 112 performs processing in the order of flow table memory access shown in Fig. 15. That is, as shown in Fig. 15, the update circuit 112 processes the multiple flows registered in the ROW address management table 110 in the order of flow4, flow1, flow3, flow4, flow1, flow3, flow5, flow2, flow5, and flow2.

[0133] 16 to 26 are diagrams illustrating the transition of processing by the update circuit 112 in the burst control circuit 106, with Fig. 16 showing the initial state (T=0) and Figs. 17 to 26 showing states 1 to 10, respectively. For convenience, flow table memory access is shown at the top of each of Figs. 16 to 26, and a dashed square indicates which state of flow table memory access T=0 to T=10 each figure is in.

[0134] 8 to 14, the ROW address of flow5 is "aaac", the ROW address of flow4 is "bbbb", the ROW address of flow3 is "aaaa", the ROW address of flow2 is "dddd", and the ROW address of flow1 is "aaaa". In other words, in these flows 1 to 5, the ROW addresses of flow1 and flow3 are the same.

[0135] In the initial state (T=0), as shown in FIG. 16, the count value outstanding and the value of the previous ROW address are both "0" (see symbol P11 in FIG. 16).

[0136] In the initial state illustrated in FIG. 16, the ROW address management table 110 is in the same state as the ROW address management table 110 registered by the new registration check circuit 111 in FIG.

[0137] Furthermore, in the initial state illustrated in Fig. 16, flow1 to flow5 are registered in the flow table 101. For example, in the flow table 101 illustrated in Fig. 16, flow2 is registered at the flow table address "ddd23", and "B" is registered as the count value of flow2.

[0138] Furthermore, flows 1 to 5 are registered together with their respective count values ​​in the cache 105 illustrated in Fig. 16. For example, in the cache 105 illustrated in Fig. 16, a count value "a" is registered in association with flow 1.

[0139] The update circuit 112 receives flow4 and its ROW address from the ROW address management table 110 (see symbol P12 in FIG. 16). This process corresponds to step B1 in the flowchart shown in FIG.

[0140] In state 1 (T=1), the update circuit 112 compares the ROW address "bbbb" of flow4 with the previous ROW address "0000". This process corresponds to step B2 in the flowchart shown in FIG. 5. As a result of the comparison, they do not match, so the update circuit 112 next determines whether the count value outstanding is 0. This process corresponds to step B3 in the flowchart shown in FIG. 5.

[0141] Here, since the count value outstanding is 0, the update circuit 112 issues a read request to the flow table 101 to read the count value of the flow table address "bbbb67" of flow4 (read bbbb67; see symbol P13 in FIG. 17). This process corresponds to step B5 in the flowchart shown in FIG. 5.

[0142] Furthermore, the update circuit 112 reads the count value "d" of flow4 from the cache 105 (see symbol P14 in FIG. 17).

[0143] In state 2 (T=2), the update circuit 112 compares the row address "aaaa" of the next flow 1 with the previous row address "bbbb". This process corresponds to step B2 in the flowchart shown in FIG. 5. As a result of the comparison, they do not match, so the update circuit 112 next determines whether the count value outstanding is 0. This process corresponds to step B3 in the flowchart shown in FIG. 5.

[0144] Here, since the count value outstanding is 0, the update circuit 112 issues a read request to the flow table 101 to read the count value of the flow table address "aaaa01" of flow1 (read aaaa01; see symbol P15 in FIG. 18). This process corresponds to step B5 in the flowchart shown in FIG. 5.

[0145] Furthermore, the update circuit 112 holds the count value "d" of flow4 read from the cache 105 (see symbol P16 in FIG. 18).

[0146] Furthermore, the update circuit 112 reads the count value "a" of flow1 from the cache 105 (see symbol P17 in FIG. 18).

[0147] In state 3 (T=3), the update circuit 112 compares the ROW address "aaaa" of the next flow3 with the previous ROW address "aaaa". This process corresponds to step B2 in the flowchart shown in FIG. 5. As a result of the comparison, they match, so the update circuit 112 issues a read request to the flow table 101 to read the count value of the flow table address "aaaa45" of flow3 (read aaaa45; see symbol P18 in FIG. 19). This process corresponds to step B5 in the flowchart shown in FIG. 5.

[0148] Here, since flow1 and flow3 have the same ROW address, no delay (penalty) occurs in accessing the flow table 101.

[0149] Furthermore, the update circuit 112 holds the count value "a" of flow1 read from the cache 105 (see symbol P19 in FIG. 19).

[0150] Furthermore, the update circuit 112 reads the count value "c" of flow3 from the cache 105 (see symbol P20 in FIG. 19).

[0151] Furthermore, since the ROW address “aaaa” of flow3 matches the previous ROW address “aaaa”, the update circuit 112 adds (increments) 1 to the count value outstanding. This prevents the update process of the count value of the flow table 101 by the update circuit 112.

[0152] In state 4 (T=4), in response to the read request made in state 1 (T=1), the flow table 101 returns the count value "D" of flow4 to the update circuit 112 (see symbol P21 in FIG. 20).

[0153] The update circuit 112 compares the ROW address "aaac" of the next flow 5 with the previous ROW address "aaaa". This process corresponds to step B2 in the flowchart shown in FIG. 5. As a result of the comparison, they do not match, so the update circuit 112 next determines whether the count value "outstand" is 0. This process corresponds to step B3 in the flowchart shown in FIG. 5. As the count value "outstand" is 1, the update circuit 112 waits while suppressing processing for flow 5 (memory access to the onboard memory 5). This process corresponds to step B4 in the flowchart shown in FIG. 5.

[0154] The update circuit 112 also issues a write request (write bbbb67 D + d) to rewrite the value "D + d" obtained by adding the count value "D" of flow4 returned from the flow table 101 and the count value "d" read from the cache 105 to the flow table address "bbbb67" of the flow table 101 (see symbol P23 in FIG. 20). This process corresponds to steps B7 and B8 in the flowchart shown in FIG. 5.

[0155] In state 5 (T=5), in response to the read request made in state 2 (T=2), the flow table 101 returns the count value "A" of flow1 to the update circuit 112 (see symbol P24 in FIG. 21).

[0156] The update circuit 112 issues a write request (write aaaa01 A + a) to rewrite the value obtained by adding the count value "A" of flow1 returned from the flow table 101 and the count value "a" read from the cache 105 to the flow table address "aaaa01" of the flow table 101 (see symbol P25 in FIG. 21). This process corresponds to steps B7 and B8 in the flowchart shown in FIG. 5.

[0157] Also, in the flow table 101, the count value of flow4 is updated to "D+d" (see reference symbol P26 in FIG. 21).

[0158] In this state 5, the update circuit 112 remains in a standby state without processing flow 5.

[0159] In state 6 (T=6), in response to the read request made in state 3 (T=3), the flow table 101 returns the count value "C" of flow3 to the update circuit 112 (see symbol P27 in FIG. 22).

[0160] The update circuit 112 issues a write request (write aaaa45 C + c) to rewrite the value "C + c" obtained by adding the count value "C" of flow3 returned from the flow table 101 and the count value "c" read from the cache 105 to the flow table address "aaaa45" of the flow table 101 (see symbol P28 in FIG. 22). This process corresponds to steps B7 and B8 in the flowchart shown in FIG. 5.

[0161] Here, since flow1 and flow3 have the same ROW address, no delay (penalty) occurs in accessing the flow table 101.

[0162] Furthermore, the count value "A" of flow1 returned from the flow table 101 to the update circuit 112 in state 5 and the count value "C" of flow3 returned from the flow table 101 to the update circuit 112 in state 6 are the same ROW address.

[0163] Therefore, the update circuit 112 subtracts 1 from the count value outstand. As a result, the count value outstand becomes 0 (see reference symbol P30 in FIG. 22), and the update process of the count value of the flow table 101 by the update circuit 112, which had been inhibited, is resumed.

[0164] In state 7 (T=7), the update circuit 112 compares the ROW address "aaac" of flow 5 with the previous ROW address "aaaa." This process corresponds to step B2 in the flowchart shown in FIG. 5. As a result of the comparison, they do not match, so it is next determined whether the count value outstanding is 0. This process corresponds to step B3 in the flowchart shown in FIG. 5.

[0165] Here, since the count value outstanding is 0, the update circuit 112 issues a read request to the flow table 101 to read the count value of the flow table address "aaac89" of flow5 (read aaac89; see symbol P31 in FIG. 23). This process corresponds to step B5 in the flowchart shown in FIG. 5.

[0166] In state 8 (T=8), the update circuit 112 compares the ROW address "dddd" of flow2 with the previous ROW address "aaac". This process corresponds to step B2 in the flowchart shown in FIG. 5. As a result of the comparison, they do not match, so the update circuit 112 next determines whether the count value outstanding is 0. This process corresponds to step B3 in the flowchart shown in FIG. 5.

[0167] Here, since the count value outstanding is 0, the update circuit 112 issues a read request to the flow table 101 to read the count value of the flow table address "dddd23" of flow2 (read dddd23; see symbol P32 in FIG. 24). This process corresponds to step B5 in the flowchart shown in FIG. 5.

[0168] In state 9 (T=9), in response to the read request made in state 7 (T=7), the flow table 101 returns the count value "E" of flow5 to the update circuit 112 (see symbol P33 in FIG. 25).

[0169] The update circuit 112 issues a write request (write aaac89 E + e) ​​to rewrite the value "E + e" obtained by adding the count value "e" read from the cache 105 to the count value "E" of flow5 returned from the flow table 101 to the flow table address "aaac89" of the flow table 101 (see symbol P34 in FIG. 25). This process corresponds to steps B7 and B8 in the flowchart shown in FIG. 5.

[0170] In state 10 (T=10), in response to the read request made in state 8 (T=8), the flow table 101 returns the count value "B" of flow2 to the update circuit 112 (see symbol P35 in FIG. 26).

[0171] The update circuit 112 issues a write request (writedddd23 B + b) to rewrite the value "B + b" obtained by adding the count value "b" read from the cache 105 to the count value "B" of flow2 returned from the flow table 101 to the flow table address "dddd23" of the flow table 101 (see symbol P36 in FIG. 26). This process corresponds to steps B7 and B8 in the flowchart shown in FIG. 5.

[0172] (C) Effects As described above, according to the virtual router 1 as an example of an embodiment, each cache 105 is provided with a burst control circuit 106, and each burst control circuit 106 is provided with a ROW address management table 110 that manages the flow of the same ROW address.

[0173] When the update circuit 112 updates the counter of the flow table 101, it controls the processing order of the input flows to be processed so that flows with the same ROW address in the flow table address are consecutive.

[0174] This reduces the number of times row addresses are switched for the onboard memory 5 (DRAM) when updating the counter value of the flow table 101, thereby reducing the occurrence of memory access delays (penalties). Therefore, it is possible to prevent performance degradation when updating the flow table 101 in this virtual router 1, and improve the performance of the virtual router 1.

[0175] The update circuit 112 also has a count value outstanding that manages the number of consecutive flows (number of queuings) that access the same ROW address. When the update circuit 112 detects consecutive flows that access the same ROW address at the time of a read request for the counter value from the flow table 101, the count value outstanding is incremented.

[0176] Furthermore, when the flow table 101 returns a counter value, if the update circuit 112 detects a response for consecutive flows that access the same ROW address, the update circuit 112 decrements the count value outstanding.

[0177] Then, when the count value outstanding is other than 0, the update circuit 112 suppresses processing for the flow (memory access to the onboard memory 5) and puts the flow into a standby state. This ensures that consecutive flows that access the same ROW address can be queued together, reduces consecutive memory accesses to different ROW addresses, and reduces the occurrence of memory access delays (penalties).

[0178] FIG. 27 is a diagram illustrating memory access in the onboard memory 5 (DRAM) when updating the counter value of the flow table 101 in the virtual router 1 as one example of an embodiment, in comparison with memory access in a conventional method.

[0179] In FIG. 27, symbol A indicates memory access in the DRAM when the counter value of the flow table 101 is updated by the conventional method, and symbol B indicates memory access in the DRAM when the counter value of the flow table 101 is updated by the virtual router 1 of this embodiment.

[0180] In this virtual router 1, when updating the counter value of the flow table 101, the burst control circuit 106 rearranges the flows so that flow1 and flow3, which have the same ROW address, are consecutive. This reduces the number of times the ROW address is switched, and reduces the occurrence of memory access delays (penalties).

[0181] (D) Other The disclosed technology is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present embodiment. The configurations and processes of the present embodiment can be selected or combined as needed.

[0182] For example, in the above-described embodiment, the burst control circuit 106 is provided in the FPGA 10, but this is not limiting. For example, the CPU 2 of the information processing device 20 may realize the function of the burst control circuit 106.

[0183] That is, the CPU 2 of the information processing device 20 may execute a control program to realize functions similar to those of the new registration check circuit 111, the ROW address management table 110, and the update circuit 112 described above.

[0184] Note that a program (control program) for realizing functions similar to those of the new registration check circuit 111, the ROW address management table 110, and the update circuit 112 may be provided in a form recorded on a computer-readable recording medium, such as a flexible disk, a CD (CD-ROM, CD-R, CD-RW, etc.), a DVD (DVD-ROM, DVD-RAM, DVD-R, DVD+R, DVD-RW, DVD+RW, HD DVD, etc.), a Blu-ray disc, a magnetic disk, an optical disk, or a magneto-optical disk. The computer then reads the program from the recording medium, transfers it to an internal or external storage device, and stores it for use. Alternatively, the program may be recorded on a storage device (recording medium), such as a magnetic disk, optical disk, or magneto-optical disk, and provided to the computer from the storage device via a communication path.

[0185] To realize functions similar to those of the new registration check circuit 111, the ROW address management table 110, and the update circuit 112, a program stored in an internal storage device (for example, the system memory 3) is executed by a microprocessor (for example, the CPU 2) of a computer. At this time, the program recorded on a recording medium may be read and executed by the computer.

[0186] Furthermore, the above disclosure will enable those skilled in the art to implement and manufacture the present embodiment.

[0187] (E) Supplementary Note The following additional notes are provided regarding the above-described embodiments.

[0188] (Appendix 1) An information processing device having a processor, a memory, and an FPGA (Field Programmable Gate Array) and a packet relay function, storing path information for flow control in the memory; a storage unit that stores, as a group, flows that access the same row address of the memory when updating a counter value managed in the path information; an update processing unit that updates the counter value by successively accessing the memory for a plurality of flows that have the same row address as an access destination by changing the order of the plurality of flows; An information processing device comprising:

[0189] (Appendix 2) The update processing unit: A counter for managing the number of consecutive flows that access the same row address is provided, When a read request for the counter value for the path information is made, if consecutive flows accessing the same row address are detected, the counter is incremented; When a response of a counter value from the route information is detected for a continuous flow having the same row address as an access destination, the counter is decremented; If the counter is not 0, memory access to the memory for the flow is suppressed. 2. The information processing device according to claim 1,

[0190] (Appendix 3) An information processing device having a packet relay function, the information processing device comprising a processor, a memory for storing path information for flow control, and an FPGA (Field Programmable Gate Array), a process of grouping flows that access the same row address in the memory and storing the grouped flows in a storage unit when updating a counter value managed in the path information; a process of changing the order of the plurality of flows, successively accessing the memory for the plurality of flows having the same row address as an access destination, and updating the counter value; A control method comprising:

[0191] (Appendix 4) the information processing device includes a counter for managing the number of consecutive flows that access the same ROW address; The updating process is a process of incrementing the counter when detecting consecutive flows accessing the same row address at the time of a request to read the counter value for the path information; a process of decrementing the counter when detecting a response of a continuous flow having the same ROW address as an access destination when a counter value is returned from the route information; If the counter is not 0, a process of suppressing memory access to the memory for the flow in question. 4. The control method according to claim 3, comprising:

[0192] (Appendix 5) An information processing device having a packet relay function, the information processing device comprising a processor, a memory for storing path information for flow control, and an FPGA (Field Programmable Gate Array), a process of grouping flows that access the same row address in the memory and storing the grouped flows in a storage unit when updating a counter value managed in the path information; a process of changing the order of the plurality of flows, successively accessing the memory for the plurality of flows having the same row address as an access destination, and updating the counter value; A control program that causes the processor to execute the above.

[0193] (Appendix 6) the information processing device includes a counter for managing the number of consecutive flows that access the same ROW address; The updating process is a process of incrementing the counter when detecting consecutive flows accessing the same row address at the time of a request to read the counter value for the path information; a process of decrementing the counter when detecting a response of a continuous flow having the same ROW address as an access destination when a counter value is returned from the route information; If the counter is not 0, a process of suppressing memory access to the memory for the flow in question. 6. The control program according to claim 5, comprising: [Explanation of symbols]

[0194] 1 Virtual Router 2 CPU 3. System Memory 4 PCI cards 5 Onboard Memory 10 FPGA 11 BRAM 12 registers 20 Information processing equipment 101 Flow Table 102 Memory Controller 103 Count-up section 104 Packet processing unit 105a, 105b, 105 Cache 106a, 106b, 106 Burst control circuit 110 ROW address management table 111 New registration check circuit 112 Update Circuit

Claims

1. An information processing device having a processor, a memory, and an FPGA (Field Programmable Gate Array) and a packet relay function, storing path information for flow control in the memory; a storage unit that stores, as a group, flows that access the same ROW address in the memory when updating a counter value managed in the path information; an update processing unit that performs control so that a plurality of flows having the same ROW address are processed consecutively, and performs processing to access the memory consecutively for the plurality of flows having the same ROW address as an access destination and update the counter value; An information processing device comprising:

2. The update processing unit: a counter for managing the number of consecutive flows accessing the same ROW address; When a request to read the counter value for the path information is made, if consecutive flows accessing the same ROW address are detected, the counter is incremented; When a response of a counter value from the route information is detected for consecutive flows that access the same ROW address, the counter is decremented; If the counter is not 0, memory access to the memory for the flow is suppressed.

2. The information processing apparatus according to claim 1, wherein:

3. An information processing device having a packet relay function, the information processing device comprising a processor, a memory for storing path information for flow control, and an FPGA (Field Programmable Gate Array), a process of grouping flows that access the same ROW address in the memory and storing the grouped flows in a storage unit when updating a counter value managed in the path information; a process of controlling the plurality of flows having the same ROW address to be processed consecutively, and successively accessing the memory for the plurality of flows having the same ROW address as an access destination, and updating the counter value; A control method comprising:

4. An information processing device having a packet relay function, the information processing device comprising a processor, a memory for storing path information for flow control, and an FPGA (Field Programmable Gate Array), a process of grouping flows that access the same ROW address in the memory and storing the grouped flows in a storage unit when updating a counter value managed in the path information; a process of controlling the plurality of flows having the same ROW address to be processed consecutively, and successively accessing the memory for the plurality of flows having the same ROW address as an access destination, and updating the counter value; A control program that causes the processor to execute the above.

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