Semiconductor device and manufacturing method thereof

Abstract

To a memory cell with small in size and high operation speed.SOLUTION: A first memory gate is provided on a substrate. A second memory gate is provided on the substrate. The selector gate is provided between the first memory gate and the second memory gate on the substrate. An internal spacer is provided on a side face of the selector gate. The first memory gate and the second memory gate each include capping layer at a top edge. The capping layers each have a curved side face facing the selector gate. A top edge of the internal spacer is adjacent to bottom edges of the capping layers.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to the field of semiconductor devices, and more particularly to a semiconductor device applied to a memory cell and a method for manufacturing the same. [Background technology]

[0002] With the rapid development of cutting-edge technologies such as the Internet of Things, edge computing, and artificial intelligence, the ability to process huge amounts of information is required, and memory cells play an essential role. When the amount of information that needs to be processed is huge, the number of memory cells required increases accordingly. Even electronic products with only basic functions contain millions of memory cells. Therefore, related industries are striving to improve the characteristics of memory cells, such as by simplifying the manufacturing process and reducing volume, in order to reduce costs and meet today's demands for miniaturized electronic products. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 11437392 Summary of the Invention

[0004] According to one aspect of the present invention, a semiconductor device includes a first memory gate, a second memory gate, a select gate, and an internal spacer. The first memory gate is disposed on a substrate. The second memory gate is disposed on the substrate. The select gate is disposed on the substrate between the first memory gate and the second memory gate. The internal spacer is disposed on a side of the select gate. The first memory gate and the second memory gate include capping layers disposed on upper ends thereof, the capping layers having curved sides facing the select gate, and the upper end of the internal spacer is adjacent to the lower end of the capping layer.

[0005] According to another aspect of the present invention, a method for manufacturing a semiconductor device includes the following steps: sequentially forming a first gate material stack and a hard mask on a substrate; removing a portion of the hard mask to form a first recess; forming a first spacer on a side of the hard mask facing the first recess; removing a portion of the first gate material stack not covered by the first spacer and the hard mask to form a second recess; forming an inner spacer on a side of the first gate material stack facing the second recess; forming a second gate material stack in the first recess and the second recess; removing a remaining portion of the hard mask; removing another portion of the first gate material stack not covered by the first spacer, a portion of the second gate material stack, and a portion of the first spacer to form a first memory gate, a second memory gate, and a select gate on the substrate, with the remaining portion of the first spacer forming a capping layer for the first memory gate and a capping layer for the second memory gate. [Brief explanation of the drawings]

[0006] These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

[0007] [Figure 1] 1A to 1C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 2] 1A to 1C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3] 1A to 1C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4] 1A to 1C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5] 1A to 1C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6]1A to 1C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 1A to 1C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] 1A to 1C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] 1A to 1C are schematic cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] In the following detailed description of the embodiments, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the present disclosure may be practiced. In this regard, directional terms such as top, bottom, left, right, front, back, bottom, or top are used with reference to the orientation of the figures being described. Elements of the present disclosure can be positioned in several different orientations. Thus, the directional terms are used for illustrative purposes and are in no way limiting. Also, in the following embodiments, the same or similar reference numbers are used to refer to the same or similar elements.

[0009] Hereinafter, the statement "the first pattern is formed on the second pattern" may mean "the first pattern is in direct contact with the second pattern," or it may mean "the first pattern is not in direct contact with the second pattern, and another pattern exists between the first pattern and the second pattern."

[0010] Terms such as "first," "second," and the like may be used herein to describe various elements, regions, layers, and / or sections, but it should be understood that these elements, regions, layers, and / or sections are not limited by these terms. These terms are used only to distinguish one element, region, layer, and / or section from another element, region, layer, and / or section. Terms such as "first," "second," and other numerical terms, when used herein, do not imply a sequence or order unless clearly indicated by context. Thus, a first element, region, layer, and / or section described below may be referred to as a second element, region, layer, and / or section without departing from the teachings of the embodiments. The terms used in the claims may not be identical to those used in the specification and may be used depending on the order of elements claimed in the claims.

[0011] 1 to 10 are schematic cross-sectional views illustrating steps of a method for fabricating a semiconductor device according to an embodiment of the present invention. In this embodiment, a semiconductor device 1 (see FIG. 10) is an NMOS transistor. In FIG. 1, a substrate 100 is first provided. The substrate 100 may be a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate. Next, at least one shallow trench isolation (STI) surrounding each active region is formed in the substrate 100. For example, the two insulating structures 110 in FIG. 1 may be left and right portions of the shallow trench isolation, and the region between the two insulating structures 110 may be the active region. The material of the insulating structure 110 may include a dielectric material such as silicon dioxide. Next, an ion implantation process is performed to form a well region (not shown) in the substrate 100. The dopant of the well region is adjusted depending on whether the semiconductor device 1 to be formed in a subsequent process is an NMOS transistor or a PMOS transistor. In this embodiment, the semiconductor device 1 is, for example, an NMOS transistor. Thus, the well region is a P-type well region, and the well region may be doped with a P-type dopant, such as boron, indium, or the like.

[0012] Next, a first gate material stack 20 and a hard mask 30 are sequentially formed on the substrate 100. Forming the first gate material stack 20 includes sequentially forming a gate insulating material layer 21, a charge storage material layer 22, a blocking insulating material layer 23, and a conductive gate material layer 24 on the substrate 100. The material of the gate insulating material layer 21 may include an oxide or a high-k material. The oxide may include, for example, silicon dioxide (SiO2). The high-k material may include, for example, a dielectric material having a dielectric constant greater than 10. The material of the charge storage material layer 22 may include a conductor for storing charges, such as doped polycrystalline silicon, or a non-conductor for trapping charges, such as silicon nitride (SiN), to form a charge trap layer for storing charges. The material of the blocking insulating material layer 23 may include an oxide or a high-k material. The oxide may include silicon dioxide. The high-k material may include, for example, a dielectric material having a dielectric constant greater than 10. The material of the conductive gate material layer 24 may include a conductive material such as doped polycrystalline silicon, doped amorphous silicon, a metal, or a metal compound. The material of the hard mask 30 may include, but is not limited to, silicon dioxide (SiO), silicon nitride (SiN), silicon carbide (SiC), and / or silicon oxynitride (SiON). According to one embodiment of the present invention, the material of the hard mask 30 includes silicon nitride.

[0013] Next, as shown in FIG. 2, a portion of the hard mask 30 can be removed via a semiconductor process, such as a lithography process and an etching process, to expose a portion of the top surface 20U of the first gate material stack 20 to form a first recess 50.

[0014] Next, as shown in FIG. 3 , first spacers 60 are formed on the side surfaces 30S of the hard mask 30 facing the first recess 50. For example, a first spacer material layer (not shown) may be formed through a deposition process to completely cover the upper surface 30U and the side surfaces 30S of the hard mask 30 and the upper surface 20U of the first gate material stack 20 exposed through the first recess 50. Then, a portion of the first spacer material layer is removed through an etch-back process to form the first spacers 60. The first spacers 60 may be a single material layer or a stack of material layers. The material of the first spacers 60 may include oxides and / or nitrides, such as silicon dioxide, silicon nitride, silicon oxynitride, or silicon carbonitride. According to one embodiment of the present invention, the material of the first spacers 60 includes silicon dioxide.

[0015] 4 , a self-aligned etching process P1 can be performed using the first spacers 60 and the hard mask 30 as an etching mask, and a single etch or multiple etches can be performed downward along the first spacers 60 to remove portions of the first gate material stack 20 that are not covered by the first spacers 60 and the hard mask 30 to form second recesses 70, so that a portion of the upper surface 100U of the substrate 100 is exposed, and the second recesses 70 communicate with the first recesses 50. Because the first spacers 60 and the hard mask 30 are etching masks for performing the self-aligned etching process P1, there is no need to fabricate an extra etching mask, which is beneficial to simplifying the process.

[0016] Next, as shown in FIG. 5 , an internal spacer 500 is formed on the side surface 20S of the first gate material stack 20 facing the second recess 70. Here, the internal spacer 500 includes, from the inside to the outside, a first internal spacer layer 510 and a second internal spacer layer 520. For example, a first internal spacer material layer (not shown) and a second internal spacer material layer (not shown) may be sequentially formed by a deposition process to completely cover the hard mask 30, the first spacer 60, and the upper surface 100U of the substrate 100 exposed from the second recess 70. Then, a portion of the first internal spacer material layer and a portion of the second internal spacer material layer are removed by an etching process to form the first internal spacer layer 510 and the second internal spacer layer 520. The first internal spacer layer 510 has an L-shaped cross section, and the second internal spacer layer 520 has an I-shaped cross section. That is, the first internal spacer layer 510 includes a vertical portion 511 and a horizontal extension portion 512. The extension direction of the vertical portion 511 is perpendicular to the extension direction of the horizontal extension portion 512, and the second inner spacer layer 520 has no horizontal extension portion. In other embodiments, the first inner spacer layer 510 and the second inner spacer layer 520 having an I-shaped cross section may be formed sequentially through a continuous process of deposition, etching, deposition, and etching. The materials of the first inner spacer layer 510 and the second inner spacer layer 520 may independently include oxides and / or nitrides, such as silicon dioxide, silicon nitride, silicon oxynitride, or silicon carbonitride. According to one embodiment of the present invention, the material of the first inner spacer layer 510 includes silicon dioxide, and the material of the second inner spacer layer 520 includes silicon nitride.

[0017] Next, as shown in FIG. 6 , a second gate material stack 40 is formed in the first recess 50 and the second recess 70. Forming the second gate material stack 40 may include sequentially forming a gate insulating layer 410 and a conductive gate material layer 42 on the substrate 100. The material of the gate insulating layer 410 may include an oxide, and the material of the conductive gate material layer 42 may include a conductive material such as doped polycrystalline silicon, doped amorphous silicon, a metal, or a metal compound. For example, the gate insulating layer 410 is formed by a thermal growth process. In this case, as shown in FIG. 6 , the gate insulating layer 410 has a rectangular cross section. The thermal growth process may include, but is not limited to, an in-situ steam generation (ISSG) oxidation process, a wet oxidation process, a dry oxidation process, etc. Thereafter, the conductive gate material layer 42 is formed by a deposition process, and then a planarization process, such as a chemical mechanical polishing (CMP) process and / or an etch-back process, is performed to remove a portion of the conductive gate material layer 42, so that the upper surface 42U of the conductive gate material layer 42 is aligned with the upper surface 30U of the hard mask 30. In another embodiment, the gate insulating layer 410 may be formed by a deposition process. In this case, a gate insulating film (not shown) having a U-shaped cross section is obtained in the first recess 50 and the second recess 70. In FIG. 6 , the thickness T2 of the gate insulating layer 410 is the same as the thickness T1 of the gate insulating material layer 21. However, this is merely an example, and the present invention is not limited thereto.

[0018] Next, as shown in FIG. 7, the remaining portions of the hard mask 30 can be removed by semiconductor processes such as etching and cleaning processes to expose the portions of the first gate material stack 20 that are not covered by the first spacers 60 and the second gate material stack 40.

[0019] 8 , a self-aligned etching process P2 may be performed using the first spacers 60 as an etching mask, in which a single etch or multiple etches may be performed downward along the first spacers 60 to remove portions of the first gate material stack 20 that are not covered by the first spacers 60. During the self-aligned etching process P2, portions of the second gate material stack 40 (here, portions of the conductive gate material layer 42) and portions of the first spacers 60 are also removed, forming the first memory gate 201, the second memory gate 202, and the select gate 400 on the substrate 100. The remaining portions of the first spacers 60 form the capping layer 250 of the first memory gate 201 and the capping layer 250 of the second memory gate 202. Each of the capping layers 250 has a curved side surface 250S facing the select gate 400. The remaining portions of conductive gate material layer 24, blocking insulating material layer 23, charge storage material layer 22, and gate insulating material layer 21 form the conductive gate layer 240, blocking insulating layer 230, charge storage layer 220, and gate insulating layer 210 of first memory gate 201 and second memory gate 202. The remaining portion of conductive gate material layer 42 forms the conductive gate layer 420 of select gate 400.

[0020] 7, the height H3 of the capping layer 250 is lower than the height H1 of the first spacer 60, and the capping layer 250 has a flat upper surface 250U. Compared to the conductive gate material layer 42 in FIG. 7, the height H4 of the conductive gate material layer 420 is lower than the height H2 of the conductive gate material layer 42, and the capping layer 250 does not completely cover the curved side surface 250S.

[0021] 9 , outer spacers 600 are formed on the outer surfaces 201S and 202S of the first memory gate 201 and the second memory gate 202, and an upper end 600T of the outer spacer 600 is aligned with the upper surface 250U of the capping layer 250. The outer spacer 600 includes, from the inside to the outside, a first outer spacer layer 610, a second outer spacer layer 620, and a third outer spacer layer 630. For example, a first outer spacer material layer (not shown) and a second outer spacer material layer (not shown) are sequentially formed by a deposition process to completely cover the first memory gate 201, the second memory gate 202, the select gate 400, and the exposed upper surface 100U of the substrate 100. Then, portions of the first outer spacer material layer and the second outer spacer material layer are removed by an etching process to form the first outer spacer layer 610 and the second outer spacer layer 620. Next, a third outer spacer layer 630 is formed by a semiconductor process such as a deposition process and an etching process. The first outer spacer layer 610 has an L-shaped cross section, the second outer spacer layer 620 has an I-shaped cross section, and the third outer spacer layer 630 has an I-shaped cross section. That is, the first outer spacer layer 610 includes a vertical portion 611 and a horizontal extension portion 612. The extension direction of the vertical portion 611 is perpendicular to the extension direction of the horizontal extension portion 612, and the second outer spacer layer 620 and the third outer spacer layer 630 do not have a horizontal extension portion. The materials of the first outer spacer layer 610, the second outer spacer layer 620, and the third outer spacer layer 630 may independently include oxides and / or nitrides such as silicon dioxide, silicon nitride, silicon oxynitride, or silicon carbonitride. According to an embodiment of the present disclosure, the material of the first outer spacer layer 610 includes silicon dioxide, the material of the second outer spacer layer 620 includes silicon nitride, and the material of the third outer spacer layer 630 includes silicon dioxide. In other embodiments, the first outer spacer layer 610, the second outer spacer layer 620, and the third outer spacer layer 630 having an I-shaped cross section may be formed sequentially by a continuous process of deposition, etching, deposition, etching, deposition, and etching.

[0022] Next, as shown in FIG. 10 , an ion implantation process P3 can be performed to form two doped regions 710 and 720 in the substrate 100, with the doped region 710 adjacent to the first memory gate 201 and the other doped region 720 adjacent to the second memory gate 202. The conductivity types of the two doped regions 710 and 720 are the same as each other and different from the conductivity type of the well region. In this embodiment, the well region is a P-type well region, and the two doped regions 710 and 720 are N-type doped regions. Therefore, the ion implantation process P3 is a process of implanting an N-type dopant into the substrate 100. For example, the N-type dopant may include, but is not limited to, arsenic, phosphorus, etc. This completes the fabrication of the semiconductor device 1.

[0023] The aforementioned film layers, such as the gate insulating material layer 21, the charge storage material layer 22, the blocking insulating material layer 23, the conductive gate material layer 24, the hard mask 30, the first spacer material layer, the first inner spacer material layer, the second inner spacer material layer, the gate insulating layer 410, the conductive gate material layer 42, the first outer spacer material layer, the second outer spacer material layer, and the third outer spacer material layer, can be formed by any suitable method, such as, but not limited to, molecular beam epitaxy (MBE), chemical vapor deposition (CVD), organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), and atomic layer deposition (ALD).

[0024] 10, which is a schematic cross-sectional view of a semiconductor device 1 according to an embodiment of the present disclosure. The semiconductor device 1 includes a first memory gate 201, a second memory gate 202, a select gate 400, and an inner spacer 500. The first memory gate 201 is disposed on a substrate 100, the second memory gate 202 is disposed on the substrate 100, and the select gate 400 is disposed on the substrate 100 between the first memory gate 201 and the second memory gate 202. The inner spacer 500 is disposed on a side surface 400S of the select gate 400. Each of the first memory gate 201 and the second memory gate 202 includes a capping layer 250 disposed on its upper end (not labeled). Each of the capping layers 250 has a curved side surface 250S facing the select gate 400, and an upper end 500T of the inner spacer 500 is adjacent to a lower end 250B of each of the capping layers 250. The above-mentioned "the upper end 500T of the inner spacer 500 is adjacent to the lower end 250B of the capping film 250" means that the upper end 500T of the inner spacer 500 is slightly higher than the lower end 250B of the capping film 250 that is directly in contact with it, or that the vertical distance between the upper end 500T of the inner spacer 500 and the lower end B of the capping film 250 that is directly in contact with it is smaller than the vertical distance between the upper end 500T of the inner spacer 500 and the upper surface 250U of the capping film 250 that is directly in contact with it.

[0025] Specifically, the first memory gate 201 includes a gate insulating film 210, a charge storage layer 220, a blocking insulating film 230, a conductive gate film 240, and a capping film 25, which are sequentially disposed on the substrate 100 from bottom to top. The second memory gate 202 includes a gate insulating film 210, a charge storage layer 220, a blocking insulating film 230, a conductive gate film 240, and a capping film 250, which are sequentially disposed on the substrate 100 from bottom to top. Each of the capping layers 250 may have a vertical side surface 250F opposite a curved side surface 250S. That is, the capping layers 250 have an asymmetric cross-sectional shape.

[0026] The materials of the gate insulating layer 210, the charge storage layer 220, the blocking insulating layer 230, the conductive gate layer 240, and the capping layer 250 may be the same as those of the gate insulating material layer 21, the charge storage material layer 22, the blocking insulating material layer 23, the conductive gate material layer 24, and the first spacer 60, respectively, and will not be repeated here. The first memory gate 201 and the second memory gate 202 are charge trapping memory cells. According to one embodiment of the present invention, the materials of the gate insulating layer 210, the charge storage layer 220, and the blocking insulating layer 230 may be oxide, nitride, and oxide, respectively. That is, the first memory gate 201 and the second memory gate 202 may be ONO-type memory cells. The operating principles of ONO-type memory cells are well known in the art and will not be repeated here.

[0027] The select gate 400 includes a gate insulating film 410 and a conductive gate film 420, which are sequentially disposed on the substrate 100 from bottom to top. The material of the conductive gate layer 420 may be the same as the material of the conductive gate material layer 42, and will not be repeated here. The upper surface 400U of the select gate 400 is lower than the upper surface 250U of the cap layer 250 and is located between the upper surface 250U of the cap layer 250 and the lower end 250B of the cap layer 250. The upper surface 400U of the select gate 400 is higher than the upper end 500T of the inner spacer 500, which is higher than the upper surface 240U of the conductive gate layer 240. This effectively isolates the influence of the upper corners of the conductive gate layer 240 on the select gate 400.

[0028] The semiconductor device 1 may further include an outer spacer 600. The outer spacer 600 is disposed on the outer surface 201S of the first memory gate 201 (see FIG. 9 ) and the outer surface 202S of the second memory gate 202 (see FIG. 9 ). An upper end 600T of the outer spacer 600 is aligned with the upper surface 250U of the capping layer 250. Each of the inner spacer 500 and the outer spacer 600 may have a multi-layer structure. Here, the inner spacer 500 has a two-layer structure and includes, from the inside to the outside, a first inner spacer layer 510 and a second inner spacer layer 520. The outer spacer 600 has a three-layer structure and includes, from the inside to the outside, a first outer spacer layer 610, a second outer spacer layer 620, and a third outer spacer layer 630. That is, the number of layers of the outer spacer 600 is greater than the number of layers of the inner spacer 500. For details of the inner spacer 500 and the outer spacer 600, please refer to the above description, and they will not be repeated here.

[0029] The semiconductor device 1 may further include two doped regions 710 and 720 disposed in the substrate 100, where the doped region 710 is disposed adjacent to the first memory gate 201 and the other doped region 720 is disposed adjacent to the second memory gate 202. As described above, the semiconductor device 1 is illustratively an NMOS transistor. The well region in the substrate 100 is a P-type well region, and the two doped regions 710 and 720 are N-type doped regions. The two doped regions 710 and 720 may be configured as a source line and a bit line for the first memory gate 201 and the second memory gate 202, respectively. In the semiconductor device 1, the first memory gate 201 and the second memory gate 202 share the select gate 400 to form a dual-bit memory cell, which is beneficial for increasing memory density and reducing volume. The first memory gate 201 and the second memory gate 202 are erased through, for example, Fowler-Nordheim (FN) tunneling or hot hole injection, and programmed by source-side injection.

[0030] Compared to the prior art, the method for manufacturing a semiconductor device of the present disclosure allows a first memory gate and a second memory gate to be simultaneously formed on both sides of a select gate, thereby allowing the first memory gate and the second memory gate to share the select gate. Compared to a single memory gate configuration using a single select gate, the present disclosure is beneficial for increasing memory density and reducing volume. Furthermore, in the method for manufacturing a semiconductor device of the present disclosure, the first spacer is used as part of an etching mask when forming the second recess that defines the select gate, and is also used as an etching mask when defining the first memory gate and the second memory gate. The remaining portion of the first spacer can be used as part of the first memory gate and part of the second memory gate. This allows the material constituting the semiconductor device to be used as an etching mask during the process, eliminating the need to separately form an etching mask for forming the second recess that defines the select gate, and for defining the first memory gate and the second memory gate. This is beneficial for simplifying the process and reducing manufacturing costs. As described above, the semiconductor device of the present disclosure has the advantages of increasing memory density, reducing volume, and reducing manufacturing costs.

[0031] Those skilled in the art will readily recognize that numerous modifications and variations of the apparatus and method may be made while retaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A semiconductor device, a first memory gate disposed on the substrate; a second memory gate disposed on the substrate; and a select gate disposed on the substrate between the first memory gate and the second memory gate; internal spacers arranged on side surfaces of the select gate, each of the first memory gate and the second memory gate including a capping layer arranged at an upper end thereof, each of the first memory gate and the second memory gate further including a gate insulating layer, a charge storage layer, a blocking insulating layer and a conductive gate layer arranged in sequence on the substrate, each of the capping layers having a curved side surface facing the select gate, an upper end of the internal spacers adjacent to a lower end of each of the capping layers, and right and left sides of the lower end of each of the capping layers being aligned with the right and left sides of the conductive gate layer, the blocking insulating layer, the charge storage layer and the gate insulating layer underlying the lower end of each of the capping layers; A semiconductor device, wherein an upper surface of the select gate is higher than the upper end of the inner spacer.

2. 2. The semiconductor device of claim 1, further comprising: outer spacers disposed on an outer surface of the first memory gate and on an outer surface of the second memory gate, wherein upper ends of the outer spacers are aligned with the upper surfaces of each of the capping layers.

3. 3. The semiconductor device according to claim 2, wherein each of said inner spacer and said outer spacer has a multi-layer structure, and the number of layers of said outer spacer is greater than the number of layers of said inner spacer.

4. 2. The semiconductor device of claim 1, further comprising: two doped regions disposed in the substrate, one of the doped regions adjacent to the first memory gate and another of the doped regions adjacent to the second memory gate.

5. 2. The semiconductor device according to claim 1, wherein the select gate comprises a gate insulating layer and a conductive gate layer disposed in sequence on the substrate.

6. The semiconductor device of claim 1 , wherein each of said capping layers has an asymmetric cross-sectional shape.

7. The semiconductor device of claim 1 , wherein each of said capping layers has a vertical side opposite said curved side.

8. The semiconductor device of claim 1 , wherein the top surface of the select gate is lower than the top surface of each of the capping layers.

9. 1. A method for manufacturing a semiconductor device, the method comprising: sequentially forming a first gate material stack and a hard mask on a substrate; removing a portion of the hard mask to form a first recess; forming a first spacer on a side of the hard mask facing the first recess; removing portions of the first gate material stack not covered by the first spacers and the hard mask to form a second recess; forming an inner spacer on a side of the first gate material stack facing the second recess; forming a second gate material stack in the first recess and the second recess; removing the remaining portion of the hard mask; removing another portion of the first gate material stack not covered by the first spacer, a portion of the second gate material stack, and a portion of the first spacer to form a first memory gate, a second memory gate, and a select gate on the substrate, wherein remaining portions of the first spacer form a capping layer for the first memory gate and a capping layer for the second memory gate.

10. 10. The method of claim 9, further comprising forming outer spacers on an outer surface of the first memory gate and on an outer surface of the second memory gate, wherein upper ends of the outer spacers are aligned with an upper surface of each of the capping layers.

11. The method of claim 10 , wherein the inner spacer and the outer spacer each have a multi-layer structure, the outer spacer having a greater number of layers than the inner spacer.

12. 10. The method of claim 9, further comprising forming two doped regions in the substrate, one of the doped regions adjacent to the first memory gate and another of the doped regions adjacent to the second memory gate.

13. 10. The method of claim 9, wherein forming the first gate material stack comprises sequentially forming a gate insulating material layer, a charge storage material layer, a blocking insulating material layer, and a conductive gate material layer over the substrate.

14. 10. The method of claim 9, wherein forming the second gate material stack comprises sequentially forming a gate insulating material layer and a conductive gate material layer over the substrate.

15. 10. The method of claim 9, wherein each of the capping layers has a curved side facing the select gate.

16. 10. The method of claim 9, wherein the inner spacers are disposed on sides of the select gate, and upper ends of the inner spacers are adjacent lower ends of each of the capping layers.

17. 10. The method of claim 9, wherein removing portions of the first gate material stack not covered by the first spacers and the hard mask is performed by a self-aligned etching process using the first spacers and the hard mask as an etch mask.

18. 10. The method of claim 9, wherein removing another portion of the first gate material stack not covered by the first spacer is performed by a self-aligned etching process using the first spacer as an etch mask.

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