Semiconductor Devices

Abstract

To solve a problem caused by a stacked structure in which an upper semiconductor chip protrudes from a lower semiconductor chip.SOLUTION: A stack 10 includes a plurality of semiconductor chips 11 stacked with the semiconductor chips 11 being shifted sequentially in the X direction, a wiring board 1 on whose surface the stack 10 is placed, and a silicon chip that is provided in a gap between the underside of the uppermost semiconductor chip 11 and the surface of the wiring board 1 and supports the uppermost semiconductor chip 11, the gap being generated by the vertical shift of the semiconductor chips 11 stacked vertically in the stack 10.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor device. [Background technology]

[0002] In a conventional semiconductor device created by stacking and packaging semiconductor chips, multiple thin semiconductor chips 101 are stacked, electrically connected using wires 102, and sealed with resin, as shown in Figure 1. In this package structure, multiple semiconductor chips 101 are stacked in a staircase-like manner, with the upper semiconductor chips projecting further than the lower semiconductor chips.

[0003] If wiring is performed using wire 102 in this state and bonding is performed for packaging, the pressure from the resin used during bonding will cause chip cracks K to occur at the boundary where the overlap between the topmost protruding semiconductor chip 101 and the semiconductor chip 101 below it ends, as shown in Figure 2. Also, when electrically connecting the topmost semiconductor chip 101 to the wiring board 103, the wires 102 become long because they do not go through the intermediate semiconductor chips 101. This causes the wires 102 to be swept away when the resin is injected, causing contact between the wires 102 and resulting in electrical problems. Figure 3 shows an example of contact S caused by the wires 102 being swept away.

[0004] Patent Document 1 discloses a semiconductor device in which upper semiconductor chips are stacked so as to protrude beyond the lower semiconductor chips. The semiconductor device includes a wiring substrate having a surface, a chip stack including a first semiconductor chip disposed above the surface, a second semiconductor chip disposed between the surface and the chip stack, a spacer disposed between the surface and the first semiconductor chip, continuously surrounding the second semiconductor chip along the surface and including a material having a thermal conductivity higher than that of silicon, and an insulating sealing layer covering the chip stack. This semiconductor device has the advantage of being highly reliable.

[0005] Patent Document 2 discloses an integrated circuit using through silicon vias (TSVs). The integrated circuit (IC) includes a substrate having a top surface and a bottom surface and circuitry on the top surface, a plurality of bonding pads formed along the periphery of the bottom surface, and a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads among the plurality of bonding pads. A first subset of bonding pads among the plurality of bonding pads are electrically coupled to the circuitry on the top surface by the through silicon vias (TSVs). The backside metal layer (BML) distributes electrical signals provided by the second subset of bonding pads. This invention has the effect of significantly improving design cycles and manufacturing yields by using TSV wire bonding.

[0006] Patent Document 3 discloses a semiconductor device including a first substrate, a plurality of semiconductor chips stacked on the first substrate and electrically connected to each other by through electrodes, and a first metal object arranged outside the plurality of semiconductor chips and connecting a power supply connection portion of the semiconductor chip located in the uppermost position among the plurality of semiconductor chips to a connection portion of the first substrate. This invention has the effect of providing a semiconductor device in which the potential difference between the uppermost and lowermost semiconductor chips in a multi-chip stacked structure using TSVs is reduced.

[0007] Patent Document 4 discloses, in some embodiments, an apparatus including an ultrasonic on-chip having through-silicon vias (TSVs), and an interposer coupled to the ultrasonic on-chip and including vias, where the ultrasonic on-chip is coupled to the interposer such that the TSVs in the ultrasonic on-chip are electrically connected to the vias in the interposer. In some embodiments, an apparatus is disclosed that includes an ultrasonic on-chip having bond pads, an interposer having the bond pads and coupled to the ultrasonic on-chip, and wire bonds extending from the bond pads on the ultrasonic on-chip to the bond pads on the interposer.

[0008] As described above, although semiconductor devices in which the upper semiconductor chip is stacked in a state where it protrudes beyond the lower semiconductor chip are known, there has been nothing to compensate for the mechanical fragility of this structure.

[0009] Furthermore, although through-silicon vias (TSVs) are known, their use is to obtain electrical connections, and they have not been used to obtain any special effects when applied to semiconductor devices in which an upper semiconductor chip protrudes beyond a lower semiconductor chip. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Japanese Patent Application Laid-Open No. 2023-129959 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-82524 [Patent Document 3] Japanese Patent Application Laid-Open No. 2017-152648 [Patent Document 4] Special Publication No. 2021-511750 Summary of the Invention [Problem to be solved by the invention]

[0011] The embodiments of the present invention have been made in consideration of the problems of conventional semiconductor devices as described above, and their purpose is to provide a semiconductor device having a structure in which an upper semiconductor chip is stacked in a state where it protrudes beyond a lower semiconductor chip, while overcoming the problems that arise from this structure. [Means for solving the problem]

[0012] A semiconductor device according to an embodiment of the present invention includes a stacked body in which a plurality of semiconductor chips are stacked with each chip being shifted sequentially in the X direction, a wiring board on which the stacked body is placed, and a silicon chip that is provided in a gap between the lower surface of the uppermost semiconductor chip and the surface of the wiring board, the gap being generated by the vertical shift of the semiconductor chips stacked one above the other in the stacked body, and that supports the uppermost semiconductor chip. A semiconductor device employing a silicon through electrode as the silicon chip, a connection pad provided on the upper surface of the uppermost semiconductor chip and a through conductor on the upper surface of the silicon chip provided on the surface of the wiring substrate are connected by a wire, and the through conductor of the silicon through electrode connects the through conductor on the upper surface of the silicon chip and a bonding pad provided on the surface of the wiring substrate. It is characterized by: [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a side view of a conventional semiconductor device produced by stacking and packaging semiconductor chips. [Figure 2] 1 is a side view showing an example of a crack occurring in a conventional semiconductor device produced by stacking and packaging semiconductor chips; [Figure 3] 1 is a perspective view showing an example in which contact occurs between adjacent wires in a conventional semiconductor device fabricated by stacking and packaging semiconductor chips; [Figure 4] 1 is a side view showing a semiconductor device according to a first embodiment of the present invention. [Figure 5] 1A and 1B are side views showing a comparison between a conventional semiconductor and a semiconductor device according to a first embodiment of the present invention. [Figure 6] FIG. 4 is a side view showing a semiconductor device according to a second embodiment of the present invention. [Figure 7] FIG. 10 is a side view showing a semiconductor device according to a third embodiment of the present invention. [Figure 8] FIG. 10 is a perspective view showing a semiconductor device according to a fourth embodiment of the present invention. [Figure 9] FIG. 10 is a perspective view showing a semiconductor device according to a fifth embodiment of the present invention. [Figure 10] FIG. 10 is a perspective view showing a semiconductor device according to a sixth embodiment of the present invention. [Figure 11] FIG. 13 is a perspective view showing a semiconductor device according to a seventh embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0022] A semiconductor device according to an embodiment of the present invention will be described below with reference to the accompanying drawings. In each drawing, the same components are assigned the same reference numerals, and duplicated explanations will be omitted. In Fig. 4, the semiconductor device according to this embodiment has a laminate 10 disposed on the surface of a wiring substrate 1 having a required thickness and a rectangular planar shape.

[0023] The stack 10 is formed by stacking a plurality of semiconductor chips 11 in a state where they are sequentially shifted in the X direction so that the uppermost ones protrude more. The number of stacked chips is determined by the specifications of the semiconductor device. In this embodiment, a silicon chip 20 is used to prevent chip cracking K shown in FIG. 2. That is, this silicon chip 20 is provided in a gap generated by the vertical shift of the semiconductor chips 11 stacked one above the other in the stack 10, between the underside of the uppermost semiconductor chip 11 and the surface of the wiring substrate 1, and supports the uppermost semiconductor chip 11 from its backside.

[0024] In this embodiment, a silicon through electrode (through silicon via (TSV)) is used as the silicon chip 20. A through conductor 21 of this silicon through electrode connects between a connection pad 15 provided on the top surface of the uppermost semiconductor chip 11 and a bonding pad 2 provided on the surface of the wiring substrate 1. In this embodiment, a bump 3 connects between the through conductor 21 of the silicon through electrode and the bonding pad 2.

[0025] With the above-described configuration, it is possible to prevent the problem of chip cracks K occurring at the boundary where the overlap between the uppermost protruding semiconductor chip 11 and the semiconductor chip 11 below it ends. Furthermore, the connection pads 15 provided on the upper surface of the uppermost semiconductor chip 11 and the through conductors 21 on the upper surface of the silicon chip 20 provided on the surface of the wiring substrate 1 are connected by wires 16, so that the through conductors 21 of the silicon through electrodes The length of the wire 16 can be made shorter than that shown in FIG. 2, and the risk of the wire 16 being swept away by the resin and coming into contact with adjacent wires 16 is reduced.

[0026] 5, the semiconductor device has a structure in which it is sealed with an insulating sealing layer made of resin 4 and then covered with a package 5 such as a conductive shielding layer. Therefore, in a conventional example in which electrical connection from the top semiconductor chip 101 to the wiring board 103 is made directly by wire 102, package 5 requires a distance La for wire 102 to be stretched (FIG. 5(a)). In contrast, since through conductor 21 is embedded in silicon chip 20, it is sufficient to use distance Lb for wiring from the tip of the top protruding semiconductor chip 11 to the silicon chip 20, taking into account the size of silicon chip 20, so that La > Lb, and the size of the device can be reduced (FIG. 5(b)).

[0027] FIG. 6 is a diagram showing a second embodiment. Silicon chips 20A in this embodiment are provided in the gaps between the undersides of the uppermost semiconductor chip 11 and the next-to-top semiconductor chip 11 and the surface of the wiring substrate 1. It can be seen that this embodiment provides more appropriate support for the protruding portions of the stack. Furthermore, a configuration such as that shown in FIG. 7 is possible. This silicon chip 20B is shaped to fill all gaps caused by misalignment between the underside of the uppermost semiconductor chip 11 and the surface of the wiring substrate. This structure can further firmly support the protruding portions of the stack.

[0028] The silicon chips 20, 20A, and 20B in the first embodiment shown in Fig. 4, the second embodiment shown in Fig. 6, and the third embodiment shown in Fig. 7 are provided with a controller C that controls at least the devices formed on the uppermost semiconductor chip 11. When the devices formed on the uppermost semiconductor chip 11 are devices that realize memories or other circuits, these devices can be controlled by the controller C. This configuration may also be employed when devices formed on several layers of semiconductor chips 11 connected to the uppermost semiconductor chip 11 are grouped together and can be controlled by a single controller C.

[0029] 8, in the stack, multiple semiconductor chips 11 are stacked in a state where they are sequentially shifted in the Y direction, which is perpendicular to the X direction on a plane. In this embodiment, as described above, it is possible to use silicon chips 20 that are sufficient to accommodate the protrusions in the X direction.

[0030] 9, a silicon chip 20 corresponding to the protrusion in the X direction and a silicon chip 50 corresponding to the protrusion in the Y direction are provided. The silicon chip 50 corresponding to the Y-direction misalignment is a gap generated by the misalignment in the Y direction of the semiconductor chips stacked one above the other in the stack, and is provided in the gap between the lower surface of the uppermost semiconductor chip and the surface of the wiring substrate, and supports the uppermost semiconductor chip from the back surface.

[0031] The configuration of the sixth embodiment is shown in Fig. 10. The silicon chip 20 and the Y-direction misalignment compliant silicon chip 50 in the fifth embodiment are provided with a controller C that controls at least the devices formed on the uppermost semiconductor chip 11.

[0032] 11 shows the seventh embodiment. The silicon chip 20 and the silicon chip 50 for Y-direction misalignment not only support the uppermost semiconductor chip 11, but also employ silicon chip through conductors 21 and 51. The through conductors of the silicon through electrodes in this silicon chip for Y-direction misalignment connect the connection pads provided on the top surface of the uppermost semiconductor chip 11 to the bonding pads provided on the surface of the wiring substrate 1, in the same manner as in FIGS. 6 and 7.

[0033] 11 may be integrally configured with the silicon chip 20. In the fourth, fifth, sixth, and seventh embodiments, the silicon chip 20 and / or the silicon chip 50 for accommodating Y-direction misalignment may be provided in the gap between the lower surface of the uppermost semiconductor chip 11 and the lower surface of the next uppermost semiconductor chip 11 and the surface of the wiring substrate 1.

[0034] Furthermore, in the fourth, fifth, sixth and seventh embodiments, the silicon chip 20 and / or the Y-direction misalignment-compatible silicon chip 50 may be shaped to fill all of the gaps caused by the misalignment from the underside of the uppermost semiconductor chip 11 to the surface of the wiring substrate 1. [Explanation of symbols]

[0035] 1. Wiring board 2 bonding pads 3. Bump 4. Resin 5 packages 10 Laminate 11 Semiconductor chips 15 connection pads 16 wires 20 Silicon Chips 20A Silicon Tip 20B silicon chip 21 Through conductor 50 Y-direction misalignment resistant silicon chip 51 Through conductor 101 Semiconductor Chip 102 Wire 103 Wiring board K Crack S contact

Claims

1. a stacked body in which a plurality of semiconductor chips are stacked in a state where they are sequentially shifted in the X direction; a wiring substrate on which the laminate is placed; a silicon chip that is provided in a gap between the lower surface of the uppermost semiconductor chip and the surface of the wiring substrate, the gap being generated by vertical misalignment of the semiconductor chips stacked one above the other in the stack, and that supports the uppermost semiconductor chip; A semiconductor device comprising: a through silicon electrode is used as the silicon chip, and a connection pad provided on the upper surface of the uppermost semiconductor chip and a through conductor on the upper surface of the silicon chip provided on the surface of the wiring substrate are connected by a wire; a through conductor of the silicon through electrode connecting the through conductor on the upper surface of the silicon chip to a bonding pad provided on the surface of the wiring substrate;

2. 2. The semiconductor device according to claim 1, further comprising a silicon chip provided in a gap between the bottom surface of the semiconductor chip next to the topmost position and the surface of the wiring substrate.

3. 3. The semiconductor device according to claim 2, further comprising a silicon chip provided in a gap between the bottom surface of the third semiconductor chip from the topmost semiconductor chip toward the surface of the wiring substrate and the surface of the wiring substrate.

4. 2. The semiconductor device according to claim 1, wherein the silicon chip is provided with a controller for controlling at least a device formed on the uppermost semiconductor chip.

5. 2. The semiconductor device according to claim 1, wherein the stacked body has a plurality of semiconductor chips stacked in a state where the semiconductor chips are sequentially shifted in a Y direction perpendicular to the X direction on a plane.

6. a gap generated by a Y-direction misalignment between the semiconductor chips stacked one above the other in the stack, the Y-direction misalignment-accommodating silicon chip being provided in the gap between the lower surface of the uppermost semiconductor chip and the surface of the wiring substrate, and supporting the uppermost semiconductor chip; 6. The semiconductor device according to claim 5, further comprising:

7. 7. The semiconductor device according to claim 6, wherein the silicon chip and the Y-direction misalignment accommodating silicon chip are integrally formed.

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