Nonvolatile memory device and method for detecting defective memory cell blocks in nonvolatile memory device

Abstract

To provide a non-volatile memory device and a method of detecting defective memory cell blocks of the non-volatile memory device.SOLUTION: A method of detecting defective memory cell blocks by a non-volatile memory system includes the steps of: executing a read operation for at least a part of memory cells included in a target memory cell block, based on an off-cell detection voltage that is different from a reference voltage for separating an off-cell to which data is not written and an on-cell to which the data is written, after executing an erase operation; counting the number of hard-off-cells having a threshold voltage higher than the off-cell detection voltage, based on the result of executing the reading operation, from memory cells; and determining whether or not the target memory cell block is a defective memory cell block, based on the number of the counted hard-off-cells.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to a memory device, and more particularly to a nonvolatile memory device and a method for detecting a defective memory cell block in the nonvolatile memory device. [Background technology]

[0002] Memory devices are used to store data and are divided into volatile memory devices and non-volatile memory devices. Flash memory devices, an example of a non-volatile memory device, are used in mobile phones, digital cameras, personal digital assistants (PDAs), mobile computing devices, fixed computing devices, and other devices.

[0003] When a nonvolatile memory performs an erase operation by applying an erase command voltage through a substrate, it is possible to determine whether leakage has occurred in a word line by checking the voltage levels of a word line in which leakage current has occurred and a normal word line after the erase operation is performed. However, when a nonvolatile memory performs a GIDL (gate induced drain leakage) erase operation, the difference in voltage levels between the leaking word line and the normal word line is not large, making it difficult to detect a memory cell block including a leaking word line. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile memory device and an operating method thereof that detects a defective memory cell block after a GIDL erase operation is performed. [Means for solving the problem]

[0005] In order to solve the above problem, the method for detecting a defective memory cell block among memory cell blocks in the nonvolatile memory system of the present invention includes the steps of performing a read operation on at least some memory cells included in a target memory cell block based on an off-cell detection voltage different from a read reference voltage after performing an erase operation, counting the number of hard off-cells among the memory cells based on the result of the read operation, and determining whether the target memory cell block is a defective memory cell block based on the counted number of hard off-cells.

[0006] In addition, the nonvolatile memory system of the present invention includes a memory device including a plurality of memory cell blocks; and a memory controller that receives data by sending a command signal to the memory device, wherein the memory controller includes a command generation unit that outputs an off-cell detection command signal to the memory device to instruct the memory device to perform a hard off-cell detection operation after performing an erase operation, and a bad memory cell block determination unit that outputs a signal indicating whether the target memory cell block is a bad memory cell block based on the number of hard off cells counted from at least some of the memory cells included in the target memory cell block in response to the off-cell detection command signal, and the memory device performs a read operation on at least some of the memory cells based on an off-cell detection voltage different from a read reference voltage in response to receiving the off-cell detection command signal.

[0007] The nonvolatile memory controller of the present invention includes a command generating unit that outputs an off-cell detection command signal to the memory device to instruct the memory device to perform a hard-off cell detection operation after performing an erase operation, and a bad memory cell block determining unit that outputs a signal indicating whether the target memory cell block is a bad memory cell block based on the number of hard-off cells counted from at least some memory cells included in the target memory cell block in response to the off-cell detection command signal. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram illustrating a memory system according to one embodiment. [Figure 2] 1 is a block diagram illustrating a memory device according to an embodiment. [Figure 3] FIG. 2 is a block diagram illustrating a memory controller according to one embodiment. [Figure 4] 1 is a diagram illustrating a vertically stacked memory cell array according to one embodiment. [Figure 5] 1 is a diagram illustrating a cell string including a leaky word line, according to one embodiment. [Figure 6] 1 is a diagram illustrating a memory cell in which leakage occurs between a word line and a channel, according to one embodiment. [Figure 7A] 10 is a diagram showing a memory cell to which an erase command voltage is input through a substrate according to a comparative example; [Figure 7B] 10 is a diagram showing voltage levels of a leakage word line and a normal word line according to an erase command voltage; [Figure 8A] 1 is a diagram illustrating a memory cell to which a GIDL erase instruction voltage is input, according to an embodiment of the present invention; [Figure 8B] 10 is a diagram showing voltage levels of a leakage word line and a normal word line according to a GIDL erase command voltage; [Figure 9] 1 is a flowchart illustrating a method for detecting a defective memory cell block according to an embodiment. [Figure 10] 10 is a diagram illustrating threshold voltage levels of a normal memory cell from which data is erased and a hard-off cell, according to one embodiment. [Figure 11] 10 is a diagram illustrating a cell string in which an off-cell detection voltage and a channel open indication voltage are applied to a leakage word line and a normal word line, respectively, according to an embodiment. [Figure 12A] 10 is a table comparing voltage differences between a detection target word line and a channel when voltages are applied to a leakage word line and a normal word line, according to one embodiment. [Figure 12B] 10 is a graph showing voltage level differences between voltages applied to a memory cell array. [Figure 13] 1 is a flowchart illustrating a hard-off cell determination method according to an embodiment. [Figure 14] 1 is a flowchart illustrating a method for determining a defective memory cell block according to an embodiment. [Figure 15] 10 is a table illustrating off-cell information stored in an off-cell information storage block, according to one embodiment. [Figure 16] 1 is a flowchart illustrating an operation sequence of a memory controller and a memory device according to one embodiment. [Figure 17] 10 is a flowchart illustrating an operation sequence of a memory controller and a memory device according to another embodiment. [Figure 18] 1 is a diagram illustrating a memory device having a C2C (Chip to Chip) structure according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0010] FIG. 1 is a block diagram schematically illustrating the configuration of a memory system according to an embodiment.

[0011] Referring to FIG. 1, the memory system includes a memory device 10 and a memory controller 20, where the memory device 10 includes a memory cell array 11, a row decoder 12, a sensing amplifier 13, and a page buffer 14, and the memory controller 20 includes a command generation unit 21, a defective memory cell block determination unit 22, and an off-cell counter 23.

[0012] The memory controller 20 can control program, read, and erase operations for the memory device 10 by providing address, command, and control signals to the memory device 10 to read data stored in the memory device 10 or write data to the memory device 10 in response to a read / write request from the host. In addition, data for a program operation and read data are transmitted and received between the memory controller 20 and the memory device 10. However, hard-off cell counting information and hard-off cell information can also be transmitted and received during a defective memory cell block detection operation.

[0013] The defective memory cell block detection operation may be an operation of detecting a memory cell block in which data cannot be written or read due to a defect occurring in the word line of the target memory cell block and / or a memory cell connected to the word line. For example, current leakage in a memory cell may cause a voltage applied to the substrate to leak to the word line. When the memory controller 20 determines that the target memory cell block is a memory cell block in which data cannot be written or read, it designates the target memory cell block as a defective memory cell block, thereby eliminating the defective memory cell block when performing a read or write operation of the memory device 10.

[0014] The memory cell array 11 may include a plurality of memory cells, which may be, for example, flash memory cells. Hereinafter, an embodiment of the present invention will be described in detail, taking as an example a case where the plurality of memory cells are NAND flash memory cells. However, the present invention is not limited thereto. In other embodiments, the plurality of memory cells may be resistive memory cells such as ReRAM (resistive RAM), PRAM (phase change RAM), or MRAM (magnetic RAM).

[0015] The row decoder 12 is connected to the memory cell array 11 through a plurality of word lines and can apply a read reference voltage or an off-cell detection voltage to memory cells of a target cell string. The row decoder 12 can apply the read reference voltage or the off-cell detection voltage to memory cells based on a command from the memory controller 20 and can identify the word line to which the voltage is to be applied based on a word line address. The target cell string is a cell string in a memory cell block for which the number of hard-off cells is to be counted. The target cell string may be a single cell string, but is not limited thereto and may also be composed of a plurality of cell strings. For example, the target cell string may be a set of cell strings that share a string selection line in a memory cell block. Hereinafter, the target cell string refers to a single or multiple cell strings for which a hard-off cell counting operation is to be performed.

[0016] The sensing amplifier 13 is connected to the memory cell array 11 and can sense data stored in the memory cell array 11. The sensing amplifier 13 can compare a current output from the memory cell array 11 with a reference current and determine the state of data written to a target memory cell based on the comparison result. Exemplarily, the sensing amplifier 13 may include a comparator and can determine that the target memory cell is an on-cell when the current level output from the memory cell array 11 is higher than the reference current, and that the target memory cell is an off-cell when the output current level is lower than the reference current.

[0017] The page buffer 14 may include a plurality of latches, and at least some of the latches may at least temporarily store hard-off cell information based on the data state of the target memory cell output from the sensing amplifier 13. According to one embodiment, the page buffer 14 may count the number of hard-off cells among the memory cells of the target cell string.

[0018] 1, the page buffer 14 and the sensing amplifier 13 are shown as separate components, but are not limited thereto, and the page buffer 14 may include the sensing amplifier 13, and the page buffer 14 may sense data stored in the memory cell array 11. Meanwhile, during a program operation, the page buffer 14 operates as a write driver and inputs data to be stored in the memory cell array 11.

[0019] After performing the erase operation, the command generator 21 of the memory controller 20 may generate an off-cell detection command signal to instruct the memory device 10 to perform a hard off-cell detection operation. The off-cell detection command signal may be a code composed of a series of bits, and the memory device 10 may perform the off-cell detection operation and detect defective memory cell blocks by receiving the off-cell detection command signal.

[0020] The off-cell counter 23 of the memory controller 20 can count the number of hard-off cells present in some memory cells based on hard-off cell information detected from some memory cells of the target memory cell block in response to an off-cell command signal. The hard-off cell information is information generated as a result of performing a read operation on the target cell string, and can be information indicating whether the memory cell to be read is a hard-off cell.

[0021] The defective memory cell block determination unit 22 of the memory controller 20 can determine whether a memory cell block including a target cell string is a defective memory cell block by receiving hard off cell counting information from the off cell counter 23 or the page buffer 14. For example, the memory cell block including the target cell string can be determined to be a defective memory cell block in response to the number of hard off cells counted from the target cell string being greater than the reference number of off cells.

[0022] In FIG. 1, the command generation unit 21, the off-cell counter 23, and the defective memory cell block judgment unit 22 of the memory controller 20 are shown as separate components, but they may also be configured as software modules that perform separate functions on a single piece of hardware.

[0023] FIG. 2 is a block diagram showing a schematic configuration of a memory device 10 according to an embodiment.

[0024] 2, the memory device 10 includes a memory cell array 11, a row decoder 12, a sensing amplifier 13, a page buffer 14, a voltage generator 15, and a control logic 16. The memory cell array 11 according to the present embodiment is an example of the memory cell array 11 of FIG. 1, and the configuration of the memory device 10 is not limited to that of FIG. 2 and may further include other components such as a data input / output unit.

[0025] The memory cell array 11 includes a plurality of memory cell blocks BLK1, BLK2, and BLKz, each of which is composed of a plurality of cell strings including a plurality of memory cells. The memory device 10 of the present invention can perform a hard-off cell sensing operation on a portion of memory cells in a target memory cell block. The hard-off cell sensing operation is performed on a cell string basis. Hereinafter, a target cell string will be referred to as a set of memory cells on which the hard-off cell sensing operation is performed. The memory cell array 11 can be connected to a row decoder 12 via word lines WL, string select lines SSL, and ground select lines GSL. Each memory cell can store one or more bits. Specifically, each memory cell can be used as a single-level cell, a multi-level cell, or a triple-level cell.

[0026] The control logic 16 can output various signals for writing data to the memory cell array 11, reading data from the memory cell array 11, or erasing data stored in the memory cell array 11, based on the command CMD, address ADDR, and control signal CTRL received from the memory controller 20. Furthermore, the control logic 16 can output various signals for detecting off-cells by receiving an off-cell detection command, thereby enabling the control logic 16 to generally control various operations within the memory device 10.

[0027] Various control signals output from the control logic 16 can be provided to the voltage generator 15, the row decoder 12, and the page buffer 14. Specifically, the control logic 16 can provide a voltage control signal CTRL_vol to the voltage generator 15, a row address to the row decoder 12, and a column address to the page buffer 14. However, the present invention is not limited thereto, and the control logic 16 can also provide other control signals to the voltage generator 15, the row decoder 12, and the page buffer 14.

[0028] The voltage generator 15 generates various types of voltages based on the voltage control signals to perform a program operation, a read operation, an erase operation, and an off-cell read operation on the memory cell array 11. Specifically, the voltage generator 15 applies a read reference voltage V to a target memory cell for reading data from among memory cells connected to a word line. READ At this time, a channel open voltage V for opening a channel between the source terminal and the drain terminal is applied to the remaining memory cells excluding the target memory cell. OPEN The voltage generator 15 can further generate a string selection line driving voltage for driving the string selection line and a ground selection line driving voltage for driving the ground selection line. The voltage generator 15 can also generate a GIDL (Gate Induced Drain Leakage) erase voltage to be provided to the memory cell array 11 and an off-cell detection voltage V for detecting a hard-off cell. DET and can further be generated.

[0029] Furthermore, the voltage generator 15 according to an embodiment may apply a word line voltage, a bit line voltage, a string selection line voltage, and a ground selection line voltage to the memory cell array 11 to perform an erase operation.

[0030] The row decoder 12 can identify a word line on which the off-cell sensing operation is to be performed among the word lines in response to a row address X-ADDR received from the control logic 16. Specifically, the row decoder 12 applies an off-cell sensing voltage V DET is applied, and the remaining word lines except the target word line are applied with a channel open voltage V OPENIn addition, the row decoder 12 can select some of the string selection lines or some of the ground selection lines in response to the row address X-ADDR received from the control logic 16 to select a target cell string for performing off-cell detection.

[0031] The page buffer 14 may determine a bit line BL on which a hard-off cell detection operation is performed for the memory cell array 11. The page buffer 14 may receive off-cell detection result information from a cell string connected to each bit line BL and store the off-cell detection result in at least one of a plurality of latches. Exemplarily, the page buffer 14 may receive off-cell detection result information regarding whether a target memory cell is a hard-off cell from the sensing amplifier 13, and if the target memory cell is a hard-off cell, may accumulate and store the number of hard-off cells in the latch. The page buffer 14 may perform a detection operation for all word lines of the target cell string and transmit the hard-off cell number information accumulated in the latch to the control logic 16.

[0032] The sensing amplifier 13 receives a current from the target cell string, which is distinguished by whether the target memory cell is on or off. The sensing amplifier 13 compares the current output from the target cell string with a reference current to output whether the target memory cell is on or off. For example, if the output current is less than the reference current, it can be determined that the channel of the target memory cell is not open and therefore no current is being output from the target cell string. If the output current is less than the reference current, it can be determined that the target memory cell is a hard-off cell. On the other hand, if the output current is equal to or greater than the reference current, it can be determined that the channel of the target memory cell is open and therefore current is being output from the target cell string. If the output current is equal to or greater than the reference current, it can be determined that the target memory cell is a normal memory cell.

[0033] The page buffer 14 and the sensing amplifier 13 are connected to each of the multiple bit lines WL, and when the target cell string is composed of multiple cell strings, the page buffer 14 connected to each bit line counts the number of hard-off cells in each cell string, and the sum of these numbers can be determined to be the number of hard-off cells in the target cell string.

[0034] FIG. 3 is a block diagram showing a schematic configuration of the memory controller 20 according to one embodiment.

[0035] 3, the memory controller 20 includes a command generator 21, a bad memory cell block determiner 22, and an off-cell counter 23. The command generator 21 can output a command signal CMD to the memory device 10 in response to a request from the host device, and can generate an off-cell detection command signal for instructing a hard off-cell detection operation in response to receiving a request to detect a bad memory cell block. The command generator 21 can output an address ADDR of a target memory cell block and a target cell string to be detected, along with the command signal CMD, to the memory device 10 and the bad memory cell block determiner 22. The command generator 21 can also output a control signal CTRL for controlling the memory device 10 to the memory device 10. The control signal CTRL is a control signal for determining a voltage applied to a word line from the memory device 10. For example, when performing an off-cell detection operation after performing an erase operation, the command generator 21 can set an off-cell detection voltage to a value between the threshold voltage level of an erased memory cell and the threshold voltage level of a hard off-cell, and output a control signal for applying the off-cell detection voltage to a word line.

[0036] The off-cell counter 23 can receive hard-off cell information DATA from the memory device 10, which indicates whether a target memory cell is a hard-off cell, and can count the hard-off cells of the target cell string while determining whether all memory cells of the target cell string are hard-off cells. The off-cell counter 23 can generate counting information CNT by counting all hard-off cells of the target cell string and provide the counting information CNT to the defective memory cell block determination unit 22.

[0037] The bad memory cell block determination unit 22 receives counting information CNT from the page buffer 14 or the off-cell counter 23 and determines whether a memory cell block including a target cell string is a bad memory cell block based on the counted number of hard-off cells. Specifically, the bad memory cell block determination unit 22 compares the number of hard-off cells included in the target cell string with a reference number of off-cells corresponding to the target cell string. If the bad memory cell block determination unit 22 determines that the number of hard-off cells is greater than the reference number of off-cells, the bad memory cell block determination unit 22 determines that the target memory cell block is a bad memory cell block by outputting a signal (SIG_bad memory cell block) indicating that the target memory cell block is a bad memory cell block to the host device and / or the memory device 10, thereby blocking data write / read operations to / from the target memory cell block. By determining that the target memory cell block is a bad memory cell block, the memory controller 20 can prevent the occurrence of an uncorrectable error correction code (UECC) when performing a read operation.

[0038] FIG. 4 is a diagram illustrating a vertically stacked memory cell array 11 according to one embodiment.

[0039] 4, memory block BLK includes NAND strings NS11 through NS33, word lines WL1 through WL8, bit lines BL1 through BL3, ground selection lines GSL1 through GSL3, string selection lines SSL1 through SSL3, and a common source line CSL. Memory block BLK may correspond to one of memory blocks BLK1 through BLKz in FIG. 2. The numbers of NAND strings, word lines, bit lines, ground selection lines, and string selection lines may vary depending on the embodiment.

[0040] NAND strings NS11, NS21, and NS31 are provided between a first bit line BL1 and a common source line CSL, NAND strings NS12, NS22, and NS32 are provided between a second bit line BL2 and the common source line CSL, and NAND strings NS13, NS23, and NS33 are provided between a third bit line BL3 and the common source line CSL. Each NAND string (e.g., NS11) may include a string select transistor SST, a plurality of memory cells MC1 through MC8, and a ground select transistor GST connected in series.

[0041] The string select transistors SST are connected to corresponding string select lines SSL1 through SSL3. The memory cells MC1 through MC8 are connected to corresponding word lines WL1 through WL8, respectively. The ground select transistors GST are connected to corresponding ground select lines GSL1 through GSL3. The string select transistors SST are connected to corresponding bit lines BL1 through BL3, and the ground select transistors GST are connected to a common source line CSL.

[0042] Figure 5 illustrates a cell string including a leaky word line, and Figure 6 illustrates a memory cell having leakage between a word line and a channel, according to one embodiment.

[0043] 5, a string select line SSL is identified in a memory cell block, thereby allowing the memory device 10 to select a target cell string. Exemplarily, a voltage for performing a read operation, a program operation, or an erase operation is applied by identifying the string select line SSL in FIG. 5, thereby allowing the memory device 10 to perform a read operation, a program operation, or an erase operation on the target cell string.

[0044] The memory device 10 can apply an erase command voltage to the memory cell array 11 through the bit line, and when performing an erase operation based on the GIDL phenomenon, the erase operation can be performed with even less current than when applying the erase command voltage through the substrate SUB.

[0045] According to the GIDL erase method, the transistors of the ground select line GSL and / or string select line SSL located at both ends of the cell string can perform the operation of a GIDL transistor. When an erase command voltage is applied to the drain electrode (or source electrode) of the GIDL transistor, a GIDL voltage lower than the erase command voltage is applied to the gate electrode. If the voltage difference between the drain electrode and gate electrode of the GIDL transistor is equal to or greater than the voltage level at which a GIDL current is generated, a GIDL current is generated, and holes due to the GIDL current are generated in the channel region of the cell string, thereby charging the channel region. As a result, the memory device 10 of the present invention can perform an erase operation through the bit line BL and / or the substrate SUB based on the GIDL phenomenon.

[0046] During the process of programming, reading, and erasing data in the memory cell array 11, the memory cell may deteriorate, causing leakage current between the word line and the channel. That is, when a voltage for reading or writing is applied to the word line, current leaks to the channel, and the memory cell, which determines whether electrons tunnel to the floating gate based on the potential difference between the channel and the control gate, may malfunction. Hereinafter, a word line in which leakage occurs between the word line and the channel is referred to as a leaky word line, and a memory cell in which leakage occurs is referred to as a leaky memory cell 500.

[0047] For example, when writing data to a memory cell connected to a leakage word line, a positive voltage is applied through the leakage word line and the drain terminal, and electrons must be tunneled to the floating gate based on the potential difference between the channel and the control gate. However, because leakage occurs between the leakage word line and the channel, a high potential difference cannot be induced between the channel and the control gate, and therefore data cannot be written to the memory cell.

[0048] FIG. 7A is a diagram showing a memory cell to which an erase command voltage is input through a substrate according to a comparative example, and FIG. 7B is a diagram showing the voltage levels of a leakage word line and a normal word line according to the erase command voltage.

[0049] The memory device 10 can apply an erase command voltage to a memory cell through the channel hole. When the erase command voltage is applied to a normal memory cell, electrons trapped in the floating gate escape to the outside of the floating gate through the tunnel oxide layer, and the memory device 10 can erase data written in the memory cell. When the erase command voltage is applied to a normal memory cell, the word line WL and the channel hole SUB are separated, so the erase command voltage V is applied through the channel hole SUB. erase Ideally, the word line voltage would not be affected even if a high erase command voltage is applied to the memory cell, but as in the first section of FIG. 7B, when a high erase command voltage is applied, the voltage of the normal word line may also rise.

[0050] As shown in FIG. 7A, the leaking memory cell 500 connected to the leaking word line WL4 is applied with an erase command voltage V erase is applied, a leakage current occurs between the channel hole SUB and the leakage word line WL4, so that the erase command voltage V eraseA portion of the voltage applied to the leakage word line WL4 is applied to the leakage word line WL4, so that a voltage higher than that applied to the normal word line is applied to the leakage word line WL4 during the erase operation, as shown in the first section of FIG.

[0051] In the first period T1 of FIG. 7B, the memory device 10 applies a high level erase command voltage V erase When the erase instruction voltage V starts to be applied to the memory cells, a predetermined voltage is also applied to the normal word lines, but a voltage higher than that of the normal word lines is applied to the leakage word line WL4 due to leakage between the substrate SUB and the leakage word line WL4. erase When applying the erase command voltage V, a part of the applied voltage is discharged through the pass transistor connected to the word line. At this time, the normal word line has a voltage discharged through the pass transistor that is equal to or greater than the erase command voltage V. erase The voltage level of the normal word line drops by more than the voltage applied as a leak current. On the other hand, the voltage of the leakage word line WL4 also drops because a portion of the voltage is leaked through the pass transistor. However, because a higher voltage is applied to the leakage word line WL4 than to the normal word line due to the leakage current, the voltage leaked through the pass transistor is less than that of the normal word line.

[0052] In the second section T2, the memory device 10 applies the erase command voltage V erase After the voltage on each word line is applied, the voltage on each word line can be measured and the voltage on the word line is compared to the reference voltage V ref , the word line WL4 is determined to be a leaking word line WL4. erase While the voltage level of the word line is applied, it is possible to measure the voltage level of the word line, and based on the voltage level of the word line, it is possible to determine whether or not to treat the memory cell block as a defective memory cell block.

[0053] FIG. 8A illustrates a GIDL erase instruction voltage V GIDL8B is a diagram showing the voltage levels of the leakage word line WL4 and the normal word line WL5.

[0054] The memory device 10 according to an embodiment of the present invention can apply an erase command voltage through a bit line and perform an erase operation on memory cells of a target cell string based on the GIDL phenomenon. By applying the erase command voltage, the memory device 10 can induce the formation of a channel between the drain terminal and the source terminal, thereby allowing electrons trapped in the floating gate to escape to the outside through the tunnel oxide layer. When the GIDL erase command voltage V is applied to normal memory cells, GIDL When the GIDL erase command voltage V GIDL As a result of the application of voltage Vdd, a certain voltage rise may occur on the normal word line, as shown in the third section of FIG. 8B.

[0055] As shown in FIG. 8A, the GIDL erase command voltage V GIDL When the GIDL erase instruction voltage V GIDL 7B, a portion of the GIDL erase command voltage V GIDL is a very low voltage level compared to the erase command voltage of FIG. 7B, and the resulting leakage current is also very small.

[0056] In the first period of FIG. 8B, the memory device 10 applies the GIDL erase command voltage V GIDL When starting to apply to the cell string, a predetermined voltage is applied to the normal word line, and a low level GIDL erase instruction voltage V GIDL Therefore, a voltage of a similar level to that of the normal word line is also applied to the leakage word line WL4. When the memory device 10 applies an erase command voltage to the memory device 10 in the second period, a portion of the applied voltage is leaked through the pass transistor connected to the word line. At this time, the GIDL erase command voltage VGIDL is a low level voltage, the voltage levels of the leakage word line WL4 and the normal word line are similar.

[0057] Therefore, the memory device 10 is configured to operate at a GIDL erase instruction voltage V GIDL 7A and 7B, when an erase operation is performed by applying the GIDL erase instruction voltage V GIDL Therefore, in the method of detecting a defective memory cell block, the memory device 10 applies a low voltage level GIDL erase instruction voltage V GIDL This is a method for detecting a defective memory cell block when performing an erase operation by applying a GIDL erase instruction voltage V GIDL It is assumed that the erase operation is performed based on the

[0058] FIG. 9 is a flowchart illustrating a method for detecting a defective memory cell block according to one embodiment.

[0059] 1 and 9, after performing an erase operation, the nonvolatile memory system determines whether there are hard-off cells in the target cell string, and then determines whether the target memory cell block is a defective memory cell block based on the number of hard-off cells in the target cell string. A hard-off cell may be a memory cell having a higher threshold voltage than a normal memory cell for generating a current channel between the drain and source terminals due to leakage of channel holes.

[0060] In step S10, after performing the erase operation, the memory device 10 may perform a read operation on a plurality of memory cells connected to the target cell string based on an off-cell detection voltage different from the read reference voltage. The read reference voltage may be a voltage input to a word line to be read in order to distinguish off-cells to which no data is written from on-cells to which data is written during the read operation. The off-cell detection voltage is a reference voltage different from the read reference voltage and may be a voltage input to a word line to be detected in order to distinguish hard off-cells from normal memory cells.

[0061] In step S20, the memory system may determine whether the target memory cell is a hard-off cell based on the result of the read operation and may count the number of hard-off cells in the target cell string. The result of the read operation may be information indicating whether a channel between the source and drain of the target memory cell is opened by applying an off-cell detection voltage to the target memory cell. If the channel of the target memory cell is not opened, the memory system may determine the target memory cell as a hard-off cell.

[0062] In step S30, the memory system can determine whether the memory cell block including the target cell string is a defective memory cell block based on the counted number of hard-off cells. If the memory controller 20 determines that the memory cell block is a defective memory cell block, it can block data from being written to or read from the memory cell block by sending a signal to the memory device 10 or the host device indicating that the memory cell block is a defective memory cell block. This allows the memory system of the present invention to prevent UECC from occurring by erroneously reading data from the hard-off cells.

[0063] FIG. 10 is a diagram illustrating threshold voltage levels of a normal memory cell and a hard-off cell from which data has been erased, according to one embodiment.

[0064] The command generator 21 of the memory controller 20 may generate an off-cell detection command signal in response to receiving a defective memory cell block detection instruction from the host. The off-cell detection command signal may be a code composed of a series of bits and may be a command signal instructing the memory device 10 to perform a hard off-cell detection operation. Furthermore, the command generator 21 may generate a command for setting an off-cell detection voltage so that the memory device 10 performs the hard off-cell detection operation.

[0065] 10, the threshold voltage of the hard-off cell 1020 may have a higher voltage level than the threshold voltage of the normally erased memory cell 1010, and the normally erased memory cell 1010 may have the same threshold voltage level as a memory cell to which data is not written. Therefore, when the memory device 10 receives an off-cell detection command signal, the voltage generator 15 outputs a voltage between the threshold voltage of the normally erased memory cell 1010 and the threshold voltage of the hard-off cell 1020 as the off-cell detection voltage, and the row decoder 12 applies the off-cell detection voltage to the target word line, thereby allowing the memory device 10 to determine whether the target memory cell connected to the target word line is a hard-off cell. At this time, a channel open voltage is applied to the remaining word lines other than the target word line, thereby opening a current channel between the source and drain terminals of the remaining memory cells other than the target memory cell.

[0066] FIG. 11 illustrates the off-cell detection voltage V for the leakage word line and the normal word line, respectively, according to one embodiment. DET and channel open voltage V OPEN 1 is a diagram showing a cell string to which a voltage is applied.

[0067] Referring to FIG. 11, the memory device 10 applies an off-cell detection voltage V to a target memory cell to be detected as a hard-off cell through a target word line. DET The remaining word lines can be applied with a channel open voltage V OPEN For convenience of explanation, FIG. 11 shows a case where a channel open voltage V is applied to only one word line. OPEN , the memory device 10 of the present invention applies a channel open voltage V to all word lines except the target word line. OPEN can be applied.

[0068] 11, the first bit line BL1 is connected to a cell string including memory cells that do not leak between a channel hole and a word line, and the second bit line BL2 is connected to a cell string including memory cells that leak between a channel hole and a word line. In this case, the cell strings connected to the first bit line BL1 can share the first channel hole CH1, and the cell strings connected to the second bit line BL2 can share the second channel hole CH2.

[0069] The memory device 10 applies an off-cell detection voltage V to the third word line WL3 to determine whether the memory cell connected to the third word line WL3 is a hard-off cell. DET When the third word line WL3 is applied, the remaining word lines except the third word line WL4 are applied with a channel open voltage V OPEN A channel open voltage V can be applied to the memory cells sharing the first channel CH1 through the word line. OPEN A current channel is formed in the memory cell to which the off-cell detection voltage V is input. At this time, the memory cell is connected to the third word line WL3 and is supplied with the off-cell detection voltage V DET If the memory cell to which the off-cell detection voltage V is applied is erased successfully, DETis higher than the threshold voltage of a normally erased memory cell, a current channel can be formed. Therefore, a cell string including a normally erased memory cell forms a current channel, and a current indicating that the memory cell connected to the third word line WL3 is not a hard-off cell can be output.

[0070] In contrast, in the cell strings sharing the second channel CH2, the leaking memory cell connected to the fourth word line WL4 allows the memory device 10 to determine that the target memory cell connected to the third word line WL3 is a hard-off cell.

[0071] Figure 12A is a table comparing the voltage difference between the detection target word line and the channel when voltages are applied to the leaking word line and the normal word line according to one embodiment of Figure 11, and Figure 12B is a graph showing the voltage level difference between the voltages applied to the memory cell array 11.

[0072] 11, the cell string connected to the first bit line BL1 does not have a leaking memory cell, and the cell string connected to the second bit line BL2 has a leaking memory cell connected to the fourth word line WL4. The memory device 10 can perform a hard off-cell detection operation on the memory cells connected to the third word line WL3, and an off-cell detection voltage V DET At this time, the memory device 10 applies a channel open voltage V to the remaining word lines except the third word line WL3. OPEN The leaky memory cell can also be applied with a channel open voltage V OPEN Referring to FIG. 12A, a channel open voltage V OPEN12A and 12B, the voltage of the second channel and the voltage of the fourth word line WL4 are described as being the same due to leakage, but the voltage of the second channel and the voltage of the fourth word line WL4 may be between the voltage level of the first channel and the voltage level of the fourth word line WL4.

[0073] 12A and 12B, since no leakage current occurs in the cell strings sharing the first channel, the first channel is subjected to the substrate voltage V SUB is applied to the cell string that shares the second channel, leakage current occurs, so the second channel is connected to the channel open voltage V OPEN A voltage corresponding to the off-cell detection voltage V is applied to the memory cell. At this time, it can be determined whether a current channel is formed between the source and drain terminals based on the potential difference between the voltage applied from the word line of the memory cell and the voltage applied to the channel. The potential difference between the word line and the channel of the target memory cell to be detected among the memory cells connected to the first channel is equal to the off-cell detection voltage V. DET and the substrate voltage V SUB The off-cell detection voltage V DET and the substrate voltage V SUB Since the difference between Vdd and Vdd is higher than the threshold voltage of a normally erased memory cell, the current channel of the memory cell is then opened.

[0074] On the other hand, among the memory cells connected to the second channel, the potential difference between the word line of the target memory cell and the channel is the off-cell detection voltage V DET and the channel open voltage V OPEN According to one embodiment of FIG. 12B, the channel open voltage V OPEN is the off-cell detection voltage V DET Therefore, the off-cell detection voltage VDET and the channel open voltage V OPEN The difference between the off-cell detection voltage V and the off-cell detection voltage V is lower than the threshold voltage of the target memory cell, so a current channel cannot be formed. DET is the channel open voltage V OPEN It is set lower than, but not limited to, the channel open voltage V OPEN Although it is higher than the off-cell detection voltage V DET and the channel open voltage V OPEN It is also possible for the difference between the threshold voltages to be made lower than the threshold voltage of an erased memory cell.

[0075] That is, according to the hard-off cell detection method of the present invention, when current leakage occurs in at least one of the memory cells sharing a channel, the voltage level of the channel increases even when a detection operation is performed on memory cells that do not experience current leakage, so the threshold voltage for forming a current channel of the hard-off cell increases. Therefore, when leakage occurs, the memory device 10 can determine that at least one of the memory cells sharing the channel is a hard-off cell.

[0076] FIG. 13 is a flowchart illustrating a method for determining a hard-off cell in a target cell string according to one embodiment.

[0077] In the present invention, a target cell string is connected to a plurality of word lines, and an off-cell detection voltage is applied through the plurality of word lines, thereby enabling the memory device 10 to determine whether a memory cell connected to each word line is a hard-off cell. Illustratively, the row decoder 12 may sequentially apply the off-cell detection voltage to the word lines connected to the target cell string, and the sensing amplifier 13 may determine whether the target memory cell is a hard-off cell based on the current level output from the target cell string.

[0078] The memory device 10, which has been instructed to perform the hard off-cell detection operation, may sequentially perform the hard off-cell detection operation, starting with the first word line connected to the target cell string. In step S110, the memory device 10 may apply an off-cell detection voltage to the target word line. When the memory device 10 receives the off-cell detection command signal, the voltage generator 15 may output an off-cell detection voltage, and the row decoder 12 may apply the off-cell detection voltage to the target word line based on the received row address.

[0079] In step S120, the memory device 10 may measure a current level output from a target cell string by applying an off-cell detection voltage to a target memory cell through a target word line. At this time, a channel open voltage is applied to the remaining word lines excluding the target word line, so that the channels of the memory cells connected to the remaining word lines are open and current can be conducted. Depending on whether the channels of the target memory cells to which the off-cell detection voltage is applied are open, the target cell string may output different current levels. For example, if the threshold voltage of the target memory cell is lower than the off-cell detection voltage, the channel of the target memory cell is open, and thus the cell string may output a high current level.

[0080] In step S130, the sensing amplifier 13 compares the current output from the target cell string with a predetermined reference (critical) current. The sensing amplifier 13 also functions as a comparator circuit that outputs different levels of current / voltage when it determines that the output current is higher than the reference current and when it determines that the output current is lower than or equal to the reference current.

[0081] If the sensing amplifier 13 determines that the output current is higher than the reference current, it may output a comparison result indicating a normally erased cell in step S140, and if the sensing amplifier 13 determines that the output current is lower than or equal to the reference current, it may output a comparison result indicating a hard-off cell in step S150. Illustratively, the sensing amplifier 13 may output a comparison result of a high voltage level, allowing the memory device 10 to determine that the target memory cell is a normally erased cell, or may output a comparison result of a low voltage level, allowing the memory device 10 to determine that the target memory cell is a hard-off cell.

[0082] When the memory device 10 or the memory controller 20 determines that the target memory cell is a hard-off cell, it counts the number of hard-off cells by accumulating them one by one, and repeats the hard-off cell detection operation for the next word line to count the number of hard-off cells in the target cell string.

[0083] FIG. 14 is a flowchart illustrating a method for determining a defective memory cell block according to one embodiment.

[0084] Referring to Figures 9 and 14, the memory controller 20 of the present invention can determine whether the memory cell block including the cell string is a defective memory cell block by comparing the reference number of off cells stored corresponding to each cell string with the number of hard off cells counted in step S20.

[0085] In step S310, the memory controller 20 may load a reference number of off-cells corresponding to a target cell string from an off-cell information storage block of the memory cell array 11. The off-cell information storage block may be a memory cell block storing off-cell information, and the off-cell information may be a data table storing the reference number of off-cells measured for each cell string of the memory cell block after the memory device 10 process, as shown in FIG. 15 (described below). After the process, hard off-cells may occur due to an off-string defect, in which the cell string is not connected to the substrate, rather than a defect caused by current leakage from a word line to a channel hole. However, this is relatively less critical to data writing or reading than a defect caused by current leakage to a channel hole. The off-cell information may be information in which the number of off-cells in a cell string caused by the off-string defect is stored as the reference number of off-cells.

[0086] In step S320, the memory controller 20 may compare the reference number of off cells corresponding to each cell string with the number of hard off cells counted in step S20. If no current leakage occurs in the channel holes, even if hard off cells are detected in the target cell string, the number of counted hard off cells may be equal to or less than the reference number of off cells.

[0087] Therefore, in step S330, if the number of hard-off cells in the target cell string is greater than the reference number of off cells, the memory controller 20 can determine that the entire memory cell block including the target cell string is a defective memory cell block.In step S340, if the number of hard-off cells is less than or equal to the reference number of off cells, the memory controller 20 can determine that the cell string is a normal cell string and count hard-off cells for the next cell string.

[0088] FIG. 15 is a table illustrating off-cell information stored in an off-cell information storage block, according to one embodiment.

[0089] According to an embodiment, the memory controller 20 may determine whether a target memory cell block including a target cell string is a defective memory cell block based on the reference number of off-cells stored in the off-cell information. Referring to FIG. 15 , the target cell string may be a set of cell strings that share a string selection line, and the memory device 10 may perform a hard off-cell detection operation on the target cell string by applying an open voltage to the string selection line.

[0090] When the address of a cell string for which hard-off cells are to be detected by the memory controller 20 or the memory device 10 is specified by the address of a string select line, the memory controller 20 may count hard-off cells for the target cell string. The memory controller 20 may count a reference number of off-cells corresponding to the address of the string select line based on the off-cell information. For example, when the memory controller 20 or the memory device 10 instructs hard-off cell detection for a cell string group connected to a third string select line of a second memory block, the memory device 10 may count hard-off cells for the target cell string. In this case, according to the embodiment of FIG. 15 , the off-cell information indicates that the reference number of off-cells for the cell string group connected to the third string select line of the second memory cell block is two. Therefore, the memory controller 20 may determine whether the number of counted hard-off cells is greater than two. If the memory controller 20 determines that the number of counted hard-off cells is greater than two, the second memory cell block may be treated as a defective memory cell block.

[0091] FIG. 16 is a flow chart illustrating the sequence of operations of memory controller 20 and memory device 10 according to one embodiment.

[0092] In step S1610, the memory controller 20 may generate an off-cell detection command when receiving a hard off-cell detection instruction from the host device or at predetermined intervals. The off-cell detection command is a signal for instructing the memory device 10 to perform a hard off-cell detection operation, and may be a code composed of a series of bits. In step S1620, the memory controller 20 may generate the off-cell detection command and then transmit the off-cell detection command to the memory device 10.

[0093] In step S1630, the memory device 10 may perform a hard off-cell detection operation by receiving the off-cell detection command. The memory device 10 may apply an off-cell detection voltage to memory cells of a target cell string, which is at least a portion of a target memory cell block, one by one, and determine whether each memory cell is a hard off cell.

[0094] In step S1640, the page buffer 14 of the memory device 10 may count the number of hard-off cells in the target cell string, and in step S1650, the memory device 10 may transmit the counted number of hard-off cells in the target cell string to the memory controller 20. The page buffer 14 of the memory device 10 may include multiple latches, and may increment and store the counting number in response to receiving information from the sensing amplifier 13 that a memory cell is a hard-off cell.

[0095] In step S1660, the memory controller 20 loads the off-cell number information and compares it with the number of hard off-cells, and in step S1670, the memory controller 20 can determine whether the memory cell block including the target cell string is a defective memory cell block based on the comparison result.

[0096] FIG. 17 is a flowchart illustrating the sequence of operations of the memory controller 20 and the memory device 10 according to another embodiment.

[0097] In the embodiment of Figure 16, the page buffer 14 of the memory device 10 can count the number of hard-off cells in the target cell string, but referring to Figure 17, the memory device 10 of the present invention can transmit hard-off cell information to the memory controller 20 every time it performs a hard-off cell detection operation. Steps S1710 to S1730 have been described above with reference to Figure 16, so detailed description thereof will be omitted.

[0098] In step S1740, the memory device 10 performs a hard-off cell detection operation on the target cell string and transmits hard-off cell information indicating whether the target memory cell is a hard-off cell to the memory controller 20. In step S1750, in response to receiving a signal indicating that the target memory cell is a hard-off cell, the memory controller 20 causes the off-cell counter 23 of the memory controller 20 to increment the number of hard-off cells by one.

[0099] In step S1760, the memory controller 20 may compare the number of counted hard-off cells with the reference number of off cells in response to receiving an end signal indicating that the hard-off cell detection operation has been performed for all memory cells of the target cell string.

[0100] In step S1770, the memory controller 20 can determine whether the memory cell block including the target cell string is a defective memory cell block based on the comparison result between the reference number of off cells and the number of hard off cells.

[0101] FIG. 18 is a diagram illustrating a memory device having a C2C (chip to chip) structure according to an embodiment.

[0102] 18, the memory device 400 may have a C2C structure. The C2C structure refers to fabricating an upper chip including a cell region CELL on a first wafer, fabricating a lower chip including a peripheral circuit region PERI on a second wafer different from the first wafer, and then connecting the upper chip and the lower chip together using a bonding method. For example, the bonding method refers to electrically connecting a bonding metal formed on a top metal layer of the upper chip to a bonding metal formed on a top metal layer of the lower chip. For example, if the bonding metal is formed of copper (Cu), the bonding method may be Cu-Cu bonding, and the bonding metal may also be formed of aluminum or tungsten.

[0103] Each of the peripheral circuit region PERI and the cell region CELL of the memory device 400 includes an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0104] The peripheral circuit region PERI includes a first substrate 210, an interlayer insulating layer 215, a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210, first metal layers 230a, 230b, and 230c connected to the plurality of circuit elements 220a, 220b, and 220c, respectively, and second metal layers 240a, 240b, and 240c formed on the first metal layers 230a, 230b, and 230c. In one embodiment, the first metal layers 230a, 230b, and 230c are formed of tungsten, which has a relatively high resistance, and the second metal layers 240a, 240b, and 240c are formed of copper, which has a relatively low resistance.

[0105] Although only the first metal layers 230a, 230b, and 230c and the second metal layers 240a, 240b, and 240c are shown and described herein, the present invention is not limited thereto, and at least one or more metal layers may be formed on the second metal layers 240a, 240b, and 240c. At least a portion of the one or more metal layers formed on the second metal layers 240a, 240b, and 240c may be formed of aluminum or the like, which has a lower resistance than copper, which forms the second metal layers 240a, 240b, and 240c.

[0106] The interlayer insulating layer 215 is disposed on the first substrate 210 to cover the plurality of circuit elements 220a, 220b, 220c, the first metal layers 230a, 230b, 230c, and the second metal layers 240a, 240b, 240c, and may include an insulating material such as silicon oxide or silicon nitride.

[0107] Lower bonding metals 271b and 272b are formed on the second metal layer 240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 271b and 272b in the peripheral circuit region PERI can be electrically connected to the upper bonding metals 371b and 372b in the cell region CELL by bonding. The lower bonding metals 271b and 272b and the upper bonding metals 371b and 372b may be formed of aluminum, copper, or tungsten.

[0108] The cell region CELL can provide at least one memory block. The cell region CELL includes a second substrate 310 and a common source line 320. A plurality of word lines 331 to 338 (collectively referred to as 330) are stacked on the second substrate 310 along a direction (Z-axis direction) perpendicular to the upper surface of the second substrate 310. A string select line and a ground select line are respectively arranged above and below the word lines 330, and a plurality of word lines 330 are arranged between the string select line and the ground select line.

[0109] In the bit line bonding region BLBA, the channel structure CH extends in a direction perpendicular to the top surface of the second substrate 310 and may penetrate the word lines 330, the string select lines, and the ground select lines. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c may also serve as a bit line contact, and the second metal layer 360c may also serve as a bit line. In one embodiment, the bit line 360c may extend along a first direction (Y-axis direction) parallel to the top surface of the second substrate 310.

[0110] 18, a region in which the channel structure CH and the bit line 360c are disposed may be defined as a bit line bonding region BLBA. The bit line 360c may be electrically connected to a circuit element 220c that provides a page buffer 393 in the peripheral circuit region PERI in the bit line bonding region BLBA. For example, the bit line 360c may be connected to upper bonding metals 371c and 372c in the peripheral circuit region PERI, and the upper bonding metals 371c and 372c may be connected to lower bonding metals 271c and 272c that are connected to the circuit element 220c of the page buffer 393.

[0111] In the word line bonding region WLBA, the word lines 330 extend in a second direction (X-axis direction) parallel to the top surface of the second substrate 310 and may be connected to a plurality of cell contact plugs 341 through 347 (collectively, 340). The word lines 330 and the cell contact plugs 340 may be connected to each other through pads formed by extending at least some of the word lines 330 to different lengths in the second direction. A first metal layer 350b and a second metal layer 360b may be sequentially connected to the top of the cell contact plug 340 connected to the word line 330. In the word line bonding region WLBA, the cell contact plug 340 may be connected to the peripheral circuit region PERI through upper bonding metals 371b and 372b of the cell region CELL and lower bonding metals 271b and 272b of the peripheral circuit region PERI.

[0112] The cell contact plug 340 may be electrically connected to a circuit element 220b that provides the row decoder 394 in the peripheral circuit region PERI. In one embodiment, the operating voltage of the circuit element 220b that provides the row decoder 394 may be different from the operating voltage of the circuit element 220c that provides the page buffer 393. For example, the operating voltage of the circuit element 220c that provides the page buffer 393 may be higher than the operating voltage of the circuit element 220b that provides the row decoder 394.

[0113] A common source line contact plug 380 is disposed in the external pad bonding region PA. The common source line contact plug 380 is formed of a conductive material such as metal, metal compound, or polysilicon and can be electrically connected to the common source line 320. A first metal layer 350a and a second metal layer 360a are sequentially stacked on the common source line contact plug 380. For example, the region where the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a are disposed may be defined as the external pad bonding region PA.

[0114] 18, a lower insulating film 201 is formed under a first substrate 210 to cover the lower surface of the first substrate 210, and a first I / O pad 205 is formed on the lower insulating film 201. The first I / O pad 205 is connected to at least one of a plurality of circuit elements 220a, 220b, and 220c disposed in the peripheral circuit region PERI via a first I / O contact plug 203 and can be separated from the first substrate 210 by the lower insulating film 201. In addition, a side insulating film is disposed between the first I / O contact plug 203 and the first substrate 210, thereby electrically isolating the first I / O contact plug 203 from the first substrate 210.

[0115] 18, an upper insulating film 301 covering the upper surface of the second substrate 310 is formed on the upper surface of the second substrate 310, and a second I / O pad 305 is disposed on the upper insulating film 301. The second I / O pad 305 can be connected to at least one of the plurality of circuit elements 220a, 220b, and 220c disposed in the peripheral circuit region PERI via a second I / O contact plug 303.

[0116] According to an embodiment, the second substrate 310 and the common source line 320 may not be disposed in the region where the second I / O contact plug 303 is disposed. Also, the second I / O pad 305 may not overlap with the word line 330 in the third direction (Z-axis direction). Referring to FIG. 18, the second I / O contact plug 303 is separated from the second substrate 310 in a direction parallel to the top surface of the second substrate 310 and can be connected to the second I / O pad 305 by penetrating the interlayer insulating layer 315 of the cell region CELL.

[0117] Depending on the embodiment, the first I / O pad 205 and the second I / O pad 305 may be selectively formed. For example, the memory device 400 may include only the first I / O pad 205 disposed on the top of the first substrate 210, or may include only the second I / O pad 305 disposed on the top of the second substrate 310. Alternatively, the memory device 400 may include both the first I / O pad 205 and the second I / O pad 305.

[0118] In the external pad bonding area PA and bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, respectively, the metal pattern of the uppermost metal layer exists as a dummy pattern, or the uppermost metal layer is empty.

[0119] In the memory device 400, a lower metal pattern 273a having the same shape as the upper metal pattern 372a of the cell region CELL may be formed in the uppermost metal layer of the peripheral circuit region PERI in the external pad bonding region PA, corresponding to the upper metal pattern 372a formed in the uppermost metal layer of the cell region CELL. The lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a separate contact in the peripheral circuit region PERI. Similarly, in the external pad bonding region PA, an upper metal pattern having the same shape as the lower metal pattern of the peripheral circuit region PERI may be formed in the uppermost metal layer of the cell region CELL, corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI.

[0120] Lower bonding metals 271b and 272b are formed on the second metal layer 240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 271b and 272b in the peripheral circuit region PERI can be electrically connected to the upper bonding metals 371b and 372b in the cell region CELL by bonding.

[0121] In addition, in the bit line bonding region BLBA, an upper metal pattern 392 having the same shape as the lower metal pattern 252 in the peripheral circuit region PERI may be formed in the uppermost metal layer of the cell region CELL, corresponding to the lower metal pattern 252 formed in the uppermost metal layer of the peripheral circuit region PERI. A contact may not be formed on the upper metal pattern 392 formed in the uppermost metal layer of the cell region CELL.

[0122] As mentioned above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used merely to explain the technical idea of ​​the present invention and are not used to limit the meaning or the scope of the present invention as described in the claims. Therefore, a person skilled in the art will understand that various modifications and equivalent embodiments are possible. Therefore, the true technical scope of protection of the present invention should be determined by the technical idea of ​​the claims. [Industrial Applicability]

[0123] The present invention is applicable to, for example, technical fields related to memory devices. [Explanation of symbols]

[0124] 10 Memory Device 11 Memory Cell Array 12 Row Decoder 13 Sensing amplifier 14 page buffer 15 Voltage generation unit 16 Control Logic 20 Memory Controller 21 Command Generation Unit 22 Defective memory cell block determination unit 23 Off-cell counter ADDR Address BL Bit Line CMD command CNT Counting Information CTRL control signal CTRL_vol voltage control signal DATA GSL Ground Select Line SSL String Selection Line V DET Off-cell detection voltage V OPEN Channel Open Voltage V READ Read Reference Voltage WL Word Line X-ADDR Row address

Claims

1. 1. A method for detecting defective memory cell blocks in a non-volatile memory system, comprising: After the erase operation is performed, performing a read operation on at least some memory cells included in the target memory cell block based on an off-cell detection voltage different from a read reference voltage that distinguishes off-cells to which no data is written and on-cells to which data is written; counting the number of hard off-cells among the memory cells based on the result of the read operation; determining whether the target memory cell block is a defective memory cell block based on the number of hard-off cells counted; The hard-off cell has a threshold voltage higher than the off-cell detection voltage due to leakage between a word line and a channel hole of a cell string.

2. The step of performing a read operation includes:

2. The method for detecting a defective memory cell block according to claim 1, further comprising setting the off-cell detection voltage to a value between a threshold voltage level of an erased memory cell and a threshold voltage level of a hard-off cell.

3. The step of performing a read operation includes: applying the off-cell detection voltage to each of a plurality of word lines connected to a target memory cell block; 3. The method of claim 1, further comprising: applying the off-cell detection voltage to each of the word lines to measure a current output from a cell string connected to a target memory cell.

4. The step of counting the number of hard-off cells includes:

4. The method of claim 3, further comprising the step of determining whether the memory cell is a hard-off cell based on the output current.

5. The step of determining whether the cell is a hard-off cell includes:

5. The method of claim 4, further comprising determining a memory cell connected to a word line to which the off-cell detection voltage is applied as the hard off cell in response to the output current being less than a reference current.

6. The step of determining whether the target memory cell block is a defective memory cell block includes: comparing the counted number of hard off cells with a reference number of off cells; 2. The method for detecting a defective memory cell block according to claim 1, further comprising: determining whether or not the target memory cell block is a defective memory cell block based on a result of the comparison.

7. The reference number of off-cells is 7. The method of claim 6, wherein the number of initially OFF cells is the number of memory cells corresponding to each string selection line of the target memory cell block.

8. The step of determining whether the target memory cell block is a defective memory cell block based on the result of the comparison includes:

8. The method for detecting a defective memory cell block according to claim 6, further comprising determining the target memory cell block as a defective memory cell block in response to the number of counted hard off cells exceeding the reference number of off cells.

9. a memory device including a plurality of blocks of memory cells; a memory controller that receives data from the memory device by sending command signals to the memory device; The memory controller a command generator for outputting an off-cell detection command signal to the memory device after the erase operation is performed, the off-cell detection command signal instructing the memory device to perform a hard off-cell detection operation; a defective memory cell block determination unit that outputs a signal indicating whether the target memory cell block is a defective memory cell block based on the number of hard off cells counted from at least some memory cells included in the target memory cell block in response to the off-cell detection command signal, The memory device is In response to receiving the off-cell detection command signal, performing a read operation on at least some of the memory cells based on an off-cell detection voltage that is different from a read reference voltage that distinguishes off-cells to which no data is written and on-cells to which data is written; The hard-off cell has a threshold voltage higher than the off-cell detection voltage due to leakage between a word line and a channel hole of a cell string.

10. The memory device is 10. The nonvolatile memory system of claim 9, further comprising a voltage generator configured to output a value between a threshold voltage level of an erased memory cell and a threshold voltage level of a hard off cell as the off-cell detection voltage in response to receiving the off-cell detection command signal.

11. The memory device is a memory cell array in which a plurality of word lines are connected to memory cells of a target cell string, thereby applying a voltage to the memory cells; a row decoder that applies the off-cell detection voltage to a target memory cell through a target word line among the plurality of word lines; 11. The nonvolatile memory system of claim 9, further comprising: a sensing amplifier configured to receive a current output from the target cell string by applying the off-cell detection voltage through the target word line.

12. The sensing amplifier 12. The nonvolatile memory system according to claim 11, wherein a signal indicating whether the target memory cell is a hard-off cell is output based on the output current.

13. The sensing amplifier 13. The nonvolatile memory system of claim 12, wherein the nonvolatile memory system outputs a signal indicating that the target memory cell is a hard-off cell in response to the output current being less than a reference current.

14. The memory device is 14. The nonvolatile memory system of claim 9, further comprising a page buffer that counts the number of hard-off cells among the at least some of the memory cells based on the result of the read operation.

15. The memory controller 14. The nonvolatile memory system of claim 9, further comprising an off-cell counter that receives a result of a read operation and counts the number of hard-off cells among at least some of the memory cells based on the result of the read operation.

16. The memory device is an off-cell information storage block for storing a block address, an SSL (string select line) address, and information on a reference number of off-cells corresponding to the block address and the SSL address; The defective memory cell block determination unit 16. The nonvolatile memory system of claim 9, wherein the system determines whether the memory cell block is a defective memory cell block by comparing the reference number of off-cells received from the off-cell information storage block with the number of hard off-cells.

17. The off-cell information storage block includes:

17. The nonvolatile memory system of claim 16, wherein an initial number of off-cells corresponding to each string selection line of the memory cell block is stored in association with the block address and the SSL address.

18. The defective memory cell block determination unit 18. The nonvolatile memory system of claim 16, wherein the target memory cell block is determined to be a defective memory cell block in response to the number of counted hard off cells being greater than the reference number of off cells.

19. a command generator for outputting an off-cell detection command signal to the memory device after the erase operation is performed, the off-cell detection command signal instructing the memory device to perform a hard off-cell detection operation; a defective memory cell block determination unit that outputs a signal indicating whether a memory cell block including a target cell string is a defective memory cell block based on the number of hard-off cells among at least some of the memory cells included in the target memory cell block in response to the off-cell detection command signal, The number of the hard-off cells is counted based on a read operation performed by the memory device on at least some of the memory cells using an off-cell detection voltage different from a read reference voltage, and the read reference voltage is used to distinguish off-cells to which no data is written from on-cells to which data is written; The hard-off cell has a threshold voltage higher than the off-cell detection voltage due to leakage between a word line and a channel hole of a cell string.

20. The defective memory cell block determination unit 20. The nonvolatile memory controller of claim 19, wherein the target memory cell block is determined to be a defective memory cell block by comparing the number of hard off-cells with a reference number of off-cells received from an off-cell information storage block storing a block address, an SSL address, and information on the reference number of off-cells corresponding to the block address and the SSL address.

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