MEMORY CONTROLLER, METHOD FOR CONTROLLING MEMORY CONTROLLER, AND PROGRAM - Patent application

Abstract

To inhibit a reduction in memory use efficiency by selecting an appropriate refresh method from among a plurality of DRAM refresh methods.SOLUTION: In a memory controller, at least one of a plurality of refresh methods varying in a refresh target area of DRAM is a refresh method of refreshing an entire area of the DRAM, and a specific event that disables access to the entire area of the DRAM occurs in a cycle longer than a refresh execution cycle using the refresh method of refreshing the entire area of the DRAM. The memory controller includes selection means for selecting one refresh method from among the plurality of refresh methods, depending on whether or not the specific event that disables access to the entire area of the DRAM occurs in a refresh execution period.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a memory controller, a control method for a memory controller, and a program. [Background technology]

[0002] In order to keep up with the increasing speed of DRAM in recent years, it has become important to adjust and calibrate the timing between the clock signal and the command signal, and between the data strobe signal and the data signal, in order to communicate correctly with the DRAM. If a timing discrepancy occurs between each signal due to fluctuations in temperature or voltage, it will be impossible to communicate correctly with the DRAM. For this reason, memory access such as reading and writing to the DRAM is periodically stopped to adjust the timing between each signal and perform calibration, but since memory access is not possible during this period, memory utilization efficiency decreases.

[0003] In response to this, a method has been devised to prevent a decrease in memory utilization efficiency by performing timing adjustment and calibration during the refresh execution period when memory access is also disabled.

[0004] Patent document 1 describes a memory controller that controls at least one delay amount to approach a reference delay amount during a period corresponding to the difference between the first BL and the second BL that occurs when the burst length (BL) of memory data is switched from the first BL to the second BL.

[0005] Patent Document 2 describes a semiconductor device having a data output buffer that writes data to a memory device, and a data input buffer that reads data from the memory device and is connected to the data output buffer by a first loopback path. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-8112 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-35229 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in recent years, in order to further improve memory utilization efficiency, there has been a trend toward using per-bank refresh, which refreshes each of the multiple areas that make up the DRAM, rather than all-bank refresh, which refreshes the entire DRAM. With per-bank refresh, memory access is possible except for the area being refreshed, so the refresh does not prevent memory access to the entire DRAM. This makes it difficult to perform timing adjustments and calibration during the refresh execution period, as was previously the case.

[0008] An object of the present disclosure is to suppress a decrease in memory utilization efficiency by selecting an appropriate refresh method from among a plurality of refresh methods for DRAM. [Means for solving the problem]

[0009] The memory controller is configured to use a plurality of refresh methods for different refresh target areas of the DRAM, and a refresh method for refreshing the entire area of ​​the DRAM. and a refresh method for refreshing a partial area of ​​the DRAM. a memory controller in which a specific event that makes it impossible to access the entire area of ​​the DRAM occurs in a period longer than a period in which the entire area of ​​the DRAM is refreshed using a refresh method that refreshes the entire area of ​​the DRAM, and the memory controller has a selection means for selecting one of the plurality of refresh methods depending on whether or not a specific event that makes it impossible to access the entire area of ​​the DRAM occurs during the refresh execution period. The selection means selects a refresh method for refreshing the entire area of ​​the DRAM when a specific event that makes it impossible to access the entire area of ​​the DRAM is expected to occur during the refresh execution period, and selects a refresh method for refreshing a part of the area of ​​the DRAM when a specific event that makes it impossible to access the entire area of ​​the DRAM is not expected to occur during the refresh execution period. do. [Effects of the Invention]

[0010] According to the present disclosure, by selecting an appropriate refresh method from among a plurality of refresh methods for DRAM, it is possible to suppress a decrease in memory utilization efficiency. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 2 is a diagram illustrating an example of the configuration of a memory controller. [Figure 2] FIG. 2 illustrates an example of the configuration of a DRAM command generation unit; [Figure 3] 10A and 10B are waveform diagrams showing the behavior of a DRAM command generation unit. [Figure 4] FIG. 2 is a diagram illustrating an example of the configuration of a memory controller. [Figure 5] FIG. 2 illustrates an example of the configuration of a DRAM command generation unit; DETAILED DESCRIPTION OF THE INVENTION

[0012] (First embodiment) FIG. 1 is a diagram illustrating an example of the configuration of a memory controller 100 according to the first embodiment. The memory controller 100 is connected to a DRAM 110 and a bus master 120. The bus master 120 transmits a memory access request, including address information and write data, to the memory controller 100. The memory controller 100 generates a DRAM command based on the memory access request received from the bus master 120 and transmits the DRAM command to the DRAM 110. The memory controller 100 also transfers data to the DRAM 110 based on the transmitted DRAM command. The DRAM 110 has multiple areas (multiple banks) and is capable of performing an all-bank refresh, which refreshes all areas (all banks) at once, and a per-bank refresh, which refreshes any area (any bank). The DRAM 110 can refresh all of the remaining banks that were not refreshed by the per-bank refresh by performing the per-bank refresh multiple times while refreshing all banks.

[0013] The DRAM 110 has a memory element including a capacitor and a transistor, and stores data in the memory element by representing a state in which a charge is stored in the memory element as "1" and a state in which no charge is stored in the memory element as "0." Since the amount of charge in the memory element of the DRAM 110 decreases over time, periodic refresh (rewriting of data) is required to prevent data loss.

[0014] The memory controller 100 includes a DRAM command generation unit 101 , a refresh timing generation unit 102 , a timing adjustment instruction unit 103 , and a timing adjustment unit 104 .

[0015] The DRAM command generation unit 101 generates a read / write command to be sent to the DRAM 110 based on a memory access request received from the bus master 120. The DRAM command generation unit 101 also generates a refresh command to refresh the DRAM 110.

[0016] The refresh timing generation unit 102 generates timing for executing a per-bank refresh. The refresh timing generation unit 102 measures the execution period of the per-bank refresh requested by the DRAM 110, and transmits refresh timing to the DRAM command generation unit 101 and the timing adjustment instruction unit 103 every time the execution period is measured.

[0017] The timing adjustment instruction unit 103 generates timings at which the timing adjustment unit 104 performs timing adjustment and calibration. In this embodiment, it is assumed that the timing adjustment and calibration must be performed at a cycle that is an integer multiple (N times) of the execution cycle of per-bank refresh. The timing adjustment instruction unit 103 transmits a timing adjustment instruction to the timing adjustment unit 104 every time it receives N refresh timings from the refresh timing generation unit 102.

[0018] The timing adjustment unit 104 receives a timing adjustment instruction from the timing adjustment instruction unit 103. In response, the timing adjustment unit 104 performs timing adjustment and calibration between the clock signal and the command signal, and between the data strobe signal and the data signal, so as to enable correct communication with the DRAM 110. The timing adjustment unit 104 transmits the clock signal and the command signal to the DRAM 110. The timing adjustment unit 104 also transmits and receives the data strobe signal and the data signal to and from the DRAM 110.

[0019] The data strobe signal is a signal that indicates the timing to read or write data in response to a read / write command.

[0020] The DRAM command generation unit 101 receives refresh timings from the refresh timing generation unit 102, and if a refresh command needs to be issued, generates either a per-bank refresh command or an all-bank refresh command. When the DRAM command generation unit 101 receives N refresh timings, that is, when it receives refresh timings for which a timing adjustment instruction is to be generated, it generates an all-bank refresh command; otherwise, it generates a per-bank refresh command.

[0021] 2 is a diagram showing an example of the configuration of the DRAM command generation unit 101 according to the first embodiment. The DRAM command generation unit 101 includes a read / write command generation unit 1011, a refresh timing management unit 1012, a refresh command generation unit 1013, and a command selection unit 1014.

[0022] The read / write command generator 1011 generates a read / write command to be sent to the DRAM 110 based on a memory access request received from the bus master 120 .

[0023] The refresh timing management unit 1012 has a timing adjustment detection counter and a per-bank refresh control counter. The timing adjustment detection counter is a counter for detecting whether timing adjustment is performed at the received refresh timing. The timing adjustment detection counter has an initial value of 0, counts up when a refresh timing is received, and is cleared to 0 when N refresh timings are received.

[0024] The per-bank refresh control counter is a counter for controlling the issuance of per-bank refresh commands. The per-bank refresh control counter has an initial value of 0, counts up when a refresh timing is received, and is cleared to 0 when M refresh timings are received. M is a value calculated by (the total number of banks in the DRAM 110 divided by the number of banks to be refreshed by one per-bank refresh command).

[0025] A case will be described in which the refresh timing management unit 1012 receives refresh timing when the value of the timing adjustment detection counter is smaller than (N-1). In this case, the refresh timing management unit 1012 transmits a refresh command generation instruction to the refresh command generation unit 1013 to instruct the generation of a per-bank refresh command. In this embodiment, the target bank of the per-bank refresh command is specified using the value of the per-bank refresh control counter, but it may also be specified using a value calculated in some way based on the value of the per-bank refresh control counter.

[0026] A case will be described in which the refresh timing management unit 1012 receives refresh timing when the value of the timing adjustment detection counter is equal to (N-1). In this case, the refresh timing management unit 1012 transmits a refresh command generation instruction to the refresh command generation unit 1013 to instruct the refresh command generation unit 1013 to generate an all-bank refresh command.

[0027] At this time, if the per-bank refresh control counter is smaller than (M-1), refresh timing management unit 1012 asserts a refresh command generation instruction mask for masking a refresh command generation instruction. While the refresh command generation instruction mask is asserted, refresh timing management unit 1012 does not send a refresh command generation instruction to refresh command generation unit 1013. When refresh timing management unit 1012 receives a refresh timing signal while the per-bank refresh control counter has the same value as (M-1), refresh timing management unit 1012 deasserts the refresh command generation instruction mask. While the refresh command generation instruction mask is deasserted, refresh timing management unit 1012 can send a refresh command generation instruction to refresh command generation unit 1013.

[0028] The refresh command generation unit 1013 generates a per-bank refresh command or an all-bank refresh command based on a refresh command generation instruction from the refresh timing management unit 1012 .

[0029] The command selection unit 1014 selects the read / write command generated by the read / write command generation unit 1011 or the refresh command generated by the refresh command generation unit 1013. Then, the command selection unit 1014 transmits the selected read / write command or refresh command to the DRAM 110 via the timing adjustment unit 104.

[0030] 3 is a waveform diagram showing the behavior of the DRAM command generation unit 101 according to the first embodiment. In FIG. 3, it is assumed that timing adjustment must be performed at a cycle 12 times (N=12) the execution cycle of the per-bank refresh. The total number of banks in the DRAM 110 is eight, and the number of banks to be refreshed by one per-bank refresh command is one. Therefore, M=8. A control method for the memory controller 100 will be described below.

[0031] At time T0, the refresh timing management unit 1012 does not receive any refresh timing.

[0032] At time T1, refresh timing management unit 1012 receives the refresh timing. At the time of reception, the value of the timing adjustment detection counter is 10, not (N-1), so timing adjustment is not performed for the received refresh timing. Therefore, refresh timing management unit 1012 transmits a refresh command generation instruction to refresh command generation unit 1013 to instruct the generation of a per-bank refresh command. Upon receiving the refresh command generation instruction to instruct the generation of a per-bank refresh command, refresh command generation unit 1013 generates the per-bank refresh command.

[0033] At times T2 to T4, the refresh timing management section 1012 does not receive any refresh timing.

[0034] At time T5, refresh timing management unit 1012 receives refresh timing. The value of the timing adjustment detection counter at the time of reception is 11, which is (N-1), so timing adjustment is performed based on the received refresh timing. Therefore, refresh timing management unit 1012 transmits a refresh command generation instruction to refresh command generation unit 1013 to instruct generation of an all-bank refresh command. Upon receiving the refresh command generation instruction to instruct generation of an all-bank refresh command, refresh command generation unit 1013 generates the all-bank refresh command. Furthermore, since the value of the per-bank refresh control counter at the time of reception is 3, which is not (M-1), refresh timing management unit 1012 asserts the refresh command generation instruction mask.

[0035] Between times T6 and T8, the refresh timing management section 1012 does not receive any refresh timing.

[0036] At time T9, refresh timing manager 1012 receives the refresh timing, but does not send a refresh command generation instruction to refresh command generator 1013 because the refresh command generation instruction mask is asserted.

[0037] Between times T10 and T12, the refresh timing management section 1012 does not receive any refresh timing.

[0038] At time T13, refresh timing manager 1012 receives the refresh timing, but does not send a refresh command generation instruction to refresh command generator 1013 because the refresh command generation instruction mask is asserted.

[0039] Between times T14 and T16, the refresh timing management section 1012 does not receive any refresh timing.

[0040] At time T17, refresh timing manager 1012 receives the refresh timing, but does not send a refresh command generation instruction to refresh command generator 1013 because the refresh command generation instruction mask is asserted.

[0041] Between times T18 and T20, the refresh timing management section 1012 does not receive any refresh timing.

[0042] At time T21, refresh timing management unit 1012 receives the refresh timing, but because the refresh command generation instruction mask is asserted, does not transmit a refresh command generation instruction to refresh command generation unit 1013. At the time of reception, the value of the per bank refresh control counter is 7, which is (M-1), so refresh timing management unit 1012 deasserts the refresh command generation instruction mask upon receiving the refresh timing.

[0043] Between times T22 and T24, the refresh timing management section 1012 does not receive any refresh timing.

[0044] At time T25, refresh timing management unit 1012 receives the refresh timing. At the time of reception, the value of the timing adjustment detection counter is 4, not (N-1), so timing adjustment is not performed for the received refresh timing. Therefore, refresh timing management unit 1012 transmits a refresh command generation instruction to refresh command generation unit 1013 to instruct the generation of a per-bank refresh command. Upon receiving the refresh command generation instruction to instruct the generation of a per-bank refresh command, refresh command generation unit 1013 generates the per-bank refresh command.

[0045] Between times T26 and T28, the refresh timing management section 1012 does not receive any refresh timing.

[0046] In this embodiment, the timing adjustment instruction unit 103 generates timings for executing timing adjustment and calibration. However, the refresh timing management unit 1012 may transmit a timing adjustment instruction to the timing adjustment unit 104 every time it receives N refresh timings from the refresh timing generation unit 102.

[0047] As described above, the refresh timing generation unit 102 generates refresh timings at a cycle four times the cycle of the clock signal. The timing adjustment instruction unit 103 transmits a timing adjustment instruction to the timing adjustment unit 104 every time it receives N (12) refresh timings from the refresh timing generation unit 102. When the timing adjustment instruction is received from the timing adjustment instruction unit 103, the timing adjustment unit 104 performs timing adjustment and calibration between the clock signal and the command signal, and between the data strobe signal and the data signal. The timing adjustment and calibration must be performed periodically to accommodate temperature and voltage changes. The execution cycle of the timing adjustment and calibration is N (12) times the refresh timing cycle.

[0048] When the refresh timing management unit 1012 receives the refresh timing, it counts up the timing adjustment detection counter and the per-bank refresh control counter. If the value of the timing adjustment detection counter is (N-1), it is the timing to perform timing adjustment and calibration. If the value of the timing adjustment detection counter is not (N-1), it is the timing to not perform timing adjustment and calibration.

[0049] During the period when the timing adjustment unit 104 is performing timing adjustment and calibration, the memory controller 100 is unable to access the DRAM 110.

[0050] Since the all-bank refresh refreshes all banks, the memory controller 100 does not access the DRAM 110 while the DRAM 110 is executing the all-bank refresh. Therefore, while the DRAM 110 is executing the all-bank refresh, the timing adjustment unit 104 can perform timing adjustment and calibration.

[0051] In contrast, the per-bank refresh refreshes some of the banks, so that while the DRAM 110 is performing the per-bank refresh, the memory controller 100 can access banks that are not being refreshed in the DRAM 110. Therefore, while the DRAM 110 is performing the per-bank refresh, the timing adjustment unit 104 cannot perform timing adjustment and calibration.

[0052] When the refresh timing management unit 1012 receives the refresh timing, if the value of the timing adjustment detection counter is (N-1), timing adjustment and calibration are performed. In this case, the refresh timing management unit 1012 transmits a refresh command generation instruction to the refresh command generation unit 1013 to instruct the generation of an all-bank refresh command.

[0053] When refresh timing management unit 1012 receives refresh timing, if the value of the timing adjustment detection counter is not (N-1), timing adjustment and calibration are not performed. In this case, refresh timing management unit 1012 transmits a refresh command generation instruction to refresh command generation unit 1013 to instruct generation of a per-bank refresh command according to the value of the per-bank refresh control counter.

[0054] The execution period of an all-bank refresh is longer than the execution period of a per-bank refresh. During the execution period of an all-bank refresh, the memory controller 100 cannot access the DRAM 110 for a long period of time. Therefore, after the all-bank refresh, the refresh timing management unit 1012 asserts a refresh command generation instruction mask to ensure a certain period during which the DRAM 110 is accessible. During the period during which the refresh command generation instruction mask is asserted, the refresh timing management unit 1012 does not send a refresh command generation instruction to the refresh command generation unit 1013 even if it receives refresh timing. As a result, a per-bank refresh is not performed during this period, and the memory controller 100 can ensure a certain period during which the DRAM 110 is accessible after the all-bank refresh.

[0055] When refresh timing management unit 1012 receives a refresh timing signal and the value of the timing adjustment detection counter is not (N-1), refresh timing management unit 1012 transmits a refresh command generation instruction in accordance with the refresh command generation instruction mask. Specifically, while the refresh command generation instruction mask is not asserted, refresh timing management unit 1012 transmits a refresh command generation instruction to instruct generation of a per bank refresh command to refresh command generation unit 1013. Furthermore, while the refresh command generation instruction mask is not asserted, refresh timing management unit 1012 does not transmit a refresh command generation instruction to refresh command generation unit 1013.

[0056] According to this embodiment, the memory controller 100 generates a refresh command for an all-bank refresh or a per-bank refresh depending on whether it is the timing for timing adjustment and calibration. Since the timing adjustment and calibration are performed during the execution of the all-bank refresh, it is possible to suppress a decrease in the utilization efficiency of the DRAM 110. Furthermore, since the timing adjustment and calibration are not performed during the execution of the per-bank refresh, it is possible to suppress a decrease in the utilization efficiency of the DRAM 110. Furthermore, since a refresh command generation instruction is not transmitted during the period in which the refresh command generation instruction mask is asserted after the all-bank refresh, it is possible to improve the utilization efficiency of the DRAM 110.

[0057] (Second embodiment) 4 is a diagram showing an example of the configuration of a memory controller 100 according to the second embodiment. The second embodiment differs from the DRAM command generation unit 101 according to the first embodiment in a different form, and is also an embodiment that can handle cases where the execution period of timing adjustment and calibration is not an integer multiple of the execution period of per-bank refresh. The following describes the differences between the second embodiment and the first embodiment.

[0058] The memory controller 100 in FIG. 4 is obtained by removing the refresh timing generation unit 102 and timing adjustment instruction unit 103 from the memory controller 100 in FIG. 1, and instead includes a DRAM command generation unit 101 and a timing adjustment unit 104.

[0059] The DRAM command generation unit 101 measures the execution period of a per-bank refresh and the execution period of a timing adjustment. When the execution timing of a per-bank refresh arrives, the DRAM command generation unit 101 determines whether or not an execution timing of a timing adjustment will occur between now and the execution timing of the next per-bank refresh. If the DRAM command generation unit 101 determines that an execution timing of a timing adjustment will occur, it generates an all-bank refresh command, and if it determines that an execution timing of a timing adjustment will not occur, it generates a per-bank refresh command. If the DRAM command generation unit 101 generates an all-bank refresh command, it transmits a timing adjustment instruction to the timing adjustment unit 104.

[0060] The timing adjustment unit 104 receives a timing adjustment instruction from the DRAM command generation unit 101. In response, the timing adjustment unit 104 performs timing adjustment and calibration between the clock signal and the command signal, and between the data strobe signal and the data signal, so as to enable correct communication with the DRAM 110.

[0061] 5 is a diagram showing an example of the configuration of the DRAM command generation unit 101 according to the second embodiment. The DRAM command generation unit 101 includes a read / write command generation unit 1011, a refresh timing management unit 1012, a refresh command generation unit 1013, and a command selection unit 1014. The DRAM command generation unit 101 further includes a refresh execution period measurement unit 1015 and a timing adjustment execution period measurement unit 1016. The read / write command generation unit 1011, the refresh command generation unit 1013, and the command selection unit 1014 are the same as those in the first embodiment.

[0062] The refresh execution cycle measurement unit 1015 has a countdown timer that measures the execution cycle of per-bank refresh. The refresh execution cycle measurement unit 1015 has an initial value of the timer that is the execution cycle of per-bank refresh, and outputs the current timer value to the refresh timing management unit 1012. When the timer value reaches 0, the refresh execution cycle measurement unit 1015 sets the timer to the execution cycle of per-bank refresh and starts measurement again.

[0063] The timing adjustment execution period measurement unit 1016 has a countdown timer that measures the execution period of timing adjustment. The initial value of the timer in the timing adjustment execution period measurement unit 1016 is the execution period of timing adjustment, and outputs the current timer value to the refresh timing management unit 1012. When the timer value reaches 0, the timing adjustment execution period measurement unit 1016 sets the execution period of timing adjustment in the timer and starts measurement again. Also, when the refresh timing management unit 1012 sends a timing adjustment instruction, the timing adjustment execution period measurement unit 1016 sets the timing execution period in the timer and starts measurement again.

[0064] The refresh timing management unit 1012 has a per-bank refresh control counter. The per-bank refresh control counter is a counter for controlling the issuance of per-bank refresh commands. The per-bank refresh control counter has an initial value of 0 and is counted up each time the refresh execution cycle measurement unit 1015 measures a refresh execution cycle. The per-bank refresh control counter is cleared to 0 when the refresh execution cycle measurement unit 1015 measures M refresh execution cycles. M is a value calculated by (the total number of banks in the DRAM 110 divided by the number of banks to be refreshed by one per-bank refresh command).

[0065] When the timer value of refresh execution cycle measurement unit 1015 reaches 0, refresh timing management unit 1012 determines whether the timer value of timing adjustment execution cycle measurement unit 1016 is equal to or greater than the per-bank refresh execution cycle. This allows refresh timing management unit 1012 to determine whether timing adjustment needs to be performed between the current and next per-bank refresh executions.

[0066] First, a case will be described in which the timer value of the timing adjustment execution cycle measurement unit 1016 is equal to or greater than the per-bank refresh execution cycle. In this case, the refresh timing management unit 1012 sends a refresh command generation instruction to the refresh command generation unit 1013 to instruct it to generate a per-bank refresh command.

[0067] Next, a case will be described where the timer value of timing adjustment execution cycle measurement unit 1016 is less than the per-bank refresh execution cycle. In this case, refresh timing management unit 1012 sends a refresh command generation instruction to instruct generation of an all-bank refresh command to refresh command generation unit 1013. At this time, if the value of the per-bank refresh control counter is smaller than (M-1), refresh timing management unit 1012 asserts a refresh command generation instruction mask that masks the refresh command generation instruction.

[0068] While the refresh command generation instruction mask is asserted, the refresh timing management unit 1012 does not send a refresh command generation instruction to the refresh command generation unit 1013. The refresh command generation instruction mask is deasserted when the timer value of the refresh execution cycle measurement unit 1015 becomes 0 while the per-bank refresh control counter has the same value as (M-1). While the refresh command generation instruction mask is not asserted, the refresh timing management unit 1012 can send a refresh command generation instruction to the refresh command generation unit 1013. Furthermore, when the refresh timing management unit 1012 instructs to generate an all-bank refresh command, it sends a timing adjustment instruction to the timing adjustment unit 104.

[0069] According to this embodiment, the memory controller 100 can also handle cases where the execution period of timing adjustment and calibration is not an integral multiple of the execution period of per-bank refresh. This embodiment can achieve the same effects as the first embodiment.

[0070] In the first and second embodiments, the timing adjustment unit 104 is described as performing timing adjustment between the data strobe signal and the data signal, but it may also perform timing adjustment between the data clock signal output by the memory controller 100 and the data signal.

[0071] As described above, the memory controller 100 can select from a plurality of refresh methods for different areas of the DRAM 110 to be refreshed. The plurality of refresh methods include all-bank refresh and per-bank refresh. The all-bank refresh is a refresh method that refreshes the entire area of ​​the DRAM 110. The per-bank refresh is a refresh method that refreshes a portion of the area of ​​the DRAM 110.

[0072] In the memory controller 100, a specific event occurs in which the entire area of ​​the DRAM 110 cannot be accessed for a period longer than the period for performing refresh by all-bank refresh. The specific event in which the entire area of ​​the DRAM 110 cannot be accessed is, for example, timing adjustment or calibration for the memory controller 100 to communicate with the DRAM 110.

[0073] The DRAM command generation unit 101 functions as a selection unit and selects one of a plurality of refresh methods depending on whether a specific event occurs that makes it impossible to access the entire area of ​​the DRAM 110 during the refresh execution period. The refresh execution period is a refresh execution period based on the refresh timing generated by the refresh timing generation unit 102 in Fig. 1 or a refresh execution period based on the refresh execution period measured by the refresh execution period measurement unit 1015 in Fig. 5. The refresh execution period is set at a predetermined cycle.

[0074] The DRAM command generation unit 101 selects all-bank refresh when a specific event occurs that makes it impossible to access all areas of the DRAM 110 during the refresh execution period, and selects per-bank refresh when no specific event occurs that makes it impossible to access all areas of the DRAM 110 during the refresh execution period.

[0075] For example, the DRAM command generation unit 101 selects all-bank refresh if timing adjustment or calibration occurs during each refresh execution period, and selects per-bank refresh if timing adjustment or calibration does not occur during each refresh execution period.

[0076] 3, the DRAM command generation unit 101 selects all-bank refresh in a refresh execution period based on the refresh timing at time T5. Then, the DRAM command generation unit 101 controls so that refresh of the DRAM 110 is not performed in one or more refresh execution periods immediately following the refresh execution period in which the all-bank refresh is selected. During that period, the refresh command generation instruction mask is asserted.

[0077] As described above, the memory controller 100 can be used with various memory controllers that are connected to the DRAM 110 and have multiple refresh methods with different refresh target areas. The memory controller 100 can suppress a decrease in memory utilization efficiency by selecting an appropriate refresh method from the multiple refresh methods depending on whether a specific event, such as timing adjustment or calibration execution, occurs during the refresh execution period.

[0078] (Other embodiments) The present disclosure can also be realized by a process in which a program that realizes one or more functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in the computer of the system or device read and execute the program. The present disclosure can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0079] It should be noted that the above-described embodiments merely illustrate specific examples of implementing the present disclosure, and the technical scope of the present disclosure should not be construed as being limited by these embodiments. In other words, the present disclosure can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0080] 100: Memory controller, 101: DRAM command generation unit, 102: Refresh timing generation unit, 103: Timing adjustment instruction unit, 104: Timing adjustment unit, 110: DRAM, 120: Bus master, 1011: Read / write command generation unit, 1012: Refresh timing management unit, 1013: Refresh command generation unit, 1014: Command selection unit, 1015: Refresh execution cycle measurement unit, 1016: Timing adjustment execution cycle measurement unit

Claims

1. A memory controller in which a plurality of refresh methods for different refresh target areas of a DRAM include a refresh method for refreshing an entire area of ​​the DRAM and a refresh method for refreshing a partial area of ​​the DRAM, and a specific event occurs in which the entire area of ​​the DRAM cannot be accessed for a period longer than a period in which refresh is performed by the refresh method for refreshing the entire area of ​​the DRAM, a selection means for selecting one of the plurality of refresh methods depending on whether or not a specific event occurs during a refresh execution period in which the entire area of ​​the DRAM cannot be accessed; The selection means If a specific event that makes it impossible to access the entire area of ​​the DRAM is expected to occur during the refresh execution period, a refresh method for refreshing the entire area of ​​the DRAM is selected; A memory controller characterized by selecting a refresh method for refreshing a portion of the DRAM when a specific event that makes it impossible to access the entire DRAM is not expected to occur during the refresh execution period.

2. 2. The memory controller according to claim 1, wherein the specific event in which the entire area of ​​the DRAM cannot be accessed is timing adjustment or calibration for communication with the DRAM.

3. The specific event in which the entire area of ​​the DRAM cannot be accessed is timing adjustment or calibration for communication with the DRAM, The refresh execution period is set at a predetermined cycle, 2. The memory controller according to claim 1, wherein the selection means selects a refresh method for refreshing an entire area of ​​the DRAM when the timing adjustment or the calibration is scheduled to occur during each refresh execution period, and selects a refresh method for refreshing a partial area of ​​the DRAM when the timing adjustment or the calibration is not scheduled to occur during the refresh execution period.

4. 4. The memory controller according to claim 3, wherein the selection means controls so that the DRAM is not refreshed during one or more refresh execution periods immediately following a refresh execution period in which a refresh method for refreshing an entire area of ​​the DRAM is selected.

5. A control method for a memory controller in which a plurality of refresh modes for different refresh target areas of a DRAM include a refresh mode for refreshing the entire area of ​​the DRAM and a refresh mode for refreshing a part of the area of ​​the DRAM, and a specific event occurs in which the entire area of ​​the DRAM cannot be accessed for a period longer than a period for performing refresh using the refresh mode for refreshing the entire area of ​​the DRAM, a selection step of selecting one of the plurality of refresh methods depending on whether or not a specific event occurs during a refresh execution period in which the entire area of ​​the DRAM cannot be accessed; In the selection step, If a specific event that makes it impossible to access the entire area of ​​the DRAM is expected to occur during the refresh execution period, a refresh method for refreshing the entire area of ​​the DRAM is selected; A control method for a memory controller, characterized in that if a specific event that makes it impossible to access the entire area of ​​the DRAM is not expected to occur during the refresh execution period, a refresh method that refreshes a portion of the area of ​​the DRAM is selected.

6. A program for causing a computer to function as the memory controller according to any one of claims 1 to 4.

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