Semiconductor Devices

Abstract

To provide a semiconductor device that comprises a thin-film transistor with excellent electric characteristics by using an oxide semiconductor layer.SOLUTION: The semiconductor device uses an In-Sn-O-based oxide semiconductor layer that contains SiOx in a channel formation region. A source region or a drain region is provided between a source electrode layer and a drain electrode layer, and the In-Sn-O-based oxide semiconductor layer that contains SiOx for the purpose of reducing a contact resistance with a wiring layer consisting of a metal material with a low electric resistance value. The source region or the drain region, and a pixel region use an In-Sn-O-based oxide semiconductor layer not containing SiOx of the same layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof. [Background technology]

[0002] There are many types of metal oxides and they are used for various purposes. Indium oxide is well known as It is a material that has been developed and is used as a transparent electrode material required for liquid crystal displays, etc. do.

[0003] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties are compounds It is a type of semiconductor. A compound semiconductor is a semiconductor made up of two or more types of atoms bonded together. Generally, metal oxides are insulators. However, the combination of elements that make up metal oxides It is known that, depending on the type of material, it can become a semiconductor.

[0004] For example, among metal oxides, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. It is known that transparent semiconductors made of such metal oxides exhibit semiconducting properties. Thin film transistors using a layer as a channel formation region have been disclosed (Patent Documents 1 to 4, Non-Patent Documents 1 to 4, See Patent Document 1. ).

[0005] Incidentally, metal oxides include not only single-component oxides but also multi-component oxides. For example, InGaO3(ZnO)m (m: natural number) having a homologous phase is a known material (non See Patent Documents 2 to 4. ).

[0006] The In-Ga-Zn oxide was used as the channel layer of a thin-film transistor. It has been confirmed that this method is applicable (see Patent Document 5, Non-Patent Documents 5 and 6). [Preliminary Technology Documents] [License]

[0007] [License 1] Special Announcement No. 60-198861 [License 2] Special Announcement No. 8-264794 [License 3] Special Notice No. 11-505377 [License 4] Special Announcement No. 2000-150900 [Patent Document 5] Special Announcement No. 2004-103957 [Non-licensed literature]

[0008] [Non-licensed Document 1] MW Prins, KO Grosse-Holz, G. Muller, JFM Cillessen, JB Giesbers, RP Weening, and RM Wolf, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett., 17 June 1996, Vol.68 p.3650-3652 [Non-licensed Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-licensed Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m(m=3,4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m(m=7,8,9, and 16) in the In2O3-ZnGa2O4-ZnO System”, J. Solid State Chem., 1995, Vol.116, p.170-173 [Non-patent document 4] Masaaki Nakamura, Noboru Kimizuka, Takahiko Mohri, Mitsumasa Isobe, "Synthesis and Crystal Structure of Homologous Phase, InFeO3(ZnO)m (m: natural number) and Its Isomorphic Compounds," Solid State Physics, 1993, Vol. 28, No. 5, pp. 317-327 [Non-patent document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, "Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor", SCIENCE, 2003, Vol.300, p.1269-1272 [Non-patent document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors", NATURE, 2004, Vol.432 p.488-492 Summary of the Invention [Problem to be solved by the invention]

[0009] One embodiment of the present invention is a thin film transistor and a pixel having excellent electrical characteristics, which are formed using an oxide semiconductor layer. An object of the present invention is to provide a display device including an electrode layer. [Means for solving the problem]

[0010] To realize an amorphous oxide semiconductor layer, a silicon oxide film is formed on a semiconductor layer having a channel formation region. Thin film transistor using an In-Sn-O-based oxide semiconductor layer containing silicon or silicon oxynitride Typically, SiO2 is 5% by weight or more and 50% by weight or less, preferably 10% by weight or less. The film was formed using an In-Sn-O oxide semiconductor target containing 100% or more and 30% or less by weight of In. In addition, by adding SiOx (x>0) which inhibits crystallization to the In-Sn-O based oxide semiconductor layer, The gate voltage of the thin film transistor is as close to 0V as possible to the positive threshold voltage. The present invention realizes a thin film transistor in which a thin film is formed.

[0011] An In-Sn-O-based oxide semiconductor layer containing SiOx is used as the semiconductor layer having a channel formation region. The electrical characteristics of thin film transistors using this material were calculated. As shown below.

[0012] The calculation was performed using Atlas manufactured by Silvaco. The structure of the calculation model is shown in Figure 35. The thin film transistor has an inverted staggered structure as shown in the figure. The gate electrode layer 801 (work function 4. 7 eV) the gate insulating layer 802 is a silicon oxynitride layer (thickness 100 nm, relative dielectric constant 4.1) The semiconductor layer 803 having a channel formation region is an In—Sn—O-based oxide semiconductor layer (thickness 5 0 nm, electron affinity 4.3 eV), and the wiring layers 804a and 804b are made of In-Sn-O oxide. A semiconductor layer (work function 4.7 eV), a channel of the semiconductor layer 803 having a channel formation region The length in the direction and the width in the channel direction are 10 μm, and the electron mobility is 0.1 cm2 / Vs, hole is 0.01cm 2 / Vs.

[0013] The conductivity of the semiconductor layer 803 is calculated from the donor (carrier) concentration as shown in FIG. Rate 3.9×10 -3 S / cm, 1.6 × 10 -3 S / cm, 8.8 x 10 -4 S / cm, 1.3×10 -4 S / cm, 1.7 × 10 -7 S / cm, 1.9 × 10 -10 S / cm, 8.0×10 -12 The electrical characteristics of the thin film transistor were calculated for the case of The gate-source voltage (Vgs [V]) and drain-source current (Ids The calculation results of the drain current (W / W [A / μm]) are shown in Figures 33(A) and 33(B). Figure 33(A) shows the results when the drain voltage is 1V, and Figure 33(B) shows the results when the drain voltage is 10V. In (B), the results for each conductivity are shown as 3.9 × 10 -3 S / cm is a downward pointing triangle t, 1.6 x 10 -3 S / cm is the dashed line, 8.8 × 10 -4 S / cm is an upward-pointing triangle dots, 1.3 x 10 -4 S / cm is dotted line, 1.7 × 10 -7 S / cm is a circle dot , 1.9×10 -10 S / cm is solid line, 8.0 × 10 -12 S / cm is a square dot It shows.

[0014] As shown in Figures 33(A) and 33(B), the conductivity of the semiconductor layer is 1.6 × 10 -3 S / cm or less In addition, the thin film transistor shown in Figure 34 has switching characteristics. The relationship between the threshold voltage and conductivity of the transistor is shown in Figure 34. The rate is 1.3 x 10 -4 If the capacitance is less than S / cm, the threshold voltage is almost 0V or less, and normal Therefore, it is possible to form a thin film transistor with a gate-off property. A thin film transistor using an In-Sn-O-based oxide semiconductor layer containing SiOx as a semiconductor layer with a region In a transistor, the conductivity of the semiconductor layer is 1.6×10 -3 S / cm or less is sufficient. , and 1.3 × 10 -4 It is more preferable to set it to S / cm or less.

[0015] In addition, the contact with the source electrode layer or the drain electrode layer made of a metal material with a low electrical resistance value is In order to reduce the gate resistance, the source electrode layer or the drain electrode layer and the In-S containing SiOx are A source region or a drain region is formed between the nO-based oxide semiconductor layer and the source region. Alternatively, one of the drain regions is formed from the same thin film layer as the pixel electrode region.

[0016] The source region, drain region, and pixel electrode region are made of In-Sn-O based material that does not contain SiOx. An oxide semiconductor layer is used.

[0017] The source electrode layer or the drain electrode layer is made of an element selected from Al, Cr, Ta, Ti, Mo, and W. The above-mentioned elements are used as components, or alloys containing the above-mentioned elements, or alloy films combining the above-mentioned elements. There are.

[0018] One aspect of the semiconductor device disclosed in this specification is a semiconductor device including a gate electrode layer, a gate insulating layer, and a SiOx a first In-Sn-O based oxide semiconductor layer containing SiOx; a source region and a drain region in contact with the oxide semiconductor layer, and a pixel electrode region; The drain region and the pixel electrode region are made of the second In-Sn-O oxide semiconductor in the same layer. It is a layer.

[0019] One embodiment of a semiconductor device disclosed in this specification is a semiconductor device including a gate electrode layer and a gate insulating layer formed on a substrate having an insulating surface. a gate insulating layer on the gate electrode layer; and a first In—Sn layer containing SiOx on the gate insulating layer. a first In—Sn—O-based oxide semiconductor layer and a second In—Sn—O-based oxide semiconductor layer including SiOx; The pixel electrode region includes a source region and a drain region, and the source region or the drain region and the pixel electrode region are The pixel electrode region is the second In—Sn—O-based oxide semiconductor layer in the same layer.

[0020] In the above structure, the conductivity of the first In—Sn—O-based oxide semiconductor layer containing SiOx is 1 .6×10 -3 S / cm or less, and even 1.3 x 10 -4 S / cm or less is preferable. The first In-Sn-O based oxide semiconductor layer containing SiOx contains SiO2 in an amount of 5% by weight or more and 50% by weight or less. % by weight or less, preferably 10% by weight to 30% by weight or more It is formed by sputtering using a solid target.

[0021] In addition, one embodiment of the present invention for realizing the above structure is to form a gate electrode on a substrate having an insulating surface. A gate electrode layer is formed, a gate insulating layer is formed on the gate electrode layer, and SiO2 is deposited on the gate insulating layer. A first In-Sn-O-based oxide semiconductor target containing 50% by weight or more of In-Sn-O-based oxide semiconductor was used. A first oxide semiconductor layer containing SiOx is formed by sputtering, and a first In A second In-Sn-O based oxide semiconductor target was used on the Sn-O based oxide semiconductor layer. The source region, drain region, and pixel electrode region are formed by sputtering. The drain region and pixel electrode region are formed of the second In-Sn-O oxide semiconductor layer in the same layer. The present invention relates to a method for manufacturing a semiconductor device.

[0022] The structure of the thin film transistor is not limited, and may be a bottom gate thin film transistor or a top gate thin film transistor. A thin film transistor of a gate type can be fabricated.

[0023] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Effects of the Invention]

[0024] One embodiment of the present invention is a semiconductor device including a highly reliable thin film transistor using an oxide semiconductor layer. To provide a conductor device. [Brief explanation of the drawings]

[0025] [Figure 1] 1A to 1C illustrate a semiconductor device. [Figure 2] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 3] 1A to 1C illustrate a semiconductor device. [Figure 4] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 5] 1A to 1C illustrate a semiconductor device. [Figure 6] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 7] 1A to 1C illustrate a semiconductor device. [Figure 8] 1A to 1C illustrate a semiconductor device. [Figure 9] 1A to 1C illustrate a semiconductor device. [Figure 10] 1A to 1C illustrate a semiconductor device. [Figure 11] 1A to 1C illustrate a semiconductor device. [Figure 12]1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 13] 1A to 1C illustrate a semiconductor device. [Figure 14] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 15] FIG. 2 illustrates a configuration of a signal line driver circuit. [Figure 16] 4 is a timing chart illustrating the operation of the signal line driver circuit. [Figure 17] 4 is a timing chart illustrating the operation of the signal line driver circuit. [Figure 18] FIG. 2 is a diagram illustrating the configuration of a shift register. [Figure 19] FIG. 19 is a diagram for explaining the connection configuration of the flip-flop shown in FIG. 18. [Figure 20] 1A and 1B are diagrams illustrating pixel equivalent circuits of a semiconductor device. [Figure 21] 1A to 1C illustrate a semiconductor device. [Figure 22] 1A to 1C illustrate a semiconductor device. [Figure 23] 1A to 1C illustrate a semiconductor device. [Figure 24] 1A to 1C illustrate a semiconductor device. [Figure 25] 1A and 1B are diagrams illustrating examples of usage of electronic paper. [Figure 26] FIG. 1 is an external view showing an example of an electronic book. [Figure 27] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 28] FIG. 1 is an external view showing an example of a gaming machine. [Figure 29] FIG. 1 is an external view showing an example of a mobile phone. [Figure 30] 1A to 1C illustrate a semiconductor device. [Figure 31] 1A to 1C illustrate a semiconductor device. [Figure 32] FIG. [Figure 33] FIG. [Figure 34] FIG. [Figure 35] FIG. 1 is a diagram illustrating a calculation model. [Figure 36] 1A to 1C illustrate a target that can be used for manufacturing a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0026] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Those skilled in the art will recognize that various changes in form and details may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should be interpreted as being limited to the following description of the embodiments. In the configuration described below, parts that have the same parts or similar functions are not included. The same reference numerals are used in common between different drawings for corresponding parts, and repeated explanations thereof will be omitted.

[0027] (Embodiment 1) A semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS.

[0028] FIG. 1A is a plan view of a thin film transistor 470 included in the semiconductor device, and FIG. 1A. The thin film transistor 470 is an inverted staggered type. The thin film transistor is a gate electrode layer on a substrate 400 having an insulating surface. 401, a gate insulating layer 402, an In-Sn-O-based oxide semiconductor layer 403 containing SiOx, The In—Sn—O-based oxide semiconductor layer 404 functions as a source region or a drain region. The semiconductor device includes an n-Sn—O-based oxide semiconductor layer 408 and a source or drain electrode layer 405 . In addition, an In—Sn—O-based oxide semiconductor layer containing SiOx is formed on the thin film transistor 470. An insulating film 407 is provided in contact with the film 403 .

[0029] The semiconductor layer having the channel formation region is made of In-S containing silicon oxide or silicon oxynitride. An In—Sn—O-based oxide semiconductor layer 40 containing SiOx is used. The conductivity of 3 is 1.6 x 10 -3 S / cm or less, and even 1.3 x 10 -4 S / cm or less is preferable It is preferable that the In-Sn-O based oxide semiconductor layer containing SiOx contains 5 wt % SiO2. In—Sn—O-based acid containing 10% by weight or more and 50% by weight or less, preferably 10% by weight or more and 30% by weight or more It is formed by sputtering using a nitride semiconductor target.

[0030] The source electrode layer or drain electrode layer 405 made of a metal material with a low electrical resistance and SiOx The In—Sn—O-based oxide semiconductor layer 403 includes a source region or a drain region. The formed In—Sn—O-based oxide semiconductor layer 404 reduces the contact resistance. Either the source or drain region is an In-Sn-O oxide semiconductor in the same layer as the pixel electrode region. Therefore, the In—Sn—O-based oxide semiconductor layer 408 serves as a source region or serves as both a drain region and a pixel electrode.

[0031] The In—Sn—O based oxide semiconductor layer 404 and the In—Sn—O based oxide semiconductor layer 408 are An In-Sn-O based oxide semiconductor layer that does not contain SiOx is used. The semiconductor layer 404 and the In—Sn—O-based oxide semiconductor layer 408 are Si-free in that they do not contain Si. This is significantly different from the In—Sn—O-based oxide semiconductor layer 403 containing Ox. The O-based oxide semiconductor layer 404 and the In—Sn—O-based oxide semiconductor layer 408 contain SiOx. The In—Sn—O-based oxide semiconductor layer 403 can have lower resistance (higher conductivity) than the In—Sn—O-based oxide semiconductor layer 403. The source region, drain region, and pixel electrode region are made of nitrogen-doped In-Sn-O based oxide. A nitride semiconductor may be used, for example, an In-Sn-O based non-single crystal film containing nitrogen. You can be there.

[0032] 2A to 2E correspond to cross-sectional views illustrating a manufacturing process of the thin film transistor 470. FIG.

[0033] In FIG. 2A, a gate electrode layer 401 is formed on a substrate 400 having an insulating surface. An insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layer 401. The base film has a function of preventing the diffusion of impurity elements from the substrate 400. A laminated structure made of one or more films selected from a bare film, a silicon nitride oxide film, and a silicon oxynitride film. The gate electrode layer 401 can be formed from a material such as molybdenum, titanium, chromium, or the like. Metallic materials such as aluminum, tantalum, tungsten, aluminum, copper, neodymium, and scandium Alternatively, an alloy material containing these as a main component can be used to form a single layer or a laminate. .

[0034] For example, the gate electrode layer 401 may have a two-layer laminate structure, such as a molybdenum layer on an aluminum layer. Two-layer structure with a layer stacked on top of a copper layer, or a two-layer structure with a molybdenum layer stacked on top of a copper layer, The titanium nitride layer and the tantalum nitride layer are laminated on the copper layer. It is preferable to use a two-layer structure in which a layer of tungsten is laminated with a layer of ribide. a tungsten layer or tungsten nitride layer and an aluminum-silicon alloy or aluminum It is preferable to use a laminated layer in which an alloy of aluminum and titanium is laminated with a titanium nitride layer or a titanium layer. It's nice.

[0035] A gate insulating layer 402 is formed on the gate electrode layer 401 .

[0036] The gate insulating layer 402 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer, which may be formed as a single layer or a stacked layer; The gate insulating layer 402 can be formed by using C It is also possible to form a silicon oxide layer by the VD method. ethyl acetate (TEOS: chemical formula Si(OC2H5)4), tetramethylsilane (TMS: chemical formula Chemical formula: Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane Methylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), Triethoxysilane (SiH(OC2H5)3), trisdimethylaminosilane (SiH Silicon-containing compounds such as (N(CH3)2)3) can be used.

[0037] On the gate insulating layer 402, an In—Sn—O-based oxide semiconductor film 430 containing SiOx, an In The In—Sn—O-based oxide semiconductor film 431 is stacked in this order. The In—Sn—O-based oxide semiconductor film 430 and the In—Sn—O-based oxide semiconductor film 431 are formed by photolithography. The oxide semiconductor layer is processed into an island shape by a roughening process.

[0038] The In—Sn—O-based oxide semiconductor film 430 containing SiOx is formed by sputtering. Before the gate insulating layer is formed, argon gas is introduced to generate plasma. Dust adhering to the surface of layer 402 may be removed.

[0039] The gate insulating layer 402, the In—Sn—O-based oxide semiconductor film 430 containing SiOx, and the In A conductive film 432 is formed over the -Sn-O-based oxide semiconductor film 431 (see FIG. 2B).

[0040] The material of the conductive film 432 is an element selected from Al, Cr, Ta, Ti, Mo, and W, or or an alloy containing the above elements as a component, or an alloy film of a combination of the above elements. In addition, Al (aluminum) and Nd (neodymium) or Sc (scandium) are combined. An alloy film in which the two are combined may also be used.

[0041] The conductive film 432 is etched by an etching process to form the source electrode layer or the drain electrode layer 40 5 is formed (see Figure 2(C)).

[0042] A mask 435 is formed on the In—Sn—O-based oxide semiconductor film 431 that does not contain SiOx. Using the source or drain electrode layer 405 and the mask 435, an I film containing SiOx was formed. The n-Sn—O-based oxide semiconductor film 430 and the In-Sn—O-based oxide semiconductor film 431 are etched. The In-Sn-O based oxide semiconductor layer 403 containing SiOx and the In-Sn-O based oxide The In—Sn—O-based oxide semiconductor layer 404 and the In—Sn—O-based oxide semiconductor layer 408 are formed (see FIG. 2(D)). Note that only a part of the In—Sn—O-based oxide semiconductor layer 403 containing SiOx is etched. The In-Sn-O based oxide semiconductor layer 4 is then formed by etching. 04 functions as a source region or a drain region, and the In—Sn—O-based oxide semiconductor layer 40 8 functions as a source region or drain region and a pixel electrode.

[0043] Through the above steps, an In—Sn—O-based oxide semiconductor layer 403 containing SiOx shown in FIG. 2(E) was obtained. An inverted staggered thin film transistor 470 having a channel formation region can be manufactured. In addition, the thin film transistor 470 is covered with an In—Sn—O-based oxide semiconductor containing SiOx. The insulating film 407 in contact with the layer 403 is formed in the pixel electrode region of the In—Sn—O-based oxide semiconductor layer 408. It is formed except on the area.

[0044] The insulating film 407 is a silicon nitride film, a silicon oxide film, or a silicon nitride film obtained by sputtering or the like. Alternatively, a single layer such as a silicon oxynitride film or a laminate of these films can be used.

[0045] Therefore, a semiconductor device having a thin film transistor and a pixel electrode layer with excellent electrical characteristics can be realized. It is possible.

[0046] (Embodiment 2) Here, in the first embodiment, a thin film transistor provided with a channel protection layer is used. 3 and 4 show examples of the semiconductor device. Therefore, the other steps can be performed in the same manner as in the first embodiment. The same parts as those in the first embodiment or parts having similar functions, and the repetition of steps are described. is omitted.

[0047] FIG. 3A is a plan view of a thin film transistor 471 included in the semiconductor device, and FIG. 3A. The thin film transistor 471 is an inverted staggered type. The thin film transistor is a gate electrode layer on a substrate 400 having an insulating surface. 401, a gate insulating layer 402, an In-Sn-O-based oxide semiconductor layer 403 containing SiOx, The channel protection layer 409 is an In—Sn—O-based oxide film that functions as a source region or a drain region. The oxide semiconductor layer 404, the In-Sn-O-based oxide semiconductor layer 408, the source electrode layer or the drain electrode layer The thin film transistor 471 includes an insulating film 407. The insulating film 407 is formed on the In—Sn—O-based oxide semiconductor layer 408 except for the pixel electrode region. It is formed.

[0048] The thin film transistor 471 of this embodiment is an In—Sn—O-based oxide semiconductor containing SiOx. A channel protection layer 409 is provided on the channel formation portion of the layer 403. The channel protection layer 409 functions as a channel stopper, so that the oxide semiconductor layer 403 Therefore, it is not etched.

[0049] The channel protection layer 409 may be made of an inorganic material (silicon oxide, silicon nitride, silicon oxynitride, silicon nitride, silicon nitride, silicon nitride, silicon dioxide ... Silicon dioxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide The sputtering method can be used for the production of the silicon nitride film. .

[0050] The semiconductor layer having the channel formation region is made of In-S containing silicon oxide or silicon oxynitride. An In—Sn—O-based oxide semiconductor layer 40 containing SiOx is used. The conductivity of 3 is 1.6 x 10 -3 S / cm or less, and even 1.3 x 10 -4 S / cm or less is preferable It is preferable that the In-Sn-O based oxide semiconductor layer containing SiOx contains 5 wt % SiO2. In—Sn—O-based acid containing 10% by weight or more and 50% by weight or less, preferably 10% by weight or more and 30% by weight or more It is formed by sputtering using a nitride semiconductor target.

[0051] The source electrode layer or drain electrode layer 405 made of a metal material with a low electrical resistance and SiOx The In—Sn—O-based oxide semiconductor layer 403 includes a source region or a drain region. The formed In—Sn—O-based oxide semiconductor layer 404 reduces the contact resistance. Either the source or drain region is an In-Sn-O oxide semiconductor in the same layer as the pixel electrode region. Therefore, the In—Sn—O-based oxide semiconductor layer 408 serves as a source region or serves as both a drain region and a pixel electrode.

[0052] The In—Sn—O based oxide semiconductor layer 404 and the In—Sn—O based oxide semiconductor layer 408 are An In-Sn-O based oxide semiconductor layer that does not contain SiOx is used.

[0053] 4A to 4E correspond to cross-sectional views illustrating a manufacturing process of the thin film transistor 471.

[0054] In FIG. 4A, a gate electrode layer 401 is formed on a substrate 400 having an insulating surface. An insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layer 401.

[0055] A gate insulating layer 402 is formed on the gate electrode layer 401 .

[0056] An In—Sn—O-based oxide semiconductor layer 403 containing SiOx and a thin film transistor (TFT) were formed on a gate insulating layer 402. A channel protection layer 409 is formed. An In—Sn—O-based oxide semiconductor layer 403 containing SiOx is formed. and the channel protection layer 409 are each processed into an island shape by a photolithography process. There are.

[0057] A gate insulating layer 402, an In—Sn—O-based oxide semiconductor layer 403 containing SiOx, and a channel An In—Sn—O-based oxide semiconductor film 431 and a conductive film 432 are formed over the protective layer 409. (See Figure 4(B)).

[0058] The conductive film 432 is etched by an etching process to form the source electrode layer or the drain electrode layer 40 5 is formed (see Figure 4(C)).

[0059] A mask 435 is formed on the In—Sn—O-based oxide semiconductor film 431 that does not contain SiOx. Using the source or drain electrode layer 405 and the mask 435, an In—Sn—O system The oxide semiconductor film 431 is etched, and the In—Sn—O-based oxide semiconductor layer 404 and the In- An Sn—O-based oxide semiconductor layer 408 is formed (see FIG. 4D). The oxide semiconductor layer 404 functions as a source region or a drain region, and the In—Sn—O oxide The organic semiconductor layer 408 functions as a source region or a drain region and a pixel electrode.

[0060] Through the above steps, an In—Sn—O-based oxide semiconductor layer 403 containing SiOx shown in FIG. 4(E) is obtained. An inverted staggered thin film transistor 470 having a channel formation region can be manufactured. In addition, the insulating film 407 covering the thin film transistor 470 and contacting the channel protection layer 409 is The In—Sn—O based oxide semiconductor layer 408 is formed on the entire surface except for the pixel electrode region.

[0061] Therefore, a semiconductor device having a thin film transistor and a pixel electrode layer with excellent electrical characteristics can be realized. It is possible.

[0062] (Embodiment 3) Another example of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS.

[0063] FIG. 5A is a plan view of a thin film transistor 460 included in the semiconductor device, and FIG. 5A. The thin film transistor 460 is a bottom gate. The transistor is a gate-type thin film transistor, and a gate electrode is disposed on a substrate 400 having an insulating surface. a gate insulating layer 402; a source or drain electrode layer 405; a source region; Alternatively, the In—Sn—O-based oxide semiconductor layer 404, In—Sn— An O-based oxide semiconductor layer 408 and an In—Sn—O-based oxide semiconductor layer 403 containing SiOx Also, the thin film transistor 460 is covered with an In—Sn—O-based oxide containing SiOx. An insulating film 407 is provided in contact with the semiconductor layer 403. The insulating film 407 is made of In-Sn- The O-based oxide semiconductor layer 408 is formed except for the pixel electrode region.

[0064] The thin film transistor 460 has a gate insulating layer in the entire area including the thin film transistor 460. A layer 402 is present between the gate insulating layer 402 and the substrate 400, which is a substrate having an insulating surface. A gate electrode layer 401 is provided. A source electrode layer or a drain electrode layer is provided on the gate insulating layer 402. The In-Sn-O-based oxide semiconductor layer 404 is an In-Sn-O-based oxide semiconductor layer 405. A gate insulating layer 402, a source electrode layer or a drain electrode layer 404, and a gate insulating layer 406 are provided. The layer electrode layer 405, the In-Sn-O based oxide semiconductor layer 404, and the In-Sn-O based oxide An In—Sn—O-based oxide semiconductor layer 403 containing SiOx is provided on the oxide semiconductor layer 408. Although not shown, a source electrode layer or a drain electrode layer is formed on the gate insulating layer 402. In addition to the electrode layer 405, a wiring layer is provided, and the wiring layer is an In—Sn—O-based oxide semiconductor containing SiOx. It extends outward from the outer periphery of the conductor layer 403 .

[0065] The semiconductor layer having the channel formation region is made of In-S containing silicon oxide or silicon oxynitride. An In—Sn—O-based oxide semiconductor layer 40 containing SiOx is used. The conductivity of 3 is 1.6 x 10 -3 S / cm or less, and even 1.3 x 10 -4 S / cm or less is preferable It is preferable that the In-Sn-O based oxide semiconductor layer containing SiOx contains 5 wt % SiO2. In—Sn—O-based acid containing 10% by weight or more and 50% by weight or less, preferably 10% by weight or more and 30% by weight or more It is formed by sputtering using a nitride semiconductor target.

[0066] The source electrode layer or drain electrode layer 405 made of a metal material with a low electrical resistance and SiOx The In—Sn—O-based oxide semiconductor layer 403 includes a source region or a drain region. The formed In—Sn—O-based oxide semiconductor layer 404 reduces the contact resistance. Either the source or drain region is an In-Sn-O oxide semiconductor in the same layer as the pixel electrode region. Therefore, the In—Sn—O-based oxide semiconductor layer 408 serves as a source region or serves as both a drain region and a pixel electrode.

[0067] The In—Sn—O based oxide semiconductor layer 404 and the In—Sn—O based oxide semiconductor layer 408 are An In-Sn-O based oxide semiconductor layer that does not contain SiOx is used.

[0068] 6A to 6E correspond to cross-sectional views illustrating a manufacturing process of the thin film transistor 460. FIG.

[0069] A gate electrode layer 401 is provided over a substrate 400 having an insulating surface. An insulating film may be provided between the substrate 400 and the gate electrode layer 401 .

[0070] A gate insulating layer 402 is formed over the gate electrode layer 401. Next, A source or drain electrode layer 405 is formed (see FIG. 6A).

[0071] An In-Sn-O oxide semiconductor film is formed, and island-shaped In- Sn—O-based oxide semiconductor films 451 and 452 are formed (see FIG. 6B).

[0072] Next, an In—Sn—O-based oxide semiconductor film containing SiOx was formed on the In—Sn—O-based oxide semiconductor films 451 and 452. An O-based oxide semiconductor film 450 is formed (see FIG. 6C).

[0073] An In-Sn-O-based oxide semiconductor film 450 containing SiOx is formed by a photolithography process. Etching is performed to form an island-shaped In-Sn-O-based oxide semiconductor layer 403 containing SiOx. (See FIG. 6D.) At this time, the In-Sn-O-based oxide semiconductor films 451 and 452 are also partially etched, and the In-Sn The —O-based oxide semiconductor layer 404 and the In—Sn—O-based oxide semiconductor layer 408 are formed.

[0074] Through the above steps, an In—Sn—O-based oxide semiconductor layer 403 containing SiOx shown in FIG. 6(E) is obtained. An inverted staggered thin film transistor 460 having a channel formation region can be manufactured. In addition, the thin film transistor 460 is covered with an In—Sn—O-based oxide semiconductor containing SiOx. The insulating film 407 in contact with the layer 403 is formed in the pixel electrode region of the In—Sn—O-based oxide semiconductor layer 408. It is formed except on the area.

[0075] Therefore, a semiconductor device having a thin film transistor and a pixel electrode layer with excellent electrical characteristics can be realized. It is possible.

[0076] (Fourth embodiment) Here, an example of a top gate type semiconductor device will be described with reference to FIG.

[0077] FIG. 7A is a plan view of a thin film transistor 480 included in the semiconductor device, and FIG. 7A. The thin film transistor 480 is a top gate. The transistor is a thin film transistor of a light-emitting type, and is formed on a substrate 400 having an insulating surface. a source electrode layer in contact with the source or drain electrode layer 405; The In-Sn-O-based oxide semiconductor layer 404 functions as a drain region. the In—Sn—O-based oxide semiconductor layer 408, the In—Sn—O-based oxide semiconductor layer 404, and the In—Sn The In—Sn—O-based oxide semiconductor layer 408 is in contact with the In—Sn—O-based oxide semiconductor layer 408. 03, a gate insulating layer 402, and a gate electrode layer 401. The insulating film 407 covers the gate insulating layer 402. The -Sn-O based oxide semiconductor layer 408 is formed except for the pixel electrode region.

[0078] The thin film transistor 480 includes a source electrode layer or a drain electrode layer 405, an In—Sn—O based The oxide semiconductor layer 404, the In—Sn—O-based oxide semiconductor layer 408, and the I-based oxide semiconductor layer 409 containing SiOx A gate insulating layer 402 is formed on the n-Sn—O-based oxide semiconductor layer 403. On the substrate 402, an In-Sn-O based oxide semiconductor layer 404 is formed. the region overlapping the In—Sn—O-based oxide semiconductor layer 403 containing SiOx; A gate electrode layer 401 is provided on the gate electrode 402 .

[0079] The semiconductor layer having the channel formation region is made of In-S containing silicon oxide or silicon oxynitride. An In—Sn—O-based oxide semiconductor layer 40 containing SiOx is used. The conductivity of 3 is 1.6 x 10 -3 S / cm or less, and even 1.3 x 10 -4 S / cm or less is preferable It is preferable that the In-Sn-O based oxide semiconductor layer containing SiOx contains 5 wt % SiO2. In—Sn—O-based acid containing 10% by weight or more and 50% by weight or less, preferably 10% by weight or more and 30% by weight or more It is formed by sputtering using a nitride semiconductor target.

[0080] The source electrode layer or drain electrode layer 405 made of a metal material with a low electrical resistance and SiOx The In—Sn—O-based oxide semiconductor layer 403 includes a source region or a drain region. The formed In—Sn—O-based oxide semiconductor layer 404 reduces the contact resistance. Either the source or drain region is an In-Sn-O oxide semiconductor in the same layer as the pixel electrode region. Therefore, the In—Sn—O-based oxide semiconductor layer 408 serves as a source region or serves as both a drain region and a pixel electrode.

[0081] The In—Sn—O based oxide semiconductor layer 404 and the In—Sn—O based oxide semiconductor layer 408 are An In-Sn-O based oxide semiconductor layer that does not contain SiOx is used.

[0082] Therefore, a semiconductor device having a thin film transistor and a pixel electrode layer with excellent electrical characteristics can be realized. It is possible.

[0083] (Embodiment 5) Here, another example of a top-gate type semiconductor device will be described with reference to FIG.

[0084] FIG. 8A is a plan view of a thin film transistor 481 included in the semiconductor device, and FIG. 8(A). The thin film transistor 481 is a top gate. The transistor is a thin film transistor of a semiconductor device, and is formed on a substrate 400 having an insulating surface. an In—Sn—O-based oxide semiconductor layer 403 containing SiOx; An In—Sn—O-based oxide film that functions as a source region or a drain region in contact with the semiconductor layer 403 The In-Sn-O-based oxide semiconductor layer 404 and the In-Sn-O-based oxide semiconductor layer 408 The source or drain electrode layer 405 and the gate insulating layer 402 are in contact with the compound semiconductor layer 404. 4, includes a gate electrode layer 401. An insulating film 407 is provided to cover the thin film transistor 481. The insulating film 407 and the gate insulating layer 402 are made of an In—Sn—O-based oxide semiconductor. Layer 408 is formed except for the pixel electrode area.

[0085] The thin film transistor 481 includes an In—Sn—O-based oxide semiconductor layer 403 containing SiOx, an I The n-Sn—O-based oxide semiconductor layer 404, the In-Sn—O-based oxide semiconductor layer 408, and the The gate insulating layer 402 is formed on the source or drain electrode layer 405. An In-Sn-O-based oxide semiconductor layer 403 containing SiOx is formed on the In-Sn- A region overlapping with the O-based oxide semiconductor layer 404 and the In—Sn—O-based oxide semiconductor layer 408 A gate electrode layer 401 is provided on the gate electrode 402 .

[0086] The semiconductor layer having the channel formation region is made of In-S containing silicon oxide or silicon oxynitride. An In—Sn—O-based oxide semiconductor layer 40 containing SiOx is used. The conductivity of 3 is 1.6 x 10 -3 S / cm or less, and even 1.3 x 10 -4 S / cm or less is preferable It is preferable that the In-Sn-O based oxide semiconductor layer containing SiOx contains 5 wt % SiO2. In—Sn—O-based acid containing 10% by weight or more and 50% by weight or less, preferably 10% by weight or more and 30% by weight or more It is formed by sputtering using a nitride semiconductor target.

[0087] The source electrode layer or drain electrode layer 405 made of a metal material with a low electrical resistance and SiOx The In—Sn—O-based oxide semiconductor layer 403 includes a source region or a drain region. The formed In—Sn—O-based oxide semiconductor layer 404 reduces the contact resistance. Either the source or drain region is an In-Sn-O oxide semiconductor in the same layer as the pixel electrode region. Therefore, the In—Sn—O-based oxide semiconductor layer 408 serves as a source region or serves as both a drain region and a pixel electrode.

[0088] The In—Sn—O based oxide semiconductor layer 404 and the In—Sn—O based oxide semiconductor layer 408 are An In-Sn-O based oxide semiconductor layer that does not contain SiOx is used.

[0089] Therefore, a semiconductor device having a thin film transistor and a pixel electrode layer with excellent electrical characteristics can be realized. It is possible.

[0090] (Embodiment 6) An In—Sn—O-based oxide semiconductor layer having a source region or a drain region and a pixel electrode region An example of a semiconductor device having a configuration in which a thin film transistor is provided in an opening formed in an insulating layer is shown below. This is shown in Figures 9 and 10.

[0091] FIG. 9A is a plan view of a thin film transistor 475 included in the semiconductor device, and FIG. 9A. The thin film transistor 475 is an inverted staggered type. The thin film transistor is a gate electrode layer on a substrate 400 having an insulating surface. 401, a gate insulating layer 402, an In-Sn-O-based oxide semiconductor layer 403 containing SiOx, A source or drain electrode layer 405, which functions as a source or drain region, n-Sn-O based oxide semiconductor layer 404, insulating layer 410, In-Sn-O based oxide semiconductor layer Including 408.

[0092] In FIG. 9, the SiOx layer does not include the SiOx layer which serves as both the source region or the drain region and the pixel electrode layer. The In—Sn—O-based oxide semiconductor layer 408 is a thin film transistor formed in an opening in the insulating layer 410. The transistor 475 is in contact with the In—Sn—O-based oxide semiconductor layer 403 containing SiOx. , electrically connected.

[0093] FIG. 10A is a plan view of a thin film transistor 476 included in the semiconductor device, and FIG. ) is a cross-sectional view taken along line Y3-Y4 in FIG. 10(A). The gate electrode is formed on a substrate 400 having an insulating surface. An electrode layer 401, a gate insulating layer 402, an In—Sn—O-based oxide semiconductor layer 4 containing SiOx 03, an insulating layer 410, a source electrode layer or a drain electrode layer 405, a source region or a drain region The In-Sn-O-based oxide semiconductor layer 404 functions as a region. It includes a conductor layer 408 .

[0094] In FIG. 10, an In—Sn—O-based oxide semiconductor serving as a source region or a drain region is The conductive layer 404 and the source region or drain region are formed of SiOx. The thin In—Sn—O-based oxide semiconductor layer 408 is formed as a thin film in the opening formed in the insulating layer 410. In contact with the In-Sn-O-based oxide semiconductor layer 403 containing SiOx of the transistor 475 In addition, a source electrode is formed on the In—Sn—O-based oxide semiconductor layer 404. The electrode layer or drain electrode layer 405 is formed, and the In—Sn—O-based oxide does not contain SiOx. An insulating film 407 is formed on the semiconductor layer 408 except for the pixel electrode region.

[0095] After forming the insulating layer that functions as a planarizing insulating film on the thin film transistor, In-Sn-O based oxide semiconductor layers are formed to form the gate electrode region, drain region, and pixel electrode region. Good too.

[0096] The planarization insulating film can be made of polyimide, acrylic, benzocyclobutene, polyamide, or epoxy. In addition to the above organic materials, low dielectric constant materials (lo wk materials), siloxane resin, PSG (phosphorus glass), BPSG (boron phosphorus glass) ) etc. can be used.

[0097] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0098] The method for forming the planarizing insulating film is not particularly limited, and may be a sputtering method, an SOG method, or the like depending on the material. Spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A coater or the like can be used.

[0099] In this embodiment mode, an example in which the thin film transistor described in Embodiment Mode 1 is applied is shown. The embodiment is not limited to this, and may be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0100] Therefore, a semiconductor device having a thin film transistor and a pixel electrode layer with excellent electrical characteristics can be realized. It is possible.

[0101] (Embodiment 7) In this embodiment, the width of the gate electrode is different from that in the first embodiment. This will be explained with reference to FIGS. 11 to 13 and 31.

[0102] FIG. 13 is a plan view of a semiconductor device having a thin film transistor 170. The thin film transistor 170 is an inverted staggered type. The thin film transistor is a gate electrode layer on a substrate 100 having an insulating surface. 101, a gate insulating layer 102, an In-Sn-O-based oxide semiconductor layer 103 containing SiOx, The In—Sn—O-based oxide semiconductor layer 104 functions as a source region or a drain region. The semiconductor device includes an n-Sn—O-based oxide semiconductor layer 110 and a source or drain electrode layer 105 . In addition, an In—Sn—O-based oxide semiconductor layer containing SiOx is formed on the thin film transistor 170. A protective insulating layer 107 is provided in contact with 103 .

[0103] The semiconductor layer having the channel formation region is made of In-S containing silicon oxide or silicon oxynitride. An In—Sn—O-based oxide semiconductor layer 10 containing SiOx is used. The conductivity of 3 is 1.6 x 10 -3 S / cm or less, and even 1.3 x 10 -4 S / cm or less is preferable It is preferable that the In-Sn-O based oxide semiconductor layer containing SiOx contains 5 wt % SiO2. In—Sn—O-based acid containing 10% by weight or more and 50% by weight or less, preferably 10% by weight or more and 30% by weight or more It is formed by sputtering using a nitride semiconductor target.

[0104] The source electrode layer or drain electrode layer 105 made of a metal material with a low electrical resistance and SiOx The In—Sn—O-based oxide semiconductor layer 103 includes a The formed In—Sn—O based oxide semiconductor layer 104 reduces the contact resistance. Either the source or drain region is an In-Sn-O oxide semiconductor in the same layer as the pixel electrode region. Therefore, the In—Sn—O based oxide semiconductor layer 110 is formed as a source region or serves as both a drain region and a pixel electrode.

[0105] The In—Sn—O based oxide semiconductor layer 104 and the In—Sn—O based oxide semiconductor layer 110 are An In-Sn-O based oxide semiconductor layer that does not contain SiOx is used. The semiconductor layer 104 and the In—Sn—O-based oxide semiconductor layer 110 are Si-free in that they do not contain Si. This is significantly different from the In—Sn—O-based oxide semiconductor layer 103 containing Ox. The O-based oxide semiconductor layer 104 and the In—Sn—O-based oxide semiconductor layer 110 contain SiOx. The In—Sn—O-based oxide semiconductor layer 103 can have lower resistance (higher conductivity) than the In—Sn—O-based oxide semiconductor layer 103. The source region, drain region, and pixel electrode region are made of nitrogen-doped In-Sn-O based oxide. A nitride semiconductor may be used, for example, an In-Sn-O based non-single crystal film containing nitrogen. You can be there.

[0106] The thin film transistor 170 serves as a switching element for the pixel portion in the semiconductor device of FIG. An example of manufacturing the semiconductor device will be described below.

[0107] A conductive layer is formed on a substrate 100 having an insulating surface. A glass substrate such as aluminoborosilicate glass or aluminoborosilicate glass can be used. do.

[0108] Next, the conductive layer is subjected to a photolithography process, a resist mask is formed, and etching is performed. By removing unnecessary portions, wiring and electrodes (gate wiring including the gate electrode layer 101, capacitor The wiring 108 and the first terminal 121 are formed.

[0109] The gate wiring including the gate electrode layer 101, the capacitance wiring 108, and the first terminal 121 of the terminal portion are Conductive materials include titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum. Selected from Mo, Cr, Nd, and Sc It can be formed in a single layer or laminated form using metal materials or alloy materials whose main components are these. Also, aluminum (Al), copper (Cu), or alloy materials with these as the main components may also be used.

[0110] For example, the gate electrode layer 101 may have a two-layer laminate structure, such as a molybdenum layer on an aluminum layer. Two-layer laminated structure with a layer stacked on top of a copper layer, or a two-layer structure with a molybdenum layer stacked on top of a copper layer, or The titanium nitride layer or tantalum nitride layer is laminated on the copper layer. It is preferable to form a two-layer structure by laminating a Ca-containing copper layer with a Ca-containing copper layer. The layer of copper oxide containing Ca is laminated on the copper layer containing Mg, and the layer of oxide containing Mg is laminated on the copper layer containing Mg. There are also three-layer laminated structures, with tungsten or tungsten nitride layers. Stainless steel layer, aluminum and silicon alloy or aluminum and titanium alloy, and nitride A titanium layer or a laminate of titanium layers is preferred.

[0111] Next, a gate insulating layer 102 is formed on the entire surface of the gate electrode layer 101. For 02, sputtering or PCVD method is used, and the film thickness is set to 50 to 400 nm.

[0112] For example, a silicon oxide film is used as the gate insulating layer 102 by sputtering, and the thickness is 100 nm. Of course, the gate insulating layer 102 is not limited to such a silicon oxide film. The film is not a silicon oxide nitride film, but a silicon nitride film, an aluminum oxide film, an aluminum nitride film, etc. Other insulating films such as aluminum, aluminum oxide nitride, and tantalum oxide are used, and The layer may be formed as a single layer or a laminated structure. When the layer is laminated, it may be formed by, for example, a PCVD method. A silicon nitride film is formed by sputtering, and then a silicon oxide film is formed on top of the silicon nitride film by sputtering. In addition, a silicon oxynitride film, a silicon nitride film, or the like is used as the gate insulating layer 102. In this case, impurities from the glass substrate, such as sodium, diffuse and form an acid above the It is possible to block the penetration of the oxide semiconductor.

[0113] Next, an In—Sn—O-based oxide semiconductor film containing SiOx is formed on the gate insulating layer 102. The In-Sn-O-based oxide semiconductor film containing SiOx contains SiO2 in an amount of 5% by weight or more and 50% by weight or less. % by weight or less, preferably 10% by weight to 30% by weight or more It is formed by sputtering using a silicon target. By including x, the formed In-Sn-O oxide semiconductor containing SiOx can be It is easy to make the In-Sn-O oxide semiconductor film containing SiOx amorphous. , by etching using a resist mask formed by a photolithography process, An In-Sn-O-based oxide semiconductor layer containing SiOx is formed. The conductivity of the —O-based oxide semiconductor layer 103 is 1.6×10 -3 S / cm or less, and 1.3x 10 -4 S / cm or less is preferable.

[0114] Next, a sputtering method was used using an In-Sn-O oxide semiconductor target that does not contain SiOx. By this method, an In-Sn-O based oxide semiconductor film containing no SiOx is formed. A resist film was formed by a photolithography process using an In-Sn-O-based oxide semiconductor film. By etching using a mask, an In-Sn-O oxide semiconductor that does not contain SiOx was obtained. Forms the body layer.

[0115] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply for the sputtering power source, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal films. It is used for.

[0116] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0117] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0118] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is used to form thin films of these compounds by chemically reacting them with each other. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0119] The In-Sn-O based oxide semiconductor layer containing SiO2, the In-Sn-O based oxide semiconductor layer, In-Sn-O based oxide semiconductor target containing SiO2 or In-Sn-O based oxide semiconductor It can be formed by sputtering using a conductive target. It is made by attaching a target material to a backing plate (a substrate for attaching the target). However, when attaching the target to the backing plate, the target is divided into two pieces. It may be bonded to a backing plate. The target is divided into parts as shown in Figure 36(A) and (B). This shows an example of bonding the laminate to a single backing plate.

[0120] FIG. 36(A) shows a backing plate 850 on which targets 851a and 851b are mounted. In this example, the image is divided into four parts, 851b, 851c, and 851d, and pasted. This is an example of a target divided into many parts, with target 852 on backing plate 850. Target 852a, 852b, 852c, 852d, 852e, 852f, ​​852g , 852h, 852i, and 9 other parts are pasted. The number of divisions of the target is shown in Figure 36. Not limited to (A) and (B). Once the target is divided, it is attached to a backing plate. This allows for the reduction of warpage in the target. When the thin film is formed on a laminated substrate, the target is particularly suitable for enlarging. Of course, you can also attach one target to one backing plate. Good too.

[0121] The etching can be wet etching or dry etching.

[0122] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0123] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (hydrogen peroxide:ammonia:water=5:2:2) can be used. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0124] In addition, the etching solution after wet etching is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium and the like contained in the oxide semiconductor layer may be recycled from the waste liquid after etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0125] The etching conditions (etching) are adjusted to suit the material so that the desired processing shape can be etched. The etching conditions (liquid, etching time, temperature, etc.) are adjusted appropriately.

[0126] Next, a photolithography process is performed to form a resist mask, and then etching is performed to remove the unwanted The necessary part (part of the gate insulating layer) is removed to reach the wiring and electrode layer made of the same material as the gate electrode layer. This contact hole will be connected to a conductive film to be formed later. For example, in the driver circuit portion, a gate electrode layer and a source electrode layer or a drain electrode layer are provided. Thin film transistors that are in direct contact with the gate electrode layer, and terminals that are electrically connected to the gate wiring of the terminal section When forming a transistor, a contact hole is formed.

[0127] Next, an In-Sn-O-based oxide semiconductor layer containing SiOx and an In-Sn-O-based oxide semiconductor layer not containing SiOx were formed. A conductive film made of a metal material is formed on an nO-based oxide semiconductor layer by a sputtering method or a vacuum deposition method. do.

[0128] The conductive film material is an element selected from Al, Cr, Ta, Ti, Mo, W, Nd, and Sc. Examples of the film include an alloy containing the above elements, an alloy film containing a combination of the above elements, etc. It can be obtained.

[0129] For example, a single layer structure of titanium film as a conductive film, or a two-layer structure of titanium film stacked on an aluminum film In addition, a Ti film can be used as a conductive film, and a N film can be stacked on the Ti film. A three-layer structure consisting of an aluminum (Al-Nd) film containing d and a Ti film formed on top of it. The conductive film may have a single layer structure of an aluminum film containing silicon.

[0130] Next, a photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching. The source or drain electrode layer 105, the second terminal 122, the first terminal 123, and the second terminal 124 are removed. A conductive layer 128 is formed to connect to the terminal 121. The second terminal 122 is connected to the source wiring ( The source electrode layer or drain electrode layer 105 is electrically connected to a source wiring including the source electrode layer or drain electrode layer 105 .

[0131] a photolithography process is performed on the In-Sn-O-based oxide semiconductor layer containing SiOx; A resist mask is formed. Using the mask, an In-Sn-O oxide semiconductor containing SiOx is deposited. The conductor layer and the In-Sn-O-based oxide semiconductor layer are etched to form an In-Sn layer containing SiOx. an In—Sn—O-based oxide semiconductor layer 103; an In—Sn—O-based oxide semiconductor layer 104; an In—Sn—O In addition, the In—Sn—O-based oxide semiconductor layer 110 containing SiOx is formed. The semiconductor layer 103 is only partially etched, forming a semiconductor layer having a groove (recess). The Sn—O-based oxide semiconductor layer 104 functions as a source region or a drain region, and the In—S The nO-based oxide semiconductor layer 110 functions as a source region or a drain region and a pixel electrode. .

[0132] In the above steps, the pixel portion is covered with an In—Sn—O-based oxide semiconductor layer 103 containing SiOx. The thin film transistor 170 and the In-Sn-O system oxide not containing SiOx are used as the panel forming region. A semiconductor device having a pixel electrode made of a nitride semiconductor layer can be fabricated. Equivalent to 13.

[0133] Also, a resist having regions of multiple thicknesses (typically two types) formed by a multi-tone mask is used. By using a resist mask, the number of resist masks can be reduced, which simplifies the process and reduces Cost reduction is possible.

[0134] Next, the protective insulating layer 107 is formed to cover the thin film transistor 170. are silicon nitride films, silicon oxide films, silicon oxynitride films obtained by sputtering or the like. A film, an aluminum oxide film, a tantalum oxide film, or the like can be used.

[0135] Next, a photolithography process is performed to form a resist mask, and the protective insulating layer 107 is By etching, the pixel electrode region of the In—Sn—O based oxide semiconductor layer 110 is exposed. In addition, the etching here creates a contact hole that reaches the second terminal 122, and the conductive layer 12 A contact hole reaching up to 8 is also formed.

[0136] The conductive layer 128 directly connected to the first terminal 121 functions as an input terminal of the gate wiring. The second terminal 122 functions as an input terminal for the source line. This is a terminal electrode for connection.

[0137] 11(A1) and 11(A2) are plan views of the gate wiring terminal portion at this stage, and The cross-sectional views are shown in Fig. 11(A1) and Fig. 11(A2) along the line E1-E2. In FIG. 11(A1), the protective insulating film 154 is removed and exposed. The conductive layer 153 is a terminal electrode for connection that functions as an input terminal. In (A1), the terminal portion has a first terminal 151 made of the same material as the gate wiring. The source wiring is connected to a conductive layer 153 made of the same material as the source wiring, and is electrically connected. The contact portion between the conductive layer 128 and the first terminal 121 shown in FIG. 12 is the same as that shown in FIG. 11(A). 1) corresponds to the portion where the conductive layer 153 and the first terminal 151 are in contact.

[0138] 11(B1) and 11(B2) are the same as the source wiring terminal portion shown in FIG. 12(C). 11(a) and 11(b) show a plan view and a cross-sectional view of different source wiring terminal portions, respectively. B1) corresponds to a cross-sectional view taken along the line F1-F2 in FIG. 11(B2). In this case, the second terminal 150 exposed by removing the protective insulating film 154 is used as an input terminal. In addition, in FIG. 11(B1), the terminal portion is a terminal electrode for connection. The electrode layer 156, which is made of the same material as the source wiring, is electrically connected to the second The electrode layer 156 overlaps the second terminal 150 via the gate insulating layer 152. 0, and the electrode layer 156 is at a different potential from the second terminal 150, e.g. If you set it to floating, GND, 0V, etc., you can reduce capacitance or static electricity for noise prevention. Capacities for countermeasures can be formed.

[0139] A plurality of gate wirings, source wirings, and capacitance wirings are provided depending on the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, and The second terminal, the third terminal with the same potential as the capacitance wiring, and so on are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0140] In this way, a thin film transistor 170, which is a bottom gate type n-channel thin film transistor, is formed. , a pixel portion having a pixel electrode and a storage capacitor, and a terminal portion can be completed. A driving circuit can also be formed on the same substrate. An active matrix display device is formed by arranging pixels in a matrix. For convenience, in this specification, such a substrate is referred to as This is called an active matrix substrate.

[0141] When manufacturing an active matrix liquid crystal display device, an active matrix substrate a liquid crystal layer is provided between the active matrix substrate and an opposing substrate on which an opposing electrode is provided; The common electrode is electrically connected to the counter electrode provided on the counter substrate. A fourth terminal electrically connected to the common electrode is provided on the active matrix substrate. This fourth terminal is used to set the common electrode to a fixed potential, such as GND or 0V. This is a terminal for connecting the

[0142] Furthermore, the present invention is not limited to the pixel configuration of FIG. 13, and examples of plan views different from FIG. 13 are shown in FIG. In FIG. 31, no capacitance wiring is provided, and the pixel electrode area is connected to the gate wiring of the adjacent pixel. This is an example in which a storage capacitor is formed by stacking an insulating film and a gate insulating layer therebetween. The third terminal connected to the line and the capacitance line can be omitted. The same parts as those in FIG. 13 will be described using the same reference numerals.

[0143] In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0144] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, which can cause afterimages. In order to improve the moving image characteristics of the LCD device, There is a driving technique called black insertion, which displays black every other frame.

[0145] In addition, the vertical synchronization frequency is set to 1.5 times the normal frequency, preferably 2 times or more, to improve the video characteristics. There is also a driving technology called double speed driving that improves the image quality.

[0146] In addition, in order to improve the video characteristics of the LCD display, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode) light source or multiple EL light sources, etc., and a surface light source is formed. There is also a driving technology that drives each light source to light intermittently within one frame period. Therefore, three or more types of LEDs may be used, or white-emitting LEDs may be used. Since multiple LEDs can be controlled, the LE can be switched in accordance with the timing of the optical modulation of the liquid crystal layer. This driving technology can also synchronize the timing of the LEDs to be turned off. This is especially useful when displaying images with a large proportion of black areas occupying the entire screen. This can reduce power consumption.

[0147] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the past.

[0148] By forming the thin film transistor using an oxide semiconductor, the manufacturing cost can be reduced. This can be done.

[0149] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0150] (Embodiment 8) In a display device, which is an example of a semiconductor device, at least a part of a driver circuit and a An example of manufacturing a thin film transistor disposed in a pixel portion will be described below.

[0151] The thin film transistors arranged in the pixel area have SiOx in the semiconductor layer with the channel formation region. an In-Sn-O based oxide semiconductor layer containing SiOx in the source region and the drain region; The semiconductor layer is an In—Sn—O-based oxide semiconductor layer formed according to any of Embodiments 1 to 7. Since the thin film transistors shown in Embodiments 1 to 7 are n-channel TFTs, Among the circuits, a part of the driver circuit can be configured with an n-channel TFT. It is formed on the same substrate as the transistor.

[0152] FIG. 1 shows an example of a block diagram of an active matrix liquid crystal display device, which is an example of a semiconductor device. The display device shown in FIG. 14(A) is a display device having a display element on a substrate 5300. A pixel portion 5301 having a plurality of pixels, a scanning line driver circuit 5302 for selecting each pixel, and a scanning line driver circuit 5303 for selecting each pixel. and a signal line driver circuit 5303 for controlling input of a video signal to the pixel.

[0153] The thin film transistors described in Embodiments 1 to 7 are n-channel TFTs. A signal line driver circuit configured with channel type TFTs will be described with reference to FIG.

[0154] The signal line driver circuit shown in FIG. 15 includes a driver IC 5601 and a group of switches 5602_1 to 5602_56. 02_M, a first wiring 5611, a second wiring 5612, a third wiring 5613 and a wiring 56 Each of the switch groups 5602_1 to 5602_M includes: A first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor It has a transistor 5603c.

[0155] The driver IC 5601 is connected to a first wiring 5611, a second wiring 5612, and a third wiring 5613. and are connected to the wirings 5621_1 to 5621_M. 5602_M are connected to the first wiring 5611, the second wiring 5612, and the third wiring 561 3 and wiring 5621_1 to 5621_5 corresponding to the switch groups 5602_1 to 5602_M, respectively. Each of the wirings 5621_1 to 5621_M is connected to the first A thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor For example, the wiring 5621 in the Jth column is connected to three signal lines via a resistor 5603c. _J (one of the wirings 5621_1 to 5621_M) is connected to the switch group 5602 The first thin film transistor 5603a, the second thin film transistor 5603b, and and the third thin film transistor 5603c, the signal line Sj-1, the signal line Sj, the signal line S j+1 is connected to the

[0156] The first wiring 5611, the second wiring 5612, and the third wiring 5613 are each connected to a signal line. The number is entered.

[0157] It is desirable that the driver IC 5601 be formed on a single crystal substrate. The switch groups 5602_1 to 5602_M are formed on the same substrate as the pixel section. Therefore, the driver IC 5601 and the switch group 5602_1 to 5602_ It is recommended to connect to M via an FPC or similar.

[0158] Next, the operation of the signal line driver circuit shown in FIG. 15 will be described with reference to the timing chart of FIG. The timing chart in FIG. 16 is explained with reference to the timing chart when the i-th scanning line Gi is selected. Furthermore, the timing chart shows the selection period of the i-th scanning line Gi. is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, when a scanning line of another row is selected, the signal line driving circuit of FIG. In this case, the same operation as in FIG. 16 is performed.

[0159] In the timing chart of FIG. 16, the wiring 5621_J in the Jth column is connected to the first thin-film transistor. a second thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor 560 When connected to signal line Sj-1, signal line Sj, and signal line Sj+1 via 3c It shows.

[0160] In the timing chart of FIG. 16, the timing at which the i-th scanning line Gi is selected, The on / off timing 5703a of the first thin film transistor 5603a, The on / off timing 5703b of the third thin film transistor 56 The on / off timing of 03c is input to 5703c and the J-th row wiring 5621_J. Illustrated is signal 5721_J.

[0161] The wirings 5621_1 to 5621_M are connected to the first sub-selection period T1 and the second sub-selection period T2. In the first sub-selection period T2 and the third sub-selection period T3, different video signals are input. For example, the video signal input to the wiring 5621_J in the first sub-selection period T1 is The signal is input to the signal line Sj-1 and input to the wiring 5621_J in the second sub-selection period T2. The video signal to be output is input to the signal line Sj, and the signal is output to the wiring 5621 during the third sub-selection period T3. The video signal input to the first sub-selection period is input to the signal line Sj+1. During the period T1, the second sub-selection period T2, and the third sub-selection period T3, the wiring 5621_ The video signals input to J are Data_j-1, Data_j, and Data_j+ Let's say it's 1.

[0162] As shown in FIG. 16, in the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c At this time, Data_j-1 input to the wiring 5621_J is turned off. The signal is input to the signal line Sj-1 via the transistor 5603a. Second sub-selection period T2 In this case, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a The third thin film transistor 5603c is turned off. The output Data_j is input to the signal line Sj via the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first The first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the third thin film transistor 56 It is input to the signal line Sj+1 via 03c.

[0163] From the above, the signal line driver circuit in FIG. 15 can achieve the following by dividing one gate selection period into three. During one gate selection period, a video signal is input from one wiring 5621 to three signal lines. Therefore, the signal line driver circuit of FIG. The number of connections between the substrate on which the display is mounted and the substrate on which the pixel section is formed is reduced to about one-third of the number of signal lines. By reducing the number of connections to about one-third, the signal line driver circuit of FIG. This can improve productivity and yield.

[0164] As shown in Figure 15, one gate selection period is divided into multiple sub-selection periods, and multiple sub-selection periods are During each selection period, a video signal is input from one line to each of multiple signal lines. As long as this can be achieved, there are no limitations on the arrangement, number, driving method, etc. of the thin film transistors.

[0165] For example, three or more signal lines are connected to one wiring in each of three or more sub-selection periods. When a video signal is input to each, a thin film transistor and a thin film transistor are controlled. However, it is necessary to divide one gate selection period into four or more sub-selection periods. Therefore, one gate selection period is divided into two or Preferably, it is divided into three sub-selection periods.

[0166] As another example, as shown in the timing chart of FIG. 17, one selection period is precharged. The first sub-selection period Tp, the first sub-selection period T1, the second sub-selection period T2, and the third selection period T3 are Furthermore, in the timing chart of FIG. 17, the scanning line Gi of the i-th row is selected. the timing at which the first thin film transistor 5603a is turned on and off; a, the on / off timing 5803b of the second thin film transistor 5603b, The on / off timing 5803c of the membrane transistor 5603c and the J-th column wiring 562 17 shows the signal 5821_J input to the precharge During the period Tp, the first thin film transistor 5603a and the second thin film transistor 5603 At this time, the input to the wiring 5621_J is turned on. The input precharge voltage Vp is applied to the first thin film transistor 5603a, the second thin film transistor 5603b, and the and the signal line Sj- 1, signal line Sj, and signal line Sj+1. The thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor At this time, the membrane transistor 5603c is turned off. a_j-1 is input to the signal line Sj-1 via the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor The third thin film transistor 5603a and the third thin film transistor 5603c are turned off. Data_j input to the wiring 5621_J is input to the second thin film transistor 5603b. During the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5 At this time, Data_j+1 input to the wiring 5621_J is The signal is input to the signal line Sj+1 via the third thin film transistor 5603c.

[0167] From the above, the signal line driver circuit of FIG. 15 to which the timing chart of FIG. 17 is applied By providing a precharge selection period before the block selection period, the signal lines can be precharged. This allows for high-speed writing of video signals to the pixels. 16 are denoted by the same reference numerals, and the same parts or similar functions are shown. A detailed description of the portion having the symbol will be omitted.

[0168] The configuration of the scanning line driving circuit will be described. The scanning line driving circuit includes a shift register, a buffer, and a In some cases, a level shifter may be included. In the circuit, a clock signal (CLK) and a start pulse signal (SP) are input to the shift register. ) is input, the selection signal is generated. The generated selection signal is The signal is buffered and amplified in the scanning line and then supplied to the corresponding scanning line. The gate electrodes of the transistors are connected. Since they must all be turned on at the same time, the buffer must be able to pass a large current. It is used.

[0169] One form of a shift register used as part of a scanning line driving circuit will be explained with reference to FIGS. 18 and 19. I will explain.

[0170] The circuit configuration of the shift register is shown in Figure 18. The shift register shown in Figure 18 is a flip-flop. It consists of multiple flip-flops 5701_1 to 5701_n. A first clock signal, a second clock signal, a start pulse signal, and a reset signal are input. It works as it is.

[0171] The connection relationship of the shift register in Fig. 18 will be explained. The shift register in Fig. 18 has i-stage Flip-flop 5701_i (flip-flop 5701_1~5701_n) In either case, the first wiring 5501 shown in FIG. 19 is connected to the seventh wiring 5717_i-1. 19 is connected to the seventh wiring 5717_i+1. 19 is connected to the seventh wiring 5717_i, and The sixth wiring 5506 is connected to the fifth wiring 5715 .

[0172] In addition, the fourth wiring 5504 shown in FIG. 19 is the second wiring in the odd-numbered flip-flops. 5712, and in the even-numbered flip-flops, it is connected to the third wiring 5713. The fifth wiring 5505 shown in FIG.

[0173] However, the first wiring 5501 shown in FIG. 19 of the first-stage flip-flop 5701_1 is 19 of the n-th stage flip-flop 5701_n. The second wiring 5502 is connected to the sixth wiring 5716 .

[0174] The first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 57 16 can be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fourth wiring 5714 and the fifth wiring 5715 are respectively connected to the first power supply line and the This may also be called the power line 2.

[0175] Next, the details of the flip-flop shown in FIG. 18 are shown in FIG. 19. The flip-flop includes a first thin film transistor 5571, a second thin film transistor 5572, A third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor a sixth thin film transistor 5575, a sixth thin film transistor 5576, a seventh thin film transistor 5577, and and an eighth thin film transistor 5578. A second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor a fifth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, The seventh thin film transistor 5577 and the eighth thin film transistor 5578 are n-channel A transistor in which the gate-source voltage (Vgs) exceeds the threshold voltage (Vth) When this occurs, the device is in a conductive state.

[0176] Next, the connection configuration of the flip-flop shown in FIG. 18 will be described below.

[0177] A first electrode (either a source electrode or a drain electrode) of the first thin film transistor 5571 is connected to a fourth wiring 5504, and a second electrode (source) of the first thin film transistor 5571 is connected to a The other of the source electrode and the drain electrode is connected to a third wiring 5503 .

[0178] A first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506, and A second electrode of the thin film transistor 5572 is connected to a third wiring 5503 .

[0179] A first electrode of the third thin film transistor 5573 is connected to a fifth wiring 5505. The second electrode of the thin film transistor 5573 is the gate electrode of the second thin film transistor 5572. , and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505. will be done.

[0180] A first electrode of the fourth thin film transistor 5574 is connected to a sixth wiring 5506, and The second electrode of the thin film transistor 5574 is the gate electrode of the second thin film transistor 5572. , and the gate electrode of the fourth thin film transistor 5574 is connected to the first thin film transistor 5 It is connected to the gate electrode of 571.

[0181] A first electrode of the fifth thin film transistor 5575 is connected to a fifth wiring 5505. The second electrode of the thin film transistor 5575 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501. will be done.

[0182] A first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506. The second electrode of the thin film transistor 5576 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the sixth thin film transistor 5576 is connected to the second thin film transistor 5 It is connected to the gate electrode of 572.

[0183] A first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506. The second electrode of the thin film transistor 5577 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502. A first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506. The second electrode of the eighth thin film transistor 5578 is connected to the gate of the second thin film transistor 5572. The gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 550. Connected to 1.

[0184] The gate electrode of the first thin film transistor 5571 and the gate electrode of the fourth thin film transistor 5574 the gate electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor The connection point of the second electrode of the seventh thin film transistor 5576 and the second electrode of the seventh thin film transistor 5577 is Further, the gate electrode of the second thin film transistor 5572, the gate electrode of the third thin film transistor 5573, and the gate electrode of the third thin film transistor 5574 are connected to the gate electrode of the second thin film transistor 5575. a second electrode of the fourth thin film transistor 5573; a second electrode of the fourth thin film transistor 5574; The gate electrode of the sixth thin film transistor 5576 and the gate electrode of the eighth thin film transistor 5578 The connection point of the two electrodes is designated as node 5544.

[0185] The first wiring 5501, the second wiring 5502, the third wiring 5503 and the fourth wiring 5504 are 504 are referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fifth wiring 5505 may be connected to a first power supply line, and the sixth wiring 5506 may be connected to a second power supply line. It can also be called a line.

[0186] In addition, the signal line driver circuit and the scanning line driver circuit are not limited to the n-channel TFTs shown in Embodiment 1. The n-channel TFT shown in Embodiment 1 can also be manufactured by Because of the high mobility, it is possible to increase the driving frequency of the driving circuit. The n-channel TFT shown in form 1 has a reduced parasitic capacitance due to the source region or drain region. For example, in the n-channel MOS transistor shown in the first embodiment, The scanning line driver circuit using panel-type TFTs can operate at high speed, so It is also possible to increase the frequency or insert a black screen. .

[0187] Furthermore, the channel width of the transistor of the scanning line driving circuit can be increased, and multiple scanning lines can be formed. By arranging the drive circuit, it is possible to achieve an even higher frame frequency. When multiple scanning line driving circuits are arranged, the scanning line driving circuits for driving the even-numbered scanning lines are The circuit for driving the odd-numbered scanning lines is placed on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is placed on the other side. By placing multiple If signals are output to the same scanning line by the scanning line driving circuit, it is advantageous for increasing the size of the display device. do.

[0188] In addition, when an active matrix light-emitting display device, which is an example of a semiconductor device, is manufactured, At least one pixel is provided with a plurality of thin film transistors, so that multiple scanning line driving circuits are required. An example of a block diagram of an active matrix light emitting display device is shown in FIG. 4(B).

[0189] The light-emitting display device shown in FIG. 14B has a plurality of pixels each having a display element over a substrate 5400. A pixel portion 5401 for selecting each pixel, a first scanning line driver circuit 5402 for selecting each pixel, and a second scanning line driver circuit 5403 for selecting each pixel. A driver circuit 5404 and a signal line driver circuit 5405 for controlling the input of a video signal to a selected pixel 403 and

[0190] In the case where a video signal input to a pixel of the light-emitting display device shown in FIG. 14(B) is in a digital format, When a pixel is turned on, it emits light or does not emit light by switching the transistor on or off. Therefore, gray scale display can be performed using area gray scale or time gray scale. The stacked gray scale method divides one pixel into multiple sub-pixels, and each sub-pixel is independently driven based on a video signal. The time gray scale method is a driving method that displays gray scales by moving the pixel. This is a driving method that displays gradation by controlling the period during which the light is turned on.

[0191] Light-emitting elements have a higher response speed than liquid crystal elements, making them more suitable for time gray scale modulation than liquid crystal elements. Specifically, when displaying using the time gray scale method, one frame period is divided into multiple subframes. Then, in accordance with the video signal, the light emitting element of the pixel is By dividing the period into multiple subframes, The total length of the period during which pixels actually emit light during one frame is controlled by the video signal. It is possible to control the brightness and display gradation.

[0192] In the light-emitting display device shown in FIG. 14B, two switching TFTs are provided for one pixel. When the first scanning line is connected to the gate of one of the switching TFTs, The signal to be output is generated by the first scanning line driver circuit 5402, and the gate of the other switching TFT is A signal input to the second scanning line, which is a wiring, is generated by a second scanning line driver circuit 5404. The example shows a signal input to the first scanning line and a signal input to the second scanning line. Both of these may be generated by one scanning line driving circuit. The number of switching TFTs in a device determines the operation of the switching element. It is possible that a plurality of scanning lines are used for each pixel. The signals input to the scanning line driver circuit 100 may all be generated by one scanning line driver circuit, or may be generated by a plurality of scanning line drivers. It may be generated by an automatic circuit.

[0193] In addition, in the light-emitting display device, the driver circuit may be configured with an n-channel TFT. A part of the driver circuit can be formed on the same substrate as the thin film transistor of the pixel portion. In addition, the signal line driver circuit and the scanning line driver circuit may be formed by using the n-channel TFTs shown in Embodiments 1 to 7. It is also possible to produce it using only FT.

[0194] The above-mentioned driving circuit is not limited to liquid crystal display devices and light-emitting display devices, but may also be used in It may also be used in electronic paper, which uses electrically connected elements to drive electronic ink. Electronic paper is also called an electrophoretic display (electrophoretic display), and has the same properties as paper. The advantages are readability, low power consumption compared to other display devices, and the possibility of making them thin and light. It has points.

[0195] Electrophoretic displays can be of various forms, but the first particle has a positive charge. A microcapsule containing a negatively charged particle and a second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particle and the second particle have different colors (colorless). (including

[0196] Thus, electrophoretic displays allow materials with high dielectric constants to migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. Electrophoretic displays do not require polarizing plates or opposing substrates, which are necessary for display devices, and are half the thickness and weight. Decrease.

[0197] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0198] Furthermore, the microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. By applying an electric field to the cell, display can be performed. An In-Sn-O-based oxide semiconductor layer containing SiOx as a conductor layer, a source region, and a drain region an In—Sn—O-based oxide semiconductor layer not containing SiO x in the semiconductor substrate; The active matrix substrate obtained by the thin film transistor formed by can be done.

[0199] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof Just use it.

[0200] Through the above steps, a highly reliable display device can be manufactured as a semiconductor device.

[0201] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0202] (Embodiment 9) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. A semiconductor device (also called a display device) having a display function can be manufactured. The transistor and part or the whole of the driver circuit are formed on the same substrate as the pixel section, On-panel formation is possible.

[0203] The display device includes a display element. The display element includes a liquid crystal element (also called a liquid crystal display element), a light-emitting element, A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by the light emitted from the light source, specifically inorganic EL (Electroluminescent) Also, electronic inks and other electronic devices are also included. A display medium whose contrast changes due to mechanical action can also be applied.

[0204] The display device also includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, the display device is manufactured by a method for manufacturing the display device. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is , each of the plurality of pixels includes means for supplying a current to the display element.

[0205] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0206] The appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described with reference to FIG. 22 shows the channel shown in the first embodiment formed on the first substrate 4001. The semiconductor layer having the formation region is an In-Sn-O-based oxide semiconductor layer containing SiOx, and the source region is The thin film transistor includes an In-Sn-O-based oxide semiconductor layer that does not contain SiOx in the drain and the drain regions. The transistors 4010 and 4011 and the liquid crystal element 4013 are disposed between the second substrate 4006 and the 22(B) is a plan view of the panel sealed with the sealant 4005. A1) corresponds to the cross section at MN in (A2).

[0207] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0208] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 22(A2) is This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0209] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 22B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 The following are examples:

[0210] The thin film transistors 4010 and 4011 are made of a semiconductor layer having a channel forming region, and are made of SiOx an In-Sn-O-based oxide semiconductor layer containing SiOx in the source and drain regions; The thin film transistor described in Embodiment 1 including an In-Sn-O-based oxide semiconductor layer is applied. In addition, any of the thin film transistors described in Embodiments 2 to 7 may be used. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors. It's Jista.

[0211] In addition, the liquid crystal element 4013 has a pixel electrode layer made of In-S, which does not contain SiOx. The nO-based oxide semiconductor layer 4030 is a source region or a drain region of the thin film transistor 4010. It also serves as a gate region, electrically connecting the thin film transistor 4010 and the liquid crystal element 4013. The counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The In-Sn-O based oxide semiconductor layer 4030 not containing SiOx and the counter electrode layer 4 The portion where the liquid crystal layer 4008 overlaps with the liquid crystal element 4013. The In-Sn-O based oxide semiconductor layer 4030 and the counter electrode layer 4031 are not made of SiOx. Insulating layers 4032 and 4033 are provided, each of which functions as an alignment film. A liquid crystal layer 4008 is sandwiched between them via a film 033.

[0212] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Aluminum foil can also be used with PVF film or polyester film. A sheet sandwiched between films can also be used.

[0213] 4035 is a columnar spacer obtained by selectively etching the insulating film. An In—Sn—O-based oxide semiconductor layer 4030 not containing SiOx and a counter electrode layer 4031 The spacers are provided to control the distance between the cells (cell gap). The counter electrode layer 4031 may be formed on the same substrate as the thin film transistor 4010. The common connection portion is electrically connected to a common potential line disposed between the pair of substrates. The counter electrode layer 4031 and the common potential line are electrically connected via the conductive particles. The conductive particles are contained in the sealing material 4005.

[0214] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 10 μs to It is optically isotropic, requiring no alignment treatment, and has little viewing angle dependency. stomach.

[0215] In addition to transmissive LCD devices, this can also be applied to reflective LCD devices and semi-transmissive LCD devices. can.

[0216] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a colored layer and a display element are provided on the inner side. In this example, the polarizing plate is provided on the inner side of the substrate. In addition, the laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment, and the materials of the polarizing plate and the colored layer and The conditions may be appropriately set depending on the manufacturing process conditions. A light film may also be provided.

[0217] In addition, in order to reduce the surface irregularities of the thin film transistor and improve the reliability of the thin film transistor, To improve the performance, an insulating layer is formed on the thin film transistor to function as a planarizing insulating film and a protective film. The protective film may be resistant to pollutants and impurities such as organic matter, metal matter, and water vapor floating in the air. The purpose of the protective film is to prevent the intrusion of foreign substances, and a dense film is preferable. , silicon oxide film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, nitrogen a single layer of an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film; Although an example in which the protective film is formed by sputtering is shown, the method is not particularly limited and various methods can be used. The method may be as follows.

[0218] Here, an insulating layer 4020 having a stacked structure is formed as a protective film. As the first layer of the silicon dioxide film, a silicon dioxide film is formed by sputtering. By using the above, it is possible to prevent hillocks in the aluminum film used as the source electrode layer and the drain electrode layer. It is effective in stopping.

[0219] In addition, an insulating layer is formed as the second layer of the protective film. Then, a silicon nitride film is formed by sputtering. When a silicon nitride film is used as a protective film, Mobile ions such as thorium penetrate into the semiconductor region and change the electrical properties of the TFT. can be suppressed.

[0220] The planarization insulating film can be made of polyimide, acrylic, benzocyclobutene, polyamide, or epoxy. In addition to the above organic materials, low dielectric constant materials (lo wk materials), siloxane resin, PSG (phosphorus glass), BPSG (boron phosphorus glass) ) etc. can be used.

[0221] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0222] The method for forming the planarizing insulating film is not particularly limited, and may be a sputtering method, an SOG method, or the like depending on the material. Spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A coater or the like can be used.

[0223] The counter electrode layer 4031 is made of indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide A conductive material having light-transmitting properties, such as indium tin oxide doped with silicon oxide, may be used. This can be done.

[0224] The counter electrode layer 4031 is made of a conductive material containing a conductive polymer. The pixel electrode formed using the conductive composition can be formed by The resistance is 10,000Ω / □ or less, and the transmittance at a wavelength of 550 nm is 70% or more. It is also preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm or more. Preferably, it is below.

[0225] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0226] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0227] The terminal electrode 4016 is made of the same conductive film as the source wiring layer of the thin film transistors 4010 and 4011. It is formed by

[0228] The terminal electrode 4016 is electrically connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. are electrically connected.

[0229] In FIG. 22, a signal line driver circuit 4003 is separately formed and mounted on a first substrate 4001. The present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0230] FIG. 23 shows a semiconductor device using a TFT substrate 2600 fabricated by the fabrication method disclosed herein. 1 shows an example of a semiconductor device configured as a liquid crystal display module.

[0231] FIG. 23 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate is fixed by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate and the bonding material 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is required for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. The wiring board 2609 is connected to the wiring circuit section 2608 of the TFT substrate 2600, and the controller It also incorporates external circuits such as a polarizing plate and a power supply circuit. The layers may be laminated with a retardation film interposed therebetween.

[0232] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) can be used.

[0233] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0234] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0235] (Embodiment 10) An example of the semiconductor device is electronic paper.

[0236] Figure 30 shows an active matrix electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device is the thin film transistor shown in Embodiment 1. The semiconductor layer with the channel formation region is made of In-Sn- containing SiOx. O-based oxide semiconductor layer, In-Sn-O containing no SiOx in the source and drain regions The thin film transistor includes a SiO 2 -based oxide semiconductor layer. The transistor can also be applied as the thin film transistor 581 of this embodiment.

[0237] The electronic paper in Figure 30 is an example of a display device that uses the twisting ball display method. The ball display method uses spherical particles painted in black and white between the electrode layers used as display elements. The display is controlled by controlling the orientation of the spherical particles by creating a potential difference between the electrode layers. This is how to do it.

[0238] The thin film transistor 581 provided on the substrate 580 is a thin film transistor of a bottom gate structure. and a pixel electrode layer made of In, which does not contain SiOx, and which serves as both a source region or a drain region and a pixel electrode layer. The insulating layer 585 is in contact with the Sn—O-based oxide semiconductor layer 587 through an opening formed in the insulating layer 585. , and are electrically connected to the In—Sn—O-based oxide semiconductor layer 587 that does not contain SiOx. Between the electrode layer 588 there is a black area 590a and a white area 590b, and the area is filled with liquid. A spherical particle 589 is provided that includes a cavity 594 filled therein, and the spherical particle 589 The periphery of the electrode layer 588 is filled with a filler 595 such as resin (see FIG. 30). The electrode layer 588 corresponds to an electrode (counter electrode). The common connection portion is electrically connected to a common potential line disposed between the pair of substrates. The electrode layer 588 can be electrically connected to a common potential line through the conductive particles. .

[0239] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm are used. When an electric field is applied to the microcapsules by the pixel electrode layer and the common electrode layer, the white particles When the black particles move in the opposite direction, white or black can be displayed. The display element used is an electrophoretic display element, which is generally called electronic paper. Since electrophoretic display elements have a higher reflectivity than liquid crystal display elements, auxiliary lights are not required. It consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the , a semiconductor device with a display function (simply a display device, or a semiconductor device equipped with a display device) from a radio wave source Even if the device (also called the body device) is moved away, the displayed image can be saved. become.

[0240] Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured. .

[0241] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0242] (Embodiment 11) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that utilizes electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0243] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0244] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0245] FIG. 20 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0246] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. The present study is an n-channel semiconductor device using an In-Sn-O-based oxide semiconductor layer containing SiOx as the channel formation region. An example in which two capacitor-type transistors are used in one pixel is shown.

[0247] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, It has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. It is electrically connected to a common potential line formed on the substrate.

[0248] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0249] The capacitor element 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. The gate capacitance of the driving transistor 6402 is determined by the channel region A capacitance may be formed between the gate electrode and the transistor.

[0250] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is connected to The driving transistor 6402 is either fully on or off. A video signal is input, that is, the driving transistor 6402 is operated in a linear region. The driving transistor 6402 is operated in a linear region, so that the voltage of the driving transistor 6402 is higher than the voltage of the power supply line 6407. A high voltage is applied to the gate of the driving transistor 6402. The signal line 6405 is connected to A voltage equal to or greater than (power supply line voltage+Vth of the driving transistor 6402) is applied.

[0251] Furthermore, when analog grayscale driving is performed instead of digital time grayscale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 20 can be used.

[0252] When analog gradation driving is performed, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or greater than the forward voltage of the light emitting element 64 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and It should be noted that the driving transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The potential of the light emitting element is made higher than the gate potential of the capacitor 6402. A current corresponding to a video signal is passed through 6404, enabling analog gradation driving.

[0253] Note that the pixel configuration shown in Fig. 20 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0254] Next, the configuration of the light emitting element will be described with reference to FIG. 21. Here, the driving TFT is The cross-sectional structure of a pixel will be explained using the example of the type shown in Figures 21(A), (B), and (C). The TFTs 7001, 7011, and 7021, which are driving TFTs used in semiconductor devices, are actually A semiconductor having a channel formation region that can be manufactured in the same manner as the thin film transistor shown in the first embodiment. The layer is an In-Sn-O-based oxide semiconductor layer containing SiOx, and the source and drain regions are S The thin film transistor includes an In-Sn-O-based oxide semiconductor layer that does not contain iOx. The thin film transistors shown in Embodiments 2 to 7 are referred to as TFTs 7001, 7011, and 7021. It can also be applied as follows.

[0255] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and top emission. There are light-emitting elements with a double-sided emission structure that emits light from the side, and the pixel configuration is It can also be applied to optical elements.

[0256] A light emitting element with a top emission structure will be described with reference to FIG.

[0257] In FIG. 21(A), a TFT 7001 which is a driving TFT is an n-type, and a light emitting element 7002 emits light. FIG. 21(A) shows a cross-sectional view of a pixel when incident light exits the anode 7005 side. A cathode 7003 of the light emitting element 7002 and a TFT 7001 which is a driving TFT are electrically connected. A cathode 7003, a light-emitting layer 7004, and an anode 7005 are laminated in this order on a reflective film 7006. The cathode 7003, which is an In-Sn-O based oxide semiconductor film that does not contain SiOx, The light emitting element 7 The reflective film 7006 can be made of various materials as long as it is a film that reflects light. Examples include Ca, Al, CaF, MgAg, and AlLi. The light-emitting layer 7004 may be composed of a single layer or a plurality of layers stacked together. If it is made up of multiple layers, it should be made up of I that does not contain SiOx. An electron injection layer, an electron transport layer, and a light-emitting layer are formed on the cathode 7003, which is an n-Sn-O-based oxide semiconductor film. The hole transport layer and the hole injection layer are laminated in this order. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a light-transmitting conductive material, for example, oxide. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, and indium with silicon oxide added. A light-transmitting conductive film such as an aluminum tin oxide film may also be used.

[0258] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in FIG. 21(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as shown by the mark.

[0259] Next, a light emitting element with a bottom emission structure will be described with reference to FIG. When 011 is n-type and light emitted from the light emitting element 7012 is emitted to the cathode 7013 side, 21(B) shows a cross-sectional view of the pixel. Cathode 7013, a transparent In-Sn-O oxide semiconductor film that does not contain SiOx On top of this, a light-emitting layer 7014 of a light-emitting element 7012 and an anode 7015 are laminated in this order. The cathode 7013, which is an In-Sn-O based oxide semiconductor film containing no x, is The light emitting element 7012 has a source region or a drain region and a pixel electrode layer. When the anode 7015 is light-transmitting, a light-transmitting layer is formed on the anode so as to cover the anode. A shielding film 7016 for reflection or shielding may be formed. As in the case of 21(A), an In-Sn-O-based oxide semiconductor material that does not contain SiOx is used. The light-emitting layer 7014 can be formed of a single layer, as in FIG. The anode 701 may be formed by laminating a plurality of layers. 5 does not need to transmit light, but similar to FIG. 21(A), a conductive material having light-transmitting properties can be used. The shielding film 7016 can be formed by using, for example, a metal that reflects light. However, the material is not limited to a metal film. For example, a resin containing a black pigment may be used. It can also be done as follows.

[0260] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 21B, light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0261] Next, a light emitting element with a dual emission structure will be described with reference to FIG. In this example, a transparent SiOx-free I A light-emitting layer 7024 and an anode 7025 are formed on a cathode 7023, which is an n-Sn-O-based oxide semiconductor film. The cathode 7023 does not contain SiOx, as in the case of FIG. In-Sn-O based oxide semiconductor materials containing no SiOx can be used. The cathode 7023, which is a Sn-O based oxide semiconductor film, is It serves as both a drain region and a pixel electrode layer, and functions as an electrode of the light-emitting element 7022. The light-emitting layer 7024 may be composed of a single layer or a plurality of layers, as in FIG. The anode 7025 may be configured as a laminate of the anodes 7021 and 7022 shown in FIG. Similarly, the light-transmitting conductive material can be used.

[0262] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 is the light-emitting element 70. In the case of the pixel shown in FIG. 21C, the light emitted from the light emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0263] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0264] The thin film transistor (driving TFT) that controls the driving of the light emitting element and the light emitting element are electrically However, the current control TFT is connected between the driving TFT and the light emitting element. The configuration may be such that the power supply is connected to the power supply.

[0265] The semiconductor device is not limited to the configuration shown in FIG. 21, and may be any of the semiconductor devices disclosed in this specification. Various modifications based on the technical concept are possible.

[0266] Next, the appearance and structure of a light-emitting display panel (also referred to as a light-emitting panel), which is one mode of a semiconductor device, will be described. The cross section will be explained with reference to FIG. 24. FIG. 24 shows a thin film transistor formed on a first substrate. The flat surface of the panel is formed by sealing the transistor and the light-emitting element between the second substrate and the panel with a sealing material. 24(B) corresponds to a cross-sectional view taken along line HI in FIG. 24(A).

[0267] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0268] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 24B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45 shows an example of a thin film transistor 4509 included in a line driver circuit 4503a.

[0269] The thin film transistors 4509 and 4510 are made of a semiconductor layer having a channel formation region, and are made of SiOx an In-Sn-O-based oxide semiconductor layer containing SiOx in the source and drain regions; The thin film transistor described in Embodiment 1 including an In-Sn-O-based oxide semiconductor layer is applied. In addition, any of the thin film transistors described in Embodiments 2 to 7 may be used. The thin film transistors 4509 and 4510 are n-channel thin film transistors.

[0270] The light-emitting element 4511 has a pixel electrode made of SiOx. The In—Sn—O-based oxide semiconductor layer 4517 does not contain the In—Sn—O-based oxide semiconductor layer 4517. The semiconductor layer of the thin film transistor 4510 and the light emitting element The light-emitting element 4511 is electrically connected to the light-emitting element 4511. The light-emitting element 4511 does not contain SiOx. The stack of the In-Sn-O-based oxide semiconductor layer 4517, the electroluminescent layer 4512, and the electrode layer 4513 The layer structure is not limited to the configuration shown. The configuration of the light emitting element 4511 can be changed appropriately depending on the application.

[0271] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an In-Sn-O-based oxide semiconductor layer 4517 that does not contain SiOx. An opening is formed on the top, and the sidewall of the opening becomes an inclined surface formed with a continuous curvature. It is preferable to form it as follows.

[0272] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0273] The electrode layer 451 is formed so as to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 4511. A protective film may be formed on the insulating film 3 and the partition wall 4520. The protective film may be a silicon nitride film, a nitride oxide film, or the like. Silicon nitride films, DLC films, etc. can be formed.

[0274] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0275] The terminal electrode 4516 is electrically connected to the thin film transistors 4509 and 4510. It is formed from the same conductive film as the source wiring layer.

[0276] The terminal electrode 4516 is connected to the terminal of the FPC 4518a via an anisotropic conductive film 4519. are electrically connected.

[0277] In the case of a substrate positioned in the direction of light extraction from the light emitting element 4511, the first substrate 4 501, the second substrate 4506 must be transparent. In that case, a glass plate, a plate Light-transmitting material such as plastic board, polyester film or acrylic film Fees are used.

[0278] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's fine.

[0279] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0280] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted, and the configuration is not limited to that of FIG.

[0281] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0282] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0283] (Embodiment 12) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, trains, etc. It can be used for in-car advertising, displaying on various cards such as credit cards, etc. Examples of electronic devices are shown in Figures 25 and 26.

[0284] FIG. 25(A) shows a poster 2631 made of electronic paper. In the case of printed matter, the exchange of advertisements is done manually, but in the case of electronically By using sub-paper, the display of advertisements can be changed in a short time. The poster is designed to be able to send and receive information wirelessly. Good too.

[0285] FIG. 25(B) shows an advertisement 2632 inside a vehicle such as a train. In the case of paper-based printed matter, the advertisements are exchanged manually. By using electronic paper, it is possible to change the display of advertisements in a short time without requiring a lot of manpower. In addition, the display is stable and the image is not distorted. It may be configured to be able to receive.

[0286] 26 shows an example of an electronic book 2700. For example, the electronic book 2700 includes: It consists of two housings, housing 2701 and housing 2703. The body 2703 is integrated with a shaft 2711, and the opening and closing movement is performed around the shaft 2711. This configuration allows the device to operate like a paper book. This becomes:

[0287] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 26) and An image can be displayed on the display unit 2707 in FIG.

[0288] 26 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. It may also be configured to include a touch panel, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. That's fine.

[0289] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0290] (Embodiment 13) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable Examples include game machines, mobile information terminals, sound reproduction devices, and large game machines such as pachinko machines. do.

[0291] FIG. 27(A) shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In this case, the housing 9601 is supported by a stand 9605. This shows a configuration in which the above is supported.

[0292] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 In addition, the remote control operation device 9610 can operate the video. A display unit 9607 for displaying information output from 9610 may be provided.

[0293] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0294] FIG. 27B shows an example of a digital photo frame 9700. The photo frame 9700 has a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example, images taken with a digital camera. By displaying the image data, it can function like a normal photo frame.

[0295] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a recording medium for a digital photo frame as it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0296] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0297] FIG. 28(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 28(A) also includes a speaker unit 9884, a recording medium insertion unit 988 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and It is sufficient if the semiconductor device disclosed in the above is included, and other auxiliary equipment is appropriately provided. The portable gaming machine shown in FIG. 28(A) can be used to play the game data recorded on a recording medium. The function of reading out programs or data and displaying them on the display, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 28(A) has the function of sharing information by performing the above. The functions are not limited to these, and various functions can be provided.

[0298] FIG. 28(B) shows an example of a slot machine 9900, which is a large gaming machine. The machine 9900 has a display unit 9903 built into a housing 9901. Machine 9900 also has other operating means such as a start lever and stop switch, coin It is equipped with an insertion slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is The present invention is not limited to the above, and may be configured to include at least the semiconductor device disclosed in this specification. , and other auxiliary equipment may be provided as appropriate.

[0299] FIG. 29(A) is a perspective view showing an example of a portable computer.

[0300] The portable computer of FIG. 29(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display portion 9303 and a keyboard. The lower housing 9302 having the card 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to input data on the keyboard, the hinge unit can be opened. The user can perform input operations by looking at the display portion 9303.

[0301] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching the lower housing 9302. The lower housing 9302 has a computing function unit such as a hard disk. It has an external connection port 9305 into which a communication cable conforming to the SB communication standard is inserted. There are.

[0302] The upper housing 9301 further includes a display unit 93 that can be slid into the upper housing 9301 and stored therein. 07, which allows for a wide display screen. The orientation of the screen of the 9307 can be adjusted by the user. If it is a panel, input operations can be performed by touching a part of the retractable display section.

[0303] The display portion 9303 or the storable display portion 9307 may be a liquid crystal display panel, an organic light emitting element, or The display device uses a light-emitting display panel made of inorganic light-emitting elements.

[0304] The portable computer shown in FIG. 29(A) is configured with a receiver and the like, and can be used as a television. It is possible to receive broadcasts and display images on the display unit. The display unit 9307 is slid open while the hinge unit connecting the display unit 9307 to the body 9302 is kept closed. The entire screen is exposed by tilting the screen, and the user can watch TV broadcasts by adjusting the screen angle. In this case, the hinge unit is opened to prevent the display unit 9303 from displaying anything. It only activates the circuitry to display the TV broadcast, so it consumes the minimum amount of power. This is useful in portable computers with limited battery capacity.

[0305] FIG. 29(B) shows a portable telephone that can be worn on the user's arm like a wristwatch. FIG. 10 is a perspective view showing an example of a story.

[0306] This mobile phone includes a main body having at least a communication device with a telephone function and a battery, A band for attaching the body to the arm, and an adjustment unit 92 for adjusting the fastening state of the band to the arm 05, it is composed of a display unit 9201, a speaker 9207, and a microphone 9208.

[0307] The main body also has an operation switch 9203, which is used for power input and display switching. In addition to the switch and the switch to start shooting, there are also other switches, such as a button that starts an internet program when pressed. Each function can be assigned using the operation switch 9203. Cut.

[0308] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the display portion 9201. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 29(B) shows a display button 9202 displayed on a display unit 9201, and Input can be made by touching the screen.

[0309] The main body also contains an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. It has a camera unit 9206 with a step. Note that it is not necessary to provide a camera unit.

[0310] The mobile phone shown in FIG. 29(B) is configured with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in memory etc. It is possible to record television broadcasts in memory by using a storage device. The mobile phone shown in B) may have a function capable of collecting location information such as GPS.

[0311] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in Figure 29(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force-actuable panel.

[0312] Although FIG. 29(B) illustrates an electronic device that is worn on the arm, it is not limited to this. It is sufficient that the device has a portable shape. [Example]

[0313] In-S containing SiOx used in the semiconductor layer having the channel formation region of a thin-film transistor An nO-based oxide semiconductor film was formed, which will be described in detail below.

[0314] In-Sn-O oxide semiconductor target containing SiO2 (In2O3:SnO2:Si O2 = 85:10:5 (wt%)) was used to prepare specimens A, B, and C by sputtering. An In-Sn-O-based oxide semiconductor film containing SiO2 was prepared, and its conductivity was measured. The film formation conditions and electrical conductivities of Samples B and C are shown in Table 1.

[0315] [Table 1]

[0316] In Table 1, the oxygen flow rate ratio is the ratio of the oxygen flow rate flowed during film formation to the argon flow rate. As shown in Table 1, the conductivity of sample A with an oxygen flow rate of 4% is 4 .20E+01(4.20×10)S / cm, sample B with an oxygen flow rate of 29% is 3.76E -07(3.73×10 -7)S / cm, and sample C with an oxygen flow rate of 40% is 9.25E-1 0(9.25×10 -10 )S / cm.

[0317] From the above calculation results, the semiconductor layer having the channel formation region is made of In-Sn containing SiOx. In thin-film transistors using -O-based oxide semiconductor layers, the conductivity of the semiconductor layer is 1.6 x10 -3 S / cm or less, and even 1.3 x 10 -4 A value of S / cm or less is preferred.

[0318] Therefore, the In-Sn-O-based oxide semiconductor films containing SiO2 of Sample B and Sample C have a SiO2 content of 1.3 x10 -4 Because the conductivity is low (less than 1000 S / cm), the SiO2-containing I Fabrication of thin film transistors with good electrical characteristics using n-Sn-O oxide semiconductor films can be done.

Claims

1. an oxide semiconductor layer; a gate electrode having a two-layer structure in which a molybdenum layer is stacked on an aluminum layer; a first insulating layer provided between the oxide semiconductor layer and the gate electrode; an electrode electrically connected to the oxide semiconductor layer; an oxide layer electrically connected to the oxide semiconductor layer; a second insulating layer provided above the oxide semiconductor layer and above the electrode; the oxide semiconductor layer is provided above the gate electrode, the oxide layer has a region in contact with an upper surface of the second insulating layer and a side surface of the second insulating layer at an opening provided in a portion of the second insulating layer; the opening has a region that does not overlap with the oxide semiconductor layer, the oxide layer has a region that functions as a source region or a drain region, and a region that functions as a pixel electrode; the oxide semiconductor layer contains In and Sn, a first end of the oxide semiconductor layer extends beyond a first end of the gate electrode, and a second end of the oxide semiconductor layer extends beyond a second end of the gate electrode, in a cross-sectional view of the oxide semiconductor layer in a channel length direction.

2. an oxide semiconductor layer; a gate electrode having a two-layer structure in which a molybdenum layer is stacked on an aluminum layer; a first insulating layer provided between the oxide semiconductor layer and the gate electrode; an electrode made of a metal material electrically connected to the oxide semiconductor layer; an oxide layer electrically connected to the oxide semiconductor layer; a second insulating layer provided above the oxide semiconductor layer and above the electrode; the oxide semiconductor layer is provided above the gate electrode, the oxide layer has a region in contact with an upper surface of the second insulating layer and a side surface of the second insulating layer at an opening provided in a portion of the second insulating layer; the opening has a region that does not overlap with the oxide semiconductor layer, the oxide layer has a region that functions as a source region or a drain region, and a region that functions as a pixel electrode; the oxide semiconductor layer contains In and Sn, a first end of the oxide semiconductor layer extends beyond a first end of the gate electrode, and a second end of the oxide semiconductor layer extends beyond a second end of the gate electrode, in a cross-sectional view of the oxide semiconductor layer in a channel length direction.

3. an oxide semiconductor layer; a gate electrode having a two-layer structure in which a molybdenum layer is stacked on an aluminum layer; a first insulating layer provided between the oxide semiconductor layer and the gate electrode; an electrode electrically connected to the oxide semiconductor layer; an oxide layer electrically connected to the oxide semiconductor layer; a second insulating layer provided above the oxide semiconductor layer and above the electrode; the gate electrode extends in a first direction; the electrodes extend in a second direction intersecting the first direction; the gate electrode has a first region extending in the second direction; the oxide semiconductor layer is provided above the gate electrode, the oxide semiconductor layer has a region overlapping with the first region, the oxide layer has a region in contact with an upper surface of the second insulating layer and a side surface of the second insulating layer at an opening provided in a portion of the second insulating layer; the opening has a region that does not overlap with the oxide semiconductor layer, the oxide layer has a region that functions as a source region or a drain region, and a region that functions as a pixel electrode; the oxide semiconductor layer contains In and Sn, a first end of the oxide semiconductor layer extends beyond a first end of the gate electrode, and a second end of the oxide semiconductor layer extends beyond a second end of the gate electrode, in a cross-sectional view of the oxide semiconductor layer in a channel length direction.

4. an oxide semiconductor layer; a gate electrode having a two-layer structure in which a molybdenum layer is stacked on an aluminum layer; a first insulating layer provided between the oxide semiconductor layer and the gate electrode; an electrode made of a metal material electrically connected to the oxide semiconductor layer; an oxide layer electrically connected to the oxide semiconductor layer; a second insulating layer provided above the oxide semiconductor layer and above the electrode; the gate electrode extends in a first direction; the electrodes extend in a second direction intersecting the first direction; the gate electrode has a first region extending in the second direction; the oxide semiconductor layer is provided above the gate electrode, the oxide semiconductor layer has a region overlapping with the first region, the oxide layer has a region in contact with an upper surface of the second insulating layer and a side surface of the second insulating layer at an opening provided in a portion of the second insulating layer; the opening has a region that does not overlap with the oxide semiconductor layer, the oxide layer has a region that functions as a source region or a drain region, and a region that functions as a pixel electrode; the oxide semiconductor layer contains In and Sn, a first end of the oxide semiconductor layer extends beyond a first end of the gate electrode, and a second end of the oxide semiconductor layer extends beyond a second end of the gate electrode, in a cross-sectional view of the oxide semiconductor layer in a channel length direction.

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