METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE

Abstract

To provide a manufacturing method of a silicon carbide semiconductor device which prevents inter-layer exfoliation caused by excessive carbon when forming an ohmic contact, attains reduction of contact resistance and is capable of improving Vf and IFSM characteristics, and the silicon carbide semiconductor device.SOLUTION: A manufacturing method of a silicon carbide semiconductor device includes: a first step of selectively forming a semiconductor region of a second conductivity type on a first principal surface of a semiconductor substrate consisting of silicon carbide; a second step of forming a nickel layer on the semiconductor region; a third step of performing ion implantation of aluminum on the nickel layer; a fourth step of forming an ohmic contact layer, which performs ohmic junction, in the semiconductor region by performing heat treatment on the nickel layer in which aluminum is implanted; a fifth step of forming a first electrode which is in contact with the ohmic contact layer, the semiconductor region and the semiconductor substrate; and a sixth step of forming a second electrode on a second principal surface of the semiconductor substrate.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) semiconductors have recently been attracting attention as a semiconductor material that can be used to fabricate semiconductor devices (hereinafter referred to as silicon carbide semiconductor devices) that exceed the limits of semiconductor devices using silicon (Si) semiconductors. In particular, silicon carbide semiconductors are expected to be applied to high-voltage (e.g., 1700 V or higher) semiconductor devices, taking advantage of their characteristics of higher breakdown field strength and higher thermal conductivity compared to silicon semiconductors.

[0003] When the silicon carbide semiconductor device is a diode (hereinafter referred to as a silicon carbide diode), n - n-type drift region - Because the design specifications for the epitaxial layer can be set to a thin thickness and a high impurity concentration, silicon carbide diodes with a breakdown voltage of up to about 3300 V generally have a Schottky barrier diode (SBD) structure. The SBD structure is formed by a semiconductor substrate and a front electrode made of a metal layer provided on the front surface of the semiconductor substrate.

[0004] Typically, SBD structures have problems such as high electric field strength at the junction between the semiconductor substrate and the front electrode, which increases reverse leakage current due to electron tunneling through the Schottky barrier when a reverse voltage is applied, or increased reverse leakage current due to surface defects inherent to silicon carbide.For this reason, silicon carbide diodes have been proposed that employ a Junction Barrier Schottky (JBS) structure, which combines a Schottky junction and a pn junction on the front side of an n-type semiconductor substrate.

[0005] The structure of a conventional silicon carbide diode with a JBS structure will be described. Fig. 24 is a plan view showing the layout of a conventional silicon carbide semiconductor device as viewed from the front surface side of a semiconductor substrate. Fig. 25 is a cross-sectional view showing the cross-sectional structure taken along line A-A' in Fig. 24. Fig. 24 does not show the breakdown voltage structure of the edge termination region, or the front surface electrode and field oxide film disposed on the front surface of the semiconductor substrate.

[0006] 24 and 25 show a conventional silicon carbide semiconductor device 140 in which an SBD structure (Schottky region 104) formed by a Schottky junction between n-type semiconductor substrate 101 and Schottky metal 106 in the lowest layer of front surface electrode 114 is mixed with a JBS structure (pn diode region 103) formed by a pn junction between p-type well region 102 and n-type semiconductor substrate 101 on the front surface side of n-type semiconductor substrate 101 in active region 110. FIG. 26 is a circuit diagram of an SBD with a JBS structure. As shown in FIG. 26, the silicon carbide diode with a JBS structure has a Schottky diode 141 and a pn diode 142 connected in parallel.

[0007] In addition, for example, a nickel silicide layer 116 is formed in the pn diode region 103 to form an ohmic contact with the p-type well region 102. In Figure 24, the striped nickel silicide layer 116 extending in a direction parallel to the front surface of the n-type semiconductor substrate 101 is shown by hatching.

[0008] P-type well regions 102 are selectively provided in a surface region on the front surface of n-type semiconductor substrate 101 in active region 110. The front surface of n-type semiconductor substrate 101 is exposed between adjacent p-type well regions 102. A pn ​​junction is formed between p-type well regions 102 and n-type semiconductor substrate 101. The n-type semiconductor substrate 101 between adjacent p-type well regions 102 forms a Schottky junction with Schottky metal 106 provided on the front surface of n-type semiconductor substrate 101.

[0009] By adopting a JBS structure in which a Schottky junction and a pn junction are mixed at the junction surface between n-type semiconductor substrate 101 and front surface electrode 114 in this manner, the electric field strength at the junction surface between n-type semiconductor substrate 101 and front surface electrode 114 can be reduced, making it possible to suppress reverse leakage current to the same level as that of an FWD (Free Wheeling Diode) using a silicon semiconductor.

[0010] Front surface electrode 114 is composed of anode electrode 107 and Schottky metal 106, and cathode electrode 108 serving as a back surface electrode is provided on the back surface of n-type semiconductor substrate 101. Also, breakdown voltage structure 115 is arranged in edge termination region 130.

[0011] In a conventional method for manufacturing a silicon carbide diode with a JBS structure, the ohmic contact between the p-type well region 102 and the nickel silicide layer 116 is formed as follows: First, a nickel layer and an aluminum layer are deposited in this order on the p-type well region 102 and the n-type semiconductor substrate 101, and then low-temperature sintering is performed to form an aluminum-nickel compound layer. Next, the nickel layer remaining on the surface of the aluminum-nickel compound layer is removed, and then high-temperature sintering is performed to cause a silicide reaction between silicon atoms in the semiconductor substrate and nickel atoms in the aluminum-nickel compound layer, forming a nickel silicide (NiSi) film 116 that serves as an ohmic electrode that makes an ohmic contact with the p-type well region 102.

[0012] As a method for forming an ohmic contact, a method has been proposed in which a laminated film containing a nickel layer and an aluminum layer is formed on a p-type impurity region, and the laminated film is heat-treated to form a p-type ohmic electrode containing an alloy of nickel, aluminum, silicon, and carbon on the p-type impurity region (see, for example, Patent Document 1 below).

[0013] Furthermore, as another method for forming an ohmic contact, a method has been proposed which includes providing a p-type silicon carbide layer having a first main surface and a second main surface opposite the first main surface, and implanting ions into the p-type silicon carbide layer from the first main surface by plasma immersion ion implantation to form an implanted layer adjacent to the first main surface (see, for example, Patent Document 2 below). [Prior art documents] [Patent documents]

[0014] [Patent Document 1] Patent No. 4291875 [Patent Document 2] Patent Publication No. 2021-125685 Summary of the Invention [Problem to be solved by the invention]

[0015] Here, if a nickel silicide layer 116 (ohmic electrode) is provided between the n-type semiconductor substrate 101 and the Schottky metal 106 in contact with only the p-type well region 102 in order to improve the surge current resistance of the above-described conventional silicon carbide semiconductor device 140 (a silicon carbide diode with a JBS structure), excess carbon (C) is generated due to the formation of the silicide layer. A certain amount of excess carbon may precipitate in the form of clusters, causing problems such as delamination and breakage. Furthermore, the excess carbon also inhibits the formation of the nickel silicide layer 116, which is intended to reduce contact resistance.

[0016] For this reason, methods have been proposed that add a process to remove excess carbon or form a metal layer on the nickel layer surface that reacts with carbon to suppress carbon deposition on the metal surface. However, due to the difference in melting temperatures between nickel and the carbon-reactive metal, metal variations and stress are unevenly distributed, making it difficult to control the formation of the nickel silicide layer 116, and there are issues such as increased contact resistance due to excessive formation, making it impossible to achieve the specified design value for surge current withstand capability (IFSM), and deteriorating forward voltage (Vf) characteristics.

[0017] In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device, and a silicon carbide semiconductor device, which are capable of preventing delamination due to excess carbon when forming ohmic contacts, reducing contact resistance, and improving Vf and IFSM characteristics. [Means for solving the problem]

[0018] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First conductivity type A first step is performed to selectively form a semiconductor region of a second conductivity type on a first main surface of a semiconductor substrate. Next, a second step is performed to form a nickel layer on the semiconductor region. Next, a third step is performed to ion-implant aluminum into the nickel layer. Next, a fourth step is performed to form an ohmic contact layer that makes an ohmic contact with the semiconductor region by heat-treating the nickel layer into which aluminum has been implanted. Next, a first electrode that contacts the ohmic contact layer, the semiconductor region, and the semiconductor substrate is formed. the first electrode forming a Schottky junction with the semiconductor substrate; Next, a sixth step is performed in which a second electrode is formed on the second main surface of the semiconductor substrate.

[0019] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the first step selectively forms a first semiconductor region of a second conductivity type on a first main surface of the semiconductor substrate, and after forming the first semiconductor region, selectively forms a second semiconductor region of the second conductivity type, having a higher impurity concentration than the first semiconductor region, in a surface layer of the first semiconductor region, thereby forming the semiconductor region composed of the first semiconductor region and the second semiconductor region.

[0020] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, in the third step, aluminum ions are implanted so that the peak of the aluminum concentration is present on the interface side of the nickel layer and the semiconductor region within the nickel layer.

[0021] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, it further includes a seventh step of ion-implanting nickel into the nickel layer and the semiconductor region after the second step and before the third step.

[0022] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, in the seventh step, nickel ions are implanted so that a concentration peak of the implanted nickel exists on the interface side between the nickel layer and the semiconductor region within the semiconductor region.

[0023] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the second step further includes an eighth step of forming the nickel layer over the entire surface of the semiconductor substrate, and removing the nickel layer other than that on the semiconductor region prior to the fourth step.

[0024] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, it further includes a ninth step of forming an oxide film on the semiconductor region after the first step and before the second step, the second step forming a nickel layer on the oxide film, and a tenth step of removing unreacted nickel after the fourth step.

[0025] Moreover, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the third step includes ion-implanting aluminum into the semiconductor substrate and the nickel layer on the semiconductor region.

[0026] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, further includes an eleventh step of forming a resist on the nickel layer on the semiconductor substrate after the second step and before the third step, and is characterized in that in the third step, aluminum ions are implanted into the nickel layer on the semiconductor substrate.

[0027] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. First conductivity type a semiconductor substrate; a semiconductor region of a second conductivity type selectively provided on a first main surface of the semiconductor substrate; an ohmic contact layer in ohmic contact with the semiconductor region; and a first electrode in contact with the ohmic contact layer, the semiconductor region, and the semiconductor substrate. the first electrode forming a Schottky junction with the semiconductor substrate; and a second electrode provided on the second main surface of the semiconductor substrate. The ohmic contact layer is composed of a nickel silicide layer in contact with the semiconductor region and a carbon compound layer provided on the nickel silicide layer, the nickel silicide layer and the carbon compound layer containing aluminum, and the aluminum concentration in the carbon compound layer is higher than that of the nickel silicide layer.

[0028] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the aluminum concentration in the carbon compound layer has a concentration peak located in the nickel silicide layer on the interface side between the nickel silicide layer and the carbon compound layer.

[0029] According to the above-described invention, by providing a carbon reactive metal above the ohmic contact layer and controlling the amount thereof, it is possible to suppress an increase in contact resistance due to excessive formation of the nickel silicide layer, a change in shape due to volume fluctuation, and a change in characteristics due to stress, and also to suppress defects such as delamination and breakage due to the generation of excess carbon, thereby reducing the contact resistance and improving the Vf and IFSM characteristics.

[0030] After the nickel layer is deposited, Al ion implantation for forming the carbon compound layer is performed. + By implanting the ions so that they reach the p-type region (the second semiconductor region of the second conductivity type), the nickel silicide layer is easily formed due to the ion implantation damage, and the annealing temperature can be reduced. + The increased aluminum concentration on the surface of the p-type region facilitates ohmic contact with the nickel silicide layer. + Nickel is ion-implanted near the interface between the mold region and the nickel layer to facilitate the formation of a nickel silicide layer. [Effects of the Invention]

[0031] The silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention have the following advantages: when forming ohmic contacts, delamination due to excess carbon can be prevented, contact resistance can be reduced, and Vf and IFSM characteristics can be improved. [Brief explanation of the drawings]

[0032] [Figure 1] 1 is a plan view showing a layout of a silicon carbide semiconductor device according to an embodiment as viewed from the front surface side of a semiconductor substrate. [Figure 2] 2 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. 1. [Figure 3] 3 is an enlarged cross-sectional view and concentration profile of region S in FIG. 2. [Figure 4] 1 is a flowchart outlining a first method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 5] 1A to 1C are cross-sectional views (part 1) illustrating a state during manufacturing according to a first method for manufacturing a silicon carbide semiconductor device in accordance with an embodiment. [Figure 6] 10 is a cross-sectional view (part 2) illustrating a state during manufacturing according to the first method for manufacturing a silicon carbide semiconductor device in accordance with the embodiment. [Figure 7]10A and 10B are cross-sectional views (part 3) illustrating a state during manufacturing by the first method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 8] 10 is a cross-sectional view (part 4) showing a state during manufacturing according to the first method for manufacturing a silicon carbide semiconductor device in accordance with the embodiment. [Figure 9] 10 is a cross-sectional view (part 5) showing a state during manufacturing according to the first method for manufacturing a silicon carbide semiconductor device in accordance with the embodiment. [Figure 10] 10 is a cross-sectional view (part 6) showing a state during manufacturing according to the first method for manufacturing a silicon carbide semiconductor device in accordance with the embodiment. FIG. [Figure 11] 10 is a cross-sectional view (part 7) showing a state during manufacturing according to the first method for manufacturing a silicon carbide semiconductor device in accordance with the embodiment. [Figure 12] 10 is a cross-sectional view (part 8) showing a state during manufacturing according to the first method for manufacturing a silicon carbide semiconductor device in accordance with the embodiment. FIG. [Figure 13] 9 is a cross-sectional view showing a state during manufacturing according to the first method for manufacturing a silicon carbide semiconductor device in accordance with the embodiment; FIG. [Figure 14] 10 is an enlarged cross-sectional view of region S1 after step S13 when the nickel layer is thin, and the concentration profiles of implanted Ni and Al. [Figure 15] 10 is an enlarged cross-sectional view of a region S1 after step S13 when the nickel layer is thick, and the concentration profiles of implanted Ni and Al. [Figure 16] 10 is a flowchart outlining a second method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 17] 10A to 10C are cross-sectional views (part 1) illustrating a state during manufacturing according to a second method for manufacturing a silicon carbide semiconductor device in accordance with an embodiment. [Figure 18] 10A and 10B are cross-sectional views (part 2) illustrating a state during manufacturing by the second manufacturing method of the silicon carbide semiconductor device according to the embodiment. [Figure 19] 10 is a flowchart outlining a third method for manufacturing a silicon carbide semiconductor device according to the embodiment. [Figure 20]10A to 10C are cross-sectional views (part 1) illustrating a state during manufacturing according to a third method for manufacturing a silicon carbide semiconductor device in accordance with an embodiment. [Figure 21] 10A and 10B are cross-sectional views (part 2) illustrating a state during manufacturing by the third manufacturing method of the silicon carbide semiconductor device according to the embodiment. [Figure 22] 10A and 10B are cross-sectional views (part 3) illustrating a state during manufacturing according to a third method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 23] 10 is a cross-sectional view (part 4) illustrating a state during manufacturing by the third manufacturing method of the silicon carbide semiconductor device according to the embodiment. [Figure 24] FIG. 1 is a plan view showing a layout of a conventional silicon carbide semiconductor device as viewed from the front surface side of a semiconductor substrate. [Figure 25] 25 is a cross-sectional view showing the cross-sectional structure taken along the line AA' in FIG. 24. [Figure 26] This is a circuit diagram of an SBD with a JBS structure. DETAILED DESCRIPTION OF THE INVENTION

[0033] Preferred embodiments of a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, + and - appended to n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with that prefix, respectively. In the following description of the embodiments and the accompanying drawings, similar components are given the same reference numerals, and duplicate explanations will be omitted. In the notation of Miller indices, "-" refers to a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index.

[0034] (Embodiment) The structure of a silicon carbide semiconductor device according to an embodiment will be described. Fig. 1 is a plan view showing a layout of a silicon carbide semiconductor device according to an embodiment as viewed from the front surface side of a semiconductor substrate. A silicon carbide semiconductor device 40 according to the embodiment shown in Fig. 1 is a silicon carbide diode in which, on the front surface side of an n-type semiconductor substrate 1 in an active region 10, an SBD structure (Schottky region 4) formed by a Schottky junction between a front surface electrode (first electrode) 14 (see Fig. 2) and the n-type semiconductor substrate 1, and a JBS structure (pn diode region 3) formed by a pn junction between a p-type well region 2 (see Fig. 2) and the n-type semiconductor substrate 1 are mixed.

[0035] The Schottky regions 4 and the pn diode regions 3 (see FIG. 2) are arranged in a substantially uniform pattern and at substantially equal intervals within the surface of the active region 10. The Schottky regions 4 and the pn diode regions 3 are arranged, for example, in stripes extending in the same direction parallel to the front surface of the n-type semiconductor substrate 1, and are alternately and repeatedly arranged in contact with each other in the short direction perpendicular to the long direction of the stripes.

[0036] Active region 10 is a region through which current flows when the silicon carbide diode is in the on state. Active region 10 has, for example, a substantially rectangular planar shape and is located approximately in the center of n-type semiconductor substrate 1. Edge termination region 30 is a region between active region 10 and the edge of n-type semiconductor substrate 1, and surrounds the periphery of active region 10. Edge termination region 30 is a region that relieves the electric field on the front surface side of n-type semiconductor substrate 1 and maintains a breakdown voltage. The breakdown voltage is the limit voltage at which the element does not malfunction or break down.

[0037] A breakdown voltage structure 15 such as a field limiting ring (FLR) or junction termination extension (JTE) structure is disposed in edge termination region 30. The JTE structure is a breakdown voltage structure having a substantially rectangular planar shape in which multiple p-type regions with different impurity concentrations are arranged around active region 10, with p-type regions with lower impurity concentrations being disposed as they move away from the inside (the center side of n-type semiconductor substrate 1) to the outside (the edge side of n-type semiconductor substrate 1).

[0038] Front surface electrode 14 is provided on the front surface of n-type semiconductor substrate 1 in active region 10. Front surface electrode 14 is in contact with n-type semiconductor substrate 1 and p-type well region 2 and is electrically connected to n-type semiconductor substrate 1 and p-type well region 2.

[0039] Next, a cross-sectional structure of silicon carbide semiconductor device 40 according to an embodiment will be described. Fig. 2 is a cross-sectional view showing the cross-sectional structure taken along line A-A' in Fig. 1. As described above, silicon carbide semiconductor device 40 according to the embodiment has a JBS structure having an SBD structure and a pn diode structure of silicon carbide diodes in active region 10 of n-type semiconductor substrate 1 made of silicon carbide, and has a breakdown voltage structure (not shown) in edge termination region 30.

[0040] The n-type semiconductor substrate 1 is made of silicon carbide. + On the front surface of the silicon carbide substrate, - n type drift region - It is an epitaxial substrate with a layer of n-type epitaxial layers. + The silicon carbide substrate is + The n-type semiconductor substrate 1 is an n-type cathode region. - The main surface (n - n type drift region - The surface of the n-type epitaxial layer) is the front surface, + The main surface of the silicon carbide substrate (n + The back surface of the n-type silicon carbide substrate 1 is referred to as the back surface. +A cathode electrode (second electrode) 8 is provided on the entire surface of the n-type silicon carbide substrate (back surface), + The semiconductor substrate is electrically connected to the silicon carbide substrate.

[0041] One or more p-type well regions 2 constituting a pn diode structure are selectively provided in a surface region on the front surface side of n-type semiconductor substrate 1. P-type well regions 2 are provided on the front surface of n-type semiconductor substrate 1. P-type well regions 2 are exposed on the front surface of n-type semiconductor substrate 1. A front surface electrode 14 is provided on the entire front surface of n-type semiconductor substrate 1.

[0042] The front surface electrode 14 has a laminated structure in which an anode electrode 7 and a Schottky metal 6 are laminated in this order. In addition, the front surface electrode 14 has a bottom ohmic contact layer 12 selectively provided between the front surface of the n-type semiconductor substrate 1 and the Schottky metal 6. A p-type well region 2 having a higher impurity concentration than the p-type well region 2 is provided in the p-type well region 2. + A mold region 17 is provided, and p + An ohmic contact layer 12 is provided on the mold region 17 .

[0043] As will be described later, the ohmic contact layer 12 is formed by reacting the surface region of the n-type semiconductor substrate 1 with the metal material film (nickel layer 11 and Al region 22, see FIGS. 14 and 15) at the contact points between the p-type well region 2 and the metal material film deposited on the front surface of the n-type semiconductor substrate 1 through heat treatment. For this reason, the ohmic contact layer 12 is provided in the surface region of the front surface of the n-type semiconductor substrate 1 and is formed in the p + The ohmic contact layer 12 is in contact with the p-type region 17 and protrudes from the front surface of the n-type semiconductor substrate 1 in a direction away from the front surface of the n-type semiconductor substrate 1. + The nickel silicide layer 16 is provided on the mold region 17, and the carbon compound layer 18 is provided on the nickel silicide layer 16. + The mold region 17, the nickel silicide layer 16, and the carbon compound layer 18 have approximately the same width.

[0044] The Schottky metal 6 is provided on the entire front surface of the n-type semiconductor substrate 1 and is in contact with the n-type semiconductor substrate 1 and the p-type well region 2. The junction of the Schottky metal 6 with the n-type semiconductor substrate 1 is the Schottky region 4, which forms a Schottky junction with the n-type semiconductor substrate 1. The Schottky metal 6 forms an ohmic contact with the p-type well region 2 via an ohmic contact layer 12. The anode electrode 7 covers the entire surface of the Schottky metal 6 and is electrically connected to the Schottky metal 6 and to the ohmic contact layer 12 via the Schottky metal 6. The anode electrode 7 is, for example, an aluminum silicon (AlSi) film, but may also be an aluminum film.

[0045] 3 is an enlarged cross-sectional view and concentration profile of the region S in FIG. 2. The graph in FIG. 3 shows the concentration profile of the carbon compound layer 18 from the surface to the surface of the carbon compound layer 18. + The concentrations of nickel (Ni), carbon (C), silicon (Si) and aluminum (Al) are shown in the graph up to the type region 17. As shown in FIG. + The mold region 17 is a silicon carbide layer, mainly composed of silicon and carbon, with low concentrations of nickel and aluminum. On the other hand, the nickel silicide layer 16 and the carbon compound layer 18 of the ohmic contact layer 12 contain nickel and aluminum in addition to silicon and carbon. In particular, the nickel silicide layer 16 is mainly composed of nickel and silicon because nickel silicide is formed. The carbon compound layer 18 is mainly composed of nickel, carbon, and aluminum.

[0046] The carbon compound layer 18 has a lower silicon concentration and higher carbon and aluminum concentrations than the nickel silicide layer 16. In the carbon compound layer 18, the carbon and aluminum have concentration peaks on the side in contact with the nickel silicide layer 16.

[0047] This is because aluminum is a carbon-reactive metal, and excess carbon generated when nickel and silicon react in the nickel silicide layer 16 reacts with aluminum, capturing the carbon as AlC in the carbon compound layer 18. This reduces the deposition of excess carbon on the surface of the ohmic contact layer 12.

[0048] As described above, in the embodiment, by providing a carbon reactive metal above the ohmic contact layer 12 and controlling the amount thereof, it is possible to suppress an increase in contact resistance due to excessive formation of the nickel silicide layer 16, a change in shape due to volume fluctuation, and a change in characteristics due to stress, and also to suppress defects such as delamination and breakage due to the generation of excess carbon, thereby reducing the contact resistance and improving the Vf and IFSM characteristics.

[0049] (Method for manufacturing silicon carbide semiconductor device according to embodiment) Next, a method for manufacturing a silicon carbide semiconductor device 40 according to an embodiment will be described. Fig. 4 is a flowchart outlining a first method for manufacturing a silicon carbide semiconductor device according to an embodiment. Figs. 5 to 13 are cross-sectional views showing states during manufacturing according to the first method for manufacturing a silicon carbide semiconductor device according to an embodiment. Figs. 4 to 13 will explain in detail the steps from the step of forming ohmic contact layer 12 onwards.

[0050] First, n + As a silicon carbide substrate (semiconductor wafer), for example, 5 × 10 18 / cm 3 A four-layer hexagonal silicon carbide (4H-SiC) substrate doped with nitrogen (N) is prepared. + The front surface of the silicon carbide substrate may have an off-angle of, for example, about 4° with respect to the (0001) plane. + On the front surface of the silicon carbide substrate, - The drift region is, for example, 1.8 × 10 16 / cm 3 Nitrogen doped n - A type epitaxial layer is grown.

[0051] n + n-type cathode region + The thickness of the silicon carbide substrate may be, for example, about 350 μm. - n type drift region - The thickness of the n-type epitaxial layer may be, for example, about 6 μm. + n type silicon carbide substrate on the front surface - n type drift region - As described above, the n-type semiconductor substrate 1 is fabricated by laminating an n-type epitaxial layer. - The main surface (first main surface) on the side of the mold drift region is the front surface, and n + The main surface (second main surface) on the silicon carbide substrate side is referred to as the back surface.

[0052] Next, by photolithography and ion implantation of p-type impurities such as aluminum, one or more p-type well regions (first semiconductor regions of the second conductivity type) 2 constituting a pn diode structure are selectively formed in the surface region of the front surface of the n-type semiconductor substrate 1 in the active region 10 (see FIG. 1). The multiple p-type well regions 2 are arranged at equal intervals in a direction parallel to the front surface of the n-type semiconductor substrate 1, for example, at intervals of about 2 μm.

[0053] Next, as shown in FIG. 5, an oxide film 19 is formed on the entire front surface of the n-type semiconductor substrate 1, and a resist (not shown) is formed on the oxide film 19. The oxide film 19 is formed by, for example, thermal oxidation and chemical vapor deposition (CVD). Next, the oxide film 19 and the resist are selectively removed by photolithography and etching, leaving a p + An opening is formed in a region where the p-type region 17 is to be formed (step S11). Next, p-type impurities are implanted into the opening to form p + A type region (second semiconductor region of the second conductivity type) 17 is formed.

[0054] Next, the resist is removed, and a heat treatment (activation annealing) is performed to activate the entire region formed by ion implantation. For example, the heat treatment (annealing) is performed in an inert gas atmosphere at about 1000° C., and the p-type well region 2, p + An activation process is carried out on the mold region 17. As described above, the ion implantation regions may be activated all at once by a single heat treatment, or activation may be carried out by performing a heat treatment each time an ion implantation is carried out.

[0055] 6, a nickel layer 11 is formed on the entire front surface of the n-type semiconductor substrate 1 by, for example, sputtering (step S12). The nickel layer 11 is also formed in the openings of the oxide film 19. + It contacts the mold area 17 .

[0056] 7, a resist 20 is formed on the entire front surface of the n-type semiconductor substrate 1. Next, the resist 20 is selectively removed by photolithography to form a p + An opening is formed in the region where the mold region 17 is formed. Next, aluminum is injected into the opening at a dose of 1×10 16 / cm 3 More than 1×10 17 / cm 3 The following ion implantation is performed to form an Al region 22 in the nickel layer 11 (step S13). Before the aluminum ion implantation, nickel is implanted into the opening with a dose of 1×10 15 / cm 3 More than 1×10 16 / cm 3 A Ni region (not shown) having a high concentration of nickel may be formed in the nickel layer 11 by the following ion implantation.

[0057] Here, Figure 14 is an enlarged cross-sectional view of region S1 after S13 when the nickel layer is thin, and shows the concentration profiles of implanted Ni and Al. Figure 15 is an enlarged cross-sectional view of region S1 after S13 when the nickel layer is thick, and shows the concentration profiles of implanted Ni and Al. The graphs in Figures 14 and 15 show the concentrations of implanted aluminum and nickel from the surface of nickel layer 11 to p-type well region 2.

[0058] 14 and 15, aluminum is ion-implanted to form an Al region 22 in the nickel layer 11. At this time, the peak of the aluminum concentration is in the nickel layer 11, and the aluminum is p + The ion implantation is performed so that the aluminum reaches the p-type region 17. That is, the aluminum is implanted into the nickel layer 11 and the p-type region 17. + The aluminum ions are implanted across the interface with the nickel layer 11. + On the other hand, when nickel ions are implanted, the nickel layer 11 and the p + A Ni region (not shown) is formed across the interface with the type region 17, and the peak concentration of the implanted nickel is p + The ion implantation is performed so that the nickel concentration is within the type region 17. The peak concentration of the implanted nickel is p + It is preferably on the nickel layer 11 side in the mold region 17 .

[0059] Here, the thickness of the nickel layer 11 is preferably 0.1 μm or more and 0.5 μm or less. When the thickness of the nickel layer 11 is thin as shown in FIG. 14, for example, 0.2 μm or less, a special high-acceleration ion implantation device is not required, and the nickel layer 11 and p + Since the aluminum can be implanted near the interface with the p-type region 17 with high precision and the variations can be reduced, the half-width of the aluminum concentration can be narrowed and the peak of the aluminum concentration can be located between the nickel layer 11 and the p-type region 17. + On the other hand, when the thickness of the nickel layer 11 is large as shown in FIG. 15, for example, when the thickness is 0.2 μm or more and 0.5 μm or less, the p +Since aluminum penetrates deep into the type region 17, the contact resistance can be reduced. However, if the thickness is greater than 0.5 μm, a high-acceleration ion implantation device is required, and the nickel layer 11 and the p + This is not preferable because it increases the variation in implantation near the interface with mold region 17 and lowers the peak aluminum concentration, resulting in greater variation in the finished product. When increasing the thickness of nickel layer 11, a thin nickel layer 11 may be laminated, ion implantation is performed, and then another nickel layer may be laminated on top of that, and the same effect as when nickel layer 11 is thin can be obtained.

[0060] In this manner, in the embodiment, after the nickel layer 11 is deposited, Al ion implantation for forming the carbon compound layer 18 is performed by p + By performing the ion implantation so as to reach the p-type region 17, the nickel silicide layer 16 can be easily formed due to ion implantation damage, and the annealing temperature can be reduced. + The increased aluminum concentration on the surface of the type region 17 facilitates ohmic contact with the nickel silicide layer 16. In addition, by ion implanting nickel, p + Nickel is ion-implanted near the interface between the mold region 17 and the nickel layer 11, further facilitating the formation of the nickel silicide layer 16.

[0061] In addition, when aluminum is ion-implanted, the p + It is preferable that 5% to 20% of the implanted aluminum reaches the interface between the nickel layer 11 and the nickel silicide region 17. In addition, it is preferable that the thickness of the nickel silicide layer 16 is secured while the nickel layer 11 and the p + To facilitate implantation near the interface with the mold region 17, the thickness of the nickel layer 11 is made thin and the ion implantation acceleration voltage is lowered, thereby suppressing variations in aluminum due to ion implantation and enabling accurate formation. This allows for efficient reaction even with ion implantation that involves a smaller amount of metal than with metal lamination.

[0062] In addition, the thickness of the nickel layer 11 is reduced, and nickel is separated from the nickel layer 11 by p+ By implanting ions across the interface with the type region 17, the nickel silicide layer 16 can be easily formed, and the variations in aluminum in the Al region 22 can be suppressed, allowing for accurate formation. Also, the nickel silicide layer 16 can be formed by implanting an inert gas instead of nickel, but in that case, the p + It is preferable to prevent the inert gas from reaching the mold region 17. Dynamic mixing, in which nickel is injected while the nickel layer 11 is being deposited, is also possible, and in this case the thickness of the nickel layer 11 can be minimized.

[0063] Next, as shown in FIG. 8, the resist is removed (step S14). Next, as shown in FIG. 9, annealing (heat treatment) is performed at a temperature of 600° C. or higher and 1000° C. or lower. This causes a silicide reaction between silicon atoms in the semiconductor substrate and nickel atoms in the aluminum-nickel compound layer, resulting in p + A nickel silicide (NiSi) film 16 and a carbon compound layer 18 are formed to form an ohmic electrode by forming an ohmic contact with the mold region 17 (step S15).

[0064] The heat treatment in step S15 causes the nickel layer 11 and p + Silicon atoms in the n-type semiconductor substrate 1 are thermally diffused into the nickel layer 11 at the contact points with the Al region 17. This silicide reaction produces a nickel silicide layer 16 in the nickel layer 11. Carbon remaining in the n-type semiconductor substrate 1 due to the silicide reaction (hereinafter referred to as excess carbon) bonds with aluminum, which is a carbon reaction metal, in the Al region 22, producing a carbon compound layer 18. This forms the ohmic contact layer 12 shown in FIG.

[0065] Next, as shown in FIG. 10, the unreacted nickel layer 11 is removed (step S16). Here, the ohmic contact layer 12 is formed by a single heat treatment. However, the contact resistance may be reduced by performing a first heat treatment, removing the unreacted nickel layer 11, and then a second heat treatment at a higher temperature than the first. In the process of step S16, the entire front surface of the n-type semiconductor substrate 1 is etched by wet etching using, for example, phosphonitric acid and acetic acid. Next, as shown in FIG. 11, the oxide film 19 is removed (step S17). Next, as shown in FIG. 12, a Schottky metal 6 is formed on the entire front surface of the n-type semiconductor substrate 1 by, for example, sputtering (step S18). Next, as shown in FIG. 13, an anode electrode 7 is formed on the surface of the Schottky metal 6 (step S19).

[0066] Next, the front surface of the n-type semiconductor substrate 1 (semiconductor wafer) is covered with a protective film (not shown) for protection, and then the n-type semiconductor substrate 1 is polished from the back side to thin the n-type semiconductor substrate 1 to the product thickness. Next, the back surface (n + After nickel or titanium is formed on the entire surface of the n-type silicon carbide substrate (back surface), laser annealing is performed to form cathode electrode 8. Thereafter, the protective film on the front surface of n-type semiconductor substrate 1 is removed, and then n-type semiconductor substrate 1 is diced (cut) into individual chips, thereby completing silicon carbide semiconductor device 40 shown in FIGS.

[0067] Next, a second method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. Fig. 16 is a flowchart showing an outline of the second method for manufacturing a silicon carbide semiconductor device according to an embodiment. Figs. 17 and 18 are cross-sectional views showing a state during manufacturing by the second method for manufacturing a silicon carbide semiconductor device according to an embodiment. Here, illustrations that are the same as those used in the first manufacturing method during manufacturing will be omitted, and the description will be made with reference to the drawings of the first manufacturing method.

[0068] The second manufacturing method differs from the first manufacturing method in that the formation and removal of resist 20 are not performed when implanting aluminum ions, and by reducing the number of steps involved, the manufacturing method can be performed in fewer steps than the first manufacturing method. First, as with the first manufacturing method, the process is performed up to the step of selectively forming p-type well region 2.

[0069] Next, as shown in FIG. 5, an oxide film 19 is formed on the entire front surface of the n-type semiconductor substrate 1, and a resist (not shown) is formed on the oxide film 19. The oxide film 19 is formed by, for example, thermal oxidation and chemical vapor deposition. Next, the oxide film 19 and the resist are selectively removed by photolithography and etching, leaving a p + An opening is formed in the region where the p-type region 17 is to be formed (step S21). Next, p-type impurities are implanted into the opening to form p + A mold region 17 is formed.

[0070] Next, the resist is removed, and a heat treatment (activation annealing) is performed to activate the entire region formed by ion implantation. For example, the heat treatment (annealing) is performed in an inert gas atmosphere at about 1000° C., and the p-type well region 2, p + An activation process is carried out on the mold region 17. As described above, the ion implantation regions may be activated all at once by a single heat treatment, or activation may be carried out by performing a heat treatment each time an ion implantation is carried out.

[0071] 6, a nickel layer 11 is formed on the entire front surface of the n-type semiconductor substrate 1 by, for example, sputtering (step S22). The nickel layer 11 is also formed in the openings of the oxide film 19. + It contacts the mold area 17 .

[0072] 17, aluminum is ion-implanted into the entire surface of the nickel layer 11 to form an Al region 22 in the nickel layer 11 (step S23). Furthermore, before the aluminum ion-implantation, nickel may be ion-implanted into the opening to form a Ni region (not shown) in the nickel layer 11. Here, the enlarged cross-sectional view of region S1 and the Ni and Al concentration profiles are the same as those in the first manufacturing method.

[0073] In the second manufacturing method, since the resist 20 is not provided, the Al region 22 is formed over the entire surface in the nickel layer 11. Furthermore, aluminum is also implanted into the interface between the n-type semiconductor substrate 1 and the nickel layer 11.

[0074] Next, as shown in FIG. 18, annealing (heat treatment) is performed to cause a silicide reaction between silicon atoms in the semiconductor substrate and nickel atoms in the aluminum-nickel compound layer, resulting in p + A nickel silicide (NiSi) film 16 and a carbon compound layer 18 are formed to serve as ohmic electrodes that make ohmic contact with the mold region 17 (step S24).

[0075] Next, as shown in FIG. 10, unreacted nickel layer 11 is removed (step S25). In the process of step S25, the entire front surface of n-type semiconductor substrate 1 is etched by wet etching using, for example, phosphonitric acid and acetic acid. Next, as shown in FIG. 11, oxide film 19 is removed (step S26). Next, as shown in FIG. 12, Schottky metal 6 is formed on the entire front surface of n-type semiconductor substrate 1 by, for example, sputtering (step S27). Next, as shown in FIG. 13, an anode electrode 7 is formed on the surface of Schottky metal 6 (step S28).

[0076] Next, the front surface of the n-type semiconductor substrate 1 (semiconductor wafer) is covered with a protective film (not shown) for protection, and then the n-type semiconductor substrate 1 is polished from the back side to thin the n-type semiconductor substrate 1 to the product thickness. Next, the back surface (n +After nickel or titanium is formed on the entire surface of the n-type silicon carbide substrate (back surface), laser annealing is performed to form cathode electrode 8. Thereafter, the protective film on the front surface of n-type semiconductor substrate 1 is removed, and then n-type semiconductor substrate 1 is diced (cut) into individual chips, thereby completing silicon carbide semiconductor device 40 shown in FIGS.

[0077] Next, a third method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. Fig. 19 is a flowchart showing an outline of the third method for manufacturing a silicon carbide semiconductor device according to an embodiment. Figs. 20 to 23 are cross-sectional views showing states during manufacturing by the third method for manufacturing a silicon carbide semiconductor device according to an embodiment. Here, illustrations that are the same as those used in the first manufacturing method during manufacturing will be omitted, and the description will be made with reference to the figures for the first manufacturing method.

[0078] The third manufacturing method differs from the first manufacturing method in that the formation and removal of oxide film 19 are not performed when aluminum ions are implanted, and by reducing the number of steps involved, the manufacturing method can be performed in fewer steps than the first manufacturing method. First, as with the first manufacturing method, the process is performed up to the step of selectively forming p-type well region 2.

[0079] Next, as shown in FIG. 20, a nickel layer 11 is formed on the entire front surface of the n-type semiconductor substrate 1 by, for example, sputtering (step S31). + It contacts the mold area 17 .

[0080] 21, a resist 20 is formed on the entire front surface of the n-type semiconductor substrate 1. Next, the resist 20 is selectively removed by photolithography to form a p + An opening is formed in the region where the mold region 17 is formed. Next, aluminum ions are implanted into the opening to form an Al region 22 in the nickel layer 11 (step S32). Alternatively, before the aluminum ions are implanted, nickel ions may be implanted into the opening to form a Ni region (not shown) in the nickel layer 11. Here, the enlarged cross-sectional view of region S1 and the Ni and Al concentration profiles are the same as those in the first manufacturing method.

[0081] Next, as shown in FIG. 22, the resist 20 is removed (step S33). Next, as shown in FIG. 23, the nickel layer 11 other than the nickel layer 11 on the Al region 22 is removed (step S34). Next, as shown in FIG. 11, annealing (heat treatment) is performed to cause a silicide reaction between silicon atoms in the semiconductor substrate and nickel atoms in the aluminum-nickel compound layer, resulting in p + A nickel silicide (NiSi) film 16 and a carbon compound layer 18 are formed to serve as ohmic electrodes that make ohmic contact with the mold region 17 (step S35).

[0082] 12, a Schottky metal 6 is formed on the entire front surface of the n-type semiconductor substrate 1 by, for example, sputtering (step S36). Next, an anode electrode 7 is formed on the surface of the Schottky metal 6 (step S37), as shown in FIG.

[0083] Next, the front surface of the n-type semiconductor substrate 1 (semiconductor wafer) is covered with a protective film (not shown) for protection, and then the n-type semiconductor substrate 1 is polished from the back side to thin the n-type semiconductor substrate 1 to the product thickness. Next, the back surface (n + After nickel or titanium is formed on the entire surface of the n-type silicon carbide substrate (back surface), laser annealing is performed to form cathode electrode 8. Thereafter, the protective film on the front surface of n-type semiconductor substrate 1 is removed, and then n-type semiconductor substrate 1 is diced (cut) into individual chips, thereby completing silicon carbide semiconductor device 40 shown in FIGS.

[0084] Furthermore, although the embodiments have been described with respect to silicon carbide diodes with a JBS structure, the present invention can also be applied to the front electrode of SiC-MOSFETs. The n-type source region of a MOSFET is nickel silicide, and a carbon layer is formed, making the front electrode prone to peeling. However, because it is not provided over the entire surface like a Schottky diode, the front electrode is less likely to peel off. However, by implanting Al ions into the n-type source region to form an Al region and then generating a carbon compound layer by annealing, peeling of the front electrode due to excess carbon can be prevented. When ions are implanted over the entire surface, including the n-type source region, inexpensive manufacturing is possible without increasing the number of steps such as photolithography. Furthermore, it is possible to form a p-type MOSFET without implanting ions into the n-type source region using photolithography. + When ion implantation is performed only in the n-type contact region, the contact resistance with the n-type source region is kept low while the p + This also has the effect of reducing the contact resistance of the n-type contact region. Furthermore, by implanting ions such as Ti so that they reach the interface of the n-type source region, the temperature required for forming Ti silicide can be reduced.

[0085] As described above, according to the embodiment, by providing a carbon reactive metal above the ohmic contact layer and controlling the amount of the carbon reactive metal, it is possible to suppress an increase in contact resistance due to excessive formation of the nickel silicide layer, a change in shape due to volume fluctuation, and a change in characteristics due to stress, and also to suppress defects such as delamination and breakage due to the generation of excess carbon, thereby reducing the contact resistance and improving the Vf and IFSM characteristics.

[0086] After the nickel layer is deposited, Al ion implantation for forming the carbon compound layer is performed. + By performing the ion implantation so as to reach the p-type region, the nickel silicide layer can be easily formed due to the ion implantation damage, and the annealing temperature can be reduced. + The increased aluminum concentration on the surface of the p-type region facilitates ohmic contact with the nickel silicide layer. +Nickel is ion-implanted near the interface between the mold region and the nickel layer to facilitate the formation of a nickel silicide layer.

[0087] The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. The present invention is applicable to silicon carbide semiconductor devices having ohmic electrodes in ohmic contact with p-type regions arranged in a predetermined pattern.

[0088] Specifically, for example, the present invention provides a semiconductor device that includes a p-type region (or a p-type region disposed between the p-type region and the main surface of the semiconductor substrate). + The present invention is useful for a silicon carbide semiconductor device having a configuration for reducing the contact resistance between a p-type contact region and an ohmic electrode, and a silicon carbide semiconductor device having a structure in which an ohmic electrode making ohmic contact with a p-type region is in contact with an oxide film. [Industrial Applicability]

[0089] INDUSTRIAL APPLICABILITY As described above, the method for manufacturing a silicon carbide semiconductor device and the silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines and the like. [Explanation of symbols]

[0090] 1, 101 n-type semiconductor substrate 2, 102 p-type well region 3, 103 pn diode area 4, 104 Schottky region 6, 106 Schottky metal 7, 107 Anode electrode 8, 108 cathode electrode 10, 110 active area 11 Nickel layer 12 Ohmic contact layer 14, 114 Front electrode 15, 115 pressure-resistant structure 16, 116 Nickel silicide layer 17 p + type area 18 Carbon compound layer 19 Oxide film 20 Resist 22 Al area 30, 130 Edge termination area 40, 140 Silicon carbide semiconductor device 141 Schottky diode 142 pn diode

Claims

1. a first step of selectively forming a semiconductor region of a second conductivity type on a first main surface of a semiconductor substrate of a first conductivity type made of silicon carbide; a second step of forming a nickel layer on the semiconductor region; a third step of ion-implanting aluminum into the nickel layer; a fourth step of forming an ohmic contact layer that makes an ohmic contact with the semiconductor region by heat treating the nickel layer into which the aluminum has been implanted; a fifth step of forming a first electrode in contact with the ohmic contact layer, the semiconductor region, and the semiconductor substrate, the first electrode forming a Schottky junction with the semiconductor substrate; a sixth step of forming a second electrode on a second main surface of the semiconductor substrate; 2. A method for manufacturing a silicon carbide semiconductor device, comprising:

2. 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the first step selectively forms a first semiconductor region of a second conductivity type on a first main surface of the semiconductor substrate, and after forming the first semiconductor region, selectively forms a second semiconductor region of the second conductivity type, having an impurity concentration higher than that of the first semiconductor region, in a surface layer of the first semiconductor region, thereby forming the semiconductor region composed of the first semiconductor region and the second semiconductor region.

3. 3. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the third step, aluminum ions are implanted so that a peak of the aluminum concentration is present in the nickel layer on an interface side between the nickel layer and the semiconductor region.

4. After the second step and before the third step, 4. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising a seventh step of ion-implanting nickel into said nickel layer and said semiconductor region.

5. 5. The method for manufacturing a silicon carbide semiconductor device according to claim 4, wherein in the seventh step, nickel ions are implanted such that a concentration peak of the implanted nickel exists on an interface side between the nickel layer and the semiconductor region within the semiconductor region.

6. the second step is to form the nickel layer on the entire surface of the semiconductor substrate; 6. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising, before said fourth step, an eighth step of removing said nickel layer except for on said semiconductor region.

7. After the first step and before the second step, A ninth step of forming an oxide film on the semiconductor region, the second step includes forming a nickel layer on the oxide film; 7. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising a tenth step of removing unreacted nickel after said fourth step.

8. 8. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the third step, aluminum ions are implanted into the semiconductor substrate and the nickel layer on the semiconductor region.

9. After the second step and before the third step, An eleventh step of forming a resist on the nickel layer on the semiconductor substrate, 9. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the third step, aluminum ions are implanted into the nickel layer on the semiconductor substrate.

10. a semiconductor substrate of a first conductivity type made of silicon carbide; a second conductivity type semiconductor region selectively provided on the first main surface of the semiconductor substrate; an ohmic contact layer that is in ohmic contact with the semiconductor region; a first electrode in contact with the ohmic contact layer, the semiconductor region, and the semiconductor substrate, the first electrode forming a Schottky junction with the semiconductor substrate; a second electrode provided on a second main surface of the semiconductor substrate; Equipped with the ohmic contact layer is composed of a nickel silicide layer in contact with the semiconductor region and a carbon compound layer provided on the nickel silicide layer; 10. A silicon carbide semiconductor device, wherein the nickel silicide layer and the carbon compound layer contain aluminum, and the aluminum in the carbon compound layer has a higher concentration than the aluminum in the nickel silicide layer.

11. 11. The silicon carbide semiconductor device according to claim 10, wherein the aluminum concentration in the carbon compound layer has a peak at an interface between the nickel silicide layer and the carbon compound layer within the nickel silicide layer.

Images