Semiconductor device and standby current reduction method

Abstract

To reduce a standby current of a semiconductor device.SOLUTION: A semiconductor device 10a includes: smoothing capacitor circuits 11a1-11aN each including a switch circuit 15 switching, depending on a first control signal, whether a power supply potential VDD2 can be applied to a power line 18, capacitive elements 16a-16d connected between the power line 18 and a power line 19 providing a power supply potential VSS, and a leakage current detection circuit 17 detecting a leakage current in the capacitive elements 16a-16d; a storage circuit 12 storing detection results of the leakage current; and a smoothing capacitor setting circuit 13 supplying, to a smoothing capacitor circuit where the leakage current has been detected among the smoothing capacitor circuits 11a1-11aN, the first control signal to stop the application of the power supply potential VDD2 to the power supply line 18 of the smoothing capacitor circuit, on the basis of the detection results stored in the storage circuit 12, in a standby state.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for reducing standby current. [Background technology]

[0002] In semiconductor devices, a plurality of capacitance elements are connected between a power supply line and ground to smooth power supply noise and suppress fluctuations in the power supply voltage. Such capacitance elements are sometimes called smoothing capacitances. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-233719 [Patent Document 2] Japanese Patent Application Publication No. 2017-195306 [Patent Document 3] Japanese Patent Application Laid-Open No. 2003-017569 Summary of the Invention [Problem to be solved by the invention]

[0004] If there is a capacitance element with a large leakage current among the multiple capacitance elements used as smoothing capacitances, the standby current of the semiconductor device may increase due to the influence of that capacitance element, and the semiconductor device may be determined to be defective during testing before shipping.

[0005] In one aspect, the present invention aims to provide a semiconductor device capable of reducing standby current and a method for reducing standby current. [Means for solving the problem]

[0006] In one embodiment, A semiconductor device in which a standby state period including a standby period and an operating period are repeated after a power supply is turned on,a first capacitance element connected between the first power supply line and a second power supply line having a second power supply potential lower than the first power supply potential; Every time the standby state is entered a plurality of smoothing capacitance circuits each including a first detection circuit for detecting a first detection result; and a storage circuit for storing a first detection result of the first detection circuit; The aforementioned Standby state Every time it becomes and a smoothing capacitance setting circuit that supplies the first control signal to the first smoothing capacitance circuit, which stops the application of the first power supply potential to the first power supply line of a first smoothing capacitance circuit in which the first leakage current is detected, among the plurality of smoothing capacitance circuits, based on the first detection result stored in the memory circuit.

[0007] Also, in one embodiment, a method for reducing standby current is provided. [Effects of the Invention]

[0008] In one aspect, the present invention can reduce the standby current of a semiconductor device. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram illustrating an example of a semiconductor device according to a first embodiment; [Figure 2] FIG. 1 is a diagram illustrating a circuit configuration of an example of a leakage current detection circuit. [Figure 3] 10 is a timing chart showing an example of the operation of a semiconductor device when a leakage current occurs; [Figure 4] 10 is a timing chart showing an example of the operation of the semiconductor device when no leakage current occurs; [Figure 5] FIG. 1 is a diagram illustrating a semiconductor device according to a first comparative example. [Figure 6] FIG. 10 is a diagram illustrating a semiconductor device of a second comparative example. [Figure 7]FIG. 10 illustrates an example of a semiconductor device according to a second embodiment. [Figure 8] FIG. 2 is a diagram illustrating an example of a smoothing capacitance setting circuit. [Figure 9] 10 is a timing chart showing an example of the operation of a semiconductor device when a leakage current occurs; [Figure 10] 10 is a timing chart showing an example of the operation of the semiconductor device when no leakage current occurs; [Figure 11] 10 is a timing chart showing an example of setting a control signal for a smoothing capacitance circuit in which a leak current is detected. [Figure 12] 10 is a timing chart showing an example of setting a control signal for a smoothing capacitance circuit in which no leakage current is detected; [Figure 13] FIG. 10 illustrates an example of a semiconductor device according to a third embodiment. [Figure 14] FIG. 10 is a diagram illustrating an example of setting a control signal supplied to a smoothing capacitance circuit. [Figure 15] FIG. 10 is a diagram illustrating an example of a smoothing capacitance setting circuit in the semiconductor device according to the third embodiment. [Figure 16] 15 is a timing chart showing an example of the operation of the semiconductor device in Case 1 in FIG. 14 in which a leakage current is detected. [Figure 17] 15 is a timing chart showing an example of the operation of the semiconductor device in Case 2 in FIG. 14 in which a leakage current is detected. [Figure 18] FIG. 1 is a diagram illustrating a circuit configuration of an example of a leakage current detection circuit. [Figure 19] FIG. 10 is a diagram illustrating a modified example of a smoothing capacitance circuit. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the invention will be described with reference to the drawings. (First embodiment) FIG. 1 is a diagram illustrating an example of a semiconductor device according to a first embodiment.

[0011] The semiconductor device 10a according to the first embodiment is, for example, a one-chip semiconductor integrated circuit, and includes a plurality of smoothing capacitance circuits 11a1, 11a2, ..., 11aN, a memory circuit 12, and a smoothing capacitance setting circuit 13. Other internal circuits of the semiconductor device 10a are not shown in the drawing.

[0012] The smoothing capacitance circuits 11a1 to 11aN are provided on the periphery of the semiconductor device 10a and smooth out power supply noise to suppress fluctuations in the power supply voltage. An example of the smoothing capacitance circuit 11a1 is shown in Figure 1. The other smoothing capacitance circuits 11a2 to 11aN have the same circuit configuration as the smoothing capacitance circuit 11a1.

[0013] The smoothing capacitance circuit 11a1 includes a switch circuit 15, capacitance elements (four capacitance elements 16a, 16b, 16c, and 16d in the example of FIG. 1), and a leakage current detection circuit 17. The switch circuit 15 controls whether or not the power supply potential VDD2 is applied to the power supply line 18 using a control signal SETP. <1> ,SETN <1> The power supply potential VDD2 is, for example, a potential obtained by stepping down the power supply potential VDD1, which is an external power supply potential. For example, VDD1=3.3V and VDD2=1.8V. However, if the withstand voltage of the capacitance elements 16a to 16d is higher than the power supply potential VDD1, the smoothing capacitance circuit 11a1 described above can be applied even when the power supply potential VDD1 is used, just as when the power supply potential VDD2 is used. The potential VDE indicates the potential of the power supply line 18.

[0014] The switch circuit 15 includes, for example, a p-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) (hereinafter abbreviated as pMOS) 15a and an n-channel MOSFET (hereinafter abbreviated as nMOS) 15b. A power supply potential VDD2 is applied to the source of the pMOS 15a, and the drain of the pMOS 15a is connected to the drain of the nMOS 15b and the power supply line 18. The source of the nMOS 15b is grounded. A control signal SETP is applied to the gate of the pMOS 15a. <1> is input to the gate of nMOS15b, and the control signal SETN <1> is entered.

[0015] The capacitance elements 16a to 16d are connected between the power supply line 18 and a power supply line 19 having a power supply potential (VSS (ground potential) in the example of FIG. 1) lower than the power supply potential VDD2. That is, in the example of FIG. 1, one end of each of the capacitance elements 16a to 16d is connected to the power supply line 18, and the other end is connected to the power supply line 19.

[0016] The capacitive elements 16a to 16d may be, for example, MOS capacitors or ferroelectric capacitors. The number of capacitive elements is not limited to four, and may be one.

[0017] The leakage current detection circuit 17 detects leakage current in the capacitance elements 16a to 16d. The input terminal of the leakage current detection circuit 17 is connected to the power supply line 18, and the output terminal of the leakage current detection circuit 17 outputs a detection result DET indicating the detection result of the leakage current (presence or absence of leakage current). <1> will be output.

[0018] The memory circuit 12 stores the detection results of the leakage current in each of the smoothing capacitance circuits 11a1 to 11aN. The memory circuit 12 may be a volatile memory circuit such as a RAM (Random Access Memory), or a non-volatile memory circuit such as an EEPROM (Electrically Erasable Programmable Read-Only Memory), a flash memory, or a ferroelectric memory.

[0019] The smoothing capacitance setting circuit 13 outputs a control signal SETP to the smoothing capacitance circuits 11a1 to 11aN based on the detection result of the leakage current stored in the memory circuit 12. <1> ~SETP <n>,SETN <1> ~SETN <n>When the semiconductor device 10a is in a standby state, the smoothing capacitance setting circuit 13 supplies a control signal to the smoothing capacitance circuit in which a leakage current is detected, to stop application of the power supply potential VDD2 to the power supply line 18 of the smoothing capacitance circuit.

[0020] When the semiconductor device 10a is in operation, the smoothing capacitance setting circuit 13 supplies a control signal to the smoothing capacitance circuit in which a leakage current has been detected, for applying a power supply potential VDD2 to the power supply line 18 of the smoothing capacitance circuit.

[0021] FIG. 2 is a diagram showing a circuit configuration of an example of a leakage current detection circuit. The leakage current detection circuit 17 includes an inverter circuit 17a, a pMOS 17b, an nMOS 17c, and inverter circuits 17d and 17e.

[0022] The control signal SETP is input to the input terminal of the inverter circuit 17a. <1> is input to the inverter circuit 17a. The output terminal of the inverter circuit 17a is connected to the gate of the nMOS 17c. The gate of the pMOS 17b is connected to the power supply line 18 and is at the potential VDE. The power supply potential VDD2 is applied to the source of the pMOS 17b, and the drain of the pMOS 17b is connected to the drain of the nMOS 17c and the input terminal of the inverter circuit 17d. The source of the nMOS 17c is grounded. The inverter circuits 17d and 17e connected in series function as a buffer circuit, and the output of the buffer circuit (the output of the inverter circuit 17e) is converted into the detection result DET <1> is.

[0023] Although not shown in the figure, the output terminal of the leakage current detection circuit 17 is connected to the smoothing capacitance setting circuit 13. Note that a bus holder that holds the output state of the leakage current detection circuit 17 may also be connected to the output terminal of the leakage current detection circuit 17.

[0024] Next, an example of operation of the semiconductor device 10a (a method for reducing standby current) will be described, focusing on the operation at the time of initial setting of the smoothing capacitance circuits 11a1 to 11aN by the smoothing capacitance setting circuit 13. 3 is a timing chart showing an example of the operation of the semiconductor device when a leakage current occurs. In FIG. 3, signals CEB, SET, ACT, a control signal SETN <1> ,SETP <1> , potential VDE, detection result DET <1> An example of the time variation of is shown.

[0025] The signal CEB is a chip enable signal whose logic level becomes L (low) level (for example, ground potential) when the semiconductor device 10a is operating. The signal SET is a signal whose logic level becomes H (high) level (for example, power supply potential VDD2) when the latch circuit in the smoothing capacitance setting circuit 13 holds the leakage current detection result. The signal ACT is a signal whose logic level becomes H level when the capacitance elements (such as capacitance elements 16a to 16d) of the smoothing capacitance circuits 11a1 to 11aN are charged and when the semiconductor device 10a is in standby or operating mode. The signal CEB is a signal input from outside (outside the chip) the semiconductor device 10a, which is, for example, a one-chip semiconductor integrated circuit. The signals SET and ACT are, for example, signals generated by a control circuit (such as a command generating circuit, not shown) in the semiconductor device 10a.

[0026] When the logic level of the signal ACT rises from L level to H level (timing t1), the smoothing capacitance setting circuit 13 outputs the control signal SETN <1> ,SETP <1> The logic level of falls from H level to L level. As a result, the pMOS 15a of the switch circuit 15 of the smoothing capacitance circuit 11a1 turns on and the nMOS 15b turns off, so that the potential VDE starts to rise and the capacitance elements 16a to 16d start to charge. The potential VDE rises to the power supply potential VDD2.

[0027] When the logic level of the signal ACT falls from H level to L level (timing t2), the smoothing capacitance setting circuit 13 sets the control signal SETP <1> The logic level of this signal is raised to H level, which turns off the pMOS 15a of the switch circuit 15, puts the power supply line 18 in a floating state, and starts the leakage current detection period.

[0028] Although not shown in the figure, the smoothing capacitance setting circuit 13 supplies a control signal SETP to the smoothing capacitance circuits 11a2 to 11aN. <2> ~SETP <n>,SETN <2> ~SETN <n>Regarding the control signal SETN <1> ,SETP <1> Change it in the same way.

[0029] When a leak current occurs in any of the capacitance elements 16a to 16d of the smoothing capacitance circuit 11a1, the potential VDE drops as shown in Fig. 3. When the potential VDE becomes equal to or lower than the threshold value of the pMOS 17b of the leakage current detection circuit 17, the pMOS 17b turns on, and the detection result DET <1> At this time, the smoothing capacitance setting circuit 13 sets the control signal SETN <1> The logic level of this signal rises to H level, thereby turning on the nMOS 15b of the switch circuit 15.

[0030] When the logic level of the signal SET rises to H level (timing t3), a latch period begins in which the latch circuit in the smoothing capacitance setting circuit 13 holds the detection result of the leakage current. Although not shown in the drawing, the detection result of the leakage current is then stored in the storage circuit 12. This completes the initial setting of the smoothing capacitance circuits 11a1 to 11aN.

[0031] When the logic level of the signal SET falls to L level and the logic level of the signal ACT rises to H level (timing t4), the standby period starts. At this time, the control signal SETN supplied to the smoothing capacitance circuit 11a1 in which the leakage current is detected <1> ,SETP <1> The logic level of remains at H level. Therefore, the switch circuit 15 stops the application of the power supply potential VDD2 to the power supply line 18. Note that in the smoothing capacitance circuits in which no leakage current is detected, the application of the power supply potential VDD2 to the power supply line 18 is not stopped.

[0032] When the logic level of the signal CEB falls to the L level (timing t5), the standby period ends and the normal operation period of the semiconductor device 10a begins. <1> ,SETP <1> This causes the pMOS 15a of the switch circuit 15 to turn on, the power supply potential VDD2 is applied again to the power supply line 18 of the smoothing capacitance circuit 11a1 in which the leakage current has been detected, and the potential VDE starts to rise.

[0033] 4 is a timing chart showing an example of the operation of the semiconductor device when no leakage current occurs. In FIG. 4, similarly to FIG. 3, signals CEB, SET, ACT, and a control signal SETN are <1> ,SETP <1> , potential VDE, detection result DET <1> An example of the time variation of is shown.

[0034] If no leakage current occurs, the potential VDE does not drop during the leakage detection period from timing t2 to timing t3. <1> and the control signal SETN <1> The logic level of remains at the L level. Therefore, even during the standby period from timing t4 to timing t5, the power supply potential VDD2 is applied to the power supply line 18. In other words, the potential VDE remains at the power supply potential VDD2.

[0035] Next, before describing the effects of the semiconductor device 10a of the first embodiment, a comparative example will be described. (Comparative Example) FIG. 5 is a diagram showing a semiconductor device of a first comparative example.

[0036] The semiconductor device 10b has a smoothing capacitance circuit 11b provided on the periphery of the semiconductor device 10b. The smoothing capacitance circuit 11b has a plurality of capacitance elements 11b1, 11b2, 11b3, 11b4, ... provided between a power supply line 18 to which a power supply potential VDD2 is applied and a power supply line 19 having a power supply potential VSS. The resistance indicated by the dotted line indicates the parasitic resistance of the capacitance element 11b1.

[0037] In such a semiconductor device 10b, if a leakage current flows through the capacitive element 11b1 in the direction indicated by the arrow in FIG. 5, the standby current of the semiconductor device 10b increases, and the semiconductor device 10b may be determined to be defective during testing before shipping. For example, if the standby current exceeds 200 μA, the semiconductor device 10b may be determined to be defective and may not be shipped. When stacked ferroelectric capacitors (formed by stacking multiple ferroelectric capacitors in the thickness direction) are used as the capacitive elements 11b1, 11b2, 11b3, 11b4, ..., the leakage current varies greatly.

[0038] When the semiconductor device 10b is applied, which has a relatively large current, it is desirable that the capacitance value of the capacitive element used as the smoothing capacitance is about 20 nF, but this will result in a large leakage current. On the other hand, this leakage current has little effect on the operation of the semiconductor device 10b at startup.

[0039] FIG. 6 is a diagram showing a semiconductor device of a second comparative example. Semiconductor device 10c includes smoothing capacitance circuit 11c provided on the periphery of semiconductor device 10c. Smoothing capacitance circuit 11c includes a plurality of pairs of capacitance elements connected in series between power supply line 18 to which power supply potential VDD2 is applied and power supply line 19 having power supply potential VSS. For example, a pair of capacitance elements 11c1 and 11c2, a pair of capacitance elements 11c3 and 11c4, and a pair of capacitance elements 11c5 and 11c6 are connected between power supply line 18 and power supply line 19. The resistances indicated by dotted lines represent the parasitic resistances of capacitance elements 11c1 and 11c2.

[0040] In such a semiconductor device 10c, even if the parasitic resistance of one of the series-connected capacitance elements 11c1 and 11c2 is small, if the parasitic resistance of the other is large, the leakage current flowing in the direction indicated by the arrow in FIG. 6 can be reduced.

[0041] However, when two capacitance elements with the same capacitance value are connected in series, the capacitance value is reduced to half compared to when a single capacitance element is connected. To obtain a capacitance value equivalent to that of the smoothing capacitance circuit 11b in the semiconductor device 10b of Comparative Example 1, the area of ​​the capacitance elements is four times that of the semiconductor device 10b.

[0042] (Effects of the semiconductor device 10a of the first embodiment) 1, the semiconductor device 10a of the first embodiment differs from the semiconductor devices 10b and 10c of the comparative examples 1 and 2 in that a plurality of capacitance elements functioning as smoothing capacitances are divided into a plurality of blocks as smoothing capacitance circuits 11a1 to 11aN. Each of the smoothing capacitance circuits 11a1 to 11aN is provided with a switch circuit (for example, switch circuit 15) that switches whether or not the power supply potential VDD2 is applied to the power supply line 18. Furthermore, each of the smoothing capacitance circuits 11a1 to 11aN detects leakage current, and the detection result is stored in the memory circuit 12.

[0043] Then, based on the leakage current detection result stored in the memory circuit 12, the smoothing capacitance setting circuit 13 stops the application of the power supply potential VDD2 to the power supply line 18 of the smoothing capacitance circuit in which the leakage current is detected when the semiconductor device 10a is in standby state.

[0044] As a result, the capacitance elements in the smoothing capacitance circuit in which the application of the power supply potential VDD2 to the power supply line 18 has been stopped are not used as smoothing capacitances, and the standby current is no longer increased due to leakage current, thereby reducing the standby current of the semiconductor device 10a.

[0045] In addition, in a smoothing capacitance circuit in which no leakage current is detected, the application of the power supply potential VDD2 to the power supply line 18 is not stopped even in the standby state, so that unnecessary charging and discharging of electric charges is suppressed.

[0046] Furthermore, during normal operation of the semiconductor device 10a, the leakage current has little effect on the startup operation of the semiconductor device 10a. Therefore, when the semiconductor device 10a is in the standby state, the application of the power supply potential VDD2 to the power supply line 18 of the smoothing capacitance circuit is stopped, but by restarting the application of the power supply potential VDD2 to the smoothing capacitance circuit, the capacitance element included in the smoothing capacitance circuit can be used as a smoothing capacitance.

[0047] Furthermore, the semiconductor device 10a can reduce the leakage current without connecting a capacitance element in series between the power supply lines 18 and 19 as in the semiconductor device 10c of Comparative Example 2, and therefore can suppress an increase in area due to the capacitance element.

[0048] (Second embodiment) FIG. 7 is a diagram illustrating an example of a semiconductor device according to the second embodiment. The semiconductor device 20 of the second embodiment is, for example, a one-chip semiconductor integrated circuit including a ferroelectric memory 21.

[0049] The semiconductor device 20 includes a ferroelectric memory 21, an address decoder 22, a row decoder 23, a column decoder 24, a command generating circuit 25, an oscillator / counter circuit 26, a timing circuit 27, a regulator 28, and an input / output circuit 29. The semiconductor device 20 further includes smoothing capacitance circuits 30a1, 30a2, ..., 30aN, a smoothing capacitance setting circuit 31, and a switch circuit 32.

[0050] The ferroelectric memory 21 has a memory cell array consisting of a plurality of ferroelectric memory cells arranged in a matrix, and a plurality of bit lines, a plurality of word lines, and a plurality of plate lines, each connected to one of the plurality of ferroelectric memory cells. A detection result storage unit 21a that stores the detection result of the leakage current is provided in a part of the memory cell array. The detection result storage unit 21a is an example of the storage circuit 12 shown in FIG. 1.

[0051] The ferroelectric memory 21 includes a driver circuit, a sense amplifier, a column switch, a write amplifier, and the like. The address decoder 22 generates a row address and a column address from the address signal ADDRESS received from outside the semiconductor device 20, based on the command generated by the command generating circuit 25. Then, the address decoder 22 supplies the row address to a row decoder 23 and the column address to a column decoder 24.

[0052] The row decoder 23 generates a row decode signal by decoding the row address at a timing based on a timing signal generated by a timing circuit 27, and supplies the generated row decode signal to a driver circuit of the ferroelectric memory 21. The driver circuit applies a predetermined voltage for a predetermined period to a word line or plate line designated by the row decode signal among a plurality of word lines.

[0053] The column decoder 24 generates a column decode signal by decoding the column address. The generated column decode signal is supplied to a column switch of the ferroelectric memory 21, and the column switch selects one of the multiple bit lines to connect to a write amplifier or an input / output circuit 29 based on the column decode signal.

[0054] The command generating circuit 25 generates various commands (signals ACT, SET, PWON, RESTORE, etc.) in synchronization with a clock signal supplied from an oscillator / counter circuit 26, based on signals CEB, WEB, OEB, and MODE received from outside the semiconductor device 20. The signal CEB is a chip enable signal, the signal WEB is a write enable signal, the signal OEB is an output enable signal, and the signal MODE is a mode signal indicating the operation mode.

[0055] When the reset state is released by the power-on reset signal POR, the oscillator / counter circuit 26 outputs the leakage current detection result DET <1> ~DET <n>The number of times the detection result DET is written to the detection result storage unit 21a and the number of times the detection result DET is read from the detection result storage unit 21a are counted. The count result is supplied to the command generating circuit 25. <1> ~DET <n>As will be described later, n bits are read and written at a time, so the number of times it takes to complete reading and writing all N bits is T=N / n.

[0056] The timing circuit 27 generates timing signals that determine the operation timings of the row decoder 23 , the regulator 28 , and the input / output circuit 29 based on the commands generated by the command generating circuit 25 .

[0057] The regulator 28 generates a power supply potential VDD2 by stepping down the external power supply potential VDD1 based on the timing signal generated by the timing circuit 27. The regulator 28 also generates a power-on reset signal POR.

[0058] The input / output circuit 29 includes a write buffer that receives and holds, for example, the leakage current detection result Q<1:n> and write data supplied from outside the semiconductor device 20 via the switch circuit 32 and the bus "BUS." The write buffer may have a function of holding data read by the sense amplifier of the ferroelectric memory 21 for write back. The input / output circuit 29 also holds and outputs the value of the data determined by the sense amplifier.

[0059] The smoothing capacitance circuits 30a1 to 30aN are provided on the periphery of the semiconductor device 20 and smooth out power supply noise to suppress fluctuations in the power supply voltage. Each of the smoothing capacitance circuits 30a1 to 30aN has the same circuit configuration as the smoothing capacitance circuit 11a1 shown in FIG.

[0060] The smoothing capacitance setting circuit 31 performs the following operation based on the signals ACT, SET, and PWON generated by the command generating circuit 25 and the power-on reset signal POR supplied from the regulator .

[0061] The smoothing capacitance setting circuit 31 receives the detection result DET of the leakage current from the smoothing capacitance circuits 30a1 to 30aN. <1> ~DET <n>, and stores them, and also outputs the detection results Q <1> ~Q <n>to the switch circuit 32.

[0062] Furthermore, the smoothing capacitance setting circuit 31 detects the leakage current detection result DET stored in the detection result storage unit 21a. <1> ~DET <n>The smoothing capacitance setting circuit 31 receives and holds the detection result DET <1> ~DET <n>Based on this, the control signal SETP is sent to the smoothing capacitance circuits 30a1 to 30aN. <1> ~SETP <n>,SETN <1> ~SETN <n>In FIG. 7, the control signal SETP <1> ~SETP <n>These are collectively referred to as SETP<1:N> and the control signal SETN <1> ~SETN <n>These are collectively written as SETN<1:N>.

[0063] Based on a signal RESTORE generated by a command generating circuit 25, the switch circuit 32 switches between connecting the external terminal through which write data and read data are input and output to the input / output circuit 29, or connecting the smoothing capacitance setting circuit 31 to the input / output circuit 29.

[0064] FIG. 8 is a diagram illustrating an example of a smoothing capacitance setting circuit. The smoothing capacitance setting circuit 31 includes a selection circuit 31a, latch circuits 31b1, 31b2, ..., 31bN, and control signal setting circuits 31c1, 31c2, ..., 31cN. In FIG. 8, the latch circuits 31b1 to 31bN are <1> ,LAT <2> ,…,LAT <n>The control signal setting circuits 31c1 to 31cN are represented as SET <1> ,SET <2> ,…,SET <n>It is written as follows.

[0065] When detecting a leakage current in the smoothing capacitance circuits 30a1 to 30aN, the selection circuit 31a outputs the N-bit detection results DET held by the latch circuits 31b1 to 31bN. <1> ~DET <n>Select n bits at a time and obtain the detection result Q <1> ~Q <n>The selection circuit 31a supplies the detection result DET of the leakage current stored in the detection result storage unit 21a to the switch circuit 32. <1> ~DET <n>The detection result Q is output from the switch circuit 32 n bits at a time. <1> ~Q <n>Then, the selection circuit 31a selects n latch circuits 31b1 to 31bN and outputs the detection result Q <1> ~Q <n>supply.

[0066] When the reset state is released by the power-on reset signal POR, the latch circuits 31b1 to 31bN output the detection result DET based on the signals ACT and SET. <1> ~DET <n>Hold.

[0067] When the logic level of the signal PWON is at H level, the control signal setting circuits 31c1 to 31cN output the detection results DET held in the latch circuits 31b1 to 31bN. <1> ~DET <n>Based on this, the control signal SETP <1> ~SETP <n>,SETN <1> ~SETN <n>are supplied to the smoothing capacitance circuits 30a1 to 30aN.

[0068] Next, an example of the operation of the semiconductor device 20 will be described, focusing on the operation at the time of initial setting of the smoothing capacitance circuits 30a1 to 30aN by the smoothing capacitance setting circuit 31. 9 is a timing chart showing an example of the operation of the semiconductor device when a leakage current occurs. In FIG. 9, the signals CEB, RESTORE, PWON, ACT, and SET, the control signal SETN <1> ,SETP <1> , potential VDE, detection result DET <1> ,Q <1> An example of the time variation of is shown.

[0069] When the logic level of the signal ACT rises from L level to H level (timing t10), the control signal setting circuit 31c1 of the smoothing capacitance setting circuit 31 sets the control signal SETN <1> ,SETP <1> The logic level of this signal falls from H level to L level. As a result, the potential VDE starts to rise in the smoothing capacitance circuit 30a1, and the capacitance elements (capacitance elements 16a to 16d in the example of FIG. 1) included in the smoothing capacitance circuit 30a1 start to charge. The potential VDE rises to the power supply potential VDD2.

[0070] When the logic levels of the signals PWON and ACT fall from H level to L level (timing t11), the control signal setting circuit 31c1 sets the control signal SETP <1> The logic level of this signal is raised to H level, which causes the power supply line (power supply line 18 in the example of FIG. 1) connected to the capacitance element included in the smoothing capacitance circuit 30a1 to enter a floating state, and a period for detecting leakage current begins.

[0071] Although not shown in the figure, the control signal setting circuits 31c2 to 31cN set the control signals SETP to be supplied to the smoothing capacitance circuits 30a2 to 30aN. <2> ~SETP <n>,SETN <2> ~SETN <n>Regarding the control signal SETN <1> ,SETP <1> Change it in the same way.

[0072] When a leakage current occurs in the capacitance element included in the smoothing capacitance circuit 30a1, the potential VDE drops as shown in Fig. 9. When the potential VDE becomes equal to or lower than a predetermined threshold value (equal to or lower than the threshold value of the pMOS 17b of the leakage current detection circuit 17 as shown in Fig. 2), the detection result DET <1> At this time, the control signal setting circuit 31c1 sets the logic level of the control signal SETN <1> The logic level of this signal is raised to H level, whereby the power supply line connected to the capacitance element included in the smoothing capacitance circuit 30a1 is grounded via the switch circuit 15 as shown in FIG.

[0073] When the logic level of the signal SET rises to H level (timing t12), the latch circuits 31b1 to 31bN in the smoothing capacitance setting circuit 31 output the leak current detection result DET <1> ~DET <n>This is the latch period in which the

[0074] When the logic levels of the signals RESTORE, PWON, and ACT rise to the H level and the logic level of the signal SET falls to the L level (timing t13), the detection result DET <1> ~DET <n>The storage period for storing the detected result in the detection result storage unit 21a starts.

[0075] During the storage period, the N-bit detection results DET held in the latch circuits 31b1 to 31bN are <1> ~DET <n>is selected by the selection circuit 31a at n bits, and the detection result Q <1> ~Q <n>9, the detection result DET <1> Since the logic level of is H level, at timing t13, the detection result Q <1> When the logic level of the signal RESTORE is at the H level, the switch circuit 32 connects the smoothing capacitance setting circuit 31 and the input / output circuit 29. When the logic level of the signal RESTORE is at the H level, the address decoder 22 generates a row address and a column address that specify the detection result storage section 21a of the ferroelectric memory 21 as a storage area. As a result, the detection result Q <1> ~Q <n>is written and stored in the detection result storage unit 21a via the input / output circuit 29. When N=T×n, such processing is repeated T times.

[0076] Detection result DET <1> ~DET <n>When the saving of the data is completed, the logic level of the signal RESTORE falls to the L level (timing t14). This completes the initial setting of the smoothing capacitance circuits 30a1 to 30aN, and the standby period begins. At this time, the control signal SETN supplied to the smoothing capacitance circuit 30a1 in which the leakage current has been detected <1> ,SETP <1> remains at the H level. Therefore, the application of the power supply potential VDD2 to the power supply line to which the capacitive element is connected in the smoothing capacitance circuit 30a1 is stopped. Note that in the smoothing capacitance circuit in which no leakage current is detected, the application of the power supply potential VDD2 to the power supply line to which the capacitive element is connected is not stopped.

[0077] When the logic level of the signal CEB falls to the L level (timing t15), the standby period ends and the normal operation period of the semiconductor device 20 begins. At this time, the control signal setting circuit 31c1 sets the control signal SETN <1> ,SETP <1> The logic level of falls to L. As a result, the power supply potential VDD2 is applied again to the power supply line connected to the capacitance element of the smoothing capacitance circuit 30a1 in which the leakage current has been detected, and the potential VDE starts to rise.

[0078] 10 is a timing chart showing an example of the operation of the semiconductor device when no leakage current occurs. In FIG. 10, similarly to FIG. 9, the signals CEB, RESTORE, PWON, ACT, SET, and the control signal SETN are <1> ,SETP <1> , potential VDE, detection result DET <1> ,Q <1> An example of the time variation of is shown.

[0079] If no leakage current occurs, the potential VDE does not drop during the leakage detection period from timing t11 to timing t12. <1> and the control signal SETN <1> The logic level of remains at the L level. Therefore, even during the standby period from timing t14 to timing t15, the power supply potential VDD2 is applied to the power supply line to which the capacitive element in the smoothing capacitance circuit 30a1 is connected. In other words, the potential VDE remains at the power supply potential VDD2.

[0080] Next, an example of the operation of the smoothing capacitance setting circuit 31 when the semiconductor device 20 is started up after the initial setting will be described. 11 is a timing chart showing an example of setting control signals for a smoothing capacitance circuit in which a leak current is detected. In FIG. 11, the power-on reset signal POR, the signals RESTORE, PWON, and ACT, and the control signal SETN are <1> ,SETP <1> , potential VDE, detection result DET <1> ,Q <1> 11 shows an example of the time change of the control signal SETN supplied to the smoothing capacitance circuit 30a1 at the time of startup when a leak current is detected in the smoothing capacitance circuit 30a1 at the time of initialization. <1> ,SETP <1> An example of the configuration is shown.

[0081] When the power supply to the semiconductor device 20 is turned on and the logic levels of the power-on reset signal POR and the signals RESTORE and PWON rise to the H level (timing t20), the leakage current detection result DET <1> ~DET <n>The readout period begins.

[0082] During the readout period, the detection result DET stored in the detection result storage unit 21a is <1> ~DET <n>The detection result Q is n bits at a time. <1> ~Q <n>When a leak current is detected in the smoothing capacitance circuit 30a1, the detection result Q <1> The logic level of the smoothing capacitance setting circuit 31 rises to H level. <1> ~Q <n>via the switch circuit 32. The selection circuit 31a then selects n latch circuits 31b1 to 31bN and outputs the detection result Q <1> ~Q <n>When N=T×n, this process is repeated T times, and the detection results DET are supplied to the latch circuits 31b1 to 31bN. <1> ~DET <n>is maintained.

[0083] At timing t20, the control signal SETN <1> ~SETN <n>,SETP<1>~SETP <n>The logic level of falls to the L level. As a result, the power supply potential VDD2 is applied to the power supply lines to which the capacitive elements of the smoothing capacitance circuits 30a1 to 30aN are connected, and the potential VDE rises to the power supply potential VDD2.

[0084] When the logic level of the signal RESTORE falls to the L level and the signal ACT rises to the H level (timing t21), the standby period begins. During the standby period, the control signal setting circuits 31c1 to 31cN output the detection results DET held in the latch circuits 31b1 to 31bN. <1> ~DET <n>Based on the control signal SETN <1> ~SETN <n>,SETP<1>~SETP <n>Then, the control signal setting circuits 31c1 to 31cN set the set control signal SETN <1> ~SETN <n>,SETP<1>~SETP <n>11, the control signal setting circuit 31c1 supplies the control signal SETN <1> ,SETP <1> The logic level of this signal is set to H level and supplied to the smoothing capacitance circuit 30a1. As a result, the application of the power supply potential VDD2 to the power supply line to which the capacitance element is connected in the smoothing capacitance circuit 30a1 is stopped. Note that in smoothing capacitance circuits in which no leakage current is detected, the application of the power supply potential VDD2 to the power supply line to which the capacitance element is connected is not stopped.

[0085] 9 and 10, when the logic level of the signal CEB falls to the L level, the standby period ends and the normal operation period of the semiconductor device 20 starts (timing t22). <1> ,SETP <1> The logic level of falls to L. As a result, the power supply potential VDD2 is applied again to the power supply line connected to the capacitance element of the smoothing capacitance circuit 30a1 in which the leakage current has been detected, and the potential VDE starts to rise.

[0086] Therefore, the capacitance element included in the smoothing capacitance circuit 30a1 in which the leak current is detected is also used as a smoothing capacitance. 12 is a timing chart showing an example of setting control signals for a smoothing capacitance circuit in which no leakage current is detected. In FIG. 12, similarly to FIG. 11, the power-on reset signal POR, the signals RESTORE, PWON, ACT, and the control signal SETN are set. <1> ,SETP <1> , potential VDE, detection result DET <1> ,Q <1> 12 shows an example of the time change of the control signal SETN supplied to the smoothing capacitance circuit 30a1 at the time of startup when no leakage current is detected in the smoothing capacitance circuit 30a1 at the time of initialization. <1> ,SETP <1> An example of the configuration is shown.

[0087] If no leakage current is detected in the smoothing capacitance circuit 30a1, the detection result Q <1> Therefore, during the standby period from timing t21 to t22, the control signal setting circuit 31c1 sets the control signal SETN <1> ,SETP <1> The logic level of is set to L level and supplied to the smoothing capacitance circuit 30a1. Therefore, even during the standby period, the power supply potential VDD2 is applied to the power supply line to which the capacitive element in the smoothing capacitance circuit 30a1 is connected. In other words, the potential VDE remains at the power supply potential VDD2.

[0088] The semiconductor device 20 of the second embodiment as described above also achieves the same effects as the semiconductor device 10a of the first embodiment. That is, in a smoothing capacitance circuit in which a leakage current is detected, stopping the application of the power supply potential to the power supply line connected to the capacitance element during standby prevents the leakage current from increasing the standby current. As a result, the standby current of the semiconductor device 20 can be reduced.

[0089] Furthermore, in a smoothing capacitance circuit in which no leakage current is detected, the application of the power supply potential VDD2 to the power supply line to which the capacitance element is connected is not stopped even in the standby state, so that unnecessary charging and discharging of electric charges is suppressed.

[0090] Furthermore, during normal operation of the semiconductor device 20, by resuming the application of the power supply potential VDD2 to the smoothing capacitance circuit to which the application of the power supply potential VDD2 was stopped during standby state, the capacitance element included in the smoothing capacitance circuit can be used as a smoothing capacitance.

[0091] Furthermore, the semiconductor device 20 can reduce the standby current without connecting a capacitance element in series between the power supply lines 18 and 19 as in the semiconductor device 10c of Comparative Example 2, and therefore can suppress an increase in area due to the capacitance element.

[0092] Since the semiconductor device 20 of the second embodiment includes the ferroelectric memory 21, the capacitance elements included in the smoothing capacitance circuits 30a1 to 30aN can be ferroelectric capacitors, and thus can be manufactured in the manufacturing process of the ferroelectric memory 21. If stacked ferroelectric capacitors are used, the leakage current varies greatly. However, as described above, the semiconductor device 20 of the second embodiment can individually control whether or not to apply the power supply potential VDD2 to the smoothing capacitance circuits in which leakage current is detected, so that the standby current can be reduced even when ferroelectric capacitors are used as capacitance elements.

[0093] (Third embodiment) FIG. 13 is a diagram illustrating an example of a semiconductor device according to the third embodiment. The semiconductor device 40 of the third embodiment is, for example, a one-chip semiconductor integrated circuit, and includes a plurality of smoothing capacitance circuits 41a1, 41a2, ..., 41aN, a memory circuit 42, and a smoothing capacitance setting circuit 43. Other internal circuits of the semiconductor device 40 are not shown in the drawing.

[0094] The smoothing capacitance circuits 41a1 to 41aN are provided on the periphery of the semiconductor device 40 and smooth out power supply noise to suppress fluctuations in the power supply voltage. An example of the smoothing capacitance circuit 41a1 is shown in Fig. 13. The other smoothing capacitance circuits 41a2 to 41aN have the same circuit configuration as the smoothing capacitance circuit 41a1.

[0095] The smoothing capacitance circuit 41a1 includes a switch circuit 45, capacitance elements (eight capacitance elements 46a1, 46a2, 46a3, 46a4, 46b1, 46b2, 46b3, and 46b4 in the example of FIG. 1), and leakage current detection circuits 47a and 47b.

[0096] The switch circuit 45 controls whether or not the power supply potential VDD1 is applied to the power supply line 48a using a control signal SET1P. <1> ,SET1N <1> Furthermore, the switch circuit 45 controls whether or not the power supply potential VDD2 is applied to the power supply line 48b by a control signal SET2P <1> ,SET2N <1> Switch accordingly.

[0097] The power supply potential VDD2 is a potential obtained by stepping down the power supply potential VDD1. Note that the potential VDE1 indicates the potential of the power supply line 48a, and the potential VDE2 indicates the potential of the power supply line 48b. The switch circuit 45 includes, for example, pMOSs 45a and 45c and nMOSs 45b and 45d. The power supply potential VDD1 is applied to the source of the pMOS 45a, and the drain of the pMOS 45a is connected to the drain of the nMOS 45b and the power supply line 48a. The source of the nMOS 45b is grounded. A control signal SET1P is applied to the gate of the pMOS 45a. <1> is input to the gate of nMOS45b, and the control signal SET1N <1> The power supply potential VDD2 is applied to the source of the pMOS 45c, and the drain of the pMOS 45c is connected to the drain of the nMOS 45d and the power supply line 48b. The source of the nMOS 45d is grounded. The control signal SET2P is applied to the gate of the pMOS 45c. <1> is input to the gate of nMOS45d, and the control signal SET2N <1> is entered.

[0098] Capacitor elements 46a1-46a4 are connected between power supply line 48a and power supply line 48b. That is, in the example of Fig. 13, one end of capacitor elements 46a1-46a4 is connected to power supply line 48a, and the other end is connected to power supply line 48b. Capacitor elements 46b1-46b4 are connected between power supply line 48b and power supply line 49, which has a power supply potential lower than power supply potential VDD2 (power supply potential VSS in the example of Fig. 13). That is, in the example of Fig. 13, one end of capacitor elements 46b1-46b4 is connected to power supply line 48b, and the other end is connected to power supply line 49.

[0099] For example, the capacitive elements 46a1 to 46a4 are arranged on the IN side (inside) of the semiconductor device 40, and the capacitive elements 46b1 to 46b4 are arranged on the OUT side (outside) of the semiconductor device 40.

[0100] The capacitive elements 46a1-46a4 and 46b1-46b4 may be, for example, MOS capacitors or ferroelectric capacitors. The number of capacitive elements connected between the power supply lines 48a and 48b and the number of capacitive elements connected between the power supply lines 48b and 49 are not limited to four, and may be one.

[0101] The leakage current detection circuit 47a detects leakage current in the capacitance elements 46a1 to 46a4. The input terminal of the leakage current detection circuit 47a is connected to the power supply line 48a, and the output terminal of the leakage current detection circuit 47a outputs a detection result DET1 indicating the detection result of the leakage current. <1> will be output.

[0102] The leakage current detection circuit 47b detects leakage current in the capacitance elements 46b1 to 46b4. The input terminal of the leakage current detection circuit 47b is connected to the power supply line 48b, and the output terminal of the leakage current detection circuit 47b outputs a detection result DET2 indicating the detection result of the leakage current. <1> will be output.

[0103] The storage circuit 42 stores the detection results of the leakage current in each of the smoothing capacitance circuits 41a1 to 41aN. The storage circuit 42 may be a volatile storage circuit such as a RAM, or a non-volatile storage circuit such as an EEPROM, a flash memory, or a ferroelectric memory.

[0104] The smoothing capacitance setting circuit 43 outputs a control signal SET1P to the smoothing capacitance circuits 41a1 to 41aN based on the detection result of the leakage current of the capacitance elements 46a1 to 46a4 stored in the storage circuit . <1> ~SET1P <n>,SET1N <1> ~SET1N <n>Furthermore, the smoothing capacitance setting circuit 43 supplies the control signal SET2P to the smoothing capacitance circuits 41a1 to 41aN based on the detection result of the leakage current of the capacitance elements 46b1 to 46b4 stored in the storage circuit 42. <1> ~SET2P <n>,SET2N <1> ~SET2N <n>supply.

[0105] When the semiconductor device 40 is in a standby state, the smoothing capacitance setting circuit 43 supplies a control signal to a smoothing capacitance circuit in which a leakage current is detected in the capacitance elements 46a1-46a4, to stop application of the power supply potential VDD1 to the power supply line 48a of the smoothing capacitance circuit. Also, when the semiconductor device 40 is in a standby state, the smoothing capacitance setting circuit 43 supplies a control signal to a smoothing capacitance circuit in which a leakage current is detected in the capacitance elements 46b1-46b4, to stop application of the power supply potential VDD2 to the power supply line 48b of the smoothing capacitance circuit.

[0106] When the semiconductor device 40 is in operation, the smoothing capacitance setting circuit 43 supplies a control signal to the smoothing capacitance circuit in which a leakage current is detected, causing the smoothing capacitance circuit to apply a power supply potential VDD1 to the power supply line 48a and a power supply potential VDD2 to the power supply line 48b.

[0107] The circuit configuration of the leakage current detection circuit 47b is the same as the circuit configuration of the leakage current detection circuit 17 shown in Fig. 2. However, in the leakage current detection circuit 47b, the control signal SET2P is supplied to the inverter circuit 17a of Fig. 2. <1> An example of the circuit configuration of the leakage current detection circuit 47a will be described later (see FIG. 18).

[0108] Although not shown in the figure, the output terminals of the leakage current detection circuits 47a and 47b are connected to the smoothing capacitance setting circuit 43. A bus holder that holds the output state of the leakage current detection circuits 47a and 47b may be further connected to the output terminals of the leakage current detection circuits 47a and 47b.

[0109] 14 is a diagram showing an example of setting the control signal supplied to the smoothing capacitance circuit 41a1. In FIG. 14, the control signal SET1P is set in two cases: when no leakage current is detected in the smoothing capacitance circuit 41a1, and when a leakage current is detected. <1> ,SET1N <1> ,SET2P <1> ,SET2N <1> An example of the configuration is shown.

[0110] In FIG. 14, the control signal SET1P <1> ,SET1N <1> ,SET2P <1> ,SET2N <1> However, they are abbreviated as 1P, 1N, 2P, and 2N. In the semiconductor device 40 of the third embodiment, the detection of the leakage current is performed by the control signal SET1P. <1> ,SET1N <1> ,SET2P <1> ,SET2N <1> This is done with all the logic levels set to L level (setting procedure (1)).

[0111] When no leakage current is detected, the leakage current detection circuits 47a and 47b output the detection result DET1. <1> ,DET2 <2> In this case, even in the standby state, the logic level of the control signal SET1P <1> ,SET1N <1> ,SET2P <1> ,SET2N <1> The logic level of each of these signals is maintained at L level. As a result, the capacitive elements 46a1 to 46a4 and 46b1 to 46b4 all function as smoothing capacitors.

[0112] In the first case where a leakage current is detected, the detection result DET1 output by the leakage current detection circuit 47a is <1> The logic level of the detection result DET2 output by the leakage current detection circuit 47b is H level. <1> The logic level of the control signal SET1P is at the L level. That is, a leakage current occurs in one of the capacitive elements 46a1 to 46a4, but no leakage current occurs in the capacitive elements 46b1 to 46b4. In this case, in the standby state, <1> The logic level of the control signal SET1N is set to H level. <1> ,SET2P <1> ,SET2N <1> The logic level of is set to L level (setting procedure (2)). As a result, the pMOS 45a of the switch circuit 45 is turned off, and the application of the power supply potential VDD1 to the power supply line 48a is stopped. Therefore, the leakage current disappears. On the other hand, the pMOS 45c is not turned off, and the application of the power supply potential VDD2 to the power supply line 48b continues, and the capacitive elements 46b1 to 46b4 function as smoothing capacitors.

[0113] In the second case where a leakage current is detected, the detection result DET1 output from the leakage current detection circuits 47a and 47b is <1> ,DET2 <1> The logic level of the control signal SET1P is H. That is, a leakage current occurs in one of the capacitive elements 46a1 to 46a4, and a leakage current also occurs in one of the capacitive elements 46b1 to 46b4. In this case, in the standby state, the control signal SET1P <1> ,SET1N <1> ,SET2P <1> ,SET2N <1> The logic levels of these are all set to H level (setting procedure (2)). This turns off the pMOSs 45a and 45c of the switch circuit 45, stopping the application of the power supply potentials VDD1 and VDD2 to the power supply lines 48a and 48b. As a result, all of the capacitive elements 46a1 to 46a4 and 46b1 to 46b4 no longer function as smoothing capacitors in the standby state, but leakage current can be eliminated.

[0114] The semiconductor device 40 of the third embodiment as described above can also be applied as a semiconductor device 20 having a ferroelectric memory 21 as shown in Fig. 7. In that case, a smoothing capacitance setting circuit 43 as shown below is used instead of the smoothing capacitance setting circuit 31 shown in Fig. 8.

[0115] FIG. 15 is a diagram illustrating an example of a smoothing capacitance setting circuit in the semiconductor device according to the third embodiment. The smoothing capacitance setting circuit 43 includes a selection circuit 43a, latch circuits 43b1, 43b2, . . . , 43bN, and control signal setting circuits 43c1, 43c2, .

[0116] When detecting a leak current in the smoothing capacitance circuits 41a1 to 41aN, the selection circuit 43a selects the N×2-bit detection result DET1 held by the latch circuits 43b1 to 43bN. <1> ~DET1 <n>DET2 <1> ~DET2 <n>Then, the selection circuit 43a selects n bits of the detection result Q <1> ~Q <n>to the switch circuit 32.

[0117] The selection circuit 43a also selects the leakage current detection result DET1 stored in the detection result storage unit 21a. <1> ~DET1 <n>DET2 <1> ~DET2 <n>The detection result Q is output from the switch circuit 32 n bits at a time. <1> ~Q <n>Then, the selection circuit 43a selects n / 2 latch circuits 43b1 to 43bN and outputs the detection result Q <1> ~Q <n>supply.

[0118] When the reset state is released by the power-on reset signal POR, the latch circuits 43b1 to 43bN output the detection result DET1 based on the signals ACT and SET. <1> ~DET1 <n>DET2 <1> ~DET2 <n>For example, the latch circuit 43b1 holds the detection result DET1 <1> ,DET2 <1> Hold.

[0119] When the logic level of the signal PWON is at H level, the control signal setting circuits 43c1 to 43cN output the detection results DET1 held in the latch circuits 43b1 to 43bN. <1> ~DET1 <n>DET2 <1> ~DET2 <n>receive.

[0120] Then, the control signal setting circuits 43c1 to 43cN output the detection results DET1 <1> ~DET1 <n>Based on this, the control signal SET1P <1> ~SET1P <n>,SET1N <1> ~SET1N <n>The control signal setting circuits 43c1 to 43cN supply the detection results DET2 <1> ~DET2 <n>Based on this, the control signal SET2P <1> ~SET2P <n>,SET2N <1> ~SET2N <n>are supplied to the smoothing capacitance circuits 41a1 to 41aN.

[0121] Next, an example of the operation of the semiconductor device 40 will be described, focusing on the operation during initial setting of the smoothing capacitance circuits 41a1 to 41aN by the smoothing capacitance setting circuit 43, when the semiconductor device 40 is applied as a semiconductor device 20 having a ferroelectric memory 21 as shown in FIG.

[0122] Fig. 16 is a timing chart showing an example of the operation of the semiconductor device in Case 1 in which the leakage current is detected in Fig. 14. Fig. 16 shows the signals CEB, RESTORE, PWON, ACT, and SET, the control signal SET1N <1> ,SET1P <1> , potential VDE1, detection result DET1 <1> ,Q <1> An example of the time variation of is shown.

[0123] When the logic level of the signal ACT rises from L level to H level (timing t30), the control signal setting circuit 43c1 of the smoothing capacitance setting circuit 43 sets the control signal SET1N <1> ,SET1P <1> The logic level of the control signal SET2N falls from H level to L level. <1> ,SET2P <1> The logic level of the signal is also lowered from H level to L level.

[0124] As a result, the potential VDE1 (and the potential VDE2, not shown) in the smoothing capacitance circuit 41a1 starts to rise, and the capacitance elements 46a1 to 46a4 and 46b1 to 46b4 included in the smoothing capacitance circuit 41a1 start to charge. The potential VDE1 rises to VDD1.

[0125] When the logic levels of the signals PWON and ACT fall from H level to L level (timing t31), the leakage current detection period begins. When a leakage current occurs in the capacitive elements 46a1 to 46a4 selected for the power supply line 48a, the potential VDE1 drops as shown in Fig. 16. When the potential VDE1 becomes equal to or lower than a predetermined threshold, the detection result DET1 <1> At this time, the control signal setting circuit 43c1 sets the control signal SET1P <1> The logic level of this signal rises to H level, causing the potential VDE1 of the power supply line 48a to go into a high impedance state.

[0126] When the logic level of the signal SET rises to H level (timing t32), the latch circuits 43b1 to 43bN in the smoothing capacitance setting circuit 43 output the leak current detection result DET1 <1> ~DET1 <n>DET2 <1> ~DET2 <n>This is the latch period in which the

[0127] When the logic levels of the signals RESTORE, PWON, and ACT rise to the H level and the logic level of the signal SET falls to the L level (timing t33), the detection result DET1 <1> ~DET1 <n>DET2 <1> ~DET2 <n>The retention period begins.

[0128] Detection result DET1 <1> ~DET1 <n>DET2 <1> ~DET2 <n>When the saving of the capacitances is completed, the logic level of the signal RESTORE falls to the L level (timing t34), which ends the initial setting of the smoothing capacitance circuits 41a1 to 41aN and starts the standby period.

[0129] At this time, the control signal SET1N supplied to the smoothing capacitance circuit 41a1 in which the leak current is detected <1> ,SET1P <1> The logic level of the control signal SET1N <1> For L level, control signal SET1P <1> Therefore, the application of the power supply potential VDD1 to the power supply line 48a in the smoothing capacitance circuit 41a1 is stopped. <1> ,SET2P <1> The logic level of remains at level L. Furthermore, in the smoothing capacitance circuits in which no leakage current is detected, the application of the power supply potentials VDD1 and VDD2 to the power supply lines 48a and 48b is not stopped.

[0130] When the logic level of the signal CEB falls to the L level (timing t35), the standby period ends and the normal operation period of the semiconductor device 40 begins. At this time, the control signal setting circuit 43c1 sets the control signal SET1P <1> The logic level of this signal falls to the L level. As a result, the power supply potential VDD1 is applied again to the power supply line 48a of the smoothing capacitance circuit 41a1 in which the leakage current was detected, and the potential VDE1 starts to rise. Then, the capacitance elements 46a1 to 46a4 and 46b1 to 46b4 all function as smoothing capacitances.

[0131] Fig. 17 is a timing chart showing an example of the operation of the semiconductor device in Case 2 where the leakage current is detected in Fig. 14. Fig. 17 shows the signals CEB, RESTORE, PWON, ACT, and SET, the control signal SET1N <1> ,SET1P <1> , potential VDE1, detection result DET1 <1> ,DET2 <1> ,Q <1> An example of the time variation of is shown.

[0132] In case 2 in which a leakage current is detected in FIG. 14, at timing t31a, the detection result DET1 <1> ,DET2 <1> At this time, the control signal setting circuit 43c1 sets the control signal SET1N <1> ,SET1P <1> , and the control signal SET2N <1> ,SET2P <1> The logic level of this signal is raised to H level, thereby grounding the power supply line 48a.

[0133] During the standby period, the control signal SET1N supplied to the smoothing capacitance circuit 41a1 in which the leakage current is detected is <1> ,SET1P <1> and control signal SET2N <1> ,SET2P <1> The logic level of remains at level H. As a result, all of the capacitance elements 46a1 to 46a4 and 46b1 to 46b4 of the smoothing capacitance circuit 41a1 no longer function as smoothing capacitances.

[0134] On the other hand, during the operation period, the control signal setting circuit 43c1 sets the control signal SET1N <1> ,SET1P <1> The logic level of this signal falls to the L level. As a result, the power supply potentials VDD1 and VDD2 are applied again to the power supply lines 48a and 48b of the smoothing capacitance circuit 41a1 in which the leakage current was detected, and the potential VDE1 starts to rise. Then, all of the capacitance elements 46a1 to 46a4 and 46b1 to 46b4 function as smoothing capacitances.

[0135] According to the semiconductor device 40 of the third embodiment described above, the same effects as those of the semiconductor device 20 of the second embodiment can be obtained, and the following effects can also be obtained. By providing a capacitance element between the power supply lines 48a and 48b and between the power supply lines 48b and 49, a capacitance element with a relatively low resistance (for example, a ferroelectric capacitor) can be used as, for example, a smoothing capacitance for the power supply potential VDD1, which is the external power supply potential.

[0136] Furthermore, since capacitance elements are not simply connected in series between the power supply lines 18 and 19 as in Comparative Example 2, it is possible to increase the number of capacitance elements functioning as smoothing capacitance while suppressing an increase in area due to the capacitance elements. For example, even if the smoothing capacitance circuits in which leakage current is detected account for 5% of the total and these smoothing capacitance circuits are not used, the increase in area due to capacitance elements required to obtain a capacitance value equivalent to that of the smoothing capacitance circuit 11b of the semiconductor device 10b of Comparative Example 1 can be suppressed to about 1.05 times.

[0137] 13, the capacitance elements are arranged in a two-stage configuration, but this is not limiting. The power supply potential VDD1 may be increased to a power supply potential other than VDD2 obtained by stepping down the power supply potential VDD1, and the number of power supply lines may also be increased, so that the capacitance elements are arranged in a three-stage or more configuration.

[0138] Fig. 18 is a diagram showing the circuit configuration of an example of a leakage current detection circuit, in which the same elements as those shown in Fig. 2 are denoted by the same reference numerals. The leakage current detection circuit 47a includes an AND (logical product) circuit 47a1, a pMOS 47a2, and an nMOS 47a3 in addition to the elements of the leakage current detection circuit 17 shown in FIG.

[0139] The AND circuit 47a1 outputs a signal STBY, which is the logical AND of the signals xRESTORE, PWON, and ACT. The signal xRESTORE is a signal obtained by inverting the logic level of the signal RESTORE described above.

[0140] The signal STBY is input to the gate of the pMOS 47a2, the power supply voltage VDD2 is applied to the source of the pMOS 47a2, and the drain of the pMOS 47a2 is connected to the source of the pMOS 17b.

[0141] The signal STBY is input to the gate of the nMOS 47a3, the drain of the nMOS 47a3 is connected to the input terminal of the inverter circuit 17d, and the source of the pMOS 47a3 is grounded.

[0142] In the leakage current detection circuit 47a, when the circuit is in standby mode (when the logic levels of the signals xRESTORE, PWON, and ACT are H and the logic level of the signal STBY is H), the pMOS 47a2 is turned off. That is, the supply of the power supply potential VDD2 is cut off. Also, the nMOS 47a3 is turned on, and the input terminal of the inverter circuit 17d is grounded.

[0143] Therefore, even if the potential VDE1 of the power supply line 48a is in a high impedance state during standby, the occurrence of leakage current can be suppressed. (Variation) Fig. 19 is a diagram showing a modified example of a smoothing capacitance circuit, in which the same elements as those shown in Fig. 13 are denoted by the same reference numerals as in Fig. 13.

[0144] In the modified smoothing capacitance circuit 50, a VDE2 initialization circuit 51 is connected to the power supply line 48b. The VDE2 initialization circuit 51 sets the potential VDE2 at power-on to approximately (VDD1-VSS) / 2. This causes the capacitance elements 46a1-46a4 and 46b1-46b4 to all function as smoothing capacitances for the power supply potential VDD1, preventing noise from affecting the power supply potential VDD2.

[0145] A switch may be provided so that such a VDE2 initialization circuit 51 can be connected to the power supply line 48b instead of the pMOS 45c and nMOS 45d shown in FIG. 13 when the power supply is turned on.

[0146] While one aspect of the semiconductor device and standby current reduction method of the present invention has been described above based on the embodiment, these are merely examples and the present invention is not limited to the above description. [Explanation of symbols]

[0147] 10a Semiconductor device 11a1~11aN smoothing capacitor circuit 12 Memory circuit 13 Smoothing capacitance setting circuit 15 Switch Circuit 15a pMOS 15b nMOS 16a to 16d Capacitor elements 17 Leakage current detection circuit 18,19 Power line< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A semiconductor device in which a standby state period including a standby period and an operating period are repeated after a power supply is turned on, a plurality of smoothing capacitance circuits each including: a switch circuit that switches whether or not a first power supply potential is applied to a first power supply line in response to a first control signal; a first capacitance element that is connected between the first power supply line and a second power supply line that has a second power supply potential that is lower than the first power supply potential; and a first detection circuit that detects a first leakage current in the first capacitance element every time the standby state is entered; a storage circuit that stores a first detection result of the first detection circuit; a smoothing capacitance setting circuit that supplies the first control signal to the first smoothing capacitance circuit, which is a first smoothing capacitance circuit among the plurality of smoothing capacitance circuits and in which the first leakage current has been detected, based on the first detection result stored in the memory circuit, each time the standby state is entered; and A semiconductor device having:

2. 2. The semiconductor device according to claim 1, wherein the smoothing capacitance setting circuit supplies the first control signal, which applies the first power supply potential to the first power supply line, to all of the first smoothing capacitance circuits during the operating period after the standby state.

3. 3. The semiconductor device according to claim 1, wherein the smoothing capacitance setting circuit supplies the first control signal to the smoothing capacitance circuit each time the standby state is entered, based on the first detection result stored in the memory circuit, to continue applying the first power supply potential to the first power supply line of a smoothing capacitance circuit among the plurality of smoothing capacitance circuits in which the first leakage current is not detected.

4. 4. The semiconductor device according to claim 1, wherein the smoothing capacitance setting circuit includes a latch circuit that holds the first detection result read from the memory circuit at the time of startup.

5. 5. The semiconductor device according to claim 1, wherein the memory circuit is provided in a part of a memory cell array of a ferroelectric memory.

6. 6. The semiconductor device according to claim 1, wherein the first capacitance element is a ferroelectric capacitor.

7. Each of the plurality of smoothing capacitance circuits a third power supply line having a third power supply potential lower than the second power supply potential; a second capacitance element connected between the second power supply line and the third power supply line; a second detection circuit that detects a second leakage current in the second capacitance element; and the switch circuit switches whether or not the second power supply potential is applied to the second power supply line in response to a second control signal; the storage circuit stores the first detection result and the second detection result of the second detection circuit; the smoothing capacitance setting circuit, in the standby state, supplies the second control signal to the second smoothing capacitance circuit, based on the second detection result, for stopping application of the second power supply potential to the second power supply line of the second smoothing capacitance circuit in which the second leakage current is detected; The semiconductor device according to claim 1 .

8. 8. The semiconductor device according to claim 7, wherein the second capacitance element is a ferroelectric capacitor.

9. 9. The semiconductor device according to claim 7, further comprising an initialization circuit that sets the second power supply potential to an intermediate potential between the first power supply potential and the third power supply potential at startup.

10. a plurality of smoothing capacitance circuits each including: a switch circuit that switches whether or not a first power supply potential is applied to a first power supply line in response to a first control signal; a first capacitance element that is connected between the first power supply line and a second power supply line that has a second power supply potential that is lower than the first power supply potential; and a first detection circuit that detects a first leakage current in the first capacitance element every time the device enters a standby state; a storage circuit that stores a first detection result of the first detection circuit; A smoothing capacitance setting circuit; a standby current reduction method for a semiconductor device in which a standby state period including a standby period and an operating period are repeated after a power supply is started, The smoothing capacitance setting circuit is every time the standby state is entered, the first control signal for stopping application of the first power supply potential to the first power supply line of a first smoothing capacitance circuit in which the first leakage current has been detected among the plurality of smoothing capacitance circuits is supplied to the first smoothing capacitance circuit based on the first detection result stored in the memory circuit; Standby current reduction method.

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