Chamber configuration and process for particle control

Abstract

An exemplary processing method can include generating a plasma of a cleaning precursor in a remote region of a semiconductor processing chamber. The method can include flowing plasma effluents of the cleaning precursor into a processing region of the semiconductor processing chamber. The method can include contacting a substrate support with the plasma effluents for a first period of time. The method can include lowering the substrate support from a first position to a second position while continuously flowing the plasma effluents of the cleaning precursor. The method can include cleaning the processing region of the semiconductor processing chamber for a second period of time.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 17 / 071,506, filed October 15, 2020, entitled "CHAMBER CONFIGURATIONS AND PROCESSES FOR PARTICLE CONTROL," which is incorporated herein by reference in its entirety.

[0002]

[0002] The technology herein relates to components and apparatus for semiconductor manufacturing. More particularly, the technology herein relates to processes for producing material films for semiconductor processing. [Background technology]

[0003]

[0003] Integrated circuits are made possible by processes that create intricately patterned layers of material on substrate surfaces. Creating patterned materials on substrates requires controlled methods for forming and removing materials. Some processes utilize plasma-enhanced precursors to facilitate the deposition or removal steps. Particles can be generated during the development or removal of materials on a substrate, and these particles can be removed or pumped out of the chamber. Depending on the flow paths created within the processing chamber, these particles can redeposit on surfaces within the semiconductor processing chamber, causing buildup. This buildup can lead to arcing and other problems due to particles falling back onto the substrate. Cleaning steps can be performed after substrate processing, but these cleaning processes can incompletely clean the chamber's surfaces and recesses.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to fabricate high quality devices and structures. The technology herein addresses this and other needs. Summary of the Invention

[0005]

[0005] An exemplary processing method can include generating a plasma of a cleaning precursor in a remote region of a semiconductor processing chamber. The method can include flowing plasma effluents of the cleaning precursor into a processing region of the semiconductor processing chamber. The method can include contacting a substrate support with the plasma effluents for a first period of time. The method can include lowering the substrate support from a first position to a second position while continuously flowing the plasma effluents of the cleaning precursor. The method can include cleaning the processing region of the semiconductor processing chamber for a second period of time.

[0006] In some embodiments, the cleaning precursor can be or can include a halogen-containing precursor. The second period can be longer than the first period. The substrate support can be at a distance of about 20 mm or less from the faceplate at the first position. The substrate support can be at a distance of about 30 mm or more from the faceplate at the second position. A plasma power of about 1000 W or more can be maintained to generate plasma effluents of the cleaning precursor. A processing region can be defined by the faceplate and the substrate support. The processing region can be further defined by an inner isolator extending radially around the processing region. The inner isolator can be positioned on a ledge defined by the outer isolator. The outer isolator can be positioned on a conductive ring. The conductive ring can be positioned on the body of the semiconductor processing chamber. A liner can extend along the body of the semiconductor processing chamber toward the inner isolator and the conductive ring. A gap of about 20 mils or greater may be maintained between the inner isolator and a conductive ring disposed on the body of the semiconductor processing chamber adjacent to the surface of the conductive ring.

[0007] Some embodiments of the technology herein may include a semiconductor processing method. The method may include flowing plasma effluents of a cleaning precursor into a processing region of a semiconductor processing chamber. The method may include contacting a substrate support with the plasma effluents for a first period of time. The method may include lowering the substrate support from a first position to a second position while continuously flowing the plasma effluents of the cleaning precursor. The method may include cleaning the processing region of the semiconductor processing chamber for a second period of time at least 20% longer than the first period of time.

[0008] In some embodiments, plasma power can be maintained at about 1000 W or greater to generate plasma effluents of the cleaning precursor. The first time period can be about 40% or less of the total cleaning time. The substrate support can be about 20 mm or less from the faceplate in the first position and about 30 mm or greater from the faceplate in the second position. The semiconductor processing chamber can include an inner isolator extending radially around a processing region of the semiconductor processing chamber. The semiconductor processing chamber can include an outer isolator defining a recessed ledge, with the inner isolator mounted on the recessed ledge. The semiconductor processing chamber can include a semiconductor processing chamber body. The semiconductor processing chamber can include a conductive ring mounted on the semiconductor processing chamber body. In some embodiments, a gap of about 50 mils or greater can be maintained between the inner isolator and the conductive ring proximate a surface of the conductive ring mounted on the semiconductor processing chamber body. The method can include flowing plasma effluents of the cleaning precursor into the gap during the second time period.

[0009] The above-described techniques may provide numerous advantages over conventional systems and techniques. For example, embodiments of the present technology may utilize chamber components that may increase the available flow path for cleaning precursors. Additionally, cleaning processes may be performed to direct cleaning emissions into recesses within the chamber where redeposition or particle accumulation may occur. The above-described and other embodiments, along with their numerous advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

[0010]

[0010] The nature and advantages of the disclosed technology may be better understood by reference to the following portions of this specification and the drawings. [Brief explanation of the drawings]

[0011] [Figure 1] 1 illustrates a top view of an exemplary processing system in accordance with some embodiments of the technology herein. [Figure 2] 1 shows a schematic cross-sectional view of an exemplary plasma system in accordance with some embodiments of the technology herein; [Figure 3] 1 illustrates exemplary steps in a semiconductor processing method according to some embodiments of the technology herein. [Figure 4] 1 shows a schematic partial cross-sectional view of a chamber component in accordance with some embodiments of the technology herein. DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0015] Some figures are included as schematic diagrams. It should be understood that the figures are for illustrative purposes and should not be considered to scale unless specifically noted as such. Additionally, the figures are presented as schematic diagrams to aid understanding and may not include all aspects or information compared to realistic depictions and may include exaggerated material for illustrative purposes.

[0013]

[0016] In the accompanying figures, similar components and / or features may have the same reference numeral. Furthermore, various components of the same type may be distinguished by a letter following the reference numeral, which distinguishes between the similar components. When only a first reference numeral is used herein, the description is applicable to any similar component having the same first reference numeral, regardless of the subsequent letter.

[0014]

[0017] The plasma deposition process may excite one or more constituent precursors to facilitate film formation on the substrate. Any number of material films may be produced to develop semiconductor structures, including conductive and dielectric films, as well as films that facilitate material transfer and removal. For example, a hard mask film may be formed to facilitate substrate patterning while protecting underlying materials that should be kept separate. In many processing chambers, several precursors may be mixed in a gas panel and delivered to the processing region of the chamber where the substrate may be placed. Lid stack components may affect flow distribution to the processing chamber, while the integration of chamber components may result in additional recesses or flow paths within the processing chamber.

[0015]

[0018] As device feature sizes decrease, particle control for the films being fabricated can become more critical. Cleaning steps can be performed to remove residual particles and to maintain an environment that limits process drift and ensures uniformity between substrates. While cleaning processes produce satisfactory results along the path from the area where the cleaning material is applied, many processing chambers can experience particle buildup in other areas. For example, the manner in which components are positioned within the processing chamber can affect the gaps and accesses where particle deposition can occur. The cleaning material may not be able to adequately clean these areas, allowing buildup to occur. This buildup can cause particles to fall onto subsequent substrates or form conductive paths that can lead to arcing within the processing chamber. Conventional techniques can necessitate more frequent periodic disassembly to ensure component surfaces remain clean.

[0016]

[0019] The techniques herein overcome the above-mentioned challenges by configuring chamber components to provide additional access for cleaning effluents within the processing region. Additionally, the techniques herein allow for cleaning processes to be performed that ensure cleaning effluents are delivered within accesses within the chamber where accumulation may occur.

[0017]

[0020] While the following disclosure routinely identifies specific deposition processes utilizing the disclosed technology, it will be readily understood that the above systems and methods are equally applicable to other deposition, etch, and cleaning chambers, as well as to processes that may occur within these chambers. Accordingly, the technology herein should not be considered limited to use with only the specific deposition processes or chambers herein. This disclosure describes one possible system and chamber that may be used to practice methods in accordance with embodiments of the technology herein, followed by additional modifications and adaptations of this system in accordance with embodiments of the technology herein.

[0018]

[0021] FIG. 1 illustrates a top view of one embodiment of a processing system 100 with deposition, etch, bake, and cure chambers, according to an embodiment. In this illustration, a pair of front-opening unified pods 102 supplies substrates of various sizes. These substrates are received by a robot arm 104 and placed in a low-pressure holding area 106, which is then placed in one of the substrate processing chambers 108a-f located in tandem sections 109a-c. A second robot arm 110 can be used to transfer substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and vice versa. Each substrate processing chamber 108a-f can be equipped to perform several substrate processing steps, including plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PCVD), etching, pre-cleaning, degassing, alignment, and hard mask formation of semiconductor materials as described herein, in addition to other substrate processes including annealing, ashing, and the like.

[0019]

[0022] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a dielectric or other film on a substrate. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit a dielectric material on a substrate, and a third pair of processing chambers (e.g., 108a-b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to deposit a film on a substrate. Any one or more of the processes described may be performed in chambers separate from the fabrication system shown in various embodiments. It should be appreciated that additional configurations of chambers for depositing, etching, annealing, and curing a dielectric film are also contemplated by system 100.

[0020]

[0023] 2 shows a schematic cross-sectional view of an exemplary plasma system 200 in accordance with some embodiments of the technology herein. The plasma system 200 may represent a pair of processing chambers 108 that may fit into one or more of the tandem sections 109 described above and may include a substrate support assembly in accordance with embodiments of the technology herein. The plasma system 200 may generally include a chamber body 202 having a sidewall 212, a bottom wall 216, and an interior sidewall 201 that define a pair of processing regions 220A and 220B. Each of the processing regions 220A-220B may be similarly configured and may include identical components.

[0021]

[0024] For example, processing region 220B (components of which may be included in processing region 220A) may include a pedestal 228 disposed within the processing region through a passageway 222 formed in the bottom wall 216 of the plasma system 200. The pedestal 228 may provide a heater adapted to support a substrate 229 on an exposed surface (e.g., a body portion) of the pedestal. The pedestal 228 may include a heating element 232 (e.g., a resistive heating element) that may heat and control the substrate temperature to a desired process temperature. The pedestal 228 may also be heated by a remote heating element (e.g., a lamp assembly) or any other heating device.

[0022]

[0025] The body of the pedestal 228 may be coupled to the stem 226 by a flange 233. The stem 226 may electrically couple the pedestal 228 to a power outlet or power supply box 203. The power supply box 203 may include a drive system that controls the elevation and movement of the pedestal 228 within the processing region 220B. The stem 226 may also include a power interface for providing power to the pedestal 228. The power supply box 203 may also include an interface for power and temperature indicators (such as a thermocouple interface). The stem 226 may include a base assembly 238 adapted to removably couple to the power supply box 203. A perimeter ring 235 is shown on the power supply box 203. In some embodiments, the perimeter ring 235 may be a shoulder adapted as a mechanical stop or land configured to provide a mechanical interface between the base assembly 238 and the upper surface of the power supply box 203.

[0023]

[0026] A rod 230 may be included through a passage 224 formed in the bottom wall 216 of the processing region 220B, which may be utilized to position substrate lift pins 261 disposed through the body of the pedestal 228. The substrate lift pins 261 may selectively separate the substrate 229 from the pedestal to facilitate exchange of the substrate 229 with a robot utilized to transfer the substrate 229 into and out of the processing region 220B through the substrate transfer port 260.

[0024]

[0027] A chamber lid 204 may be coupled to the top of the chamber body 202. The lid 204 may include one or more precursor delivery systems 208 coupled to the lid 204. The precursor delivery system 208 may include a precursor inlet passage 240 that may deliver reactant and cleaning precursors into the processing region 220B through a dual channel showerhead 218. The cleaning precursors may be delivered to a remote plasma system unit 207, which may deliver plasma effluents into the processing chamber and processing region to perform the cleaning process. The dual channel showerhead 218 may include an annular base plate 248 having a blocker plate 244 disposed intermediate a faceplate 246. A radio frequency (RF) source 265 may be coupled to the dual channel showerhead 218, and the RF source 265 may power the dual channel showerhead 218 to facilitate generation of a plasma region between the faceplate 246 of the dual channel showerhead 218 and the pedestal 228. In some embodiments, the RF source may also be coupled to another portion of the chamber body 202 (such as the pedestal 228) to facilitate plasma generation. A dielectric isolator 258 may be disposed between the lid 204 and the dual channel showerhead 218 to prevent conduction of RF power to the lid 204. A shadow ring 206 that engages the pedestal 228 may be disposed around the pedestal 228.

[0025]

[0028] Optional cooling channels 247 may be formed in the annular base plate 248 of the gas distribution system 208 to cool the base plate 248 during operation. A heat transfer fluid (e.g., water, ethylene glycol, gas, etc.) may be circulated through the cooling channels 247 so that the base plate 248 may be maintained at a predetermined temperature. A liner assembly 227 may be positioned in the processing region 220B adjacent to the sidewalls 201, 212 of the chamber body 202 to prevent exposure of the sidewalls 201, 212 to the processing environment in the processing region 220B. The liner assembly 227 may include a peripheral pumping cavity 225 that may be coupled to a pumping system 264 configured to evacuate gases and byproducts from the processing region 220B and control the pressure in the processing region 220B. A plurality of exhaust ports 231 may be formed in the liner assembly 227. The exhaust port 231 can be configured to allow gas to flow from the processing region 220B to the peripheral pumping cavity 225 in a manner that facilitates processing in the system 200.

[0026]

[0029] While the following disclosure describes a hard mask process, it will be understood that the present technology is applicable to any number of processing steps, including formation and removal processes, performed during manufacturing. FIG. 3 illustrates exemplary steps in a semiconductor processing method 300 in accordance with some embodiments of the present technology. The method may be performed in a variety of processing chambers, including the processing system 200 described above. Method 300 may include several optional steps that may or may not be specifically associated with some method embodiments in accordance with the present technology. For example, many of these steps are described to broaden the scope of the present technology, but are not critical to the present technology or may be performed by alternative methodologies, as will be readily recognized.

[0027]

[0030] Method 300 may include additional steps prior to the commencement of the recited steps. For example, the additional processing steps may include forming structures on the semiconductor substrate, which may include both forming and removing materials. Pre-processing steps may be performed within the chamber in which method 300 is performed, or processing may be performed in one or more other processing chambers prior to providing the substrate into the semiconductor processing chamber in which method 300 is performed. Notwithstanding the above, method 300 may optionally include providing a semiconductor substrate to a processing region of a semiconductor processing chamber (such as processing system 200 described above) or other chamber that may include the components described above. The substrate may be disposed on a substrate support, which may be a pedestal (such as pedestal 228) and may be located within the processing region of the chamber (such as processing region 220 described above).

[0028]

[0031] The substrate may be any number of materials onto which materials may be deposited. The substrate may be or include silicon, germanium, a dielectric material including silicon oxide or silicon nitride, a metallic material, or any combination of these materials, which may be the substrate or a material formed on the substrate. In some embodiments, deposition may be performed, whereby one or more materials may be deposited on the substrate. For example, in some embodiments, a hard mask may be formed over one or more materials on the substrate or on the base substrate. The mask material may be a carbon-containing material, a silicon-containing material, or any number of other materials used in semiconductor processing.

[0029]

[0032] During deposition, material is formed or deposited on a substrate, but particles may be generated in the process or may flow from the substrate without being deposited on the substrate. While most of these particles may be exhausted from the processing chamber, particles may find their way into gaps between chamber components or simply redeposit on contact with exposed surfaces of the chamber, for example, at low temperatures that may promote redeposition. After this process, the substrate may be removed from the chamber. A cleaning step may then be performed to remove any remaining particles in the processing area.

[0030]

[0033] During semiconductor processing, the substrate may rise to a processing position near the faceplate or diffuser, as described above. The exhaust system (including the pumping liner) may remove unreacted materials and particles from locations below the substrate being processed. This may allow particles to redeposit in locations below the substrate support in its operating position (such as on an isolator, liner, or other components along the chamber body). Gaps between these components may allow particle flow and lead to the buildup described above. Many cleaning processes are performed with the substrate support in or near its operating position, which may limit the flow of cleaning materials to other areas mentioned above. Additionally, it may take a significant amount of time for cleaning emissions to penetrate into recesses within the chamber, causing the cleaning process to be stopped before difficult-to-access areas are thoroughly cleaned.

[0031]

[0034] In the prior art, gap sizes between components of semiconductor processing chambers may be reduced to attempt to limit particle intrusion. However, while reducing gap size may reduce the overall amount of particle intrusion, accumulation may still occur over time. This reduction in gap may also reduce the ability of cleaning materials to access these areas, making removal more difficult. The techniques herein enable tuning of cleaning processes to facilitate particle removal and even modifying the configuration of chamber components to increase access within these areas. Increasing gap size may seem counterintuitive, as it may allow for easier particle accumulation and intrusion. In some chamber configurations, particle access within the formed gaps may actually increase, which may result in redeposition or accumulation with each processing cycle. However, increasing gaps may also enhance access for cleaning materials, making it easier to remove buildup within the gaps and more effectively cleaning various locations within the processing region. Furthermore, adjusting the cleaning process of method 300 to improve flow in these areas (even if it results in additional accumulation) may improve cleaning.

[0032]

[0035] After the substrate is removed from the processing region of the chamber, the substrate support may be raised back to or toward an operating position within the processing chamber (e.g., proximate a faceplate within the processing chamber). In step 305, a plasma may be formed from one or more cleaning precursors. The cleaning precursors may include halogen-containing precursors, oxygen-containing precursors, or hydrogen-containing precursors, but may also be any other substance that may be used in a semiconductor cleaning process. The precursors may be flowed into the processing chamber or into a remote plasma source, as described above, that may generate plasma effluents of the precursors. In step 310, the precursors may be flowed into a processing region of the semiconductor processing chamber, where the effluents may interact with chamber components to remove particles and other reaction or deposition products.

[0033]

[0036] The cleaning effluents may interact with any number of chamber components while flowing through the processing chamber, and may flow to remove deposition by-products from a faceplate (which, together with the substrate support, may at least partially define a processing region). The effluents may also contact the substrate support at a first position near the faceplate. The substrate support being in a raised position may increase the occurrence of interaction between the effluents and the surface of the substrate support, which may ensure sufficient removal occurs on the surface of the substrate support where deposition occurred during processing. The contact may occur for a first period of time during which removal may occur. After the first period of time, while the plasma effluent is still flowing into the processing region, in step 315, the substrate support may be lowered from the first position to a second position.

[0034]

[0037] Lowering the substrate support may allow the cleaning precursor or plasma effluents easier access further into the processing region. This may allow the cleaning precursor to flow into gaps between chamber components and increase removal from additional locations within the processing chamber. The cleaning may continue for a second period of time with the substrate support in the lowered second position in step 320. After the additional cleaning time, the cleaning may be stopped and a subsequent substrate may be provided for processing, or other steps (such as seasoning) may be performed.

[0035]

[0038] The cleaning process can include a first period during which the substrate support is at a high position and a second period during which the substrate support is at a low position (which can represent the total cleaning time for the method 300). In some embodiments, the plasma cleaning can be performed with a shorter first period than a shorter second period, which can increase access time to lower regions in the processing space while still allowing interaction with the substrate support. Thus, in some embodiments, the first period can be about 50% or less of the total cleaning time, about 45% or less of the total cleaning time, about 40% or less of the total cleaning time, about 35% or less of the total cleaning time, about 30% or less of the total cleaning time, about 25% or less of the total cleaning time, about 20% or less of the total cleaning time, about 15% or less of the total cleaning time, about 10% or less of the total cleaning time, or less. Additionally, the second period of time may be about 50% or more of the total cleaning time, about 55% or more of the total cleaning time, about 60% or more of the total cleaning time, about 65% or more of the total cleaning time, about 70% or more of the total cleaning time, about 75% or more of the total cleaning time, about 80% or more of the total cleaning time, about 85% or more of the total cleaning time, about 90% or more of the total cleaning time, or more.

[0036]

[0039] The substrate support may be positioned at the second position for a longer period of time, which may reduce the total amount of interaction with the cleaning substance in embodiments of the technology herein. To increase long-distance removal during the cleaning process and limit recombination during cleaning, in some embodiments, the plasma power used to generate the plasma effluents may be maintained at about 1000 W or greater, and may be maintained at about 2000 W or greater, about 2500 W or greater, about 2750 W or greater, about 3000 W or greater, about 3200 W or greater, about 3400 W or greater, about 3600 W or greater, about 3800 W or greater, or greater.

[0037]

[0040] During the first time period, the substrate support may be positioned proximate to the faceplate within the processing region of the semiconductor processing chamber. In some embodiments, the distance between the substrate support and the faceplate during the first time period may be about 25 mm or less, and may be maintained at a distance of about 22 mm or less, about 20 mm or less, about 18 mm or less, about 16 mm or less, about 14 mm or less, about 12 mm or less, about 10 mm or less, or less. The substrate support may then be lowered to a second position while the plasma effluents are still flowing and thereafter maintained at the second position for the second time period. The substrate support may be maintained at a distance of about 25 mm or more from the faceplate during the second time period, and may be maintained at a distance of about 30 mm or more, about 32 mm or more, about 34 mm or more, about 36 mm or more, about 38 mm or more, about 40 mm or more, or more from the faceplate, which may provide greater access to other components that at least partially define the processing region.

[0038]

[0041] As discussed above, the chamber configuration may also be adjusted to increase the gap spacing, which may counterintuitively increase particle access and redeposition within the processing chamber. However, the chamber configuration may also allow for improved access for cleaning precursors during method 300, in which case the substrate support may be maintained in a second position that allows increased access to the chamber components. FIG. 4 shows a schematic partial cross-sectional view of chamber components of an exemplary processing chamber 400, in accordance with some embodiments of the technology herein. It should be understood that any of the features, components, or characteristics of chamber 200 may also be included in chamber 400, and that chamber 400 may exhibit additional details of aspects of chamber 200 described above.

[0039]

[0042] As shown, the chamber 400 may include a chamber body 405. A face plate 410 may be included, at least partially defining a processing region from above. A substrate support 415 may be included, which is shown in a first position (e.g., proximate the face plate described above). An inner isolator 420 may be included, extending radially around the processing region and, together with the face plate and substrate support, at least partially defining the processing region. The chamber may also include an outer isolator 425, which may define a recessed ledge 427 upon which the inner isolator 420 may be mounted. A conductive ring 430 may be located between the chamber body 405 and the outer isolator 425, and the conductive ring 430 may extend along the processing chamber and be mounted directly on the chamber body 405. Additionally, a liner 435 may extend upwardly on the inner surface of the chamber body toward the inner isolator and the conductive ring, as shown.

[0040]

[0043] Many conventional systems also include additional isolators that are installed on the liner and extend beyond the underside of the outer portion (e.g., behind) of the inner isolator. The purpose of such additional isolators may be to limit access to components behind the inner isolator by forming a choke. However, it is still possible for material to enter and accumulate in these areas. Prior art techniques sometimes attempt to limit the size of this gap to further restrict access. Even with limited access, particle accumulation can occur over time, which, while not causing the damage from accumulation described above, can lead to extended downtime for cleaning. Furthermore, although particles can still access and accumulate in the area, the ingress of cleaning precursors or cleaning effluents into the area is also restricted, which can hinder removal of the accumulation.

[0041]

[0044] As shown, increasing the gap in the present technology certainly allows particle accumulation. However, by maintaining a sufficiently large gap and performing the cleaning process as described above, the cleaning precursor's cleaning emissions can also easily access the gap region. Thus, chamber configurations according to embodiments of the present technology may actually increase deposition or accumulation within or on the surfaces of these components (such as behind the inner isolator or on the conductive ring). However, because the cleaning material has easy access to these areas, any accumulation during the processing step can be substantially or completely removed in the cleaning step, and accumulation over time can be significantly limited or prevented.

[0042]

[0045] To maintain sufficient access for cleaning effluents, the techniques herein may maintain a gap 440 between chamber components. The gap 440 may refer to the point between the back or outer annular surface of the inner isolator 420 and the bottom of the conductive ring 430 (which may extend to a bottom surface that may contact or be mounted on the chamber body 405). Additionally, the gap 440 may refer to the space maintained between any of the surfaces of the inner isolator 420 and any of the surfaces of the liner 435. The inner isolator 420 may extend vertically beyond or through a plane formed across the surface of the chamber body 405 (on which the conductive ring 430 is mounted). However, a gap spacing of about 20 mils or more, about 25 mils or more, about 30 mils or more, about 35 mils or more, about 40 mils, about 45 mils or more, about 50 mils or more, about 55 mils or more, about 60 mils or more, about 65 mils or more, about 70 mils or more, about 75 mils or more, about 80 mils or more, about 85 mils or more, about 90 mils or more, about 95 mils or more, about 100 mils or more, or more may still be maintained between any of these components. Although increasing the gap size between components along the processing region of the chamber and performing a cleaning process according to embodiments of the technology herein may increase particle buildup during the deposition process, this buildup can be easily removed by the cleaning process and may limit or prevent buildup over time.

[0043]

[0046] In the above description, for purposes of explanation, numerous details are set forth in order to facilitate an understanding of various embodiments of the technology herein. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0044]

[0047] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents may be used without departing from the essence of the embodiments. Additionally, in order to avoid unnecessarily obscuring the technology herein, some well-known processes and elements have not been described. Therefore, the above description should not be construed as limiting the scope of the technology herein.

[0045]

[0048] Where a range of values ​​is provided, unless the context clearly indicates otherwise, each intervening value between the upper and lower limit of that range is understood to be specifically disclosed, down to the smallest unit of the lower limit. Narrower ranges between any stated or unstated intervening values ​​in a stated range, as well as other stated or intervening values ​​in that stated range, if any, are included. The upper and lower limits of any such narrower range may individually be included in or excluded from the range. Each range where either, neither, or both limits are included in the narrower range is also encompassed within the technology herein, provided that there is a specifically excluded limit in the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0046]

[0049] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "a precursor" includes a plurality of such precursors, a reference to "the liner" includes a reference to one or more liners and equivalents thereof known to those skilled in the art, and so forth.

[0047]

[0050] Furthermore, the words "comprise(s) / comprising", "contain(s) / containing", and "include(s) / including", when used in this specification and the claims that follow, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims

1. generating a plasma of a cleaning precursor in a remote region of a semiconductor processing chamber; flowing plasma effluents of the cleaning precursor into a processing region of the semiconductor processing chamber, the processing region being defined by an inner isolator extending radially around the processing region, the semiconductor processing chamber comprising: The main body and a conductive ring disposed on a body of the semiconductor processing chamber; an outer isolator mounted on the conductive ring, the inner isolator mounted within a recessed ledge formed on an inner end of the outer isolator; contacting a substrate support with the plasma effluents for a first period of time; lowering the substrate support from a first position to a second position while continuing to flow plasma effluents of the cleaning precursor; cleaning the processing region of the semiconductor processing chamber for a second period of time; A semiconductor processing method comprising:

2. The semiconductor processing method of claim 1 , wherein the cleaning precursor comprises a halogen-containing precursor.

3. 2. The semiconductor processing method of claim 1, wherein said second period of time is longer than said first period of time.

4. 2. The semiconductor processing method of claim 1, wherein the substrate support is at a distance of 20 mm or less from a face plate in the first position.

5. 5. The semiconductor processing method of claim 4, wherein the substrate support is at a distance of 30 mm or more from a face plate in the second position.

6. 10. The semiconductor processing method of claim 1, wherein plasma power is maintained at 1000 W or greater to generate plasma effluents of said cleaning precursor.

7. The semiconductor processing method of claim 1 , wherein the processing region is defined by a faceplate and the substrate support.

8. 10. The semiconductor processing method of claim 1, wherein a liner extends along the body of the semiconductor processing chamber toward the inner isolator and the conductive ring.

9. 10. The semiconductor processing method of claim 8, wherein a gap of 20 mils or greater is maintained between the inner isolator and the conductive ring disposed on the body of the semiconductor processing chamber proximate a surface of the conductive ring.

10. flowing plasma effluents of a cleaning precursor into a processing region of a semiconductor processing chamber, the processing region being defined by an inner isolator extending radially around the processing region, the semiconductor processing chamber comprising: The main body and a conductive ring disposed on a body of the semiconductor processing chamber; an outer isolator mounted on the conductive ring, the inner isolator mounted within a recessed ledge formed on an inner end of the outer isolator; contacting a substrate support with the plasma effluents for a first period of time; lowering the substrate support from a first position to a second position while continuing to flow plasma effluents of the cleaning precursor; cleaning the processing region of the semiconductor processing chamber for a second time period at least 20% longer than the first time period; A semiconductor processing method comprising:

11. 11. The semiconductor processing method of claim 10, wherein plasma power is maintained at 1000 W or greater to generate plasma effluents of the cleaning precursor.

12. 11. The semiconductor processing method of claim 10, wherein the first period of time is less than or equal to 40% of the total cleaning time.

13. 11. The semiconductor processing method of claim 10, wherein the substrate support is at a distance of 20 mm or less from a face plate in the first position and at a distance of 30 mm or more from the face plate in the second position.

14. 11. The semiconductor processing method of claim 10, wherein a gap of 50 mils or greater is maintained between the inner isolator and the conductive ring disposed on the body of the semiconductor processing chamber proximate a surface of the conductive ring.

15. 15. The semiconductor processing method of claim 14, further comprising flowing the plasma effluents of the cleaning precursor into the gap during the second period of time.

16. 8. The semiconductor processing method of claim 7, wherein the faceplate is disposed on one or both of the inner isolator and the outer isolator.

17. 10. The semiconductor processing method of claim 1, wherein the top surfaces of the inner isolator and the outer isolator are coplanar.

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