Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device that has a trench contact part capable of suppressing injection of carriers from an emitter region to improve the breakdown resistance, and to provide a method of manufacturing the same.SOLUTION: A semiconductor device 100 comprises: a drift region 18 of a first conductivity type provided on a semiconductor substrate 10; a base region 14 of a second conductivity type provided above the drift region; an emitter region 12 of the first conductivity type provided above the base region; a plurality of trench parts 30 and 40 arranged in a predetermined arrangement direction on a front face 21 side of the semiconductor substrate; a trench contact part 27 provided on the front face side of the semiconductor substrate, between two adjacent trench parts among the plurality of trench parts; and a contact layer 19 of the second conductivity type provided below the trench contact part, having a doping concentration higher than that of the base region. A lower end of the trench contact part is deeper than a lower end of the emitter region. On a side wall of the trench contact part, the emitter region and the contact layer are in contact with each other.SELECTED DRAWING: Figure 1B

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] BACKGROUND ART Conventionally, semiconductor devices having trench contact portions are known (see, for example, Patent Documents 1 to 3). Patent Document 1: JP 2014-158013 A Patent Document 2: JP 2013-065724 A Patent Document 3: International Publication No. 2018 / 052099 Summary of the Invention [Problem to be solved by the invention]

[0003] It is desirable to improve the breakdown voltage of semiconductor devices having trench contact portions. [Means for solving the problem]

[0004] In a first aspect of the present invention, a first high-concentration region of the first conductivity type provided in a semiconductor substrate; a base region of a second conductivity type provided above the drift region; a first high-concentration region of the first conductivity type provided above the base region so as to be exposed on a front surface of the semiconductor substrate and having a higher doping concentration than the drift region; a plurality of trenches arranged in a predetermined arrangement direction on the front surface side of the semiconductor substrate; a recess provided on the front surface side of the semiconductor substrate between two adjacent trenches among the plurality of trenches; a trench contact portion having a conductive material filled inside the recess and connecting the semiconductor substrate to an electrode on the front surface side of the semiconductor substrate; and a second high-concentration region of the second conductivity type provided at a distance from the front surface of the semiconductor substrate and having a higher doping concentration than the base region, wherein the second high-concentration region has a first contact layer provided on the front surface side of the semiconductor substrate relative to a bottom surface of the recess, and the first contact layer is in contact with the first high-concentration region at a sidewall of the recess.

[0005] In the above semiconductor device, the first contact layer may include an extension region that extends from a lower end of the first high concentration region toward the front surface side of the semiconductor substrate and is in contact with the first high concentration region.

[0006] Any of the above semiconductor devices may further include a contact region of the second conductivity type that is exposed on the front surface of the semiconductor substrate and has a doping concentration higher than that of the base region.

[0007] In any of the above semiconductor devices, the plurality of trenches may be provided extending in a predetermined extension direction.

[0008] In any of the above semiconductor devices, the contact region may be provided at a termination portion that is an end portion of the conductive material in the extension direction.

[0009] a first high-concentration region of the first conductivity type provided above the base region so as to be exposed on a front surface of the semiconductor substrate and have a higher doping concentration than the drift region; a contact region of the second conductivity type provided so as to be exposed on the front surface of the semiconductor substrate and have a higher doping concentration than the base region; a trench contact portion having a plurality of trenches arranged in a predetermined arrangement direction on the front surface side of the semiconductor substrate, a recess provided on the front surface side of the semiconductor substrate between two adjacent trenches among the plurality of trenches, the recess having a conductive material filled inside the recess and connecting the semiconductor substrate to an electrode on the front surface side of the semiconductor substrate; and a second high-concentration region of the second conductivity type provided at a distance from the front surface of the semiconductor substrate and have a higher doping concentration than the base region.

[0010] In any of the above semiconductor devices, the second high-concentration region may have a first contact layer spaced apart from a bottom surface of the recess. The first contact layer may be in contact with the first high-concentration region on a sidewall of the recess. The plurality of trench portions may be provided extending in a predetermined extension direction. The contact region may be provided at a termination portion that is an end portion of the conductive material in the extension direction.

[0011] In any of the above semiconductor devices, the sidewall may be in contact with the contact region and the second high concentration region in a cross section in the arrangement direction that passes through the termination portion.

[0012] In any of the above semiconductor devices, the sidewalls and bottom surface may be covered with the contact region, the base region, and the second high concentration region in a cross section in the arrangement direction passing through the termination portion.

[0013] In any of the above semiconductor devices, the sidewall and the bottom surface may be covered by the contact region and the second high concentration region in a cross section in the arrangement direction passing through the termination portion.

[0014] In any of the above semiconductor devices, the second high concentration region may be provided so as to extend further in the extension direction than the contact region.

[0015] In any of the above semiconductor devices, the second heavily doped region may have a second contact layer in contact with a bottom surface of the recess.

[0016] In any of the above semiconductor devices, the conductive material may have a convex bottom surface that protrudes toward the back surface side of the semiconductor substrate.

[0017] In any of the above semiconductor devices, the semiconductor substrate may be a silicon substrate.

[0018] In any of the above semiconductor devices, the semiconductor substrate may be a silicon carbide substrate.

[0019] In any of the above semiconductor devices, the semiconductor substrate may be a nitride semiconductor substrate.

[0020] In any of the above semiconductor devices, the semiconductor device may be an IGBT.

[0021] In any of the above semiconductor devices, the semiconductor device may be a MOS transistor.

[0022] A third aspect of the present invention provides a method for manufacturing a semiconductor device including: a drift region of a first conductivity type provided in a semiconductor substrate; a base region of a second conductivity type provided above the drift region; a first high-concentration region of the first conductivity type provided above the base region so as to be exposed on a front surface of the semiconductor substrate and having a higher doping concentration than the drift region; and a plurality of trench portions arranged in a predetermined arrangement direction on the front surface side of the semiconductor substrate, the method including the steps of: etching the front surface side of the semiconductor substrate between two adjacent trench portions of the plurality of trench portions to form a recess; and providing a second high-concentration region of the second conductivity type spaced apart from the front surface of the semiconductor substrate, the second high-concentration region having a higher doping concentration than the base region, the second high-concentration region having a first contact layer provided closer to the front surface of the semiconductor substrate than a bottom surface of the recess; and the first contact layer being in contact with the first high-concentration region on a sidewall of the recess.

[0023] In the method for manufacturing a semiconductor device, the second heavily doped region may have a second contact layer in contact with a bottom surface of the recess.

[0024] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0025] [Figure 1A] 1 shows an example of a top view of a semiconductor device 100 according to an embodiment. [Figure 1B] FIG. 1B is a diagram showing an example of a cross section taken along aa' in FIG. 1A. [Figure 1C] FIG. 1B is a diagram showing an example of a cross section taken along the line bb' in FIG. 1A. [Figure 1D] An example of an enlarged view of the vicinity of the trench contact portion 27 is shown. [Figure 1E] An example of the doping concentration distribution around the trench contact portion 27 is shown. [Figure 1F] 1 shows an example of an enlarged cross-sectional view of the vicinity of the terminal end 28. FIG. [Figure 2] An example of an enlarged view of the vicinity of the trench contact portion 27 is shown. [Figure 3] 1 shows an example of an enlarged cross-sectional view of the vicinity of the terminal end 28. FIG. [Figure 4A] 1 shows an example of a top view of a semiconductor device 100 according to an embodiment. [Figure 4B] 4B shows an example of an enlarged cross-sectional view of the vicinity of the terminal end 28 of FIG. 4A. [Figure 5] An example of a method for manufacturing the contact layer 19 having a single layer structure will be described. [Figure 6] An example of a method for manufacturing the two-stage contact layer 19 will be described. [Figure 7] 1 shows the configuration of a semiconductor device 500 according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0026] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0027] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "top" and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the top surface and the other surface is referred to as the bottom surface. The directions of "top," "bottom," "front," and "back" are not limited to the direction of gravity or the direction in which the semiconductor device is attached to a substrate or the like when mounted.

[0028] In this specification, technical matters may be explained using orthogonal coordinate axes of X, Y, and Z. In this specification, a plane parallel to the top surface of the semiconductor substrate is defined as the XY plane, and the depth direction of the semiconductor substrate is defined as the Z axis. In this specification, the case where the semiconductor substrate is viewed in the Z axis direction is referred to as a planar view.

[0029] In each embodiment, an example is shown in which the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment will be opposite polarities.

[0030] In this specification, layers or regions marked with n or p have majority carriers of electrons or holes, respectively. The + and - symbols attached to n or p indicate higher and lower doping concentrations than layers or regions without the symbol, respectively. ++ indicates a higher doping concentration than +, and -- indicates a lower doping concentration than -.

[0031] In this specification, the doping concentration refers to the concentration of a dopant converted into a donor or acceptor. Therefore, the unit is / cm 3 In this specification, the difference in concentration between the donor and the acceptor (i.e., the net doping concentration) may be referred to as the doping concentration. In this case, the doping concentration can be measured by the SR method. Alternatively, the chemical concentration of the donor and the acceptor may be referred to as the doping concentration. In this case, the doping concentration can be measured by the SIMS method. Unless otherwise specified, any of the above may be used as the doping concentration. Unless otherwise specified, the peak value of the doping concentration distribution in the doping region may be referred to as the doping concentration in the doping region.

[0032] In this specification, the dose refers to the number of ions implanted into a wafer per unit area during ion implantation. Therefore, the unit is / cm 2 The dose of a semiconductor region can be expressed as an integral concentration obtained by integrating the doping concentration over the depth direction of the semiconductor region. The unit of the integral concentration is / cm 2 Therefore, the dose amount and the integrated concentration may be treated as the same thing. The integrated concentration may be the integral value up to the half-width, and when the spectrum overlaps with that of another semiconductor region, the influence of the other semiconductor region may be excluded from the calculation.

[0033] Therefore, in this specification, the high or low doping concentration can be interpreted as the high or low dose amount. That is, when the doping concentration of one region is higher than the doping concentration of another region, it can be understood that the dose amount of the one region is higher than the dose amount of the other region.

[0034] 1A shows an example of a top view of a semiconductor device 100 according to an embodiment. The semiconductor device 100 of this example is a semiconductor chip including a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). Note that the semiconductor device 100 may be an IGBT or a MOS transistor.

[0035] The transistor section 70 is a region obtained by projecting the collector region 22 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 has a second conductivity type. In this example, the collector region 22 is, for example, a P+ type. The transistor section 70 includes a transistor such as an IGBT. The transistor section 70 includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80.

[0036] The diode section 80 is a region obtained by projecting a cathode region 82 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. In this example, the cathode region 82 is an N+ type, for example. The diode section 80 includes a diode such as a free wheel diode (FWD) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.

[0037] FIG. 1A shows the region around the chip edge, which is the edge side of semiconductor device 100, and omits other regions. For example, an edge termination structure may be provided in the region on the negative side of semiconductor device 100 in the Y-axis direction in this example. The edge termination structure reduces electric field concentration on the upper surface side of semiconductor substrate 10. The edge termination structure may have, for example, a guard ring, a field plate, a resurf, or a structure combining these. Note that, for convenience, this example describes the edge on the negative side of the Y-axis direction, but the same applies to other edges of semiconductor device 100.

[0038] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0039] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on a front surface 21 of a semiconductor substrate 10. The front surface 21 will be described later. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0040] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. The gate metal layer 50 is provided above the gate trench portion 40 and the well region 17.

[0041] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. For example, at least a portion of the emitter electrode 52 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. At least a portion of the gate metal layer 50 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed of titanium, a titanium compound, or the like below the region formed of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0042] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 sandwiched therebetween. The interlayer insulating film 38 is omitted in Fig. 1A. A contact hole 54, a contact hole 55, and a contact hole 56 are provided to penetrate the interlayer insulating film 38.

[0043] The contact hole 55 connects the gate metal layer 50 to the gate conductive portion in the transistor portion 70. Inside the contact hole 55, a plug made of tungsten or the like may be formed.

[0044] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. Inside the contact hole 56, a plug made of tungsten or the like may be formed.

[0045] The connection portion 25 electrically connects a front surface electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material, such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film, such as an oxide film.

[0046] The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portions 40 in this example may have two extension portions 41 extending along an extension direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 that connects the two extension portions 41.

[0047] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 41. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

[0048] The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. Like the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). Like the gate trench portion 40, the dummy trench portion 30 of this example may have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction and a connection portion 33 connecting the two extension portions 31.

[0049] The transistor section 70 of this example has a structure in which two gate trench sections 40 and three dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 of this example has gate trench sections 40 and dummy trench sections 30 in a ratio of 2:3. For example, the transistor section 70 has one extension section 31 between two extension sections 41. The transistor section 70 also has two extension sections 31 adjacent to the gate trench section 40.

[0050] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 1:1 or 2:4. Furthermore, the transistor portion 70 may have no dummy trench portions 30 and may be entirely made up of gate trench portions 40, which is called a full gate structure.

[0051] The well region 17 is a second conductivity type region provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18 described below. The well region 17 is an example of a well region provided on the edge side of the semiconductor device 100. The well region 17 is, for example, P+ type. The well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.

[0052] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are also provided above the contact region 15 in the diode section 80. The contact holes 54 are provided above the contact region 15 in the boundary section 90. The contact holes 54 are provided above the base region 14 in the diode section 80. None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction. In this way, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the extension direction.

[0053] The trench contact portion 27 electrically connects the emitter electrode 52 and the semiconductor substrate 10. The trench contact portion 27 is provided in the contact hole 54. The trench contact portion 27 is provided to extend in the extension direction.

[0054] The termination portion 28 is an end portion in the extension direction of the trench contact portion 27. The termination portion 28 is provided in a region of the mesa portion 71 where the contact region 15 is formed on the front surface 21. The termination portion 28 may also be provided in a region of the mesa portion 81 or the mesa portion 91 where the contact region 15 is formed on the front surface 21.

[0055] The boundary portion 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 has a contact region 15. In this example, the boundary portion 90 does not have an emitter region 12. In one example, the trench portion of the boundary portion 90 is a dummy trench portion 30. In this example, the boundary portion 90 is arranged so that both ends in the X-axis direction are dummy trench portions 30.

[0056] Mesa portion 71, mesa portion 91, and mesa portion 81 are mesa portions provided adjacent to trench portions in a plane parallel to front surface 21 of semiconductor substrate 10. A mesa portion is a portion of semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion from front surface 21 of semiconductor substrate 10 to the deepest bottom of each trench portion. An extension portion of each trench portion may be considered as one trench portion. In other words, the region sandwiched between the two extension portions may be considered as a mesa portion.

[0057] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter regions 12 and the contact regions 15 are provided alternately in the extension direction.

[0058] The mesa portion 91 is provided in the boundary portion 90. The mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The mesa portion 91 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0059] The mesa portion 81 is provided in a region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0060] The base region 14 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10 in the transistor section 70 and the diode section 80. The base region 14 is, for example, a P-type. The base region 14 may be provided on the front surface 21 of the semiconductor substrate 10 at both ends in the Y-axis direction of the mesa section 71 and the mesa section 91. Note that FIG. 1A shows only one end of the base region 14 in the Y-axis direction.

[0061] The emitter region 12 is a region of the first conductivity type having a higher doping concentration than the drift region 18. In this example, the emitter region 12 is, for example, N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71 in contact with the gate trench portion 40. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0062] Furthermore, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30. The emitter region 12 does not have to be provided in the mesa portion 81 and the mesa portion 91.

[0063] The contact region 15 is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the contact region 15 is, for example, a P+ type. In this example, the contact region 15 is provided on the front surface 21 of the mesa portion 71, the mesa portion 81, and the mesa portion 91. The contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71, the mesa portion 81, or the mesa portion 91 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40. Furthermore, the contact region 15 may or may not be in contact with the dummy trench portion 30. In this example, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

[0064] 1B is a diagram showing an example of the a-a' cross section in FIG. 1A. The a-a' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70. In the a-a' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0065] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0066] The buffer region 20 is a region of a first conductivity type provided below the drift region 18. In this example, the buffer region 20 is, for example, N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0067] The collector region 22 is provided below the buffer region 20 in the transistor section 70. The cathode region 82 is provided below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80.

[0068] The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal.

[0069] The base region 14 is a second conductivity type region provided above the drift region 18 in the mesa portion 71, the mesa portion 91, and the mesa portion 81. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0070] The emitter region 12 is provided between the base region 14 and the front surface 21. In this example, the emitter region 12 is provided in the mesa portion 71, but is not provided in the mesa portion 81 or the mesa portion 91. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0071] The contact region 15 is provided above the base region 14 in the mesa portion 81 and the mesa portion 91. The contact region 15 is provided in contact with the dummy trench portion 30 in the mesa portion 81 and the mesa portion 91. In other cross sections, the contact region 15 may be provided on the front surface 21 of the mesa portion 71.

[0072] The trench contact portion 27 has a conductive material filled in the contact hole 54. The trench contact portion 27 is provided between two adjacent trench portions among the plurality of trench portions. The trench contact portion 27 is provided on the front surface 21 side in contact with the contact layer 19. The trench contact portion 27 of this example is provided from the front surface 21 to penetrate the emitter region 12. The trench contact portion 27 may have the same material as the emitter electrode 52.

[0073] The bottom end of the trench contact portion 27 is deeper than the bottom end of the emitter region 12. By providing the trench contact portion 27, the resistance of the base region 14 is reduced, making it easier to extract minority carriers (e.g., holes). This improves the breakdown resistance, such as the latch-up resistance, caused by minority carriers.

[0074] The trench contact portion 27 has a substantially flat bottom surface. The bottom surface of the trench contact portion 27 is covered with the contact layer 19. The trench contact portion 27 in this example has a tapered shape with inclined sidewalls. However, the sidewalls of the trench contact portion 27 may be provided substantially perpendicular to the front surface 21.

[0075] The contact layer 19 is provided below the trench contact portion 27. The contact layer 19 is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the contact layer 19 is of P+ type, for example. For example, the contact layer 19 is formed by ion implantation of boron (B) or boron fluoride (BF2). The contact layer 19 may have the same doping concentration as the contact region 15. The contact layer 19 suppresses latch-up by extracting minority carriers.

[0076] The contact layer 19 is provided on the sidewalls and bottom surface of the trench contact portion 27. In this example, the contact layer 19 is provided in each of the mesa portion 71, the mesa portion 81, and the mesa portion 91. The contact layer 19 may be provided extending in the Y-axis direction.

[0077] The emitter region 12 and the contact layer 19 are in contact with each other on the sidewall of the trench contact portion 27. In this example, the sidewall of the trench contact portion 27 is covered with the emitter region 12 and the contact layer 19. In other words, the trench contact portion 27 is not in contact with the base region 14.

[0078] In this example, the contact between the emitter region 12 and the contact layer 19 can suppress carrier injection from the emitter region 12 and improve breakdown resistance. Furthermore, even when a large current flows through the semiconductor device 100, the contact layer 19 can improve the efficiency of extracting minority carriers and stabilize the potential of the base region 14.

[0079] The accumulation region 16 is a region of a first conductivity type that is provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. In this example, the accumulation region 16 is, for example, an N+ type. The accumulation region 16 is provided in the transistor section 70 and the diode section 80. However, the accumulation region 16 does not necessarily have to be provided.

[0080] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. The dose of ion implantation into the accumulation region 16 is 1E12 cm -2 Above, 1E13cm -2 The ion implantation dose of the accumulation region 16 may be 3E12 cm -2 Above, 6E12cm -2 By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced. Note that E represents a power of 10, and for example, 1E12 cm -2 is 1 x 10 12 cm -2 means.

[0081] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these regions to reach the drift region 18. The trenches penetrating the doped regions are not limited to those formed in the order of forming the doped regions and then the trenches. The trenches penetrating the doped regions also include those formed after the trenches have been formed.

[0082] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38.

[0083] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side, across the gate insulating film 42, in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0084] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 with an interlayer insulating film 38.

[0085] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be provided so as to penetrate the interlayer insulating film 38.

[0086] Fig. 1C is a diagram showing an example of the bb' cross section in Fig. 1A. The bb' cross section is an XZ plane passing through the contact region 15 in the transistor section 70.

[0087] In the b-b' cross section, the mesa portion 71 has the base region 14, the contact region 15, the accumulation region 16, and the contact layer 19. As in the a-a' cross section, the mesa portion 91 has the base region 14, the contact region 15, the accumulation region 16, and the contact layer 19. In the b-b' cross section, the mesa portion 71 has the same structure as the mesa portion 91. As in the a-a' cross section, the mesa portion 81 has the base region 14, the contact region 15, the accumulation region 16, and the contact layer 19.

[0088] 1D shows an example of an enlarged view of the vicinity of the trench contact portion 27. In this example, the description will be given using the mesa portion 71 between the dummy trench portion 30 and the gate trench portion 40, but the mesa portion 81 or the mesa portion 91 may have a similar structure.

[0089] Mesa width WM is the width of the mesa in the X-axis direction. The mesa 71, the mesa 81, and the mesa 91 have the same mesa width W M In this example, the mesa width W M is 0.8 μm or more and 1.5 μm or less.

[0090] The length A is the length in the arrangement direction where the bottom ends of the emitter regions 12 contact the base region 14. For example, the length A is greater than 0.1 μm and less than 0.3 μm.

[0091] The length B is the shortest distance between the contact layer 19 and an adjacent trench among the multiple trenches. The contact layer 19 is spaced apart from the adjacent trench to form a channel. For example, the length B is 0.1 μm or more. This can improve breakdown resistance while avoiding any effect on the gate threshold voltage Vth.

[0092] Length A is greater than length B. That is, the width of base region 14, through which minority carriers pass, is smaller than the width of the lower surface of emitter region 12. This makes it easier for minority carriers to be extracted by contact layer 19 before they move near emitter region 12.

[0093] The extension region E is a region in the contact layer 19 that extends toward the front surface 21 beyond the lower end of the emitter region 12. Providing the extension region E ensures reliable contact between the emitter region 12 and the contact layer 19. Furthermore, the efficiency of extracting minority carriers improves, making it easier to suppress latch-up.

[0094] The length C is the difference between the depth of the top end of the contact layer 19 and the depth of the bottom end of the emitter region 12. In other words, the length C indicates the amount of extension of the extension region E into the emitter region 12. The larger the length C, the more the contact layer 19 extends into the emitter region 12.

[0095] Length D is the maximum distance in the arrangement direction from the sidewall bottom 29 of the trench contact portion 27 to the outer circumferential surface of the contact layer 19. In this example, length D is greater than length B. That is, the contact layer 19 extends closer to the trench portion than the sidewall bottom 29 of the trench contact portion 27. This makes it easier to guide minority carriers to the contact layer 19, and can suppress the amount of minority carriers that pass between the contact layer 19 and the trench portion and move toward the emitter region 12.

[0096] The trench contact portion 27 has a concave bottom surface recessed toward the back surface 23. In this example, the concave bottom surface of the trench contact portion 27 is recessed from the sidewall bottom 29 toward the center of the trench contact portion 27. The bottom surface of the trench contact portion 27 may be recessed in an arc shape. The concave bottom surface of the trench contact portion 27 is formed by etching to form the contact hole 54 of the trench contact portion 27.

[0097] The length L1 is the difference between the lower end of the emitter region 12 and the bottom surface of the trench contact portion 27. The longer the length L1, the more the trench contact portion 27 extends from the emitter region 12, making it easier to extract minority carriers. In the semiconductor device 100 of this example, the contact layer 19 is in contact with the emitter region 12, so even if the length L1 is large, the injection of carriers from the emitter region 12 can be suppressed.

[0098] The length L2 is the distance from the front surface 21 to the upper end of the dummy conductive portion 34 or the upper end of the gate conductive portion 44. When the dummy conductive portion 34 or the gate conductive portion 44 has a recess at its upper end, the length L2 may be the distance from the front surface 21 to the uppermost end of the dummy conductive portion 34 or the gate conductive portion 44. For example, the length L2 is not less than 0.1 μm and not more than 0.4 μm.

[0099] Depth D12 is the depth from the front surface 21 to the lower end of the emitter region 12. For example, depth D12 is 0.3 μm or more and 0.7 μm or less. Depth D12 may be greater than length L2. That is, the emitter region 12 is provided extending from the front surface 21 to a depth facing the dummy conductive portion 34 or the gate conductive portion 44.

[0100] Depth D27 is the depth from the front surface 21 to the bottom surface of trench contact portion 27. In this example, depth D27 is the depth from the front surface 21 to the bottom end of the sidewall of trench contact portion 27. Depth D27 is greater than depth D12. For example, depth D27 is 0.5 μm or more and 1.0 μm or less.

[0101] FIG. 1E shows an example of the doping concentration distribution around the trench contact portion 27. The vertical axis represents the doping concentration (cm -2 ), and the horizontal axis represents the distance (μm) from the top end of the contact layer 19 in the depth direction. The solid line represents the doping concentration distribution at the Z-Z' position. The dashed line represents the doping concentration in the emitter region 12 at the same depth as the solid line.

[0102] The contact layer 19 is formed by ion implantation through the trench contact portion 27. The contact layer 19 has one peak, but may have multiple peaks. The peak position of the contact layer 19 may be formed at a position deeper than the bottom end of the emitter region 12. The peak of the contact layer 19 in this example is approximately 1E20 cm -2 is.

[0103] The doping concentration distribution in this example is merely an example, and the magnitude and depth of the doping concentration peak may be changed as appropriate to achieve the semiconductor device 100 disclosed in the present specification.

[0104] 1F shows an example of an enlarged cross-sectional view of the vicinity of the terminal end 28. The drawing shows an XZ plane passing through the terminal end 28.

[0105] The sidewall of the termination 28 of the trench contact 27 is covered with a region of the second conductivity type. In this example, the sidewall of the termination 28 of the trench contact 27 is covered with the contact region 15 and the contact layer 19. In this way, the contact layer 19 may be provided in contact with either the emitter region 12 or the contact region 15.

[0106] Length A' is the length in the arrangement direction where the bottom end of contact region 15 contacts base region 14. For example, length A' is greater than 0.1 μm and less than 0.3 μm.

[0107] Depth D15 is the depth from the front surface 21 to the bottom end of the contact region 15. For example, depth D15 is 0.3 μm or more and 0.7 μm or less. Depth D15 may be greater than length L2. Depth D15 may be the same as or different from depth D12 of the emitter region 12.

[0108] 2 shows an example of an enlarged view of the vicinity of the trench contact portion 27. In this example, the contact layer 19 includes two contact layers: a contact layer 19a and a contact layer 19b. The contact layer 19a is an example of a first contact layer, and the contact layer 19b is an example of a second contact layer.

[0109] The contact layer 19a is provided on the side wall of the trench contact portion 27. The contact layer 19a is provided in contact with the emitter region 12. The contact layer 19a has an extension region E that extends beyond the lower end of the emitter region 12 toward the front surface 21. Even when the trench contact portion 27 is provided to protrude from the emitter region 12 toward the back surface 23, the contact layer 19a is in contact with the emitter region 12. This improves the efficiency of extracting minority carriers and suppresses latch-up.

[0110] The contact layer 19b is provided below the contact layer 19a on the sidewall of the trench contact portion 27. The contact layer 19b is provided in contact with the contact layer 19a on the sidewall of the trench contact portion 27. That is, the sidewall of the trench contact portion 27 is covered with the emitter region 12, the contact layer 19a, and the contact layer 19b.

[0111] The doping concentration of the contact layer 19a may be the same as the doping concentration of the contact layer 19b. Also, the doping concentrations of the contact layers 19a and 19b may be the same as the doping concentration of the contact region 15. Also, the doping concentration of the contact layer 19a may be lower than the doping concentration of the contact layer 19b.

[0112] Length B1 is the shortest distance between contact layer 19a and an adjacent trench among the multiple trenches. Length B2 is the shortest distance between contact layer 19b and an adjacent trench among the multiple trenches. Length B1 is greater than length B2. This allows contact layer 19b to reliably extract minority carriers.

[0113] 3 shows an example of an enlarged cross-sectional view of the vicinity of the terminal end 28. The drawing shows an XZ plane passing through the terminal end 28. In this example, differences from the cross-sectional view of FIG. 1D will be particularly described.

[0114] The sidewall of termination portion 28 is covered with a region of the second conductivity type. In this example, contact layer 19 is provided on the sidewall of termination portion 28. The sidewall of termination portion 28 is covered with base region 14, contact region 15, and contact layer 19. In this way, when contact region 15 is provided on front surface 21, contact layer 19 may be provided at a distance from contact region 15.

[0115] 4A shows an example of a top view of a semiconductor device 100 according to an embodiment. The semiconductor device 100 of this example differs from the top view of FIG. 1A in that the termination portion 28 of the front surface 21 is provided in the emitter region 12. In this example, differences from the top view of FIG. 1A will be particularly described.

[0116] The base region 14 is provided adjacent to the emitter region 12 in the mesa portion 71. The emitter regions 12 and the contact regions 15 are provided alternately in the Y-axis direction on the front surface 21. The termination portion 28 of this example is provided in the region where the emitter regions 12 are formed.

[0117] 4B shows an example of an enlarged cross-sectional view of the vicinity of the termination portion 28 in FIG. 4A. The figure shows an XZ plane passing through the termination portion 28. The semiconductor device 100 of this example differs from the cross-sectional view of FIG. 1F in that an emitter region 12 is provided on the front surface 21 of the termination portion 28. In this example, differences from the cross-sectional view of FIG. 1F will be particularly described.

[0118] The sidewalls of the termination 28 of the trench contact 27 are covered with the emitter region 12 and the contact layer 19. The contact layer 19 is provided in contact with the emitter region 12, as shown in Figure 4B.

[0119] FIG. 5 shows an example of a method for manufacturing the contact layer 19 having a single layer structure.

[0120] In step S100, the emitter region 12 and the base region 14 are formed in the semiconductor substrate 10. In addition, an interlayer insulating film 38 is formed on the upper surface of the emitter region 12 on the front surface 21.

[0121] In step S102, contact holes 54 are formed by etching through the emitter region 12 to the base region 14. Here, an oxide film mask is formed above the semiconductor substrate 10 by etching the interlayer insulating film 38.

[0122] In step S104, using the interlayer insulating film 38 as a mask, ions are implanted to form the contact layer 19. The dashed lines indicate the regions of the contact layer 19 into which the dopant has been implanted.

[0123] In step S106, the contact layer 19 is formed by heat treatment. The contact layer 19 may be provided by heat treatment so as to extend to the emitter region 12. As a result, the emitter region 12 and the contact layer 19 come into contact with each other on the sidewall of the trench contact portion 27.

[0124] In this example, after the contact holes 54 of the trench contact portions 27 are formed, ions are implanted to form the contact layer 19. That is, the dopant for the contact layer 19 is ion-implanted using the interlayer insulating film 38 as a mask, which improves the alignment accuracy of the contact layer 19 with respect to the trench contact portions 27.

[0125] FIG. 6 shows an example of a method for manufacturing the two-stage contact layer 19. In FIG.

[0126] In step S200, dopants are implanted to form the contact layer 19a. The dashed lines indicate the regions of the contact layer 19a where the dopants are implanted.

[0127] In step S202, the contact layer 19a is activated by heat treatment. The heat treatment for activating the contact layer 19a may be omitted, and the contact layer 19a may be heat treated together with the contact layer 19b.

[0128] In step S204, a contact hole 54 is formed by etching through the emitter region 12 to the base region 14. On the sidewall of the contact hole 54, a part of the contact layer 19a remains.

[0129] In step S206, a dopant is ion-implanted to form the contact layer 19b, followed by heat treatment. The contact layer 19b is formed below the contact layer 19a. The dashed lines indicate the regions of the contact layer 19b into which the dopant is implanted.

[0130] The width of the ion implantation for forming the contact layer 19a may be smaller than the width of the ion implantation for forming the contact layer 19b. Also, the doping concentration of the contact layer 19a may be smaller than the doping concentration of the contact layer 19b. This allows the contact layer 19b to be formed over a wider area than the contact layer 19a.

[0131] 7 shows the configuration of a semiconductor device 500 according to a comparative example. In this example, a cross-sectional view corresponding to the aa' cross section in FIG. 1A is shown.

[0132] The contact layer 519 is separated from the emitter region 512 on the sidewall of the trench contact portion 527. Therefore, in the semiconductor device 500, it is difficult to suppress the injection of carriers from the emitter region 512.

[0133] In contrast, in the semiconductor device 100, the contact layer 19 is in contact with the emitter region 12, so that the injection of carriers from the emitter region 12 can be suppressed, thereby improving the breakdown resistance.

[0134] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0135] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0136] 10 semiconductor substrate, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 17 well region, 18 drift region, 19 contact layer, 21 front surface, 22 collector region, 23 back surface, 24 collector electrode, 25 connection portion, 27 trench contact portion, 28 termination portion, 29 sidewall bottom portion, 30 dummy trench portion, 31 extension portion, 32 dummy insulating film, 33 connection portion, 34 dummy conductive portion, 38 interlayer insulating film, 40 gate Trench portion, 41...extension portion, 42...gate insulating film, 43...connection portion, 44...gate conductive portion, 50...gate metal layer, 52...emitter electrode, 54...contact hole, 55...contact hole, 56...contact hole, 70...transistor portion, 71...mesa portion, 80...diode portion, 81...mesa portion, 82...cathode region, 90...boundary portion, 91...mesa portion, 100...semiconductor device, 500...semiconductor device, 512...emitter region, 519...contact layer, 527...trench contact portion

Claims

1. a first conductivity type drift region provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; a first high concentration region of a first conductivity type provided above the base region so as to be exposed on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a plurality of trenches arranged in a predetermined arrangement direction on a front surface side of the semiconductor substrate; a trench contact portion including a recess provided on the front surface side of the semiconductor substrate between two adjacent trench portions among the plurality of trench portions, and a conductive material filled inside the recess and connecting the semiconductor substrate to an electrode on the front surface side of the semiconductor substrate; a second high concentration region of a second conductivity type provided apart from the front surface of the semiconductor substrate and having a doping concentration higher than that of the base region; Equipped with the second heavily doped region has a first contact layer provided closer to the front surface of the semiconductor substrate than the bottom surface of the recess; the first contact layer is in contact with the first high concentration region on a sidewall of the recess; The shortest distance in the arrangement direction between the first contact layer and the trench portion adjacent to the first contact layer is smaller than the distance in the depth direction of the semiconductor substrate between the lower end of the first high concentration region and the bottom surface of the recess. Semiconductor device.

2. a first conductivity type drift region provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; a first high concentration region of a first conductivity type provided above the base region so as to be exposed on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a plurality of trenches arranged in a predetermined arrangement direction on a front surface side of the semiconductor substrate; a trench contact portion including a recess provided on the front surface side of the semiconductor substrate between two adjacent trench portions among the plurality of trench portions, and a conductive material filled inside the recess and connecting the semiconductor substrate to an electrode on the front surface side of the semiconductor substrate; a second high concentration region of a second conductivity type provided apart from the front surface of the semiconductor substrate and having a doping concentration higher than that of the base region; Equipped with the second heavily doped region has a first contact layer provided closer to the front surface of the semiconductor substrate than the bottom surface of the recess; the first contact layer is in contact with the first high concentration region on a sidewall of the recess; The first contact layer extends from a lower end of the first high concentration region toward the front surface side of the semiconductor substrate and includes an extension region in contact with the first high concentration region. Semiconductor device.

3. a first conductivity type drift region provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; a first high concentration region of a first conductivity type provided above the base region so as to be exposed on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a plurality of trenches arranged in a predetermined arrangement direction on a front surface side of the semiconductor substrate; a trench contact portion including a recess provided on the front surface side of the semiconductor substrate between two adjacent trench portions among the plurality of trench portions, and a conductive material filled inside the recess and connecting the semiconductor substrate to an electrode on the front surface side of the semiconductor substrate; a second high concentration region of a second conductivity type provided apart from the front surface of the semiconductor substrate and having a doping concentration higher than that of the base region; Equipped with the second heavily doped region has a first contact layer provided closer to the front surface of the semiconductor substrate than the bottom surface of the recess; the first contact layer is in contact with the first high concentration region on a sidewall of the recess; a contact region of a second conductivity type that is exposed on the front surface of the semiconductor substrate and has a doping concentration higher than that of the base region; the plurality of trench portions are provided extending in a predetermined extension direction, The contact region is provided at a terminal end, which is an end in the extending direction of the conductive material. Semiconductor device.

4. a first conductivity type drift region provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; a first high concentration region of a first conductivity type provided above the base region so as to be exposed on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type that is exposed on the front surface of the semiconductor substrate and has a doping concentration higher than that of the base region; a plurality of trenches arranged in a predetermined arrangement direction on a front surface side of the semiconductor substrate; a trench contact portion including a recess provided on the front surface side of the semiconductor substrate between two adjacent trench portions among the plurality of trench portions, and a conductive material filled inside the recess and connecting the semiconductor substrate to an electrode on the front surface side of the semiconductor substrate; a second high concentration region of a second conductivity type provided apart from the front surface of the semiconductor substrate and having a doping concentration higher than that of the base region; Equipped with the second high concentration region has a first contact layer provided apart from a bottom surface of the recess; the first contact layer is in contact with the first high concentration region on a sidewall of the recess; the plurality of trench portions are provided extending in a predetermined extension direction, The contact region is provided at a terminal end, which is an end in the extending direction of the conductive material. Semiconductor device.

5. The sidewall is in contact with the contact region and the second high concentration region in a cross section passing through the termination portion in the arrangement direction.

5. The semiconductor device according to claim 3.

6. The sidewall and the bottom surface are covered with the contact region, the base region, and the second high-concentration region in a cross section passing through the termination portion in the arrangement direction. The semiconductor device according to claim 5 .

7. The sidewall and the bottom surface are covered with the contact region and the second high concentration region in a cross section passing through the termination portion in the arrangement direction. The semiconductor device according to claim 5 .

8. The second high concentration region is provided so as to extend further in the extension direction than the contact region. The semiconductor device according to claim 3 .

9. The second heavily doped region has a second contact layer in contact with the bottom surface of the recess. The semiconductor device according to claim 1 .

10. The conductive material has a convex bottom surface that protrudes toward the back surface of the semiconductor substrate. The semiconductor device according to claim 1 .

11. The semiconductor substrate is a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate. The semiconductor device according to claim 1 .

12. The semiconductor device is an IGBT or a MOS transistor. The semiconductor device according to claim 1 .

13. A method for manufacturing a semiconductor device comprising: a drift region of a first conductivity type provided in a semiconductor substrate; a base region of a second conductivity type provided above the drift region; a first high concentration region of the first conductivity type provided above the base region so as to be exposed on a front surface of the semiconductor substrate and having a higher doping concentration than the drift region; and a plurality of trench portions arranged in a predetermined arrangement direction on the front surface side of the semiconductor substrate, forming a recess by etching the front surface side of the semiconductor substrate between two adjacent trench portions among the plurality of trench portions; providing a second heavily doped region of a second conductivity type spaced from the front surface of the semiconductor substrate and having a higher doping concentration than the base region; Including, the second heavily doped region has a first contact layer provided closer to the front surface of the semiconductor substrate than the bottom surface of the recess; the first contact layer is in contact with the first high concentration region on a sidewall of the recess; The shortest distance in the arrangement direction between the first contact layer and the trench portion adjacent to the first contact layer is smaller than the distance in the depth direction of the semiconductor substrate between the lower end of the first high concentration region and the bottom surface of the recess. A method for manufacturing a semiconductor device.

14. A method for manufacturing a semiconductor device comprising: a drift region of a first conductivity type provided in a semiconductor substrate; a base region of a second conductivity type provided above the drift region; a first high concentration region of the first conductivity type provided above the base region so as to be exposed on a front surface of the semiconductor substrate and having a higher doping concentration than the drift region; and a plurality of trench portions arranged in a predetermined arrangement direction on the front surface side of the semiconductor substrate, forming a recess by etching the front surface side of the semiconductor substrate between two adjacent trench portions among the plurality of trench portions; providing a second heavily doped region of a second conductivity type spaced from the front surface of the semiconductor substrate and having a higher doping concentration than the base region; Including, the second heavily doped region has a first contact layer provided closer to the front surface of the semiconductor substrate than the bottom surface of the recess; the first contact layer is in contact with the first high concentration region on a sidewall of the recess; The first contact layer extends from a lower end of the first high concentration region toward the front surface side of the semiconductor substrate and includes an extension region in contact with the first high concentration region. A method for manufacturing a semiconductor device.

15. a first high concentration region of the first conductivity type provided above the base region so as to be exposed on a front surface of the semiconductor substrate, the first high concentration region having a doping concentration higher than that of the drift region; a contact region of the second conductivity type provided above the base region so as to be exposed on the front surface of the semiconductor substrate, the contact region having a doping concentration higher than that of the base region; and a plurality of trench portions extending in a predetermined extension direction and arranged in a predetermined arrangement direction on the front surface side of the semiconductor substrate, forming a recess by etching the front surface side of the semiconductor substrate between two adjacent trench portions among the plurality of trench portions; providing a second heavily doped region of a second conductivity type spaced from the front surface of the semiconductor substrate and having a higher doping concentration than the base region; Including, the second heavily doped region has a first contact layer provided closer to the front surface of the semiconductor substrate than the bottom surface of the recess; the first contact layer is in contact with the first high concentration region on a sidewall of the recess; The contact region is provided at a terminal end portion, which is an end portion of the recess in the extension direction. A method for manufacturing a semiconductor device.

16. The second heavily doped region has a second contact layer in contact with the bottom surface of the recess. The method for manufacturing a semiconductor device according to any one of claims 13 to 15.

17. a first conductivity type drift region provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; a first high concentration region of a first conductivity type provided above the base region so as to be exposed on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a plurality of trenches arranged in a predetermined arrangement direction on a front surface side of the semiconductor substrate; a trench contact portion including a recess provided on the front surface side of the semiconductor substrate between two adjacent trench portions among the plurality of trench portions, and a conductive material filled inside the recess and connecting the semiconductor substrate to an electrode on the front surface side of the semiconductor substrate; a second high concentration region of a second conductivity type provided apart from the front surface of the semiconductor substrate and having a doping concentration higher than that of the base region; Equipped with the second heavily doped region has a first contact layer provided closer to the front surface of the semiconductor substrate than a bottom surface of the recess, and a second contact layer in contact with the bottom surface of the recess; the first contact layer and the second contact layer are connected to each other, a peak position of the doping concentration in the first contact layer is shallower than a peak position of the doping concentration in the second contact layer in a depth direction of the semiconductor substrate; the first contact layer is in contact with the first high concentration region on a sidewall of the recess; The second contact layer is provided from one sidewall of the recess along the bottom surface of the recess to the other sidewall of the recess. Semiconductor device.

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