Semiconductor Package

Abstract

To provide a semiconductor package capable of obtaining stable characteristics.SOLUTION: A semiconductor package includes a first conductive member, a second conductive member, a plurality of semiconductor devices, a wiring member, a first connection member, and a second connection member. The wiring member includes a first wiring layer, a second wiring layer, a third wiring layer, and an insulation region. A direction from the first wiring layer toward the second wiring layer and a direction from the first wiring layer toward the third wiring layer are along a first direction. At least a part of the insulation region is between the first wiring layer and the third wiring layer and between the third wiring layer and the second wiring layer. The first connection member is provided between a first connection region of the wiring member and a first control electrode of each semiconductor device. The second connection member is provided between a second connection region of the wiring member and a second control electrode of each semiconductor device.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to semiconductor packages. [Background technology]

[0002] Stable characteristics are desired in semiconductor packages that include semiconductor devices such as IGBTs (insulated gate bipolar transistors). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-222916 Summary of the Invention [Problem to be solved by the invention]

[0004] Embodiments of the present invention provide a semiconductor package that provides stable characteristics. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor package includes a first conductive member, a second conductive member, a plurality of semiconductor devices, a wiring member, a first connecting member, and a second connecting member. The plurality of semiconductor devices are disposed between the first conductive member and the second conductive member. One of the plurality of semiconductor devices includes a semiconductor member, a first electrode disposed between the first conductive member and the semiconductor member, a first control electrode disposed between the first conductive member and the semiconductor member, a second control electrode disposed between the first conductive member and the semiconductor member, and a second electrode disposed between the semiconductor member and the second conductive member. The first conductive member is electrically connected to the first electrode. The second conductive member is electrically connected to the second electrode. A direction from the second control electrode to the first control electrode intersects a first direction from the first conductive member to the second conductive member. The wiring member includes a first wiring layer, a second wiring layer, a third wiring layer, and an insulating region. The direction from the first wiring layer to the second wiring layer and the direction from the first wiring layer to the third wiring layer are along the first direction. At least a portion of the insulating region is between the first wiring layer and the third wiring layer and between the third wiring layer and the second wiring layer. The position of the second wiring layer in the first direction is between the position of the insulating region in the first direction and the position of the multiple semiconductor devices in the first direction. The second wiring layer includes a first connection region and a second connection region. The first connection region is electrically connected to the first wiring layer. The third wiring layer is electrically connected to the first conductive member. The first connection member is provided between the first connection region and the first control electrode and electrically connects the first connection region to the first control electrode. The second connection member is provided between the second connection region and the second control electrode and electrically connects the second connection region to the second control electrode. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating a semiconductor package according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view illustrating the semiconductor package according to the first embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view illustrating the semiconductor package according to the first embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view illustrating a part of the semiconductor package according to the first embodiment. [Figure 5] FIG. 5 is a circuit diagram illustrating the semiconductor package according to the first embodiment. [Figure 6] 6(a) and 6(b) are schematic views illustrating the operation of the semiconductor package according to the first embodiment. [Figure 7] FIG. 7 is a circuit diagram illustrating a part of the semiconductor package according to the first embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view illustrating a semiconductor package according to the second embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view illustrating a semiconductor package according to the second embodiment. [Figure 10] FIG. 10 is a schematic view illustrating a semiconductor package according to the embodiment. [Figure 11] FIG. 11 is a schematic view illustrating a semiconductor package according to the embodiment. [Figure 12] FIG. 12 is a schematic view illustrating a semiconductor package according to the embodiment. [Figure 13] FIG. 13 is a schematic view illustrating a semiconductor package according to the embodiment. [Figure 14] FIG. 14 is a schematic view illustrating a semiconductor package according to the embodiment. [Figure 15] FIG. 15 is a schematic view illustrating a semiconductor package according to the embodiment. [Figure 16] FIG. 16 is a schematic plan view illustrating a part of the semiconductor package according to the embodiment. [Figure 17] FIG. 17 is a schematic plan view illustrating a part of the semiconductor package according to the embodiment. [Figure 18] FIG. 18 is a schematic plan view illustrating a part of the semiconductor package according to the embodiment. [Figure 19] FIG. 19 is a schematic side view illustrating a state in which the semiconductor package according to the embodiment is used. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and in each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

[0008] (First embodiment) FIG. 1 is a schematic cross-sectional view illustrating a semiconductor package according to the first embodiment. FIG. 2 is a schematic plan view illustrating the semiconductor package according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating the semiconductor package according to the first embodiment. Fig. 1 is a cross-sectional view taken along line A1-A2 in Fig. 2. Fig. 3 is a cross-sectional view taken along line B1-B2 in Fig. 2.

[0009] As shown in FIG. 1, a semiconductor package 110 according to the embodiment includes a first conductive member 61, a second conductive member 62, a plurality of semiconductor devices 15, a wiring member 20, a first connecting member 31, and a second connecting member 32.

[0010] The multiple semiconductor devices 15 are arranged between a first conductive member 61 and a second conductive member 62. A first direction D1 from the first conductive member 61 to the second conductive member 62 is defined as the Z-axis direction. A direction perpendicular to the Z-axis direction is defined as the X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is defined as the Y-axis direction. As shown in FIG. 2, the multiple semiconductor devices 15 are arranged, for example, in the XY plane. FIG. 2 illustrates a state in which the second conductive member 62 is removed.

[0011] As shown in FIG. 1, one of the plurality of semiconductor devices 15 includes a semiconductor member 15s, a first electrode 15p, a first control electrode 15a, a second control electrode 15b, and a second electrode 15q.

[0012] The first electrode 15p is provided between the first conductive member 61 and the semiconductor member 15s. The first control electrode 15a is provided between the first conductive member 61 and the semiconductor member 15s. The second control electrode 15b is provided between the first conductive member 61 and the semiconductor member 15s. The second electrode 15q is provided between the semiconductor member 15s and the second conductive member 62.

[0013] For example, one of the plurality of semiconductor devices 15 includes a first surface f1 and a second surface f2. The first surface f1 is located between the first conductive member 61 and the second surface f2. The second surface f2 is located between the first surface f1 and the second conductive member 62. The first surface f1 faces the first conductive member 61. The second surface f2 faces the second conductive member 62.

[0014] For example, the first electrode 15p, the first control electrode 15a, and the second control electrode 15b are provided on the first surface f1, and the second electrode 15q is provided on the second surface f2.

[0015] The first conductive member 61 is electrically connected to the first electrode 15p, and the second conductive member 62 is electrically connected to the second electrode 15q.

[0016] 1 and 2, the direction from the second control electrode 15b to the first control electrode 15a intersects with the first direction D1 (the direction from the first conductive member 61 to the second conductive member 62). In the example of FIGS. 1 and 2, in one of the semiconductor devices 15 of interest, the direction from the second control electrode 15b to the first control electrode 15a is along the second direction D2. The second direction D2 intersects with the first direction D1. In one example, the second direction D2 may be the X-axis direction.

[0017] 1, the wiring member 20 includes a first wiring layer 21, a second wiring layer 22, a third wiring layer 23, and an insulating region 25i. The direction from the first wiring layer 21 to the second wiring layer 22 and the direction from the third wiring layer 23 to the second wiring layer 22 are along a first direction D1. In this example, the third wiring layer 23 is located between the first wiring layer 21 and the second wiring layer 22.

[0018] At least a portion of the insulating region 25i is located between the first wiring layer 21 and the second wiring layer 22, and between the third wiring layer 23 and the second wiring layer 22. The insulating region 25i insulates these wiring layers from each other.

[0019] In the wiring member 20, the first wiring layer 21, the second wiring layer 22, the third wiring layer 23, and the insulating region 25i may be in contact with each other and may be integral with each other, or the first wiring layer 21, the second wiring layer 22, the third wiring layer 23, and the insulating region 25i may be separable from each other.

[0020] The position of the second wiring layer 22 in the first direction D1 is between the position of the insulating region 25i in the first direction D1 and the positions of the multiple semiconductor devices 15 in the first direction D1. The second wiring layer 22 faces the multiple semiconductor devices 15.

[0021] As shown in FIG. 1, the second wiring layer 22 includes a first connection region 22a and a second connection region 22b.

[0022] The first connection region 22a is electrically connected to the first wiring layer 21. In this example, the wiring member 20 further includes a first connection portion 27a. The first connection portion 27a electrically connects the first wiring layer 21 to the second connection region 22b. At least a portion of the first connection portion 27a extends in the insulating region 25i in the first direction D1 (Z-axis direction). In this example, the third wiring layer 23 includes a third wiring layer hole 23h. The first connection portion 27a passes through the third wiring layer hole 23h.

[0023] As will be described later, the third wiring layer 23 is electrically connected to the first conductive member 61.

[0024] 1, the first connection member 31 is provided between the first connection region 22a and the first control electrode 15a. The first connection member 31 electrically connects the first connection region 22a to the first control electrode 15a.

[0025] 1, the second connection member 32 is provided between the second connection region 22b and the second control electrode 15b. The second connection member 32 electrically connects the second connection region 22b to the second control electrode 15b.

[0026] 1, the semiconductor package 110 may include a first terminal T1, a second terminal T2, and a third terminal T3. The first terminal T1 is electrically connected to a first wiring layer 21. The second terminal T2 is electrically connected to a second wiring layer 22. The third terminal T3 is electrically connected to a third wiring layer 23.

[0027] In the semiconductor package 110, a current (e.g., a main current) flowing between the first conductive member 61 and the second conductive member 62 may be controlled by a signal supplied to at least one of the first terminal T1 and the second terminal T2. The current may be controlled by the potential of at least one of the first terminal T1 and the second terminal T2. The signal (or potential) may be a signal (potential) based on the potential of the third terminal T3.

[0028] The plurality of semiconductor devices 15 are transistors. For example, the plurality of semiconductor devices 15 may be IGBTs (Insulated Gate Bipolar Transistors). The first electrode 15p corresponds to, for example, an emitter electrode. The second electrode 15q corresponds to, for example, a collector electrode. The first control electrode 15a corresponds to a gate electrode. The second control electrode 15b corresponds to an electrode for controlling operation.

[0029] As will be described later, a control signal different from that input to the first terminal T1 is input to the second terminal T2. This makes it possible to reduce loss, for example, during turn-off. In this case, if the control signals input to the multiple semiconductor devices 15 are not uniform, it becomes difficult to achieve the desired loss reduction.

[0030] For example, a reference example may be considered in which the wiring connected to the first control electrode 15a and the wiring connected to the second control electrode 15b are provided in the same plane. In this case, the difference in the lengths of these wirings is large among the multiple semiconductor devices 15. Therefore, in this reference example, loss reduction is insufficient.

[0031] In the embodiment, the first wiring layer 21 connected to the first control electrode 15a and the second wiring layer 22 connected to the second control electrode 15b may overlap in the first direction D1. This reduces the difference in length between these wiring layers in the multiple semiconductor devices 15. According to the embodiment, the desired loss reduction can be effectively and stably achieved in each of the multiple semiconductor devices 15.

[0032] According to the embodiment, loss can be reduced. For example, a semiconductor package that can obtain stable characteristics can be provided. For example, the operations of a plurality of semiconductor devices 15 can be made uniform. For example, high reliability can be easily obtained.

[0033] 1, in this example, the position of the second wiring layer 22 in the first direction D1 is between the position of the first wiring layer 21 in the first direction D1 and the positions of the multiple semiconductor devices 15 in the first direction D1. The position of the third wiring layer 23 in the first direction D1 is between the position of the first wiring layer 21 in the first direction D1 and the position of the second wiring layer 22 in the first direction D1.

[0034] For example, the first wiring layer 21, the third wiring layer 23, and the second wiring layer 22 are arranged in this order. As a result, for example, the parasitic capacitance between the first wiring layer 21 and the third wiring layer 23 becomes substantially the same as the parasitic capacitance between the second wiring layer 22 and the third wiring layer 23. For example, the distortion of the signal supplied to the first wiring layer 21 is close to the distortion of the signal supplied to the second wiring layer 22. This allows for more stable loss reduction.

[0035] The distance (first distance) between the first wiring layer 21 and the third wiring layer 23 along the first direction D1 may be substantially the same as the distance (second distance) between the third wiring layer 23 and the second wiring layer 22 along the first direction D1. This allows the parasitic capacitance to be substantially the same. In one example, the second distance may be 0.5 to 1.5 times the first distance. In another example, the second distance may be 0.3 to 3.0 times the first distance. For example, high mechanical strength can be easily obtained in the wiring member 20.

[0036] In the embodiment, the first connecting member 31 and the second connecting member 32 are preferably elastic members. These wiring members are, for example, spring pins. This allows for stable connection.

[0037] 3, the first conductive member 61 may include a first base portion 61b and a first protrusion portion 61p. The first protrusion portion 61p is connected to the first base portion 61b. The first protrusion portion 61p protrudes toward the second conductive member 62 with respect to the first base portion 61b.

[0038] 3, the wiring member 20 includes, for example, a wiring member hole 20h. The first protrusion 61p passes through the wiring member hole 20h. Ends of the first protrusion 61p face the plurality of semiconductor devices 15.

[0039] 1 and 3, in this example, the semiconductor package 110 includes a first conductive plate 35a and a second conductive plate 35b. The first conductive plate 35a is located between the first protrusion 61p and the first electrode 15p. The second conductive plate 35b is located between the second electrode 15q and the second conductive member 62. The first conductive plate 35a electrically connects the first protrusion 61p to the first electrode 15p. The second conductive plate 35b electrically connects the second electrode 15q to the second conductive member 62.

[0040] At least one of the first conductive plate 35a and the second conductive plate 35b contains, for example, Mo. The first conductive plate 35a and the second conductive plate 35b are, for example, Mo plates. At least one of the first conductive member 61 and the second conductive member 62 contains, for example, Cu.

[0041] 3, the second wiring layer 22 may further include a third connection region 22c. Meanwhile, the wiring member 20 may further include a second connection portion 27b and a fourth wiring layer 24. The insulating region 25i is located between the fourth wiring layer 24 and the third connection region 22c in the first direction D1. The second connection portion 27b extends in the insulating region 25i along the first direction D1. The second connection portion 27b electrically connects the fourth wiring layer 24 to the third connection region 22c.

[0042] In this example, the wiring member 20 further includes a third connection portion 27c. The third connection portion 27c extends in the insulating region 25i along the first direction D1. The third connection portion 27c electrically connects the third connection region 22c to the third wiring layer 23.

[0043] With this configuration, the third wiring layer 23 is electrically connected to the fourth wiring layer 24 via the third connection portion 27c, the third connection region 22c, and the second connection portion 27b. The fourth wiring layer 24 is electrically connected to the first conductive member 61.

[0044] 3, in this example, semiconductor package 110 further includes a fixing member 28. Fixing member 28 includes a first fixing portion 28p and a first fixing extension portion 28e. First fixing extension portion 28e is connected to first fixing portion 28p. For example, the width of first fixing portion 28p along second direction D2 is greater than the width of first fixing extension portion 28e along second direction D2. Fixing member 28 may be, for example, a screw.

[0045] The fourth wiring layer 24, the second connection portion 27b, and the third connection region 22c are located between a portion of the first conductive member 61 and the first fixed portion 28p in the first direction D1. The first fixed extension portion 28e passes through the fourth wiring layer 24, the second connection portion 27b, and the third connection region 22c along the first direction D1. The first fixed extension portion 28e is fixed to the above-mentioned portion of the first conductive member 61. For example, the wiring member 20 is fixed to the first conductive member 61 by a fixing member 28 (e.g., a screw). The fixing member 28 electrically connects the third wiring layer 23 to the first conductive member 61.

[0046] 1 and 3, the semiconductor package 110 may further include an insulating plate 45. The insulating plate 45 is provided between the first base portion 61b and the wiring member 20. The insulating plate 45 electrically insulates the first conductive member 61 from a portion of the wiring member 20 that should be insulated. The insulating plate 45 may include, for example, glass epoxy.

[0047] 1 and 3, the semiconductor package 110 may further include an insulating member 65. As shown in FIG. 2, the insulating member 65 is provided around the plurality of semiconductor devices 15 in a plane (e.g., the XY plane) intersecting the first direction D1. At least a portion of the insulating member 65 is located between the first conductive member 61 and the second conductive member 62. The insulating member 65 includes, for example, ceramic. The insulating member 65 may be, for example, an insulator. Stable insulation can be obtained.

[0048] In the embodiment, stress in a direction from the first conductive member 61 to the plurality of semiconductor devices 15 and stress in a direction from the second conductive member 62 to the plurality of semiconductor devices 15 are applied to the plurality of semiconductor devices 15. The semiconductor package 110 is, for example, a press-pack semiconductor device (press-pack IGBT).

[0049] Thus, in the embodiment, one of the plurality of semiconductor devices 15 is an IGBT. The first electrode 15p functions as an emitter electrode. The second electrode 15q functions as a collector electrode. The current flowing between the first electrode 15p and the second electrode 15q can be controlled by the potential of at least one of the first control electrode 15a and the second control electrode 15b.

[0050] FIG. 4 is a schematic cross-sectional view illustrating a portion of a semiconductor package according to the first embodiment. FIG. 4 illustrates one of the multiple semiconductor devices 15. As shown in FIG. 4, one of the multiple semiconductor devices 15 includes a first conductive portion 51, a second conductive portion 52, a third conductive portion 53, a fourth conductive portion 54, and an element insulating portion 11i. A second element direction De2 extending from the third conductive portion 53 to the fourth conductive portion 54 intersects with a first element direction De1 extending from the first conductive portion 51 to the second conductive portion 52. The first element direction De1 may be, for example, the opposite direction to the first direction D1. The third conductive portion 53 and the fourth conductive portion 54 extend along a third element direction De3. The third element direction De3 intersects with a plane including the first element direction De1 and the second element direction De2.

[0051] As already described, one of the plurality of semiconductor devices 15 includes a semiconductor member 15s. As shown in Fig. 4, the semiconductor member 15s includes a first semiconductor region 11a of a first conductivity type, a second semiconductor region 11b of a second conductivity type, a third semiconductor region 11c of the first conductivity type, and a fourth semiconductor region 11d of the second conductivity type.

[0052] The fourth semiconductor region 11d is located between the first conductive unit 51 and the first semiconductor region 11a in the first element direction De1. The first semiconductor region 11a includes a first partial region r1, a second partial region r2, a third partial region r3, and a fourth partial region r4. The first partial region r1 is located between the fourth semiconductor region 11d and the third conductive unit 53 in the first element direction De1. The second partial region r2 is located between the fourth semiconductor region 11d and the fourth conductive unit 54 in the first element direction De1.

[0053] The third partial region r3 is located between the first partial region r1 and the second partial region r2 in the second element direction De2. The fourth partial region r4 is located between the third partial region r3 and the third semiconductor region 11c in the first element direction De1. The second semiconductor region 11b is located between the fourth partial region r4 and the third semiconductor region 11c in the first element direction De1.

[0054] The direction from the third conductive portion 53 to the fourth partial region r4, the second semiconductor region 11b, and the third semiconductor region 11c is along the second element direction De2. The second semiconductor region 11b is located between the third conductive portion 53 and the fourth conductive portion 54 in the second element direction De2.

[0055] The first conductive portion 51 is electrically connected to the fourth semiconductor region 11d, and the second conductive portion 52 is electrically connected to the third semiconductor region 11c.

[0056] The element insulating portion 11i is provided between the semiconductor member 15s and the third conductive portion 53, between the semiconductor member 15s and the fourth conductive portion 54, between the third conductive portion 53 and the second semiconductor region 11b, and between the second semiconductor region 11b and the fourth conductive portion 54. The element insulating portion 11i may be provided between the third conductive portion 53 and the third semiconductor region 11c.

[0057] The first conductive portion 51 is electrically connected to the first electrode 15p. The second conductive portion 52 is electrically connected to the second electrode 15q. The third conductive portion 53 is electrically connected to the first control electrode 15a. The fourth conductive portion 54 is electrically connected to the second control electrode 15b.

[0058] The first conductivity type is one of n-type and p-type. The second conductivity type is the other of n-type and p-type. In the following, the first conductivity type is n-type and the second conductivity type is p-type.

[0059] The first semiconductor region 11a is, for example, n - An n-type region may be provided between the first semiconductor region 11a and the second semiconductor region 11b. The second semiconductor region 11b may include, for example, a p-type region. The third semiconductor region 11c may include, for example, an n-type region. + The fourth semiconductor region 11d includes, for example, a p-region. The third semiconductor region 11c has a higher impurity concentration (for example, carrier concentration) of the first conductivity type in the third semiconductor region 11c than the first semiconductor region 11a.

[0060] In this example, a fifth semiconductor region 11e of the second conductivity type is provided. The fifth semiconductor region 11e is provided between the second semiconductor region 11b and the second conductive portion 52. The impurity concentration (for example, carrier concentration) of the second conductivity type in the fifth semiconductor region 11e is higher than the impurity concentration (for example, carrier concentration) of the second conductivity type in the second semiconductor region 11b. The fifth semiconductor region 11e is, for example, p + This is the area where good electrical connection can be achieved.

[0061] In this example, a sixth semiconductor region 11f of a first conductivity type is provided. The sixth semiconductor region 11f is provided between the fourth semiconductor region 11d and the first semiconductor region 11a. The impurity concentration (e.g., carrier concentration) of the first conductivity type in the sixth semiconductor region 11f is higher than the impurity concentration (e.g., carrier concentration) of the first conductivity type in the first semiconductor region 11a. The sixth semiconductor region 11f is, for example, an n-type region. Good electrical connection is obtained.

[0062] 4, there are provided a plurality of third conductive parts 53 and a plurality of fourth conductive parts 54. The number (density) of the plurality of fourth conductive parts 54 may be greater than the number (density) of the plurality of third conductive parts 53.

[0063] FIG. 5 is a circuit diagram illustrating the semiconductor package according to the first embodiment. 5, multiple semiconductor devices 15 are connected in parallel. A current flowing between a first conductive member 61 and a second conductive member 62 is controlled by a signal supplied to a first terminal T1 and a second terminal T2.

[0064] 6(a) and 6(b) are schematic views illustrating the operation of the semiconductor package according to the first embodiment. 6(a) illustrates the potential Vc1 of the first terminal T1. FIG. 6(b) illustrates the potential Vc2 of the second terminal T2. These potentials may be based on the potential of the third terminal T3. The horizontal axis of these figures represents time tm.

[0065] As shown in FIG. 6(a), when the potential Vc1 of the first terminal T1 relative to the potential of the third terminal T3 is the second potential V2, it corresponds to the OFF state. When the potential Vc1 is the first potential V1, it corresponds to the ON state. The second potential V2 is lower than the first potential V1. For example, the second potential V2 is negative and the first potential V1 is positive. The OFF state is formed when the potential Vc1 changes from the first potential V1 to the second potential V2.

[0066] In the OFF operation in which the potential Vc1 of the first terminal T1 changes from the first potential V1 to the second potential V2, the time when the potential changes from the first potential V1 to the second potential V2 is defined as a first time t1.

[0067] 6(b), the potential Vc2 of the second terminal T2 relative to the potential of the third terminal T3 can change from a third potential V3 to a fourth potential V4. The fourth potential V4 is lower than the third potential V3. For example, the fourth potential V4 is negative, and the third potential is positive.

[0068] 6(a) and 6(b), before the first time t1, the potential Vc2 of the second terminal T2 changes from the third potential V3 to the fourth potential V4. This makes it possible, for example, to effectively discharge carriers accumulated in the semiconductor member 15s. This makes it possible, for example, to reduce loss during turn-off.

[0069] Such control of the potential (control of the signal) may be performed by a control unit connected to the semiconductor package 110. The semiconductor package 110 may include a control unit that performs such control of the potential (control of the signal).

[0070] FIG. 7 is a circuit diagram illustrating a part of the semiconductor package according to the first embodiment. 7 illustrates one of the plurality of semiconductor devices 15. As shown in FIG. 7, the first electrode 15p is electrically connected to the first conductive member 61. The second electrode 15q is electrically connected to the second conductive member 62. The first control electrode 15a is electrically connected to the first terminal T1. The second control electrode 15b is electrically connected to the second terminal T2. The first electrode 15p is electrically connected to the third terminal T3.

[0071] For example, a parasitic inductance L1 exists in the current path between the first electrode 15p and the first conductive member 61. For example, a parasitic inductance L2 exists in the current path between the second electrode 15q and the second conductive member 62. A parasitic inductance Lg1 exists in the current path between the first control electrode 15a and the first terminal T1. A parasitic inductance Lg2 exists in the current path between the second control electrode 15b and the second terminal T2. A parasitic inductance L3 exists in the current path between the first electrode 15p and the third terminal T3.

[0072] Mutual inductance occurs between the parasitic inductance Lg1 and the parasitic inductance Lg2. Mutual inductance occurs between the parasitic inductance Lg1 and the parasitic inductance L3. Mutual inductance occurs between the parasitic inductance Lg2 and the parasitic inductance L3.

[0073] Furthermore, mutual inductance occurs between the parasitic inductance Lg1 and the parasitic inductance L1. Mutual inductance occurs between the parasitic inductance Lg1 and the parasitic inductance L2.

[0074] A mutual inductance occurs between the parasitic inductance Lg2 and the parasitic inductance L1. A mutual inductance occurs between the parasitic inductance Lg2 and the parasitic inductance L2.

[0075] Uniform operation is easily achieved by making the parasitic inductance and mutual inductance uniform among the multiple semiconductor devices 15. In the embodiment, the use of the above-described wiring member 20 makes it easy to make these inductances small and uniform. For example, signal delay can be made uniform.

[0076] For example, the parasitic inductance Lg1 causes a transmission delay in the control signal supplied to the first control electrode 15a. The parasitic inductance Lg2 causes a transmission delay in the control signal supplied to the second control electrode 15b. The difference in these parasitic inductances causes a difference in the transmission delay of these control signals. The difference in transmission delay may cause malfunction.

[0077] In the embodiment, by using the above-described wiring member 20, it is easy to make the wiring lengths uniform among the plurality of semiconductor devices 15. For example, it is possible to reduce the difference in parasitic inductance.

[0078] Mutual inductance generates an induced voltage due to the time change (dI / dt) of the signal supplied to the control electrode. The induced voltage due to mutual inductance may cause malfunction or current oscillation.

[0079] For example, when the third wiring layer 23 is provided between the first wiring layer 21 and the second wiring layer 22, the magnetic field generated by the current flowing through the first wiring layer 21 and the magnetic field generated by the current flowing through the second wiring layer 22 cancel each other out, thereby effectively suppressing the mutual inductance.

[0080] According to the embodiment, it is easy to make the wiring lengths uniform in the plurality of semiconductor devices 15. It is possible to reduce variations in parasitic inductance. For example, it is possible to suppress mutual inductance. It is possible to further suppress malfunctions.

[0081] (Second embodiment) 8 and 9 are schematic cross-sectional views illustrating a semiconductor package according to the second embodiment. Fig. 8 is a cross-sectional view corresponding to the line A1-A2 in Fig. 2. Fig. 9 is a cross-sectional view corresponding to the line B1-B2 in Fig. 2.

[0082] 8, in a semiconductor package 120 according to the embodiment, the configuration of the wiring member 20 is different from the configuration of the wiring member 20 in the semiconductor package 110. Other than this, the configuration of the semiconductor package 120 may be the same as the configuration of the semiconductor package 110.

[0083] 8, in the semiconductor package 120, the wiring member 20 includes a first wiring layer 21, a second wiring layer 22, a third wiring layer 23, and an insulating region 25i. As shown in Fig. 8, the position of the second wiring layer 22 in the first direction D1 is between the position of the third wiring layer 23 in the first direction D1 and the positions of the multiple semiconductor devices 15 in the first direction D1. The position of the first wiring layer 21 in the first direction D1 is between the position of the third wiring layer 23 in the first direction D1 and the position of the second wiring layer 22 in the first direction D1.

[0084] In such a semiconductor package 120, it is easy to make the wiring lengths uniform among the plurality of semiconductor devices 15. It is possible to reduce variations in parasitic inductance. It is possible to provide a semiconductor package that can obtain stable characteristics.

[0085] 6, before the first time t1 of the turn-off operation, the potential Vc2 of the second terminal T2 is changed from the third potential V3 to the fourth potential V4. This makes it possible to effectively discharge carriers accumulated in the semiconductor member 15s, for example, and reduce loss during turn-off. By making the number of the plurality of fourth conductive parts 54 greater than the number of the plurality of third conductive parts 53, carriers can be more effectively discharged.

[0086] When the number of the plurality of fourth conductive portions 54 is greater than the number of the plurality of third conductive portions 53, the capacitance of the second control electrode 15b becomes greater than the capacitance of the first control electrode 15a. In such a case, the second wiring layer 22 connected to the second control electrode 15b having a larger capacitance is located closer to the semiconductor device 15, thereby further suppressing waveform distortion. For example, the second wiring layer 22 is located between the first wiring layer 21 and the plurality of semiconductor devices 15. This allows for more stable operation.

[0087] An example of a semiconductor package according to an embodiment will be described below. 10 to 15 are schematic views illustrating semiconductor packages according to the embodiment. Figures 10, 13, 14 and 15 are cross-sectional views, and Figures 11 and 12 are plan views.

[0088] 10, the semiconductor package 111 has the same configuration as the semiconductor package 110. The second terminal T2 passes through the insulating member 65 and is exposed to the outside.

[0089] 11 illustrates a first surface f1 of a semiconductor package 111. A first electrode 15p, a first control electrode 15a, and a second control electrode 15b are provided on the first surface f1. These electrodes are not covered with an element insulating member 15i. A plurality of first electrodes 15p may be provided.

[0090] 12 illustrates the second surface f2 of the semiconductor package 111. A second electrode 15q is provided on the second surface f2.

[0091] 13 to 15 each illustrate a portion of the outer edge of the semiconductor package 111. As shown in FIG. 13, the second terminal T2 is electrically connected to the second wiring layer 22 by a fixing member 22f. As shown in FIG. 14, the third terminal T3 is electrically connected to the third wiring layer 23 by a fixing member 23f. As shown in FIG. 15, the first terminal T1 is electrically connected to the first wiring layer 21 by a fixing member 21f. The fixing members 21f, 22f, and 23f are, for example, conductive screws.

[0092] 16 to 18 are schematic plan views illustrating a part of the semiconductor package according to the embodiment. 16, the second control electrode 15b is provided adjacent to the first control electrode 15a in the semiconductor package 112. These control electrodes are provided in the corners of the semiconductor device 15.

[0093] As shown in FIG. 17, in a semiconductor package 113, the second control electrode 15b is provided along one side of the semiconductor device 15 and spaced apart from the first control electrode 15a.

[0094] 18, the second control electrode 15b is provided adjacent to the first control electrode 15a in the semiconductor package 114. These control electrodes are provided in the center of one side of the semiconductor device 15.

[0095] FIG. 19 is a schematic side view illustrating a state in which the semiconductor package according to the embodiment is used. 19, a plurality of semiconductor packages 110 may be stacked. The plurality of semiconductor packages 110 are provided between a first plate 81 and a second plate 82. Cooling fins 84 may be provided between the plurality of semiconductor packages 110. For example, an insulator 85 may be provided between the first plate 81 and the cooling fin 84. For example, an insulator 86 may be provided between the cooling fin 84 and the second plate 82. A spring 87 may be provided between the insulator 86 and the second plate 82. The first plate 81 and the second plate 82 may be fixed together with pressure applied by a fixing member 83 (for example, a screw).

[0096] The embodiment may include the following configurations (for example, technical solutions). (Configuration 1) a first conductive member; A second conductive member; a plurality of semiconductor devices provided between the first conductive member and the second conductive member, one of the plurality of semiconductor devices including a semiconductor member, a first electrode provided between the first conductive member and the semiconductor member, a first control electrode provided between the first conductive member and the semiconductor member, a second control electrode provided between the first conductive member and the semiconductor member, and a second electrode provided between the semiconductor member and the second conductive member, the first conductive member being electrically connected to the first electrode, the second conductive member being electrically connected to the second electrode, and a direction from the second control electrode to the first control electrode intersecting a first direction from the first conductive member to the second conductive member; a wiring member including a first wiring layer, a second wiring layer, a third wiring layer, and an insulating region, a direction from the first wiring layer to the second wiring layer and a direction from the first wiring layer to the third wiring layer are along the first direction, at least a part of the insulating region is between the first wiring layer and the third wiring layer and between the third wiring layer and the second wiring layer, a position of the second wiring layer in the first direction is between a position of the insulating region in the first direction and a position of the plurality of semiconductor devices in the first direction, the second wiring layer includes a first connection region and a second connection region, the first connection region is electrically connected to the first wiring layer, and the third wiring layer is electrically connected to the first conductive member; a first connection member provided between the first connection region and the first control electrode, electrically connecting the first connection region to the first control electrode; a second connection member provided between the second connection region and the second control electrode, the second connection member electrically connecting the second connection region to the second control electrode; A semiconductor package comprising:

[0097] (Configuration 2) the position of the second wiring layer in the first direction is between the position of the first wiring layer in the first direction and the positions of the plurality of semiconductor devices in the first direction; A semiconductor package as described in configuration 1, wherein the position of the third wiring layer in the first direction is between the position of the first wiring layer in the first direction and the position of the second wiring layer in the first direction.

[0098] (Configuration 3) The semiconductor package of configuration 2, wherein the distance along the first direction between the first wiring layer and the third wiring layer is 0.3 to 3.0 times the distance along the first direction between the third wiring layer and the second wiring layer.

[0099] (Configuration 4) the wiring member further includes a first connection portion, the first connection portion electrically connects the first wiring layer to the first connection region; 4. The semiconductor package of claim 2, wherein at least a portion of the first connection portion extends in the first direction within the insulating region.

[0100] (Configuration 5) the third wiring layer includes a third wiring layer hole; 5. The semiconductor package of claim 4, wherein the first connection portion passes through the third wiring layer hole.

[0101] (Configuration 6) the position of the second wiring layer in the first direction is between the position of the third wiring layer in the first direction and the positions of the plurality of semiconductor devices in the first direction; A semiconductor package as described in configuration 1, wherein the position of the first wiring layer in the first direction is between the position of the third wiring layer in the first direction and the position of the second wiring layer in the first direction.

[0102] (Configuration 7) 7. The semiconductor package of claim 6, wherein the capacitance of the second control electrode is greater than the capacitance of the first control electrode.

[0103] (Configuration 8) the first conductive member includes a first base portion and a first protrusion portion connected to the first base portion, the wiring member includes a wiring member hole, 8. The semiconductor package according to any one of configurations 1 to 7, wherein the first protrusion passes through the wiring member hole.

[0104] (Configuration 9) Further comprising a first conductive plate and a second conductive plate, the first conductive plate is located between the first protrusion and the first electrode, 9. The semiconductor package of claim 8, wherein the second conductive plate is between the second electrode and the second conductive member.

[0105] (Configuration 10) Further provided with an insulating plate, 10. The semiconductor package according to claim 8, wherein the insulating plate is provided between the first base portion and the wiring member.

[0106] (Configuration 11) the wiring member further includes a second connection portion and a fourth wiring layer, the first wiring layer further includes a third connection region; the insulating region is located between the fourth wiring layer and the third connection region in the first direction; the second connection portion extends in the insulating region along the first direction; 11. The semiconductor package according to any one of configurations 1 to 10, wherein the second connection portion electrically connects the fourth wiring layer to the third connection region.

[0107] (Configuration 12) Further comprising a fixing member, the fixing member includes a first fixing portion and a first fixing extension portion; the first fixed extension portion is connected to the first fixed portion; the fourth wiring layer, the second connection portion, and the third connection region are located between a part of the first conductive member and the first fixed portion in the first direction; the first fixed extension portion passes through the fourth wiring layer, the second connection portion, and the third connection region along the first direction; 12. The semiconductor package of claim 11, wherein the first fixed extension portion is fixed to the portion of the first conductive member.

[0108] (Configuration 13) 13. The semiconductor package of claim 12, wherein the fixing member is a screw.

[0109] (Configuration 14) 14. The semiconductor package according to any one of configurations 1 to 13, wherein the first connecting member and the second connecting member are elastic members.

[0110] (Configuration 15) one of the plurality of semiconductor devices is an IGBT, the first electrode functions as an emitter electrode; the second electrode functions as a collector electrode; 15. The semiconductor package according to any one of configurations 1 to 14, wherein the current flowing between the first electrode and the second electrode is controllable by the potential of at least one of the first control electrode and the second control electrode.

[0111] (Configuration 16) Further comprising an insulating member, the insulating member is provided around the plurality of semiconductor devices in a plane intersecting the first direction, 16. The semiconductor package of any one of configurations 1 to 15, wherein at least a portion of the insulating member is located between the first conductive member and the second conductive member.

[0112] (Configuration 17) a first terminal electrically connected to the first wiring layer; a second terminal electrically connected to the second wiring layer; a third terminal electrically connected to the third wiring layer; Furthermore, A semiconductor package as described in configuration 16, wherein at least one of the first terminal, the second terminal, and the third terminal passes through the insulating member in a direction intersecting the first direction.

[0113] (Configuration 18) In an OFF operation in which a potential of the first terminal relative to a potential of the third terminal changes from a first potential to a second potential, before a first time point of change from the first potential to the second potential, a potential of the second terminal relative to the potential of the third terminal can change from a third potential to a fourth potential; the second potential is lower than the first potential; 18. The semiconductor package of claim 17, wherein the fourth potential is lower than the third potential.

[0114] (Configuration 19) the one of the plurality of semiconductor devices includes a first conductive portion, a second conductive portion, a third conductive portion, a fourth conductive portion, and an element insulating portion; a second element direction from the third conductive portion to the fourth conductive portion intersects with a first element direction from the first conductive portion to the second conductive portion; the semiconductor member includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a fourth semiconductor region of the second conductivity type; the fourth semiconductor region is located between the first conductive portion and the first semiconductor region in the first element direction, the first semiconductor region includes a first partial region, a second partial region, a third partial region, and a fourth partial region; the first partial region is located between the fourth semiconductor region and the third conductive portion in the first element direction, the second partial region is located between the fourth semiconductor region and the fourth conductive portion in the first element direction, the third partial region is located between the first partial region and the second partial region in the second element direction, the fourth partial region is located between the third partial region and the third semiconductor region in the first element direction, the second semiconductor region is located between the fourth partial region and the third semiconductor region in the first element direction, a direction from the third conductive portion to the fourth partial region, the second semiconductor region, and the third semiconductor region is along the second element direction; the second semiconductor region is located between the third conductive portion and the fourth conductive portion in the second element direction, the first conductive portion is electrically connected to the fourth semiconductor region; the second conductive portion is electrically connected to the third semiconductor region, A semiconductor package described in any one of configurations 1 to 18, wherein the element insulating portion is provided between the semiconductor member and the third conductive portion, between the semiconductor member and the fourth conductive portion, between the third conductive portion and the second semiconductor region, and between the second semiconductor region and the fourth conductive portion.

[0115] (Configuration 20) A semiconductor package described in any one of configurations 1 to 19, wherein stress is applied to the plurality of semiconductor devices in a direction from the first conductive member to the plurality of semiconductor devices and stress is applied to the plurality of semiconductor devices in a direction from the second conductive member to the plurality of semiconductor devices. According to the embodiment, a semiconductor package that can obtain stable characteristics can be provided.

[0116] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of each element included in the semiconductor package, such as the conductive member, semiconductor device, wiring member, and connecting member, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from known ranges.

[0117] Furthermore, any combination of two or more elements of each specific example within the scope of technical feasibility is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0118] In addition, all semiconductor packages that can be implemented by a person skilled in the art by appropriately modifying the design based on the semiconductor package described above as an embodiment of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0119] In addition, within the scope of the concept of the present invention, a person skilled in the art may come up with various modifications and alterations, and it will be understood that these modifications and alterations also fall within the scope of the present invention.

[0120] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0121] 11a-11f...first to sixth semiconductor regions, 11i...element insulating portion, 15...semiconductor device, 15a, 15b...first and second control electrodes, 15i...element insulating member, 15p, 15q...first and second electrodes, 15s...semiconductor member, 20...wiring member, 20h...wiring member hole, 21-24...first to fourth wiring layers, 21f-23f...fixing member, 22a-22c...first to third connection regions, 23h...second wiring layer hole, 25i...insulating region, 27a-27c...first to third connection portions, 28...fixing member, 28p...first fixed portion, 28e...first fixed extension portion, 31, 32...first and second connection member, 35a, 35b...first and second conductive plates, 45...insulating plate, 51-54...first to fifth conductive portions, 61, 62...first and second conductive members, 61b...first base portion, 61p...first convex portion, 65...insulating member, 81, 82...first and second plates, 83...fixing member, 84...cooling fin, 85, 86...insulator, 87...spring, 110-114, 120...semiconductor package, D1, D2...first and second directions, De1-De3...first to third element directions, L1-L3, Lg1, Lg2...parasitic inductance, T1-T3...first to third terminals, V1-V4...first to fourth potentials, Vc1, Vc2...potential, f1, f2...first and second surfaces, r1-r4...first to fourth partial regions, t1...first time, tm...time

Claims

1. a first conductive member; A second conductive member; a plurality of semiconductor devices provided between the first conductive member and the second conductive member, one of the plurality of semiconductor devices including a semiconductor member, a first electrode provided between the first conductive member and the semiconductor member, a first control electrode provided between the first conductive member and the semiconductor member, a second control electrode provided between the first conductive member and the semiconductor member, and a second electrode provided between the semiconductor member and the second conductive member, the first conductive member being electrically connected to the first electrode, the second conductive member being electrically connected to the second electrode, and a direction from the second control electrode to the first control electrode intersecting a first direction from the first conductive member to the second conductive member; a wiring member including a first wiring layer, a second wiring layer, a third wiring layer, and an insulating region, a direction from the first wiring layer to the second wiring layer and a direction from the first wiring layer to the third wiring layer are along the first direction, at least a part of the insulating region is between the first wiring layer and the third wiring layer and between the third wiring layer and the second wiring layer, a position of the second wiring layer in the first direction is between a position of the insulating region in the first direction and a position of the plurality of semiconductor devices in the first direction, the second wiring layer includes a first connection region and a second connection region, the first connection region is electrically connected to the first wiring layer, and the third wiring layer is electrically connected to the first conductive member; a first connection member provided between the first connection region and the first control electrode, the first connection member electrically connecting the first connection region to the first control electrode; a second connection member provided between the second connection region and the second control electrode, the second connection member electrically connecting the second connection region to the second control electrode; A semiconductor package comprising:

2. the position of the second wiring layer in the first direction is between the position of the first wiring layer in the first direction and the positions of the plurality of semiconductor devices in the first direction; 2. The semiconductor package of claim 1, wherein the position of the third wiring layer in the first direction is between the position of the first wiring layer in the first direction and the position of the second wiring layer in the first direction.

3. 3. The semiconductor package of claim 2, wherein the distance along the first direction between the first wiring layer and the third wiring layer is 0.3 times or more and 3.0 times or less the distance along the first direction between the third wiring layer and the second wiring layer.

4. the wiring member further includes a first connection portion, the first connection portion electrically connects the first wiring layer to the first connection region; The semiconductor package according to claim 2 , wherein at least a portion of the first connection portion extends in the first direction through the insulating region.

5. the third wiring layer includes a third wiring layer hole; The semiconductor package according to claim 4 , wherein the first connection portion passes through the third wiring layer hole.

6. the position of the second wiring layer in the first direction is between the position of the third wiring layer in the first direction and the positions of the plurality of semiconductor devices in the first direction; 2. The semiconductor package of claim 1, wherein the position of the first wiring layer in the first direction is between the position of the third wiring layer in the first direction and the position of the second wiring layer in the first direction.

7. The semiconductor package according to claim 6 , wherein the capacitance of the second control electrode is greater than the capacitance of the first control electrode.

8. the first conductive member includes a first base portion and a first protrusion portion connected to the first base portion, the wiring member includes a wiring member hole, The semiconductor package according to claim 1 , wherein the first protrusion passes through the wiring member hole.

9. further comprising a first conductive plate and a second conductive plate; the first conductive plate is located between the first protrusion and the first electrode, The semiconductor package of claim 8 , wherein the second conductive plate is between the second electrode and the second conductive member.

10. Further provided with an insulating plate, The semiconductor package according to claim 8 , wherein the insulating plate is provided between the first base portion and the wiring member.

11. the wiring member further includes a second connection portion and a fourth wiring layer, the first wiring layer further includes a third connection region; the insulating region is located between the fourth wiring layer and the third connection region in the first direction; the second connection portion extends in the insulating region along the first direction; The semiconductor package according to claim 1 , wherein the second connection portion electrically connects the fourth wiring layer to the third connection region.

12. Further comprising a fixing member, the fixing member includes a first fixing portion and a first fixing extension portion; the first fixed extension portion is connected to the first fixed portion; the fourth wiring layer, the second connection portion, and the third connection region are located between a part of the first conductive member and the first fixed portion in the first direction; the first fixed extension portion passes through the fourth wiring layer, the second connection portion, and the third connection region along the first direction; The semiconductor package of claim 11 , wherein the first fixed extension is fixed to the portion of the first conductive member.

13. The semiconductor package according to claim 12 , wherein the fixing member is a screw.

14. The semiconductor package according to claim 1 , wherein the first connecting member and the second connecting member are elastic members.

15. the one of the plurality of semiconductor devices is an IGBT, the first electrode functions as an emitter electrode; the second electrode functions as a collector electrode; 2. The semiconductor package according to claim 1, wherein the current flowing between the first electrode and the second electrode is controllable by the potential of at least one of the first control electrode and the second control electrode.

16. Further comprising an insulating member, the insulating member is provided around the plurality of semiconductor devices in a plane intersecting the first direction, The semiconductor package according to claim 1 , wherein at least a portion of the insulating member is between the first conductive member and the second conductive member.

17. a first terminal electrically connected to the first wiring layer; a second terminal electrically connected to the second wiring layer; a third terminal electrically connected to the third wiring layer; Furthermore, The semiconductor package according to claim 16 , wherein at least one of the first terminal, the second terminal, and the third terminal passes through the insulating member in a direction intersecting the first direction.

18. In an OFF operation in which a potential of the first terminal relative to a potential of the third terminal changes from a first potential to a second potential, the potential of the second terminal relative to the potential of the third terminal can change from a third potential to a fourth potential before a first time point of change from the first potential to the second potential; the second potential is lower than the first potential; 18. The semiconductor package of claim 17, wherein the fourth potential is lower than the third potential.

19. the one of the plurality of semiconductor devices includes a first conductive portion, a second conductive portion, a third conductive portion, a fourth conductive portion, and an element insulating portion; a second element direction from the third conductive portion to the fourth conductive portion intersects with a first element direction from the first conductive portion to the second conductive portion; The semiconductor member includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a fourth semiconductor region of the second conductivity type, the fourth semiconductor region is located between the first conductive portion and the first semiconductor region in the first element direction, the first semiconductor region includes a first partial region, a second partial region, a third partial region, and a fourth partial region; the first partial region is located between the fourth semiconductor region and the third conductive portion in the first element direction, the second partial region is located between the fourth semiconductor region and the fourth conductive portion in the first element direction, the third partial region is located between the first partial region and the second partial region in the second element direction, the fourth partial region is located between the third partial region and the third semiconductor region in the first element direction, the second semiconductor region is located between the fourth partial region and the third semiconductor region in the first element direction, a direction from the third conductive portion to the fourth partial region, the second semiconductor region, and the third semiconductor region is along the second element direction; the second semiconductor region is located between the third conductive portion and the fourth conductive portion in the second element direction, the first conductive portion is electrically connected to the fourth semiconductor region; the second conductive portion is electrically connected to the third semiconductor region; A semiconductor package according to any one of claims 1 to 18, wherein the element insulating portion is provided between the semiconductor member and the third conductive portion, between the semiconductor member and the fourth conductive portion, between the third conductive portion and the second semiconductor region, and between the second semiconductor region and the fourth conductive portion.

20. 2. The semiconductor package according to claim 1, wherein stress is applied to the semiconductor devices in a direction from the first conductive member to the semiconductor devices and a direction from the second conductive member to the semiconductor devices.

Images