Synchronization of RF pulsing schemes and synchronization of sensor data acquisition

Abstract

Systems and methods for synchronizing radio frequency (RF) pulsing schemes and synchronizing sensor data collection are described. One method includes receiving, by an RF generator, a first set of one or more variable levels and one or more duty cycles of an RF signal. The method further includes receiving, by the RF generator, a synchronization signal having a plurality of pulses from a pulse controller. The method also includes generating, during clock cycles of the clock signal, multiple instances of a first plurality of states of the RF signal in synchronization with the multiple pulses of the synchronization signal. Each of the first plurality of states of the RF signal has a corresponding one of the first set of one or more variable levels and a corresponding one of the first set of one or more duty cycles.

Description

[Technical Field]

[0001] The present embodiments relate to systems and methods for synchronizing radio frequency (RF) pulsing schemes and synchronizing sensor data collection. [Background technology]

[0002] The background art description provided herein is intended to provide a general context for the present disclosure. Work by the presently named inventors, to the extent described in this background art section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure.

[0003] Plasma tools use multiple radio frequency (RF) generators. The RF generators are connected to the plasma chamber through matches. The RF generators generate RF signals and feed them into the matches. The RF signals are combined to produce a modified RF signal that is sent to the plasma chamber.

[0004] A substrate is placed in a plasma chamber for processing, and modified signals are supplied along with various gases to process the substrate, preferably to process the substrate in a desired manner.

[0005] It is in this context that the embodiments described in this disclosure arise. Summary of the Invention

[0006]

[0006] Embodiments of the present disclosure provide systems, apparatus, methods, and computer programs for synchronizing radio frequency (RF) pulsing schemes and synchronizing sensor data collection. It should be appreciated that the embodiments can be implemented in numerous ways, such as a process, an apparatus, a system, a device, or a method on a computer-readable medium. Several embodiments are described below.

[0007] In some RF pulsing implementations for plasma etch tools, a set of parameter values, such as power values, and durations of several parameter levels are downloaded to an RF generator. RF pulses are generated by the RF generator according to the power values ​​and durations. Upon receiving or internally generating a trigger pulse, the RF generator emits RF energy at a number of variable levels and durations. The RF generator may also receive a number of other parameter values ​​to improve the degree to which the RF power values ​​delivered during the variable levels match the pre-stored power values.

[0008] When multiple RF generators are present in a plasma system, it is desirable for the RF generators to emit RF signals on a synchronized schedule. As an example, this can be achieved by providing logic-level synchronization pulses to each RF generator. The logic-level synchronization pulses are delivered to the RF generators with the same timing parameters, such as frequency, duty cycle, and phase. To change the pulsing behavior of the RF generators, setpoints are updated with respect to the timing and power level of the pulses of the RF signal. The module controller can be used to perform setpoint updates and send the updates to the RF generators via a fieldbus. Because the module controller is responsible for so many other real-time control functions of the plasma system, it is difficult for the module controller to update setpoints at precise times on a timescale of less than about 0.5 seconds.

[0009] An advantageous process exists when the setpoints are updated as frequently as every 50 milliseconds. As an example, to execute a process, an embedded recipe can be downloaded and executed by each of the RF generators. The recipe can include extensive specifications for pulse level, width, and number of pulses to be emitted and can be downloaded to the RF generators. However, synchronization between steps of these recipes may not occur. That is, a recipe for one of the RF generators may need to start at a different time than a recipe for another RF generator, or changes in the pulse level of an RF signal generated by one of the RF generators should be synchronized with changes in the pulse level of another RF signal generated by another RF generator. To achieve synchronization between steps, synchronization cables can be added between the RF generators corresponding to each desired synchronized change, but this results in a rather complex plasma system that is difficult to configure and program. Furthermore, synchronization with subsystems such as measurement subsystems for endpoint detection or RF waveform analysis is difficult.

[0010] In one embodiment, a centralized synchronization device for an RF pulsing scheme is described. An example of a centralized synchronization device is a pulse controller. The centralized synchronization device allows for repeated changes in pulsing parameter values ​​on a time scale of less than about 0.5 seconds. For example, the centralized synchronization device allows for changes in pulsing parameter values ​​on a time scale between 0.1 seconds and 0.5 seconds. As another example, the centralized synchronization device allows for changes in pulsing parameter values ​​on a time scale between 0.05 seconds and 0.6 seconds.

[0011] In one embodiment, pulsing parameter value changes are achieved by direct slave-to-slave transfer using the plasma tool's existing control network, such as Fieldbus. In one embodiment, pulsing parameter value updates are achieved using a separate high-speed point-to-point communication link, such as an Ethernet cable or a high-speed Ethernet cable, or a direct system-on-chip to system-on-chip (SoC-to-SoC) link. For example, a main SoC is used to implement the pulse controller. The main SoC is directly connected to the RFG controller of the RF generator via a separate high-speed point-to-point communication link, such as a cable or optical fiber. The RFG controller includes at least one of a communication controller, a digital signal processor (DSP), one or more power controllers, and one or more frequency controllers. The cable or optical fiber is a transmission medium for transferring pulsing parameter value updates. A protocol is applied by the pulse controller to transfer the updated values ​​to the RFG controller. Communication of pulsing parameter values ​​is sometimes referred to herein as inter-central processing unit (CPU-to-CPU) communication. As another example, the pulse controller is connected to the match controller or directly to the sensor system controller via a separate high-speed point-to-point communication link, such as a cable or optical fiber. The match controller includes at least one of a communications controller and a processor. The sensor system controller also includes at least one of a communications controller and a processor. In this example, a protocol is applied by the pulse controller to forward updates to the match or sensor system controller.

[0012] In one embodiment, the systems and methods described herein include a measurement function that parameterizes an RF signal and compares an RF signal seen at a point in the RF delivery system of a plasma tool to pre-stored parameter values. For example, the envelope or pulses of the measured signal are compared to the pre-stored envelope. In this example, the results of the comparison can be used to update control parameters to optimize the match between the measured signal and the pre-stored parameter values.

[0013] In one embodiment, a pulse controller, a centralized controller separate from the module controllers, is used to send setpoint changes to the RF generators and issue a separate synchronization pulse train to the RF generators for synchronization. Setpoint changes to the RF generators are divided into two classes. The first of the two classes contains per-step parameter values ​​that do not change during a recipe step, which are programmed in the system recipe editor and sent over the fieldbus at the start of each step. The second of the two classes contains high-speed information, such as a smaller number of other parameter values, which are sent over the data channel with lower latency.

[0014] In the case of an RF generator, the lower latency data channel contains the variable level and duration of the pulse of the RF signal emitted upon receiving a synchronization signal. The RF generator does not use higher-level downloaded recipes. The latency of these lower latency data channels allows setpoint changes to be transmitted and actuated in less than the minimum pulse repetition time. For example, at a pulse repetition rate of 10 milliseconds (ms), a latency of less than 10 ms is achieved. This lower latency is achieved in one embodiment by transmitting data over a fieldbus using slave-to-slave technology and with optimizations within the RF generator to enable lower latency. In some cases, instead of slave-to-slave technology, a completely separate data transmission, such as point-to-point communication, is provided for high-speed information. For example, the data connection uses a protocol over a 1 gigabit per second (Gbps) Ethernet physical link in a point-to-point configuration. Other, more customized implementations using direct point-to-point links between processors can achieve low latency, such as less than 10 microseconds (μs), with connections up to 25 Gbps.

[0015] While the term RF generator is used herein for convenience, it should be noted that any subsystem that uses updates synchronized with an embedded recipe can be updated in a similar manner. In one embodiment, synchronization of individual pulses is achieved by issuing a pulse train to each of multiple subsystems for synchronization of the subsystems. For example, an optical emission spectrometer subsystem receives a synchronization pulse that triggers optical data collection when the synchronization pulse is at a particular logic level. Other subsystems use the rising or falling edge of the synchronization pulse signal to trigger a series of actions. Other synchronized subsystems include RF matching units, such as impedance matching circuits. Setpoint changes and pulse trains are issued by the pulse controller on a schedule derived from a recipe sent to the pulse controller via fieldbus. The recipe is changed in conjunction with new system recipe steps.

[0016] In one embodiment, the pulse controller includes instrumentation for evaluation of the RF signal reaching a physically significant point within the plasma tool, such as the RF match output or a location near the wafer plane. An analog-to-digital converter is used to measure either the RF voltage or the RF voltage envelope at that point. The pulse controller can determine in real time whether a match between the measured criteria and pre-stored criteria has been achieved. These criteria can be used to modify plasma tool parameters. For example, the settings of the RF match network components or the RF generator frequency can be modified to achieve a match, such as using a feedback loop or an artificial intelligence system. Matching can also be applied to other Equipment Intelligence systems. Other features related to human-level debugging of the plasma tool, such as capturing RF voltages for display, can also be included.

[0017] In one embodiment, a method is described. The method includes receiving, by an RF generator, a first set of one or more variable levels and one or more duty cycles of an RF signal. The method further includes receiving, by the RF generator, a synchronization signal having a plurality of pulses from a pulse controller. The method also includes generating, during clock cycles of the clock signal, a plurality of instances of the first plurality of states of the RF signal synchronously with the plurality of pulses of the synchronization signal. Each of the first plurality of states of the RF signal has a corresponding one of the first set of one or more variable levels and a corresponding one of the first set of one or more duty cycles.

[0018] In one embodiment, a pulse controller is described. The pulse controller includes a processor configured to transmit a first set of one or more variable levels and one or more duty cycles of an RF signal to an RF generator. The processor is configured to transmit a synchronization signal having a plurality of pulses to the RF generator. The synchronization signal transmits to the RF generator to enable the RF generator to generate multiple instances of a first plurality of states of the RF signal in synchronization with the multiple pulses of the synchronization signal during clock cycles of the clock signal. Each of the first plurality of states of the RF signal has a corresponding one of the one or more variable levels of the first set and a corresponding one of the one or more duty cycles of the first set. The pulse controller further includes a memory device connected to the processor.

[0019] In one embodiment, a method is described. The method includes measuring sensor data by a sensor of a sensor system. The method further includes receiving, by the sensor system, a synchronization signal having a plurality of pulses. The method also includes collecting, by the sensor system, portions of the sensor data synchronously with the plurality of pulses of the synchronization signal during clock cycles of a clock signal. The method includes transmitting the portions of the sensor data to a pulse controller.

[0020] Some advantages of the systems and methods described herein include co-locating a centralized synchronization device for pulse synchronization, pulse measurement, and setpoint updates. There is no need to download a recipe to the RF generators and then find a way to synchronize the RF generators. Detailed pulsing behavior can then be programmed with shorter and more precise process steps. RF generator requirements are reduced, resulting in cost advantages.

[0021] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0022] The present disclosure will be best understood by referring to the following description taken in conjunction with the accompanying drawings.

[0023] [Figure 1] FIG. 1 is a diagram of one embodiment of a system to illustrate the use of Ethernet for Control Automation Technology (EtherCAT) and synchronization signals for synchronization of RF signals.

[0024] [Figure 2A] FIG. 2A shows a graph to illustrate a first synchronization signal transmitted to a transformer coupled plasma (TCP) generator.

[0025] [Figure 2B] FIG. 2B shows a graph of another synchronization signal provided to the first bias generator.

[0026] [Figure 2C] FIG. 2C shows a graph of yet another synchronization signal provided to the second bias generator.

[0027] [Figure 2D] FIG. 2D shows a graph to illustrate the variation of the RF signal generated by the TCP generator in synchronization with the synchronization signal of FIG. 2A.

[0028] [Figure 2E] FIG. 2E shows a graph to illustrate the variation of the RF signal generated by the first bias generator in synchronization with the synchronization signal of FIG. 2B.

[0029] [Figure 2F] FIG. 2F shows a graph to illustrate the variation of the RF signal generated by the second bias generator in synchronization with the synchronization signal of FIG. 2C.

[0030] [Figure 2G] FIG. 2G shows a graph to illustrate the variation of the RF signal generated by the first bias generator in synchronization with the synchronization signal of FIG. 2B.

[0031] [Figure 3] FIG. 3 is one embodiment of a system to illustrate the use of an Ethernet cable to transfer information regarding variable levels and duty cycles, and information regarding the fraction of a cycle of a master clock signal over which multiple states of an RF signal are generated.

[0032] [Figure 4] FIG. 4 is a diagram of one embodiment of a system to illustrate the use of EtherCAT to sense data from sensors in a TCP match and sensors in a bias match.

[0033] [Figure 5A] FIG. 5A shows a graph to illustrate a plot of plasma intensity versus time.

[0034] [Figure 5B] FIG. 5B shows a graph to illustrate the synchronization signal versus time.

[0035] [Figure 6A] FIG. 6A shows a graph to illustrate a plot of voltage versus time.

[0036] [Figure 6B] FIG. 6B shows a graph to illustrate the synchronization signal versus time.

[0037] [Figure 6C] FIG. 6C shows a graph to illustrate a plot of voltage versus time.

[0038] [Figure 6D] FIG. 6D shows a graph to illustrate the synchronization signal versus time.

[0039] [Figure 7] FIG. 7 is a diagram of one embodiment of a system to illustrate the use of one EtherCAT train instead of multiple EtherCAT trains to transfer pulsed preset signals from the module controller to the bias match.

[0040] [Figure 8] FIG. 8 is a diagram of one embodiment of a system to illustrate that sensor data is transmitted from the sensor to the pulse controller over an Ethernet cable rather than over an EtherCAT train.

[0041] [Figure 9] FIG. 9 is a diagram of one embodiment of an RF generator to illustrate the components of the RF generator.

[0042] [Figure 10] FIG. 10 is a diagram of one embodiment of a controller, which is an example of a pulse controller or a module controller.

[0043] [Figure 11] FIG. 11 is a diagram of one embodiment of a match, where the match is an example of a TCP match or a biased match.

[0044] [Figure 12]FIG. 12 is a diagram of one embodiment of a sensor system.

[0045] [Figure 13] FIG. 13 shows a graph to illustrate the clock signal. DETAILED DESCRIPTION OF THE INVENTION

[0046] The following embodiments describe systems and methods for synchronizing radio frequency (RF) pulsing schemes and synchronizing sensor data collection. It will be apparent that the embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the embodiments.

[0047] Figure 1 shows a transformer join FIG. 1 is a diagram of one embodiment of a system 100 illustrating the use of Ethernet for Control Automation Technology (EtherCAT) and synchronization signals for synchronization of RF signals 102, 104, and 106 generated by multiple RF generators, such as a plasma (TCP) generator, bias generator 1, and bias generator 2. The system 100 includes a module controller, a pulse controller, a TCP generator, bias generator 1, bias generator 2, a TCP match, a bias match, and a plasma chamber 108.

[0048] As used herein, one example of a controller includes a processor and a memory device. The processor is connected to the memory device. Another example of a controller includes an application specific integrated circuit (ASIC) and a programmable logic device (PLD). Another example of a controller includes multiple processors and multiple memory devices. The processor is connected to the memory device. As used herein, the terms processor, microprocessor, and central processing unit (CPU) are used interchangeably herein.

[0049] Also, as used herein, an RF generator operates at a frequency of 400 kilohertz (kHz), 2 megahertz (MHz), 13.56 MHz, 27 MHz, or 60 MHz. For example, the TCP generator operates at a frequency of 13.56 MHz, bias generator 1 operates at a frequency of 400 kHz, and bias generator 2 operates at a frequency of 60 MHz. As another example, the TCP generator operates at a frequency of 27 MHz, bias generator 1 operates at a frequency of 2 MHz, and bias generator 2 operates at a frequency of 27 MHz.

[0050] An example of an impedance matching network used herein is an impedance matching circuit having a network of circuit components such as inductors, resistors, and capacitors. For example, the impedance matching network includes one or more series circuits and one or more shunts. Each series circuit includes one or more inductors and one or more capacitors, and the one or more inductors and one or more capacitors are connected in series with each other. Similarly, each shunt includes one or more inductors and one or more capacitors connected in series with each other. One of the one or more inductors and one or more capacitors of the shunt is connected to ground potential. Each of the one or more shunts is connected to a corresponding one of the one or more series circuits. The terms impedance matching network, impedance matching circuit, impedance matching housing, match housing, match enclosure, and match are used interchangeably herein.

[0051] The plasma chamber 108 includes a substrate support 110. An example of the substrate support 110 is a chuck, such as an electrostatic chuck (ESC). For example, the chuck includes a metal base and a dielectric layer on the metal base. A substrate S, such as a semiconductor wafer, is placed on the upper surface of the substrate support 110 and processed in the plasma chamber 108. The substrate support 110 includes a lower electrode made of a metal, such as aluminum or an aluminum alloy. The lower electrode is embedded in the dielectric layer of the chuck. The plasma chamber 108 further includes a TCP coil 112 and a dielectric window 114. The TCP coil 112 is disposed on the dielectric window 114, and a gap is formed between the dielectric window 114 and the substrate support 110.

[0052] The module controller is connected to the pulse controller via communication cable 116, and the pulse controller is connected to the TCP generator via communication cable 118. An example of a communication cable used herein is an Ethernet cable. An example of an Ethernet cable used herein is a twisted pair cable. By way of example, an Ethernet cable is a 100BASE-TX™ or 100BASE-T4™ cable capable of transferring data at speeds of 100 Megabits per second (Mbps) or greater. As another example, an Ethernet cable is a Category 8 cable capable of transferring data at speeds of up to 40 Gigabits per second (Gbps).

[0053] In addition, the pulse controller uses a transfer cable 120 1 to the TCP generator via a communication cable 126, to bias generator 1 via a transfer cable 122, and to bias generator 2 via a transfer cable 124. An example of a transfer cable used herein is a coaxial cable. Illustratively, transfer cables are used to transfer data via serial, parallel, or Universal Serial Bus (USB) protocols. The TCP generator is connected to bias generator 1 via a communication cable 126, and bias generator 1 is connected to bias generator 2 via a communication cable 128.

[0054] Also, the output O1 of the TCP generator is connected to the input I1 of the TCP match via an RF cable 130, and the output O2 of the TCP match is connected to a first end of the TCP coil 112 via an RF transmission line 132. As an example, the RF transmission line 132 includes an RF rod, an insulating material, and an RF sheath. The insulating material is disposed between the RF rod and the RF sheath. The insulating material surrounds the RF rod, and the RF sheath surrounds the insulating material.

[0055] The second opposite end of the TCP coil is connected to ground potential or a ground connection. The output O3 of the bias generator 1 is connected to the bias match input I2 via an RF cable 134. The output O4 of the bias generator 2 is connected to the bias match input I3 via an RF cable 136. The bias match output O5 is connected to the lower electrode of the substrate support 110 via an RF transmission line 139. As an example, the RF transmission line 139 includes an RF rod, an insulating material, and an RF sheath. The insulating material is disposed between the RF rod and the RF sheath. The insulating material of the RF transmission line 139 surrounds the RF rod of the RF transmission line 139, and the RF sheath of the RF transmission line 139 surrounds the insulating material. The RF transmission line 139 further includes one or more RF straps and an RF cylinder. The RF rod of the RF transmission line 139 is connected to the bias match output O5. One or more RF straps of the RF transmission line 139 connect the RF rod to the RF cylinder, which is connected to the bottom electrode of the substrate support 110 .

[0056] The module controller generates a pulsed preset signal 138 and transmits the pulsed preset signal 138 to the pulse controller via the communication cable 116. The pulsed preset signal 138 is an EtherCAT train. As an example, the pulsed preset signal 138 includes information regarding the variable levels and duty cycles of the RF signals 102, 104, and 106. The information regarding the variable levels includes the variable level for each state of the RF signal 102, the variable level for each state of the RF signal 104, and the variable level for each state of the RF signal 106. Illustratively, the variables are power or frequency. Also, in this example, the information regarding the duty cycle includes the duty cycle for each state of the variable of the RF signal 102, the duty cycle for each state of the variable of the RF signal 104, and the duty cycle for each state of the variable of the RF signal 106. Illustratively, the duty cycle of the RF signal provides a time interval or period during which each state of the variable of the RF signal is generated.

[0057] The pulse controller receives a pulsed preset signal 138 from the module controller and transmits the pulsed preset signal 138 to the TCP generator via communication cable 118. The TCP generator receives the pulsed preset signal 138, extracts information about variable levels and duty cycles for generating the RF signal 102 from the pulsed preset signal 138, and transmits the pulsed preset signal 138 to the bias generator 1 via communication cable 126 after extracting the information. The TCP generator also stores the information about variable levels and duty cycles for generating the RF signal 102 in one or more memory devices of the TCP generator.

[0058] The bias generator 1 receives the pulsed preset signal 138 and analyzes the pulsed preset signal 138 to obtain information about the variable levels and duty cycles for generating the RF signal 104. The bias generator 1 also stores the information about the variable levels and duty cycles for generating the RF signal 104 in one or more memory devices of the bias generator 1. After obtaining the information, the bias generator 1 transmits the pulsed preset signal 138 to the bias generator 2 via the communication cable 128.

[0059] The bias generator 2 receives the pulsed preset signal 138 and analyzes the pulsed preset signal 138 to extract information about variable levels and duty cycles for generating the RF signal 106 from the pulsed preset signal 138. The bias generator 2 stores the information about variable levels and duty cycles for generating the RF signal 106 in one or more memory devices of the bias generator 2. After extracting the information, the bias generator 2 sends the pulsed preset signal 138 back to the bias generator 1 via the communication cable 128.

[0060] Bias generator 1 receives a pulsed preset signal 138 from bias generator 2 and sends the pulsed preset signal 138 back to the TCP generator via communication cable 126. The TCP generator receives a pulsed preset signal 138 from bias generator 1 and sends the pulsed preset signal 138 back to the pulse controller via communication cable 118. The pulse controller receives a pulsed preset signal 138 from the TCP generator and sends the pulsed preset signal 138 back to the module controller.

[0061] The pulse controller also generates a master clock signal 141 and transmits it to the TCP generator via transmission cable 120. Illustratively, the pulse controller includes a master clock generator, such as a clock source or a digital clock, and generates a digital clock signal. The digital clock signal pulses between logic levels 1 and 0 with a 50% duty cycle. The pulse controller also transmits the master clock signal 141 to bias generator 1 via transmission cable 122 and to bias generator 2 via transmission cable 124.

[0062] The pulse controller generates a synchronization signal 140 and transmits it to the TCP generator via the transmission cable 120. An example of a synchronization signal used herein is a transistor-transistor logic (TTL) signal. The pulse controller also generates another synchronization signal 142 and transmits it to the bias generator 1 via the transmission cable 122. The pulse controller also generates another synchronization signal 144 and transmits it to the bias generator 2 via the transmission cable 124. The synchronization signal 140 is labeled as sync1 in FIG. 1, the synchronization signal 142 is labeled as sync2 in FIG. 1, and the synchronization signal 144 is labeled as sync3 in FIG. 1.

[0063] As an example, synchronization signal 144 includes one or more pulses having a frequency that is different from the frequency of one or more pulses of synchronization signal 142. Illustratively, synchronization signal 144 has two consecutive pulses that are spaced apart by a larger time interval compared to two consecutive pulses of synchronization signal 142. Similarly, as another example, synchronization signal 140 includes one or more pulses having a frequency that is different from the frequency of one or more pulses of synchronization signal 142. 140 includes one or more pulses having a frequency that is different from the frequency of one or more pulses of synchronization signal 144.

[0064] Additionally, by way of example, synchronization signal 144 may include a different number of pulses, e.g., a greater or lesser number, compared to the number of pulses in synchronization signal 142. For example, within one time interval, synchronization signal 144 may include 10 pulses, while synchronization signal 142 may include 4 pulses. As another example, within one time interval, synchronization signal 144 may include 5 pulses, while synchronization signal 142 may include 10 pulses. Similarly, by way of example, synchronization signal 144 may include a different number of pulses, e.g., a greater or lesser number, compared to the number of pulses in synchronization signal 140. Also, by way of example, synchronization signal 144 may include a different number of pulses, e.g., a greater or lesser number, compared to the number of pulses in synchronization signal 142.

[0065] As an example, after information regarding the variable level and duty cycle of RF signal 102 is stored in one or more memory devices of the TCP generator, information regarding the variable level and duty cycle of RF signal 104 is stored in one or more memory devices of bias generator 1, and information regarding the variable level and duty cycle of RF signal 106 is stored in one or more memory devices of bias generator 2, synchronization signals 140, 142, and 144 are generated and transmitted.

[0066] As an example, the pulse controller transmits synchronization signals 140, 142, and 144 in synchronization with the clock cycles of the master clock signal 141. Each of the synchronization signals 140, 142, and 144 has a series of pulses that are repeated during each cycle of the master clock signal 141. In this example, the pulsed preset signal 138 includes information regarding a portion of a cycle of the master clock signal 141 during which multiple states of the RF signal are generated. For example, the pulsed preset signal 138 includes a first time interval during cycle 1 of the master clock signal 141 during which a first series of pulses of the RF signal 102 are generated by the TCP generator. During cycle 1, each of the pulses in the first series transitions between a first variable level and a second variable level. The first variable level is different from the second variable level. The pulsed preset signal 138 also includes a second time interval during cycle 1 of the master clock signal during which a second series of pulses of the RF signal 102 are generated by the TCP generator. During cycle 1, each of the pulses in the second series transitions between a third variable level and the second variable level, the third variable level being different from the second variable level and the first variable level. The first time interval is an example of a first sub-cycle of cycle 1 of master clock signal 141, and the second time interval is an example of a second sub-cycle of cycle 1 of master clock signal 141.

[0067] As another example, the pulsed preset signal 138 includes information regarding a count of pulses of the synchronization signal 140. The information regarding the count of pulses includes a first count of the number of pulses of the synchronization signal 140 during cycle 1 of the master clock signal 141 in which a first series of pulses of the RF signal 102 transition between a first variable level and a second variable level. The information regarding the count also includes a second count of the number of pulses of the synchronization signal 140 during cycle 1 of the master clock signal 141 in which a second series of pulses of the RF signal 102 transition between a third variable level and the second variable level. The first count number of pulses is generated during a first time interval, which is an example of a first sub-cycle of cycle 1 of the master clock signal 141. The second count number of pulses is generated during a second time interval, which is an example of a second sub-cycle of cycle 1 of the master clock signal 141. The TCP generator includes a counter that determines whether the first count has been exceeded, and if so, applies second and third variable levels instead of applying the first and second variable levels to generate the RF signal 102. The counter is connected to the digital signal processor of the TCP generator.

[0068] The TCP generator receives the synchronization signal 140 and synchronizes with the synchronization signal 140 to generate the RF signal 102 having information about the variable levels and duty cycles of each state of the RF signal 102. For example, a first instance of a set of one or more states of the variables of the RF signal 102 is generated in response to receiving a first pulse of the synchronization signal 140, and a second instance of the set of one or more states of the variables of the RF signal 102 is generated in response to a second pulse of the synchronization signal 140. The second pulse is consecutive to the first pulse in that there is no other pulse between the first and second pulses. Illustratively, the set of states includes a first state and a second state. The first state has a first variable level and a first duty cycle, and the second state has a second variable level and a second duty cycle. The information about the variable levels and duty cycles of the RF signal 102 includes a first variable level, a first duty cycle, a second variable level, and a second duty cycle.

[0069] Similarly, bias generator 1 receives synchronization signal 142 and synchronizes with synchronization signal 142 to generate RF signal 104 having information about the variable level and duty cycle of each state of RF signal 104. Bias generator 2 also receives synchronization signal 144 and synchronizes with synchronization signal 144 to generate RF signal 106 having information about the variable level and duty cycle of each state of RF signal 106.

[0070] An RF signal 102 is provided at output O1 and transmitted to input I1 of the TCP match via RF cable 130. The TCP match modifies the impedance of the RF signal 102 by matching the impedance of a load connected to output O2 with the impedance of a source connected to input I1. Examples of sources connected to input I1 include RF cable 130 and a TCP generator. Examples of loads connected to output O2 include an RF transmission line 132 and a plasma chamber 108. Once the impedance of the RF signal 102 is modified, a modified RF signal 146 is provided at output O2 of the TCP match. Modified RF signal 146is supplied to the TCP coil 112 via an RF transmission line 132.

[0071] Additionally, RF signal 104 is provided at output O3 of bias generator 1 and transmitted to input I2 of the bias match via RF cable 134. Additionally, RF signal 106 is provided at output O4 of bias generator 2 and transmitted to input I3 of the bias match via RF cable 136. The bias match includes a first branch circuit and a second branch circuit. The first branch circuit includes one or more series circuits, one or more shunt circuits, or a combination thereof. Additionally, the second branch circuit includes one or more series circuits, one or more shunt circuits, or a combination thereof.

[0072] When the RF signal 104 is transferred through the first branch of the bias match, the first branch matches the impedance of a load connected to the output O5 of the bias match with the impedance of a source connected to the input I2 of the bias match to modify the impedance of the RF signal 104. An example of a source connected to the input I2 is the RF cable 134 and the bias generator 1. An example of a load connected to the output O5 is the RF transmission line 139 and the plasma chamber 108. Once the impedance of the RF signal 104 is modified, a first modified RF signal is output from the first branch.

[0073] Similarly, when the RF signal 106 is routed through the second branch of the bias match, the second branch matches the impedance of a load connected to the output O5 of the bias match with the impedance of a source connected to the input I3 of the bias match, thereby modifying the impedance of the RF signal 106. An example of a source connected to input I3 is the RF cable 136 and the bias generator 2. Once the impedance of the RF signal 106 is modified, a second modified RF signal is output from the second branch.

[0074] The first and second modified RF signals are combined, e.g., added, within the bias match to provide a combined RF signal 148 at output O5. The combined RF signal 148 is transferred via RF transmission line 139 to the lower electrode of the substrate support 110.

[0075] Additionally, one or more process gases, such as an oxygen-containing gas and a fluorine-containing gas, are supplied to the gap between the substrate support 110 and the dielectric window 114. When the one or more process gases, the modified RF signal 146, and the combined RF signal 148 are supplied to the gap in the plasma chamber 108, a plasma is struck or maintained in the plasma chamber 108. The plasma is used to process the substrate S. Examples of processing the substrate S include depositing one or more materials on the substrate S, etching the substrate S, cleaning the substrate S, polishing the substrate S, sputtering the substrate S, or combinations thereof.

[0076] Providing synchronization signals 140, 142, and 144 eliminates the need to store information about the synchronization signals. For example, the frequency at which the state of RF signal 102 is repeated does not need to be stored in one or more memory devices of TCP generator. As another example, the frequency at which the state of RF signal 104 is repeated does not need to be stored in one or more memory devices of bias generator 1. Also, as an example, the frequency at which the state of RF signal 106 is repeated does not need to be stored in one or more memory devices of bias generator 2.

[0077] In one embodiment, in addition to bias generators 1 and 2, a third bias generator is connected to the third input of the bias match.

[0078] In one embodiment, in addition to the TCP generator, a second TCP generator is connected to a second input of the TCP match.

[0079] In one embodiment, in addition to the TCP generator, a second TCP generator is connected to a second input of the TCP match, and a third TCP generator is connected to a third input of the TCP match.

[0080] In one embodiment, instead of the pulse controller generating the master clock signal 141, the module controller generates the master clock signal 141 and sends the master clock signal 141 to the pulse controller via a transmission cable. The transmission cable connects the module controller to the pulse controller. The pulse controller generates synchronization signals 140, 142, and 144 in synchronization with the master clock signal 141 received from the module controller.

[0081] In one embodiment, each RF generator, such as TCP generator, bias generator 1, and bias generator 2, has a clock source that generates a clock signal including cycles 1 and 2. For example, TCP generator has a clock source that generates a clock signal having clock cycles 1 and 2, bias generator 1 has a clock source that generates a clock signal having clock cycles 1 and 2, and bias generator 2 has a clock source that generates a clock signal having clock cycles 1 and 2. The clock signals of the clock sources of TCP generator, bias generator 1, and bias generator 2 are synchronized to master clock signal 141. For example, the clock sources of TCP generator, bias generator 1, and bias generator 2 receive master clock signal 141 and generate clock signals. The clock signals transition from logic level 0 to logic level 1 at the same time that master clock signal 141 pulses from logic level 0 to logic level 1, and transition from logic level 1 to logic level 0 at the same time that master clock signal 141 pulses from logic level 1 to logic level 0. In this embodiment, each component of the RF generator receives and operates in synchronization with a clock signal that is generated in synchronization with the master clock signal 141. For example, the controller of the TCP generator receives a clock signal from the clock source of the TCP generator and controls other components of the TCP generator to generate the RF signal 102 in synchronization with the clock signal.

[0082] In one embodiment, any synchronization signal described herein is generated by the pulse controller after it receives a trigger signal from a module controller via a transfer cable that connects the pulse controller to the module controller. The trigger signal includes a single pulse for execution of a recipe, such as a variable level and duty cycle in pulsed preset signal 138.

[0083] In one embodiment, pulsed preset signal 138 includes multiple schedules for generating multiple synchronization signals, such as synchronization signals 140, 142, and 144. For example, the schedules include information for generating the synchronization signals. Illustratively, the schedules include one or more frequencies for generating pulses of the synchronization signals. The pulse controller generates the synchronization signals according to the schedules. For example, synchronization signal 140 is generated according to a first schedule, and synchronization signal 142 is generated according to a second schedule.

[0084] In one embodiment, the master clock signal 141 is transmitted from the pulse controller to the TCP generator via a transmission cable different from transmission cable 120. The master clock signal 141 is also transmitted from the pulse controller to bias generator 1 via a transmission cable different from transmission cable 122, and from the pulse controller to bias generator 2 via a transmission cable different from transmission cable 124.

[0085] 2A shows a graph 200 to illustrate a synchronization signal 202, which is an example of the synchronization signal 140 (FIG. 1) sent to the TCP generator. The graph 200 plots the logic level of the synchronization signal 202 against time t. The logic level of the synchronization signal 202 is plotted on the y-axis and time t is plotted on the x-axis.

[0086] Time t is divided into multiple time intervals. For example, time t is divided into a first time interval between time t0 and time t1, a second time interval between time t1 and time t2, a third time interval between time t2 and time t3, etc. Note that the first time interval is equal to the second time interval, which is equal to the third time interval. Additional times t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, t17, t18, t19, t20, t21, t22, t23, t24, t25, t26, t27, t28, t29, and t30 are shown in FIG. 2A.

[0087] Synchronization signal 202 pulses at time t0, resulting in pulse 202-1. For example, synchronization signal 202 is at logic level 1 at time t0 and remains at logic level 1 from time t0 to time t0.5, where time t0.5 is halfway through the time interval between time t0 and time t1. Synchronization signal 202 also transitions from logic level 1 to logic level 0 at time t0.5 and remains at logic level t0.5 from time t0.5 to time t2, resulting in pulse 202-1.

[0088] Similarly, synchronization signal 202 is pulsed at times t2, t4, ..., t16, resulting in multiple pulses 202-2, 202-3, 202-4, 202-5, 202-6, 202-7, and 202-8. By way of example, the time interval between the generation of two consecutive pulses of synchronization signal 202 is less than approximately 0.5 seconds. For example, the time difference between the generation of pulse 202-1 and pulse 202-2 ranges from 0.05 seconds to 0.6 seconds. For another example, the time difference between the generation of pulse 202-1 and pulse 202-2 ranges from 0.01 seconds to 0.55 seconds. For yet another example, the time difference between the generation of pulse 202-1 and pulse 202-2 ranges from 0.005 seconds to 0.6 seconds.

[0089] The eighth pulse 202-8 of synchronization signal 202 ends at time t16. Synchronization signal 202 stops pulsing from time t16 to time t20. For example, synchronization signal 202 is at logic level 0 between time t14.5 and time t20. Time t14.5 is halfway through the time interval between times t14 and t15.

[0090] Cycle 1 of the occurrence of synchronization signal 202 is generated between times t0 and t20. Cycle 1 of synchronization signal 202 includes eight pulses 202-1 through 202-8 of synchronization signal 202, followed by a pulse-free time interval between times t14.5 and t20.

[0091] During cycle 1 of master clock signal 141, synchronization signals 202, 142, and 144 (FIG. 1) are divided into multiple subcycles. For example, subcycle 1 of synchronization signals 202, 142, and 144 occurs between time t0 and time t10 of cycle 1. Subcycle 2 of synchronization signals 202, 142, and 144 occurs between time t10 and time t16, and subcycle 3 of synchronization signals 202, 142, and 144 occurs between time t16 and time t20. As with cycle 1, during cycle 2 of master clock signal 141, synchronization signals 202, 142, and 144 are each divided into multiple subcycles. As an example, during cycle 2, subcycle 1 of synchronization signals 202, 142, and 144 occurs between time t20 and time t30. Cycles 1 and 2 are clock cycles of the master clock signal 141 received from the pulse controller (FIG. 1) by the TCP, Bias 1, and Bias 2 RF generators. Cycle 2 occurs between time t20 and time t40.

[0092] Synchronization signal 202 begins pulsing again at time t20, repeating eight pulses from time t20 in the same manner as eight pulses of synchronization signal 202 were generated from time t0. For example, synchronization signal 202 is at logic level 1 at time t20 and remains at that logic level from time t20 to time t20.5. 1 and time t20.5 is halfway through the time interval between times t20 and t21. Thus, synchronization signal 202 includes a first series of eight pulses 202-1 through 202-8 and a second series of eight pulses. During cycle 2, synchronization signal 202 includes eight pulses of synchronization signal 202, followed by time t 34.5 A pulseless time interval between t34 and t40 follows. Time t34.5 is halfway through the time interval between times t34 and t35. Cycle 2 of master clock signal 141 follows cycle 1 of master clock signal 141; for example, there is no other cycle between cycles 1 and 2.

[0093] In one embodiment, instead of eight consecutive pulses, synchronization signal 202 includes another number of consecutive pulses, such as two or three.

[0094] In one embodiment, instead of pulsing at a first time interval that is half the duration between two consecutive times, such as times t0 and t1, each pulse of the synchronization signal described herein is pulsed at a second time interval that is greater than or less than the first time interval. For example, synchronization signal 202 is pulsed at a second time interval ranging from time t0 to time t0.25, with time t0.25 being one-quarter of the time interval between times t0 and t1. As another example, synchronization signal 202 is pulsed at a second time interval ranging from time t0 to time t0.75, with time t0.75 being three-quarters of the time interval between times t0 and t1.

[0095] In one embodiment, the frequency of pulsing of synchronization signal 202 is different than that illustrated in FIG. 2A. For example, instead of occurring at time intervals of two time units, the pulses of synchronization signal 202 occur at time intervals of four time units. For example, instead of pulse 202-2 occurring at time t, pulse 202-2 occurs at time t, and pulse 202-3 occurs at time t. 8 t0 and t16, and so on until time t16. In this example, cycle 1 includes four pulses instead of eight pulses. In this example, a time unit is defined as the time interval between two consecutive times, such as times t0 and t1, or times t1 and t2. The frequency of the pulsing of the synchronization signal 202 is modified by a pulse controller or a module controller.

[0096] In one embodiment, each subcycle described herein has a time interval ranging from about 50 milliseconds to about 150 milliseconds, with subcycle 1 ranging from 50 milliseconds to 75 milliseconds, subcycle 2 ranging from 45 milliseconds to 160 milliseconds, and subcycle 3 ranging from 55 milliseconds to 140 milliseconds.

[0097] In one embodiment, during each cycle of master clock signal 141 (FIG. 1), there is no change in one or more process gases supplied to plasma chamber 108 (FIG. 1), and there is no change in the pressure within plasma chamber 108. For example, the pressure within plasma chamber 108 and the type of one or more process gases used within plasma chamber 108 remain the same during cycle 1. As another example, the pressure within plasma chamber 108 and the type of one or more process gases used within plasma chamber 108 remain the same during cycle 2. The pressure and / or the type of process gas may be changed between cycle 1 and cycle 2.

[0098] 2B shows a graph 204 of another synchronization signal 206, which is an example of the synchronization signal 142 (FIG. 1) provided to bias generator 1. Graph 204 plots the logic level of synchronization signal 206 versus time t. The logic level of synchronization signal 206 is plotted on the y-axis and time t is plotted on the x-axis.

[0099] Synchronization signal 206 is at logic level 0 from time t0 to time t10. Synchronization signal 206 pulses at time t10, resulting in pulse 206-1. For example, synchronization signal 206 transitions from logic level 0 to logic level 1 at time t10 and remains at logic level 1 from time t10 to time t10.5, which is halfway through the time interval between times t10 and t11. Synchronization signal 206 also transitions from logic level 1 to logic level 0 at time t10.5 and remains at logic level 0 from time t10.5 to time t12, resulting in pulse 206-1.

[0100] Similarly, synchronization signal 206 is pulsed at time t12 to produce second pulse 206-2 and at time t14 to produce third pulse 206-3. By way of example, the time interval between the generation of two consecutive pulses of synchronization signal 206 is less than approximately 0.5 seconds. For example, the time difference between the generation of pulse 206-1 and pulse 206-2 ranges from 0.05 seconds to 0.6 seconds. For another example, the time difference between the generation of pulse 206-1 and pulse 206-2 ranges from 0.01 seconds to 0.55 seconds. For yet another example, the time difference between the generation of pulse 206-1 and pulse 206-2 ranges from 0.005 seconds to 0.6 seconds.

[0101] The third pulse 206-3 of the synchronization signal 206 ends at time t16. The synchronization signal 206 stops pulsing from time t16 to time t30. For example, the synchronization signal 206 is at logic level 0 between time t16 and time t30.

[0102] Cycle 1 of the occurrence of synchronization signal 206 is generated between times t0 and t20. Cycle 1 of synchronization signal 206 includes three pulses of synchronization signal 206 followed by a pulse-free time interval between times t0 and t10.

[0103] The synchronization signal 206 begins pulsing again at time t30, repeating three pulses from time t30 in the same manner as the three pulses of the synchronization signal 206 generated from time t10. For example, the synchronization signal 206 is at logic level 1 at time t30 and remains at that logic level 1 from time t30 to time t30.5. 1 During cycle 2 of master clock signal 141, synchronization signal 206 includes three pulses of synchronization signal 202 followed by a pulse-free interval between times t20 and t30.

[0104] In one embodiment, instead of three consecutive pulses, synchronization signal 206 includes another number of consecutive pulses, such as two or five.

[0105] In one embodiment, the frequency of pulse generation of synchronization signal 206 is different from that illustrated in FIG. 2B . For example, instead of occurring at time intervals of two time units, pulses of synchronization signal 206 occur at time intervals of three time units. For example, instead of pulse 206-2 occurring at time t12, pulse 206-2 occurs at time t13 and pulse 206-3 occurs at time t16. During cycle 1 of master clock signal 141, there are no pulses after time t16.5. Time t16.5 is halfway through the time interval between times t16 and t17. In this example, cycle 1 includes three pulses of synchronization signal 206. In this example, a time unit is defined as the time interval between two consecutive times, such as times t0 and t1, or times t1 and t2. The frequency of pulse generation of synchronization signal 206 is modified by a pulse controller or a module controller.

[0106] 2C shows a graph 208 of another synchronization signal 210, which is an example of the synchronization signal 144 (FIG. 1) provided to bias generator 2. Graph 208 plots the logic level of synchronization signal 210 versus time t. The logic level of synchronization signal 210 is plotted on the y-axis and time t is plotted on the x-axis.

[0107] Synchronization signal 210 pulses in a manner similar to synchronization signal 206, resulting in multiple pulses 210-1, 210-2, and 210-3 during cycle 1. For example, synchronization signal 210 is at logic level 0 from time t0 to time t10. Synchronization signal 210 pulses at time t10, resulting in pulse 210-1. Illustratively, synchronization signal 210 transitions from logic level 0 to logic level 1 at time t10 and remains at logic level 1 from time t10 to time t10.5. Synchronization signal 210 also transitions from logic level 1 to logic level 0 at time t10.5 and remains at logic level 1 from time t10.5 to time t12. 0Synchronization signal 210 remains at 0, resulting in pulse 210-1. Similarly, synchronization signal 210 pulses at time t12, resulting in pulse 210-2, and at time t14, resulting in pulse 210-3. Synchronization signal 210 stops pulsing at time t16. Synchronization signal 210 pulses during cycle 2 in the same manner as it did during cycle 1.

[0108] In one embodiment, synchronization signal 210 differs from synchronization signal 206 (FIG. 2B) in that instead of three consecutive pulses, synchronization signal 210 includes another number of consecutive pulses, such as one or six.

[0109] In one embodiment, the frequency of the pulses of synchronization signal 210 is different than that illustrated in FIG. 2C. For example, instead of occurring at time intervals of 2 time units, the pulses of synchronization signal 206 occur at time intervals of 2.5 time units. For example, instead of pulse 210-2 occurring at time t12, pulse 210-2 occurs at time t12.5, and pulse 210 -3 occurs at time t15. Time t12.5 is halfway through the time interval between times t12 and t13. There are no pulses after time t15 during cycle 1 of the master clock signal 141. In this example, cycle 1 includes three pulses. In this example, a time unit is defined as the time interval between two consecutive times, such as times t0 and t1, or times t1 and t2. The frequency of the pulse generation of the synchronization signal 210 is modified by a pulse controller or a module controller.

[0110] 2D shows a graph 212 to illustrate a variable 216 of the RF signal 102 (FIG. 1) generated by the TCP generator in synchronization with the synchronization signal 202 (FIG. 2A). The graph 212 plots multiple variable levels of the RF signal 102 versus time t.

[0111] Each variable level of the RF signal corresponds to a state of the RF signal, for example, a first variable level is defined as a first state, a second variable level is defined as a second state, and so on.

[0112] As an example, a variable level as used herein includes an RF signal at at least one value of a variable of the RF signal. For example, a first variable level has multiple values, and a second variable level also has multiple values. The values ​​of the first variable level do not include the values ​​of the second variable level. For a further example, the minimum of all values ​​of the first variable level is greater than the maximum of all values ​​of the second variable level, such that the first variable level is greater than the second variable level. As another example, a variable level of an RF signal is the envelope of the RF signal. For example, the variable level is the maximum amplitude of the RF signal as the RF signal pulses from maximum amplitude to minimum amplitude.

[0113] The pulsing of the RF signal 102 is synchronized with the pulsing of the synchronization signal 202. For example, each pulse of the RF signal 102 is generated in response to receiving a pulse of the synchronization signal 102. Illustratively, when pulse 202-1 (FIG. 2A) of the synchronization signal 202 is received by the TCP generator, pulse 216-1 of the variable 216 is generated by the TCP generator. When pulse 202-1 of the synchronization signal 202 is received by the TCP generator, the TCP generator is enabled to generate pulse 216-1. For example, the variable 216 of the RF signal 102 has a variable level V3 at time t0 and remains at variable level V3 from time t0 to time t1. The variable 216 transitions from variable level V3 to variable level V0 at time t1. The variable 216 remains at variable level V0 from time t1 to time t2, resulting in pulse 216-1. As another example, at time t when pulse 202-1 transitions from logic level 0 to logic level 1, pulse 216-1 transitions from variable level V to variable level V. Pulse 216-1 has a first instance of states S and S of variable 216 of RF signal 102.

[0114] Similarly, additional pulses 216-2, 216-3, 216-4, and 216-5 of variable 216 are generated. Additional pulses 216-3 through 216-5 having variable level V3 are generated by the TCP generator in synchronization with pulses 202-2 through 202-5 (FIG. 2A). For example, pulse 216-2 is generated in synchronization with pulse 202-2, pulse 216-3 is generated in synchronization with pulse 202-3, and so on, with pulse 216-5 being generated in synchronization with pulse 202-5. As another example, at time t2 when pulse 202-2 (FIG. 2A) transitions from logic level 0 to logic level 1, pulse 216-2 transitions from variable level V0 to variable level V3. Pulse 216-2 has a second instance of states S1 and S0 of variable 216 of RF signal 102, pulse 216-3 has a third instance of states S1 and S0 of variable 216 of RF signal 102, and so on, with pulse 216-5 having a fifth instance of states S1 and S0 of variable 216.

[0115] It should be noted that variable levels V0 and V3 are examples of information about variable levels received in pulsed preset signal 138 (FIG. 1). Also, the duty cycle of each pulse 216-1 through 216-5 is an example of information about duty cycle received in pulsed preset signal 138. By way of example, the duty cycle of each pulse 216-1 through 216-5 is 50%. Illustratively, the duty cycle of each pulse 216-1 through 216-5 is the time interval during which the pulse has variable level V3.

[0116] Variable level V3 is greater than variable level V0 and is referred to herein as state S1 of variable 216. Variable level V0 is also referred to herein as state S0 of variable 216.

[0117] As another example, pulses 216-6, 216-7, and 216-8 of variable 216 are generated synchronously with pulses 202-6 to 202-8 of synchronization signal 202 (FIG. 2A). In this example, pulse 216-6 of variable 216 is generated by the TCP generator when pulse 202-6 (FIG. 2A) of synchronization signal 102 is received by the TCP generator. For example, variable 216 of RF signal 102 transitions from variable level V0 to variable level V4 at time t10 and remains at variable level V4 from time t10 to time t11. Variable 216 transitions from variable level V4 to variable level V0 at time t11. Variable 216 remains at variable level V0 from time t11 to time t12. As another example, at time t12 when pulse 202-7 transitions from logic level 0 to logic level 1, pulse 216-7 of variable 216 transitions from variable level V0 to variable level V4. As yet another example, at time t14 when pulse 202-8 of synchronization signal 202 transitions from logic level 0 to logic level 1, pulse 216-8 of variable 216 transitions from variable level V0 to variable level V4. Pulse 216-6 has a first instance of states S1 and S0 of variable 216, pulse 216-7 has a second instance of states S1 and S0 of variable 216, and pulse 216-8 has a third instance of states S1 and S0 of variable 216.

[0118] It should be noted that variable levels V0 and V4 are examples of information about variable levels received in pulsed preset signal 138 (FIG. 1). Also, the duty cycle of each pulse 216-6 through 216-8 is an example of information about duty cycle received in pulsed preset signal 138. By way of example, the duty cycle of each pulse 216-1 through 216-8 is 50%. Illustratively, the duty cycle of each pulse 216-6 through 216-8 is the time interval during which the pulse has variable level V4.

[0119] Furthermore, the time interval between times t10 and t16, during which state S1 of RF signal 102 has variable level V4 instead of variable level V3, is an example of information about a portion of cycle 1 of master clock signal 141 during which states S1 and S0 of RF signal 102 are generated. Also, the time interval between times t0 and t10, during which state S1 of RF signal 102 has variable level V3, is an example of information about a portion of cycle 1 of master clock signal 141 during which states S1 and S0 of RF signal 102 are generated. Variable level V4 is greater than variable level V3 and is referred to herein as state S1 of variable 216. Thus, eight pulses 216-1 through 216-8 of variable 216 are generated from time t0 to time t16 during cycle 1 of master clock signal 141.

[0120] During the time interval between times t16 and t20, the synchronization signal 202 (FIG. 2A) does not include any pulses, and therefore, the variable 216 of the RF signal 102 does not include any pulses during the time interval between times t16 and t20. During the time interval between times t16 and t20 when the synchronization signal 202 does not have a pulse, the TCP generator is prevented from generating any pulses for the variable 216. For example, the variable 216 of the RF signal 102 does not transition between multiple variable levels during the time interval between times t16 and t20. The variable 216 of the RF signal has a variable level V0 during the time interval between times t16 and t20. The variable 216 does not have any variable levels other than the variable level V0 during the time interval between times t16 and t20. Thus, the variable 216 has a single variable level V0 during the time interval between times t16 and t20. The single variable level V0 represents a single state S0. During the single state S0, there are no variable levels other than the variable level V0. Note that during the time interval between times t16 and t20, there is a single logic level 0 of synchronization signal 202. No other logic levels are present during the time interval between times t16 and t20.

[0121] Pulses 216-1 through 216-5 are generated during subcycle 1 of cycle 1 of master clock signal 141. Pulses 216-6 through 216-8 are generated during subcycle 2 of cycle 1 of master clock signal 141. Additionally, no pulses of variable 216 are generated during subcycle 3 of cycle 1 of master clock signal 141. In the same way that pulses 216-1 through 216-8 of variable 216 are generated during cycle 1 of master clock signal 141, eight pulses of variable 216 are again generated by the TCP generator during cycle 2 of master clock signal 141.

[0122] Note that the duty cycle of a state is the time interval that that state occurs as a percentage of the total time interval of all states of the pulse. For example, the duty cycle of state S1 of pulse 216-1 is 50%.

[0123] In one embodiment, each pulse of variable 216 has a duty cycle greater than or less than 50%. For example, each pulse of variable 216 has a duty cycle of 25%. As another example, each pulse of variable 216 has a duty cycle of 75%. As another example, pulses 216-1 through 216-5 each have a duty cycle of 25%, and each pulse of cycle 2 has a duty cycle of 75%.

[0124] In one embodiment, the terms sub cycle / subcycle are used interchangeably herein.

[0125] In one embodiment, the variable level V0 is the zero power level of the variable.

[0126] In one embodiment, the variable level V0 is the positive power level of the variable.

[0127] In one embodiment, instead of transitioning from variable level V0 to variable level V4, variable 216 transitions to another variable level, such as variable level V2 or variable level V6. Variable level V6 is greater than variable level V4. Variable level V2 is greater than variable level V0 and less than variable level V3.

[0128] In one embodiment, instead of transitioning from variable level V0 to variable level V3, variable 216 transitions to another variable level, such as variable level V2 or variable level V1, which is greater than variable level V0 and less than variable level V2.

[0129] In one embodiment, variable 216 has more than two states. For example, variable 216 has three, four, or five states. Illustratively, instead of transitioning between variable levels V0 and V3, variable 216 transitions between three variable levels each time a synchronization pulse of synchronization signal 202 is received by the TCP generator. When synchronization pulse 202-1 is received by the TCP generator at time t0, variable 216 transitions between the three variable levels during the time interval between times t0 and t2. When synchronization pulse 202-2 is received by the TCP generator at time t2, variable 216 again transitions between the three variable levels during the time interval between times t2 and t4.

[0130] 2E shows a graph 218 to illustrate a variable 220 of the RF signal 104 (FIG. 1) generated by the bias generator 1 in synchronization with the synchronization signal 206 (FIG. 2B). The graph 218 plots multiple variable levels of the RF signal 104 against time t.

[0131] The pulsing of the RF signal 104 is synchronized with the pulsing of the synchronization signal 206. For example, during the time interval between times t0 and t10 when the synchronization signal 206 does not have a pulse, the bias generator 1 is prevented from generating any pulses for the variable 220. For example, during the time interval between times t0 and t10, the synchronization signal 206 does not include any pulses, and therefore the variable 220 of the RF signal 104 does not include any pulses during the same time interval. The variable 220 of the RF signal 104 does not transition between multiple variable levels during the time interval between times t0 and t10. The variable 220 of the RF signal 104 has a variable level V0 during the time interval between times t0 and t10. The variable 220 does not have any variable levels other than the variable level V0 during the time interval between times t0 and t10. Thus, the variable 220 has a single variable level V0 during the time interval between times t0 and t10.

[0132] As another example, each pulse of the RF signal 104 is generated in response to receiving a pulse of the synchronization signal 206. Illustratively, when pulse 206-1 (FIG. 2B) of the synchronization signal 206 is received by bias generator 1, pulse 220-1 of the variable 220 is generated by bias generator 1, where pulse 220-1 is synchronized with pulse 206-1. When pulse 206-1 of the synchronization signal 206 is received by bias generator 1, bias generator 1 is enabled to generate pulse 220-1. For example, the variable 220 of the RF signal 104 transitions from variable level V0 to variable level V6 at time t10 and remains at variable level V6 from time t10 to time t11. The variable 220 transitions from variable level V6 to variable level V0 at time t11. The variable 220 remains at variable level V0 from time t11 to time t12, resulting in pulse 220-1. Pulse 220-1 has the first instance of states S1 and S0 of variable 220.

[0133] Similar to the generation of pulse 220-1, additional pulses 220-2 and 220-3 are generated by bias generator 1 synchronously with pulses 206-2 and 206-3. For example, pulse 220-2 is generated synchronously with pulse 206-2, and pulse 220-3 is generated synchronously with pulse 206-3. As another example, at time t12 when pulse 206-2 (FIG. 2B) transitions from logic level 0 to logic level 1, pulse 220-2 transitions from variable level V0 to variable level V6. Pulse 220-2 has a second instance of states S1 and S0 of variable 220, and pulse 220-3 has a third instance of states S1 and S0 of variable 220. Thus, three pulses 220-1 through 220-3 of variable 220 are generated from time t10 to time t16 during cycle 1 of master clock signal 141.

[0134] It should be noted that variable levels V0 and V6 of pulses 220-1 through 220-3 are an example of information about variable levels received in pulsed preset signal 138 (FIG. 1). Also, the duty cycle of each pulse 220-1 through 220-3 is an example of information about duty cycle received in pulsed preset signal 138. By way of example, the duty cycle of each pulse 220-1 through 220-3 is 50%. Illustratively, the duty cycle of each pulse 220-1 through 220-3 is the time interval during which the pulse has variable level V6.

[0135] Variable level V6 is referred to herein as state S1 of variable 220. Variable level V0 is also referred to herein as state S0 of variable 220.

[0136] During subcycle 1 of cycle 1 of master clock signal 141, no pulse is generated for variable 220. Pulses 220-1 through 220-3 are generated during subcycle 2 of cycle 1 of master clock signal 141. Additionally, during subcycle 3 of cycle 1 of master clock signal 141, no pulse is generated for variable 220. During the time interval of subcycle 3 in which synchronization signal 206 does not have a pulse, bias generator 1 is prevented from generating any pulses for variable 220.

[0137] In the same way that pulses 220-1 to 220-3 of variable 220 are generated during cycle 1 of master clock signal 141, three additional pulses of variable 220 are again generated by bias generator 1 during cycle 2 of master clock signal 141. For example, in the same way that pulses 220-1 to 220-3 are synchronized with pulses 206-1 to 206-3 of synchronization signal 206 during cycle 1 of master clock signal 141, three additional pulses of variable 220 are generated synchronized with the three pulses of synchronization signal 206 during cycle 2 of master clock signal 141.

[0138] In one embodiment, each pulse of variable 220 has a duty cycle that is greater than or less than 50%. For example, each pulse of variable 220 has a duty cycle of 25%. As another example, each pulse of variable 220 has a duty cycle of 75%. As another example, each pulse of variable 220 has a duty cycle of 25%.

[0139] In one embodiment, instead of transitioning from variable level V0 to variable level V6, variable 220 transitions to another variable level, such as variable level V2.

[0140] 2F shows a graph 222 to illustrate a variable 224 of the RF signal 106 (FIG. 1) generated by the bias generator 2 in synchronization with the synchronization signal 210 (FIG. 2C). The graph 220 plots multiple variable levels of the RF signal 106 against time t.

[0141] The pulsing of RF signal 106 is synchronized with the pulsing of synchronization signal 210. For example, during the time interval between times t0 and t10, synchronization signal 210 does not include any pulses, and therefore, variable 224 of RF signal 106 does not include any pulses during the same time interval. Variable 224 of RF signal 106 does not transition between multiple variable levels during the time interval between times t0 and t10. Variable 224 of RF signal 106 has variable level V0 during the time interval between times t0 and t10. Variable 224 does not have any variable levels other than variable level V0 during the time interval between times t0 and t10. Thus, variable 224 has a single variable level V0 during the time interval between times t0 and t10.

[0142] As another example, each pulse of the RF signal 106 is generated in response to receiving a pulse of the synchronization signal 210. When pulse 210-1 of the synchronization signal 210 is received by the bias generator 2, the bias generator 2 is enabled to generate pulse 224-1. Illustratively, when pulse 210-1 of the synchronization signal 210 (FIG. 2C) is received by the bias generator 2, pulse 224-1 of the variable 224 is generated by the bias generator 2, with pulse 224-1 being synchronized with pulse 210-1. For example, the variable 224 of the RF signal 106 remains at variable level V0 from time t10 to time t11, and transitions from variable level V0 to variable level V2 at time t11. The variable 224 transitions from variable level V2 to variable level V0 at time t12, resulting in pulse 224-1. Pulse 224-1 has a first instance of states S1 and S0 of the variable 224.

[0143] Similar to the generation of pulse 224-1, additional pulses 224-2 and 224-3 are generated by bias generator 1 in synchronization with pulses 210-2 and 210-3 of synchronization signal 210. For example, pulse 224-2 is generated in synchronization with pulse 210-2, and pulse 224-3 is generated in synchronization with pulse 210-3. As another example, after time t12, when pulse 210-2 (FIG. 2B) transitions from logic level 0 to logic level 1, pulse 224-2 transitions from variable level V0 to variable level V2. Pulse 224-2 remains at variable level V0 from time t12 to time t13, and transitions from variable level V0 to variable level V2 at time t13. In this manner, three pulses 224-1 through 224-3 of variable 220 are generated from time t10 to time t16 during cycle 1 of master clock signal 141. Pulse 224-2 has a second instance of states S1 and S0 of variable 224, and pulse 224-3 has a third instance of states S1 and S0 of variable 224.

[0144] It should be noted that the variable levels V0 and V2 of variable 224 are an example of information about the variable level received in pulsed preset signal 138 (FIG. 1). Also, the duty cycle of each pulse 224-1 to 224-3 is an example of information about the duty cycle received in pulsed preset signal 138. By way of example, the duty cycle of each pulse 224-1 to 224-3 is 50%. Illustratively, the duty cycle of each pulse 224-1 to 224-3 is the time interval during which the pulse has variable level V2.

[0145] In the same way that pulses 224-1 to 224-3 of variable 224 are generated during cycle 1 of master clock signal 141, three additional pulses of variable 224 are again generated by bias generator 2 during cycle 2 of master clock signal 141. For example, in the same way that pulses 224-1 to 224-3 are synchronized with pulses 210-1 to 210-3 of synchronization signal 210, three additional pulses of variable 224 are generated during cycle 2 of master clock signal 141 synchronized with the three pulses of synchronization signal 210.

[0146] The variable level V2 is referred to herein as the state S1 of the variable 224. The variable level V0 is referred to herein as the state S0 of the variable 224.

[0147] During subcycle 1 of cycle 1 of master clock signal 141, no pulse is generated for variable 224. During the time interval between times t0 and t10, when synchronization signal 210 does not have a pulse, bias generator 2 is disabled from generating any pulses for variable 224. Pulses 224-1 through 224-3 are generated during subcycle 2 of cycle 1 of master clock signal 141. Also, during subcycle 3 of cycle 1 of master clock signal 141, no pulse is generated for variable 224. During the time interval between times t16 and t20, when synchronization signal 210 does not have a pulse, bias generator 2 is disabled from generating any pulses for variable 224.

[0148] In one embodiment, each pulse of variable 224 has a duty cycle greater than or less than 50%. For example, each pulse of variable 224 has a duty cycle of 25%. As another example, each pulse of variable 224 has a duty cycle of 75%. As another example, pulses 224-1 through 224- 3 Each of these has a duty cycle of 25%.

[0149] In one embodiment, instead of transitioning from variable level V0 to variable level V2, variable 224 transitions to another variable level, such as variable level V6 or variable level V3.

[0150] 2G shows a graph 230 to illustrate a variable 232 of the RF signal 104 (FIG. 1) generated by the bias generator 1 in synchronization with the synchronization signal 206 (FIG. 2B). The graph 230 plots multiple variable levels of the variable 232 of the RF signal 104 versus time t.

[0151] The pulsing of variable 232 is synchronized with the pulsing of synchronization signal 206. For example, during the time interval between times t0 and t10, synchronization signal 206 does not include any pulses, and therefore, variable 232 of RF signal 104 does not include any pulses during the same time interval. Variable 232 of RF signal 104 does not transition between multiple variable levels during the time interval between times t0 and t10. Variable 232 of RF signal 104 has variable level V0 during the time interval between times t0 and t10. Variable 232 does not have any variable levels other than variable level V0 during the time interval between times t0 and t10. Thus, variable 232 has a single variable level V0 during the time interval between times t0 and t10.

[0152] As another example, each series of variable levels of variable 232 is generated in response to receiving a pulse of synchronization signal 206. To illustrate, when pulse 206-1 (FIG. 2B) of synchronization signal 206 is received by bias generator 1, series 232-1 of variable levels of variable 232 is generated by bias generator 1, with series 232-1 of pulses synchronized with pulse 206-1. For example, variable 232 of RF signal 104 transitions from variable level V0 to variable level V5 at time t10 and remains at variable level V5 from time t10 to time t10.5. Variable level V5 is greater than variable level V4 but less than variable level V6. Variable level V5 is also defined as state S4 of variable 232. Variable 232 transitions from variable level V5 to variable level V4 at time t10.5. Variable 232 remains at variable level V4 from time t10.5 to time t11. Variable level V4 is defined as state S3 of variable 232. Variable 232 transitions from variable level V4 to variable level V3 at time t11. Variable 232 remains at variable level V3 from time t11 to time t11.5, which is halfway through the time interval between times t11 and t12. Variable level V3 is defined as state S2 of variable 232. Variable 232 transitions from variable level V3 to variable level V2 at time t11.5. Variable 232 remains at variable level V2 from time t11.5 to time t12, resulting in series 232-1. Variable level V2 is defined as state S1 of variable 232.

[0153] Series 232-1 includes occurrences, e.g., first instances, of states S4, S3, S2, and S1 of variable 232. Each state S1 through S4 of series 232-1 represents a different variable level of RF signal 104. For example, state S4 of variable 232 is a first variable level of RF signal 104, state S3 of variable 232 is a second variable level of RF signal 104, state S2 of variable 232 is a third variable level of RF signal 104, and state S1 of variable 232 is a fourth variable level of RF signal 104. Each state S1 through S4 also has a duty cycle. For example, the duty cycle of each state S1 through S4 of series 232-1 is 25%.

[0154] In a similar manner as series 232-1 of variable levels of variable 232 is generated, additional series 232-2 and 232-3 of variable levels of variable 232 are generated by bias generator 1 in synchronization with pulses 206-2 and 206-3. For example, series 232-2 is generated in synchronization with pulse 206-2, and series 232-3 is generated in synchronization with pulse 206-3. As another example, at time t12 when pulse 206-2 (FIG. 2B) transitions from logic level 0 to logic level 1, series 232-2 transitions from variable level V0 to variable level V5, further transitions from variable level V5 to variable level V4, transitions from variable level V4 to variable level V3, and transitions from variable level V3 to variable level V2. Thus, three series 232-1 through 232-3 of multiple variable levels of variable 232 are generated from time t10 to time t16 during cycle 1 of master clock signal 141. Series 232-2 includes the second instances of states S4, S3, S2, and S1 of variable 232, and series 232-3 includes the third instances of states S4, S3, S2, and S1 of variable 232.

[0155] It should be noted that variable levels V5, V4, V3, and V2 are examples of information about variable levels received in pulsed preset signal 138 (FIG. 1). Also, the duty cycle of each variable level in each series 232-1 to 232-3 is an example of information about duty cycle received in pulsed preset signal 138. As an example, the duty cycle of state S4 of series 232-1 is 25%, the duty cycle of state S3 of series 232-1 is 25%, the duty cycle of state S2 of series 232-1 is 25%, and the duty cycle of state S1 of series 232-1 is 25%. Illustratively, the duty cycle of each variable level in each series 232-1 to 232-3 is the time interval during which the variable level occurs.

[0156] During subcycle 1 of cycle 1 of master clock signal 141, no pulse is generated in variable 232. Series 232 -1 to Series 232 A −3 is generated during subcycle 2 of cycle 1 of master clock signal 141. Also, during subcycle 3 of cycle 1 of master clock signal 141, no pulse is generated for variable 232.

[0157] In the same way that series 232-1 to 232-3 of variable 232 are generated during cycle 1 of master clock signal 141, three additional series of variable levels of variable 232 are again generated by bias generator 1 during cycle 2 of master clock signal 141. For example, in the same way that series 232-1 to 232-3 are synchronized with pulses 206-1 to 206-3 of synchronization signal 206, three additional series of variable levels V5, V4, V3, and V2 of variable 232 are generated synchronized with the three pulses of synchronization signal 206 during cycle 2 of master clock signal 141.

[0158] In one embodiment, one variable level of variable 232 has a different, e.g., greater or lesser, duty cycle than one or more of the remaining variable levels of variable 232. For example, variable level V4 of series 232-1 has a 40% duty cycle, and variable level V3 of series 232-1 has a 30% duty cycle. In this example, variable level V2 of series 232-1 has a 20% duty cycle, and variable level V1 of series 232-1 has a 10% duty cycle. The duty cycles of states S1 through S4 of variable 232 add up to 100%, i.e., a total of 100%. As another example, variable level V4 of series 232-1 has a 25% duty cycle, and variable level V3 of series 232-1 has a 25% duty cycle. In this example, variable level V2 of series 232-1 has a 30% duty cycle and variable level V1 of series 232-1 has a 20% duty cycle.

[0159] In one embodiment, instead of transitioning from the first variable level to the second variable level, variable 232 transitions to a third variable level different from the second variable level. For example, instead of transitioning from variable level V5 to variable level V4, variable 232 transitions from variable level V5 to variable level V3 or variable level V6. As another example, instead of transitioning from variable level V4 to variable level V3, variable 232 transitions from variable level V4 to variable level V2 or variable level V5.

[0160] In one embodiment, variable 232 includes a number of states different from four. For example, variable 232 includes three states, five states, or six states. Illustratively, during a time interval beginning at time t10 and ending at time t12, a first series of three variable levels or three states of variable 232 is formed when variable 232 transitions from variable level V0 to variable level V5 at time t10, further transitions from variable level V5 to variable level V3, and then transitions from variable level V3 to variable level V2 at time t12. In this example, during a time interval beginning at time t12 and ending at time t14, a second series of three variable levels of variable 232 is formed when variable 232 transitions from variable level V2 to variable level V5 at time t12, further transitions from variable level V5 to variable level V3, and then transitions from variable level V3 to variable level V2 at time t14. Further, in this example, during the time interval beginning at time t14 and ending at time t16, a third series of three variable levels of variable 232 is formed when variable 232 transitions from variable level V2 to variable level V5 at time t14, further transitions from variable level V5 to variable level V3, and then transitions from variable level V3 to variable level V2 at time t16.

[0161] In one embodiment, series of variable levels for a different number of variables than illustrated in Figure 2G are generated. For example, instead of three series 232-1 to 232-3, two series 232-1 and 232 Only −2 is generated by bias generator 1. As another example, in addition to the three series 232-1 to 232-3, a fourth series is generated by bias generator 1. The fourth series is the same as any of the three series 232-1 to 232-3.

[0162] In one embodiment, the variable 232 is generated by the bias generator 2 or the TCP generator. For example, if the synchronization signal 206 is an example of the synchronization signal 140 sent to the TCP generator, the variable 232 is from the RF signal 102 (FIG. 1) generated by the TCP generator. As another example, if the synchronization signal 206 is an example of the synchronization signal 144 sent to the bias generator 2, the variable 232 is from the RF signal 106 (FIG. 1) generated by the bias generator 2.

[0163] In one embodiment, the terms series of pulses and pulses are used interchangeably herein. For example, series 232-1 is the first pulse of variable 232, and series 232-2 is the second pulse of variable 232.

[0164] In one embodiment, the same synchronization signal, such as a single synchronization signal, is transmitted from the pulse controller to two or more of the TCP generator, bias generator 1, and bias generator 2. For example, synchronization signal 140 is transmitted to the TCP generator, bias generator 1, and bias generator 2. As another example, synchronization signal 142 is transmitted to the TCP generator, bias generator 1, and bias generator 2. In this embodiment, two or more of the TCP generator, bias generator 1, and bias generator 2 synchronize with the same synchronization signal to generate two or more of the RF signals 102, 104, and 106. It should be noted that in this embodiment, the variable level of one of the RF signals 102, 104, and 106 may be different from the variable levels of the remaining ones of the RF signals 102, 104, and 106. Illustratively, the variable of RF signal 102 has three states, and the variable of RF signal 104 has four states. Because the same synchronization signal is received by two or more of the RF generators, the frequencies of the instances of the states of the variables in RF signals 102, 104, and 106 are the same. For example, when synchronization signal 202 is received by TCP generator and bias generator 1, TCP generator generates RF signal 102 having a first instance of three states of the variable at time t0, and bias generator 1 generates RF signal 104 having a first instance of four states of the variable at time t0. In this example, TCP generator generates RF signal 102 having a second instance of three states of the variable at time t2, and bias generator 1 generates RF signal 104 having a second instance of four states of the variable at time t2.

[0165] 3 is an embodiment of a system 300 to illustrate the use of Ethernet cables 302, 304, and 306 to transfer information regarding variable levels and duty cycles and information regarding the fraction of a cycle of the master clock signal 141 at which multiple states of the RF signal are generated. System 300 is the same as system 100 of FIG. 1, except that in system 300, instead of an EtherCAT train, information regarding variable levels and duty cycles and information regarding the fraction of a cycle of the master clock signal 141 is transferred from the pulse controller to the TCP generator and bias generators 1 and 2 via Ethernet cables 302, 304, and 306. The pulse controller is connected to the TCP generator via Ethernet cable 302, to bias generator 1 via Ethernet cable 304, and to bias generator 2 via Ethernet cable 306.

[0166] System 300 includes a module controller, a pulse controller, a TCP generator, bias generator 1, bias generator 2, a TCP match, a bias match, and a plasma chamber 108. The module controller sends a pulsed preset signal 138 to the pulse controller via communication cable 116. Upon receiving the pulsed preset signal 138, the pulse controller identifies and extracts from the pulsed preset signal 138 information regarding the variable level and duty cycle of RF signal 102 and information regarding the portion of a cycle of master clock signal 141 during which the multiple states of RF signal 102 are generated. For example, the pulse controller identifies from pulsed preset signal 138 that, for the time interval of subcycle 1 of cycle 1 of master clock signal 141, the duty cycle of variable 216 (FIG. 2D) is 50% and that variable 216 transitions between variable levels V3 and V0. The pulse controller also determines from pulsed preset signal 138 that the duty cycle of variable 216 is 50% and that variable 216 transitions between variable levels V4 and V0 for the time interval of subcycle 2 of cycle 1 of master clock signal 141. The pulse controller also determines from pulsed preset signal 138 that the duty cycle of variable 216 is 0% and that variable 216 remains at variable level V0 for the time interval of subcycle 3 of cycle 1 of master clock signal 141. The pulse controller also determines from pulsed preset signal 138 that the variable level and duty cycle of variable 216 are repeated during subcycles 1, 2, and 3 of cycle 2 of master clock signal 141 in the same way that the variable level and duty cycle of variable 216 are generated during subcycles 1, 2, and 3 of cycle 1 of master clock signal 141.

[0167] The pulse controller generates a pulsed preset signal 308 having information about the variable level and duty cycle of the RF signal 102 and information about the portion of the cycle of the master clock signal 141 at which the multiple states of the RF signal 102 are generated, and transmits the pulsed preset signal 308 to the TCP generator via the Ethernet cable 302. Upon receiving the pulsed preset signal 308, the TCP generator stores the information about the variable level and duty cycle of the RF signal 102 and information about the portion of the cycle of the master clock signal 141 at which the multiple states of the RF signal 102 are generated in one or more memory devices of the TCP generator. Upon receiving the synchronization signal 140 via the transmission cable 120, the TCP generator synchronizes with the synchronization signal 140 to generate an RF signal 102 having information about the variable level and duty cycle of the RF signal 102 and information about the portion of the cycle of the master clock signal 141 at which the multiple states of the RF signal 102 are generated.

[0168] Similarly, upon receiving pulsed preset signal 138, the pulse controller identifies and extracts from pulsed preset signal 138 information regarding the variable level and duty cycle of RF signal 104 and information regarding the portion of a cycle of master clock signal 141 during which the multiple states of RF signal 104 are generated. For example, the pulse controller identifies from pulsed preset signal 138 that the duty cycle of variable 220 (FIG. 2E) is 0% and that variable 220 remains at variable level V0 for the time interval of subcycle 1 of cycle 1 of master clock signal 141. The pulse controller also identifies from pulsed preset signal 138 that the duty cycle of variable 220 is 50% and that variable 220 transitions between variable levels V6 and V0 for the time interval of subcycle 2 of cycle 1 of master clock signal 141. The pulse controller also determines from the pulsed preset signal 138 that the duty cycle of variable 220 is 0% and that variable 220 remains at the variable level V0 for the time interval of subcycle 3 of cycle 1 of the master clock signal 141. The pulse controller also determines from the pulsed preset signal 138 that the variable level and duty cycle of variable 220 are repeated during subcycles 1, 2, and 3 of cycle 2 of the master clock signal 141 in the same way that the variable level and duty cycle of variable 220 are generated during subcycles 1, 2, and 3 of cycle 1 of the master clock signal 141.

[0169] The pulse controller generates a pulsed preset signal 310 having information about the variable level and duty cycle of the RF signal 104 and information about the portion of the cycle of the master clock signal 141 at which the multiple states of the RF signal 104 are generated, and transmits the pulsed preset signal 310 to the bias generator 1 via the Ethernet cable 304. Upon receiving the pulsed preset signal 310, the bias generator 1 stores the information about the variable level and duty cycle of the RF signal 104 and information about the portion of the cycle of the master clock signal 141 at which the multiple states of the RF signal 104 are generated in one or more memory devices of the bias generator 1. Upon receiving the synchronization signal 142 via the transmission cable 122, the bias generator 1 synchronizes with the synchronization signal 142 to generate the RF signal 104 having information about the variable level and duty cycle of the RF signal 104 and information about the portion of the cycle of the master clock signal 141 at which the multiple states of the RF signal 104 are generated.

[0170] Additionally, upon receiving pulsed preset signal 138, pulse controller 138 identifies and extracts from pulsed preset signal 138 information regarding the variable level and duty cycle of RF signal 106 and information regarding the portion of a cycle of master clock signal 141 during which the multiple states of RF signal 106 are generated. For example, pulse controller 138 identifies from pulsed preset signal 138 that the duty cycle of variable 224 (FIG. 2F) is 0% and that variable 224 remains at variable level V0 for the time interval of subcycle 1 of cycle 1 of master clock signal 141. Pulse controller 138 also identifies from pulsed preset signal 138 that the duty cycle of variable 224 is 50% and that variable 224 transitions between variable levels V2 and V0 for the time interval of subcycle 2 of cycle 1 of master clock signal 141. The pulse controller also determines from the pulsed preset signal 138 that the duty cycle of variable 224 is 0% and that variable 224 remains at the variable level V0 for the time interval of subcycle 3 of cycle 1 of the master clock signal 141. The pulse controller also determines from the pulsed preset signal 138 that the variable level and duty cycle of variable 224 are repeated during subcycles 1, 2, and 3 of cycle 2 of the master clock signal 141 in the same way that the variable level and duty cycle of variable 220 are generated during subcycles 1, 2, and 3 of cycle 1 of the master clock signal 141.

[0171] The pulse controller generates a pulsed preset signal 312 having information about the variable level and duty cycle of the RF signal 106 and information about the portion of the cycle of the master clock signal 141 at which the multiple states of the RF signal 106 are generated, and transmits the pulsed preset signal 312 to the bias generator 2 via the Ethernet cable 306. Upon receiving the pulsed preset signal 312, the bias generator 2 stores the information about the variable level and duty cycle of the RF signal 106 and information about the portion of the cycle of the master clock signal 141 at which the multiple states of the RF signal 106 are generated in one or more memory devices of the bias generator 2. Upon receiving the synchronization signal 144 via the transmission cable 124, the bias generator 2 synchronizes with the synchronization signal 144 to generate the RF signal 106 having information about the variable level and duty cycle of the RF signal 106 and information about the portion of the cycle of the master clock signal 141 at which the multiple states of the RF signal 106 are generated.

[0172] In one embodiment, a connection cable is used in place of each of the Ethernet cables 302, 304, and 306. An example of a connection cable is a cable capable of transferring data at a speed greater than 10 Gbps. The connection cable provides a connection between the CPUs. For example, the connection cable can transfer data at a speed ranging from 10 Gbps to 40 Gbps. Another example of a connection cable is a transfer cable.

[0173] FIG. 4 is a diagram of one embodiment of a system 400 illustrating the use of EtherCAT to sense data from a sensor 402 in a TCP match and a sensor 404 in a bias match. An example of each sensor 402 and 404 is a voltage sensor, a current sensor, a complex voltage-current sensor, or a power sensor. For example, each sensor 402 and 404 senses data such as voltage data, current data, a power value, or a complex voltage-current value. For example, sensor 402 is connected to input I1 of the TCP match. For another example, sensor 402 is connected to output O2 of the TCP match. For example, sensor 404 is connected to input I2 or I3 of the bias match. For another example, sensor 404 is connected to output O4 of the bias match.

[0174] System 400 is similar to system 100 (FIG. 1) except that system 400 includes a communication cable 406 and another communication cable 408. System 400 further includes a voltage sensor system 410 and an optical emission spectroscopy (OES) system 412.

[0175] The voltage sensor system 410 includes a voltage detector or sensor, a controller, and an analog-to-digital converter (ADC). The voltage sensor senses a wafer bias, such as a voltage, at the substrate support 110. For example, the voltage sensor senses data such as voltage data or a voltage value. The controller of the voltage sensor system 410 is connected to the ADC and the voltage sensor of the voltage sensor system 410. The OES system 412 includes an OES, a controller, and an ADC. The controller of the OES system 412 is connected to the ADC and the OES of the OES system 412. The OES senses the intensity of light emitted from the plasma in the plasma chamber 108. For example, the OES measures data on the intensity of light reflected from the top surface of the substrate S toward the OES.

[0176] System 400 includes a module controller, a pulse controller, a TCP generator, bias generators 1 and 2, plasma chamber 108, a TCP match with sensor 402, a bias match with sensor 404, a voltage sensor system 410, and an OES system 412. A communication cable 406 connects the pulse controller to the TCP match, and a communication cable 408 connects the TCP match to the bias match. The pulse controller is connected to the TCP match via a transfer cable 414 and to the bias match via a transfer cable 417.

[0177] The voltage sensor system 410 is connected to the substrate support 110. The OES system 412 is disposed on a sidewall 424 of the plasma chamber 108 other than the sidewall 424. For example, a window is disposed on the sidewall 424, and the OES of the OES system 412 faces the window. A pulse controller is connected to the voltage sensor system 410 via a transfer cable 420 and to the OES system 412 via a transfer cable 422.

[0178] The pulse controller generates a factor control signal 415, which is an EtherCAT train, and sends the factor control signal 415 to the TCP match via the communication cable 406. The factor control signal 415 includes instructions to a match controller in the TCP match to change a factor of the TCP match to achieve a predetermined factor, such as capacitance, inductance, or a combination thereof. The factor control signal 415 further includes another instruction to a match controller in the bias match to change a factor of the bias match to achieve a preset factor.

[0179] Upon receiving the factor control signal 415, the TCP match obtains a predetermined factor for the TCP match from the factor control signal 415. Based on the predetermined factor, the match controller of the TCP match controls a TCP motor in the TCP match to further control the circuit components of the TCP match. The circuit components of the TCP match are controlled to change the factor of the circuit components to achieve the predetermined factor. For example, the motor of the TCP match controls a first plate of a capacitor of the TCP match to rotate relative to a second plate of the capacitor to achieve a predetermined capacitance.

[0180] After obtaining the predetermined factor from the factor control signal 415, the TCP match transmits the factor control signal 415 to the bias match via the communication cable 408. Upon receiving the factor control signal 415, the bias match obtains a preset factor for the bias match from the factor control signal 415. Based on the preset factor, the match controller of the bias match controls a bias motor in the bias match to further control the circuit components of the bias match. The circuit components of the bias match are controlled to change the factor of the circuit components to achieve the preset factor. For example, the motor controls the first plate of the capacitor of the bias match to rotate relative to the second plate of the capacitor to achieve the preset capacitance.

[0181] After obtaining the preset factor from the factor control signal 415, the bias match sends the factor control signal 415 back to the TCP match via the communication cable 408. The TCP match sends the factor control signal 415 received from the bias match back to the pulse controller.

[0182] Furthermore, after the instructions to realize the predetermined factors are applied by the match controller of the TCP match and the RF signals 102, 104, and 106 are generated, the pulse controller generates a synchronization signal 416 and sends the synchronization signal 416 to the TCP match via a transmission cable 414. Furthermore, after the instructions to realize the preset factors are applied by the match controller of the bias match and the RF signals 102, 104, and 106 are generated, the pulse controller generates another synchronization signal 418 and sends the synchronization signal 418 to the bias match via a transmission cable 417. The synchronization signal 416 is labeled as sync4a in FIG. 4, and the synchronization signal 418 is labeled as sync4b in FIG. 4.

[0183] In response to receiving the synchronization signal 416, the match controller in the TCP match controls the ADC of the TCP match to collect data sensed by the sensor 402 in synchronization with the synchronization signal 416. The collected data is transmitted from the TCP match to the pulse controller. For example, the synchronization signal 416 includes a series of pulses including a first pulse and a second pulse. In response to receiving the first pulse of the synchronization signal 416 for the first time interval, the match controller of the TCP match controls the ADC of the TCP match to convert the data sensed by the sensor 402 from analog to digital format for the first time interval and output digital data for the first time interval. The ADC of the TCP match is connected to the sensor 402. The match controller of the TCP match receives the digital data output for the first time interval from the ADC of the TCP match and stores the digital data in the memory device of the match controller. Upon receiving the factor control signal 415 returned from the bias match, the match controller accesses the digital data for the first time interval from the memory device. The digital data regarding the time interval is then embedded into a factor control signal 415 and transmitted to the pulse controller via communication cable 406.

[0184] Similarly, in response to receiving a second pulse of the synchronization signal 416 for the second time interval, the match controller of the TCP match controls the ADC of the TCP match to convert the data sensed by the sensor 402 from analog to digital format for the second time interval and output the digital data for the second time interval. The match controller of the TCP match receives the digital data output for the second time interval from the ADC of the TCP match and stores the digital data in the memory device of the match controller. Upon receiving the factor control signal 415 returned from the bias match, the match controller accesses the digital data for the second time interval from the memory device. The digital data for the second time interval is embedded in the factor control signal 415 and transmitted to the pulse controller via the communication cable 406. During time intervals when no pulse of the synchronization signal 416 is received by the TCP match, the match controller of the TCP match does not control the ADC to convert the data sensed by the sensor 402 from analog to digital format.

[0185] Similarly, in response to receiving the synchronization signal 418, the match controller in the bias match controls the sensor 404 to provide data sensed by the sensor 404 to the pulse controller in synchronization with the synchronization signal 418. For example, the synchronization signal 418 includes a series of pulses including a first pulse and a second pulse. In response to receiving the first pulse of the synchronization signal 418 for the first time interval, the match controller of the bias match controls the ADC of the bias match to convert the data sensed by the sensor 404 from analog to digital format for the first time interval and output digital data for the first time interval. The ADC of the bias match is connected to the sensor 404. The match controller of the bias match receives the digital data output for the first time interval from the ADC of the bias match and stores the digital data in the memory device of the match controller. When the factor control signal 415 is received from the TCP match, the match controller accesses the digital data for the first time interval from the memory device. The digital data for the first time interval is embedded in a factor control signal 415 and sent back to the TCP match via communication cable 408, and from the TCP match via communication cable 408. 406 is sent back to the pulse controller via

[0186] Similarly, in response to receiving a second pulse of the synchronization signal 418 for the second time interval, the match controller of the bias match controls the ADC of the bias match to convert the data sensed by the sensor 404 from analog to digital format for the second time interval and output the digital data for the second time interval. The match controller of the bias match receives the digital data output for the second time interval from the ADC of the bias match and stores the digital data in the memory device of the match controller. When a factor control signal 415 is received from the bias match, the match controller accesses the digital data for the second time interval from the memory device. The digital data for the second time interval is then embedded in the factor control signal 415 and sent back to the TCP match via the communication cable 408, and from the TCP match to the pulse controller. During time intervals when a pulse of the synchronization signal 418 is not received by the bias match, the match controller of the bias match does not control the ADC to convert the data sensed by the sensor 404 from analog to digital format.

[0187] The pulse controller also generates a synchronization signal 426 and transmits it to the voltage sensor system 410 via the transfer cable 420. The synchronization signal 426 is labeled as sync5 in FIG. 4. In response to receiving the synchronization signal 426, the controller in the voltage sensor system 410 controls the voltage sensor of the voltage sensor system 410 to provide data sensed by the voltage sensor to the pulse controller in synchronization with the synchronization signal 426. As an example, the synchronization signal 426 includes a series of pulses including a first pulse and a second pulse. In response to receiving the first pulse of the synchronization signal 426 for the first time interval, the controller of the voltage sensor system 410 controls the ADC of the voltage sensor system 410 to convert the data sensed by the voltage sensor from analog to digital format for the first time interval and output the digital data for the first time interval. The ADC of the voltage sensor system 410 is connected to the voltage sensor of the voltage sensor system 410. The controller of the voltage sensor system 410 receives the digital data output for the first time interval from the ADC of the voltage sensor system 410 and transmits the digital data to the pulse controller via the transfer cable 420. Similarly, in response to receiving a second pulse of the synchronization signal 426 for the second time interval, the controller of the voltage sensor system 410 controls the ADC of the voltage sensor system 410 to convert the data sensed by the voltage sensor from analog format to digital format for the second time interval and output the digital data for the second time interval. The controller of the voltage sensor system 410 receives the digital data output for the second time interval from the ADC of the voltage sensor system 410 and transmits the digital data to the pulse controller via the transfer cable 420. During time intervals when no pulse of the synchronization signal 426 is received by the voltage sensor system 410, the controller of the voltage sensor system 410 does not control the ADC of the voltage sensor system 410 to convert the data sensed by the voltage sensor from analog format to digital format.

[0188] Further, the pulse controller generates a synchronization signal 428 and transmits the synchronization signal 428 to the OES system 412 via the transfer cable 422. The synchronization signal 428 is labeled as sync6 in FIG. 4 . In response to receiving the synchronization signal 428, the controller within the OES system 412 controls the OES of the OES system 412 to provide data sensed by the OES to the pulse controller in synchronization with the synchronization signal 428. As an example, the synchronization signal 428 includes a series of pulses including a first pulse and a second pulse. In response to receiving the first pulse of the synchronization signal 428 for the first time interval, the controller of the OES system 412 controls the ADC of the OES system 412 to convert the data sensed by the OES from analog to digital format for the first time interval and output the digital data for the first time interval. The controller of the OES system 412 receives the digital data output for the first time interval from the ADC of the OES system 412 and transmits the digital data to the pulse controller via the transfer cable 422. Similarly, in response to receiving a second pulse of synchronization signal 428 for the second time interval, the controller of OES system 412 controls the ADC of OES system 412 to convert the data sensed by the OES from analog format to digital format for the second time interval and output the digital data for the second time interval. The controller of OES system 412 receives the digital data output for the second time interval from the ADC of OES system 412 and transmits the digital data to the pulse controller via transfer cable 422. During time intervals when a pulse of synchronization signal 428 is not received by OES system 412, the controller of OES system 412 does not control the ADC of OES system 412 to convert the data sensed by the OES from analog format to digital format.

[0189] The synchronization signals 416, 418, 426, and 428 are generated by a pulse controller in synchronization with the master clock signal 141. For example, each of the synchronization signals 416, 418, 426, and 428 comprises a series of pulses that repeat during each cycle of the master clock signal 141.

[0190] In one embodiment, instead of the voltage sensors in voltage sensor system 410, power sensors, or complex voltage-current sensors, are used.

[0191] In one embodiment, instead of placing the sensor 402 within the TCP match, the sensor 402 is placed outside the TCP match.

[0192] In one embodiment, instead of placing the sensor 404 within the bias match, the sensor 404 is placed outside the TCP match.

[0193] In one embodiment, system 400 does not include one or more (but not all) of sensor 402 , sensor 404 , voltage sensor system 410 , and OES system 412 .

[0194] In one embodiment, the module controller generates the factor control signal 415 and sends the factor control signal 415 to the pulse controller via communication cable 116. The pulse controller sends the factor control signal 415 to the TCP match via communication cable 406.

[0195] In one embodiment, the terms data and value are used interchangeably herein.

[0196] 5A shows a graph 500 illustrating a plot of plasma intensity 502 versus time t. The intensity 502 is detected by an OES. The intensity 502 is plotted on the y-axis and time t is plotted on the x-axis.

[0197] 5B shows a graph 504 to illustrate synchronization signal 506 versus time t. Graph 504 plots the logic level of synchronization signal 506 on the y-axis and time t on the x-axis. Synchronization signal 506 is an example of synchronization signal 428 (FIG. 4).

[0198] Synchronization signal 506 is not pulsed from time t0 to time t6. For example, synchronization signal 506 has a logic level 0 from time t0 to time t6. Synchronization signal 506 pulses at time t6. For example, synchronization signal 506 transitions from logic level 0 to logic level 1 at time t6 and remains at logic level 1 from time t6 to time t6.5, which is halfway through the time interval between times t5 and t6. Synchronization signal 506 also transitions from logic level 1 to logic level 0 at time t6.5 to form pulse 506-1 and remains at logic level 0 from time t6.5 to time t9. Synchronization signal 506 pulses again at time t9. For example, synchronization signal 506 transitions from logic level 0 to logic level 1 at time t9 and remains at logic level 1 from time t9 to time t10. Also, synchronization signal 506 transitions from logic level 1 to logic level 0 at time t10 to form pulse 506-2 and remains at logic level 0 from time t10 to time t20, which occurs at the end of cycle 1 of master clock signal 141.

[0199] During cycle 1 of master clock signal 141, synchronization signal 506 includes a pulse-free time interval between times t0 and t6, followed by pulse 506-1. Also during cycle 1 of master clock signal 141, pulse 506-1 is followed by a pulse-free time interval between times t6.5 and t9, which is followed by pulse 506-2. During cycle 1 of master clock signal 141, pulse 506-2 is followed by a pulse-free time interval between times t10 and t20 during cycle 1 of master clock signal 141.

[0200] Similar to during cycle 1 of master clock signal 141, synchronization signal 506 is not pulsed from time t20 to time t26 during cycle 2 of master clock signal 141, pulses at time t26, is not pulsed between time t26.5 and time t29, pulses again at time t29, and is not pulsed between times t30 and t40. Time t26.5 is halfway through the time interval between times t26 and t27.

[0201] The ADC of OES system 412 (FIG. 4) begins and ends sampling of data sensed by the OES from analog to digital form in synchronization with synchronization signal 506. For example, during the time interval between times t0 and t6, intensity 502 detected by the OES is not sampled by the ADC of OES system 412. In this example, during the time interval between times t6 and t6.5, intensity 502 detected by the OES is sampled by the ADC of OES system 412. The intensity sampled during the time interval between times t6 and t6.5 is represented by portion 502-1. Also, in this example, during the time interval between times t6.5 and t9, intensity 502 detected by the OES is not sampled by the ADC of OES system 412. Continuing the example, during the time interval between times t9 and t10, intensity 502 detected by the OES is sampled by the ADC of OES system 412. The intensity sampled during the time interval between times t9 and t10 is represented by portion 502-2. Also in this example, during the time interval between times t10 and t20, intensity 502 detected by the OES is not sampled by the ADC of OES system 412. Similar to during cycle 1 of master clock signal 141, intensity 502 may or may not be sampled by the ADC of OES system 412 during cycle 2 of master clock signal 141.

[0202] In one embodiment, all pulses of synchronization signal 506 have the same duration. For example, instead of transitioning at time t10, pulse 506-2 transitions from logic level 1 to logic level 0 at time t9.5. Time t9.5 is halfway between times t9 and t10. In this embodiment, an ADC connected to the OES converts data sensed by the OES from analog to digital format when each pulse of synchronization signal 506 is received by the ADC. The ADC converts data sensed by the OES for a fixed time period for each pulse of synchronization signal 506. For example, the ADC converts data sensed by the OES for a fixed time period between times t6 and t9 when the rising edge of pulse 506-1 is received by the ADC, and converts data sensed by the OES for a fixed time period between times t9 and t12 when the rising edge of pulse 506-2 is received by the ADC. The fixed time period begins at time t6, when the rising edge of pulse 506-1 occurs. An example of a fixed time is a time interval that is one time unit, two time units, or 2.5 time units apart. In this example, a time unit is defined as the time interval between two consecutive times, such as times t0 and t1, or times t1 and t2. After the fixed time, the ADC stops sampling the data sensed by the OES until the next consecutive pulse of the synchronization signal 506 is received by the ADC. The data sensed by the OES is again sampled by the ADC of the OES system 412 for a fixed time period starting at time t9. At time t9, the rising edge of pulse 506-2 occurs. Note that a rising edge of a pulse, as used herein, is an edge that transitions from logic level 0 to logic level 1. As used herein, a rising edge of a pulse Falling Note that an edge is an edge that transitions from a logic level 1 to a logic level 0.

[0203] In one embodiment, instead of starting to collect data sensed by the OES on the rising edge of each pulse of synchronization signal 506, collection begins for a fixed time on the falling edge of the pulse. For example, suppose pulse 506-2 transitions from logic level 1 to logic level 0 at time t9.5 instead of time t10. In this embodiment, the ADC connected to the OES converts the data sensed by the OES from analog to digital format at the time of the falling edge of each pulse of synchronization signal 506 received by the ADC. The ADC converts the data sensed by the OES for a fixed time starting from the falling edge of the pulse of synchronization signal 506. For example, the ADC converts the data sensed by the OES for a fixed time between times t6.5 and t9.5, the fixed time beginning at time t6.5 when the falling edge of pulse 506-1 is received by the ADC. After a fixed time, the ADC stops sampling the data sensed by the OES until the falling edge of the next successive pulse of synchronization signal 506, such as the falling edge of pulse 506-2, is received by the ADC. The data sensed by the OES is again sampled for a fixed time starting at time t9.5. Note that as used herein, a falling edge of a pulse is the edge that transitions from logic level 0 to logic level 1.

[0204] In one embodiment, instead of two consecutive pulses, synchronization signal 506 includes another number of consecutive pulses, such as three or four.

[0205] In one embodiment, the frequency of the pulses of synchronization signal 506 is different from that illustrated in FIG. 5B. For example, instead of occurring at time intervals of three time units, the pulses of synchronization signal 506 occur at time intervals of two time units. For example, instead of pulse 506-2 occurring at time t, pulse 506-2 occurs at time t. In this example, a time unit is defined as the time interval between two consecutive times, such as times t and t, or times t and t.

[0206] 6A shows a graph 600 illustrating a plot of voltage 602 versus time t. The voltage 602 is measured by sensor 402 (FIG. 4). The voltage 602 is plotted on the y-axis and time t is plotted on the x-axis. The voltage 602 fluctuates between a maximum value Vmax and a minimum value Vmin.

[0207] 6B shows a graph 604 to illustrate a synchronization signal 606 versus time t. The graph 604 plots the logic level of the synchronization signal 606 on the y-axis and time t on the x-axis. The synchronization signal 606 is an example of the synchronization signal 416 (FIG. 4).

[0208] Synchronization signal 606 pulses at time t0. For example, synchronization signal 606 transitions from logic level 0 to logic level 1 at time t0 and remains at logic level 1 from time t0 to time t0.5. Synchronization signal 606 also transitions from logic level 1 to logic level 0 at time t0.5 to form pulse 606-1 and remains at logic level 0 from time t0.5 to time t4.

[0209] Synchronization signal 606 is not pulsed from time t0.5 to time t4. For example, synchronization signal 606 has a logic level 0 from time t0.5 to time t4. Synchronization signal 606 pulses at time t4. For example, synchronization signal 606 transitions from logic level 0 to logic level 1 at time t4 and remains at logic level 1 from time t4 to time t5. Synchronization signal 606 also transitions from logic level 1 to logic level 0 at time t5 to form pulse 606-2 and remains at logic level 0 from time t5 to time t20.

[0210] During cycle 1 of master clock signal 141, pulse 606-1 is followed by a pulse-free time interval between times t0.5 and t4, which is followed by pulse 606-2. During cycle 1 of master clock signal 141, synchronization signal 606 includes a pulse-free time interval of synchronization signal 606 between times t5 and t20.

[0211] Similar to during cycle 1 of the master clock signal 141, during cycle 2 of the master clock signal 141, the synchronization signal 606 is pulsed during the time interval between times t20 and t20.5, is not pulsed from time t20.5 to time t24, is pulsed during the time interval between times t24 and t25, and is not pulsed between time t25 and time t40.

[0212] The ADC coupled to the sensor 402 ( FIG. 4 ) begins and ends sampling of data sensed by the sensor 402 from analog to digital form in synchronization with the synchronization signal 606. For example, during the time interval between times t0 and t0.5, the voltage 602 measured by the sensor 402 is sampled by the ADC coupled to the sensor 402. The voltage sampled during the time interval between times t0 and t0.5 is represented by portion 602-1. In this example, during the time interval between times t0.5 and t4, the voltage 602 measured by the sensor 402 is not sampled by the ADC coupled to the sensor 402. In this example, during the time interval between times t4 and t5, the voltage 602 sensed by the sensor 402 is sampled by the ADC coupled to the sensor 402. The voltage 602 sampled during the time interval between times t4 and t5 is represented by portion 602-2. Also in this example, during the time interval between times t5 and t20, voltage 602 detected by sensor 402 is not sampled by the ADC connected to sensor 402. Similar to during cycle 1 of master clock signal 141, voltage 602 may or may not be sampled by the ADC connected to sensor 402 during cycle 2 of master clock signal 141.

[0213] In one embodiment, instead of two consecutive pulses, synchronization signal 606 includes another number of consecutive pulses, such as three or four.

[0214] In one embodiment, the frequency of the pulses of synchronization signal 606 is different from that illustrated in FIG. 6B. For example, instead of occurring at time intervals of four time units, the pulses of synchronization signal 606 occur at time intervals of three time units. For example, instead of pulse 606-2 occurring at time t, pulse 606-2 occurs at time t. In this example, a time unit is defined as the time interval between two consecutive times, such as times t and t, or times t and t.

[0215] In one embodiment, voltage 602 is measured by sensor 404 (FIG. 4) in the bias match instead of sensor 402. In this embodiment, synchronization signal 606 is an example of synchronization signal 418 that is provided to the bias match to receive measurement data from sensor 404 in synchronization with synchronization signal 418 (FIG. 4).

[0216] In one embodiment, voltage 602 is measured by a voltage sensor of voltage sensor system 410 (FIG. 4) instead of sensor 402. In this embodiment, synchronization signal 606 is an example of synchronization signal 426 that is provided to voltage sensor system 410 to receive measurement data from a voltage sensor of voltage sensor system 410 in synchronization with synchronization signal 426 (FIG. 4).

[0217] In one embodiment, all pulses of the synchronization signal 606 are of the same duration. For example, instead of transitioning at time t5, pulse 606-2 transitions from logic level 1 to logic level 0 at time t4.5. Time t4.5 is halfway through the time interval between times t4 and t5. In this embodiment, the ADC connected to the sensor 402 converts the data sensed by the sensor 402 from analog to digital format when each pulse of the synchronization signal 606 is received by the ADC. The ADC converts the data sensed by the sensor 402 for a fixed time period for each pulse of the synchronization signal 606. For example, the ADC converts the data sensed by the sensor 402 for a fixed time period between times t0 and t4 when the rising edge of pulse 606-1 is received by the ADC, and converts the data sensed by the sensor 402 for a fixed time period between times t4 and t7 when the rising edge of pulse 606-2 is received by the ADC. To illustrate, starting at time t0, the ADC converts data sensed by the sensor 402 from analog to digital format until a certain time is reached. After the certain time, the ADC stops sampling data sensed by the sensor 402 until the next successive pulse of the synchronization signal 606 is received by the ADC. For example, the ADC stops converting data from time t2 to time t4. Starting at time t4, the ADC converts data sensed by the sensor 402 from analog to digital format until a certain time is reached, at time t6.

[0218] In one embodiment, instead of starting to collect data sensed by the sensor 402 on the rising edge of a pulse of the synchronization signal 606, collection begins for a fixed time period, with the fixed time period beginning with the falling edge of the pulse. In this embodiment, an ADC connected to the sensor 402 converts the data sensed by the sensor 402 from analog to digital format at the time of the falling edge of each pulse of the synchronization signal 606 received by the ADC. The ADC converts the data sensed by the sensor 402 for a fixed time period after the falling edge of the pulse of the synchronization signal 606. For example, the ADC converts the data sensed by the sensor 402 for a fixed time period between times t0.5 and t4.5 after the falling edge of pulse 606-1 is received by the ADC. The fixed time period begins at time t0.5. The ADC stops sampling the data sensed by the sensor 402 after the fixed time period until the falling edge of the next successive pulse of the synchronization signal 606, such as pulse 606-2, is received by the ADC. The ADC continues to convert data sensed by sensor 402 for a fixed time period after the falling edge of pulse 606-2. For example, suppose pulse 606-2 transitions from logic level 1 to logic level 0 at time t4.5 instead of transitioning at time t5. The ADC converts data sensed by sensor 402 starting at time t4.5 until the fixed time period is reached.

[0219] 6C shows a graph 608 illustrating a plot of voltage 610 versus time t. The voltage 610 is measured by the bias match sensor 404 (FIG. 4). The voltage 610 is plotted on the y-axis and time t is plotted on the x-axis. The voltage 610 fluctuates between a maximum value Vbmax and a minimum value Vbmin.

[0220] 6D shows a graph 612 to illustrate synchronization signal 614 versus time t. Graph 612 plots the logic level of synchronization signal 614 on the y-axis and time t on the x-axis. Synchronization signal 614 is an example of synchronization signal 418 (FIG. 4) provided to bias match.

[0221] Synchronization signal 614 pulses at time t0. For example, synchronization signal 614 transitions from logic level 0 to logic level 1 at time t0 and remains at logic level 1 from time t0 to time t2. Synchronization signal 614 also transitions from logic level 1 to logic level 0 at time t2 to form pulse 614-1 and remains at logic level 0 from time t2 to time t5.

[0222] Synchronization signal 614 is not pulsed from time t2 to time t5. For example, synchronization signal 614 has a logic level 0 from time t2 to time t5. Synchronization signal 614 pulses at time t5. For example, synchronization signal 614 transitions from logic level 0 to logic level 1 at time t5 and remains at logic level 1 from time t5 to time t6. Synchronization signal 614 also transitions from logic level 1 to logic level 0 at time t6 to form pulse 614-2 and remains at logic level 0 from time t6 to time t20.

[0223] During cycle 1 of master clock signal 141, pulse 614-1 is followed by a pulse-free time interval between times t2 and t5, which is followed by pulse 614-2. During cycle 1 of master clock signal 141, pulse 614-2 is followed by a pulse-free time interval of synchronization signal 614 between times t6 and t20.

[0224] Similar to during cycle 1 of master clock signal 141, synchronization signal 614 pulses during cycle 2 of master clock signal 141 during the time interval between time t20 and time t22, is not pulsed from time t22 to time t25, is pulsed during the time interval between time t25 and t26, and is not pulsed from time t26 to time t40.

[0225] The ADC coupled to the sensor 404 ( FIG. 4 ) begins and ends sampling of data sensed by the sensor 404 from analog to digital format in synchronization with the synchronization signal 614. For example, during the time interval between times t0 and t2, the voltage 610 measured by the sensor 404 is sampled by the ADC coupled to the sensor 404. The voltage sampled during the time interval between times t0 and t2 is represented by portion 610-1. In this example, during the time interval between times t2 and t5, the voltage 610 measured by the sensor 404 is not sampled by the ADC coupled to the sensor 404. In this example, during the time interval between times t5 and t6, the voltage 610 sensed by the sensor 404 is sampled by the ADC coupled to the sensor 404. The voltage 610 sampled during the time interval between times t5 and t6 is represented by portion 610-2. Also in this example, during the time interval between times t6 and t20, voltage 610 detected by sensor 404 is not sampled by the ADC connected to sensor 404. Similar to during cycle 1 of master clock signal 141, voltage 610 may or may not be sampled by the ADC connected to sensor 404 during cycle 2 of master clock signal 141.

[0226] In one embodiment, instead of two consecutive pulses, synchronization signal 614 includes another number of consecutive pulses, such as three or four.

[0227] In one embodiment, the frequency of the pulses of synchronization signal 614 is different from that illustrated in FIG. 6D. For example, instead of occurring at time intervals of five time units, the pulses of synchronization signal 614 occur at time intervals of six time units. For example, instead of pulse 614-2 occurring at time t, pulse 614-2 occurs at time t. In this example, a time unit is defined as the time interval between two consecutive times, such as times t and t, or times t and t.

[0228] In one embodiment, voltage 610 is measured by sensor 402 (FIG. 4) in the TCP match instead of sensor 404. In this embodiment, synchronization signal 614 is an example of synchronization signal 416 that is provided to the TCP match to receive measurement data from sensor 402 in synchronization with synchronization signal 416 (FIG. 4).

[0229] In one embodiment, voltage 610 is measured by a voltage sensor of voltage sensor system 410 (FIG. 4) instead of sensor 404. In this embodiment, synchronization signal 614 is an example of synchronization signal 426 that is provided to voltage sensor system 410 to receive measurement data from a voltage sensor of voltage sensor system 410 in synchronization with synchronization signal 426 (FIG. 4).

[0230] In one embodiment, all pulses of synchronization signal 614 are of the same duration. For example, suppose pulse 614-2 transitions from logic level 1 to logic level 0 at time t7 instead of transitioning at time t6. In this embodiment, the ADC connected to bias match sensor 404 generates a synchronization signal 614 As each pulse of the sync signal is received by the ADC, it converts the data sensed by the sensor 404 from analog to digital form. 614The ADC converts the data sensed by the sensor 404 for a fixed time period for each pulse of the synchronization signal 614. For example, the ADC converts the data sensed by the sensor 404 for a fixed time period between times t0 and t5 when the rising edge of pulse 614-1 is received by the ADC, and converts the data sensed by the sensor 404 for a fixed time period between times t5 and t10 when the rising edge of pulse 614-2 is received by the ADC. Illustratively, starting at time t0, the ADC converts the data sensed by the sensor 404 from analog to digital format until the fixed time period is reached. After the fixed time period, the ADC stops sampling the data sensed by the sensor 404 until the next successive pulse of the synchronization signal 614 is received by the ADC. For example, the ADC stops converting data from time t3 to time t5. The ADC converts the data sensed by the sensor 404 from analog to digital format starting at time t5 until the fixed time period is reached.

[0231] In one embodiment, instead of starting to collect data sensed by the sensor 404 on the rising edge of a pulse of the synchronization signal 614, collection begins for a fixed time, with the fixed time beginning with the falling edge of the pulse. In this embodiment, an ADC connected to the sensor 404 converts the data sensed by the sensor 404 from analog to digital format at the time of the falling edge of each pulse of the synchronization signal 614 received by the ADC. The ADC converts the data sensed by the sensor 404 for a fixed time after the falling edge of the pulse of the synchronization signal 614. For example, the ADC converts the data sensed by the sensor 404 for a fixed time between times t2 and t3 after the falling edge of pulse 614-1 is received by the ADC. The fixed time begins at time t2. The ADC stops sampling the data sensed by the sensor 404 after the fixed time until the falling edge of the next successive pulse of the synchronization signal 614, such as pulse 614-2, is received by the ADC. The ADC continues to convert data sensed by sensor 404 for a fixed time period after the falling edge of pulse 614-2. For example, suppose pulse 614-2 transitions from logic level 1 to logic level 0 at time t7 instead of transitioning at time t6. The ADC converts data sensed by sensor 404 starting at time t7 until the fixed time period is reached.

[0232] 7 is a diagram of one embodiment of a system 700 to illustrate the use of one, e.g., a single EtherCAT train, instead of multiple EtherCAT trains, to transfer the pulsed preset signal 138 from the module controller to the bias match. System 700 includes the same components as system 400 of FIG. 4, except that system 700 does not use communication cable 126 connecting the TCP generator to bias generator 1. Rather, system 700 includes communication cable 702 connecting the TCP generator to the TCP match, communication cable 704 connecting the TCP match to bias generator 1, and communication cable 708 connecting bias generator 2 to the bias match.

[0233] Furthermore, the TCP generator includes a sensor 710, the bias generator 1 includes a sensor 712, and the bias generator 2 includes a sensor 714. An example of each of the sensors 710, 712, and 714 is a voltage sensor, a current sensor, a complex voltage-current sensor, or a power sensor. For example, the data sensed by each of the sensors 710, 712, and 714 includes a voltage value, a current value, a power value, or a complex current-voltage value. The pulse controller is connected to the TCP generator via a transfer cable 716, to the bias generator 1 via a transfer cable 718, and to the bias generator 2 via a transfer cable 720.

[0234] Also in system 700, pulsed preset signal 138 includes the same instructions as those included in factor control signal 415 (FIG. 4). For example, pulsed preset signal 138 includes instructions to a controller in TCP match to change a factor of the TCP match to achieve a predetermined factor. Pulsed preset signal 138 further includes another instruction to a controller in bias match to change a factor of the bias match to achieve a preset factor.

[0235] The pulsed preset signal 138 is transmitted from the TCP generator to the TCP match via communication cable 702. Upon receiving the pulsed preset signal 138, the TCP match applies instructions to modify the factors of the TCP match to achieve the predetermined factors and transmits the pulsed preset signal 138 to the bias generator 1 via communication cable 704. The bias generator 1 applies the same functions to the pulsed preset signal 138 as described above with respect to FIG. 1 and transmits the pulsed preset signal to the bias generator 2 via communication cable 128. The bias generator 2 applies the same functions to the pulsed preset signal 138 as described above with respect to FIG. 1 and transmits the pulsed preset signal 138 to the bias match via communication cable 708.

[0236] Upon receiving the pulsed preset signal 138, the bias match applies instructions to change the bias match factors to achieve the preset factors. Also, upon receiving the pulsed preset signal 138 from the bias generator 2, the match controller of the bias match receives and collects data sensed by the sensor 404 in the manner described above with reference to FIG. 4. The collected data is accessed by the match controller of the bias match. The collected data is then embedded into the pulsed preset signal 138 by the bias match. After embedding the data, the bias match transmits the pulsed preset signal 138 to the bias generator 2 via the communication cable 708.

[0237] The pulse controller generates a synchronization signal 724 and transmits the synchronization signal 724 to the TCP generator via the transmission cable 716. Similarly, the pulse controller generates a synchronization signal 726 and transmits the synchronization signal 726 to the bias generator 1 via the transmission cable 718. The pulse controller also generates a synchronization signal 728 and transmits the synchronization signal 728 to the bias generator 2 via the transmission cable 720.

[0238] In response to receiving the synchronization signal 728, the controller in the bias generator 2 controls the ADC of the bias generator 2 to collect data sensed by the sensor 714 in synchronization with the synchronization signal 728. The collected data is transmitted from the bias generator 2 to the bias generator 1 via the communication cable 128 to send the collected data back to the pulse controller. For example, the synchronization signal 728 includes a series of pulses including a first pulse and a second pulse. In response to receiving the first pulse of the synchronization signal 728 for the first time interval, the controller of the bias generator 2 controls the ADC connected to the sensor 714 to convert the data sensed by the sensor 714 from analog to digital format for the first time interval and output the digital data for the first time interval. The controller of the bias generator 2 receives the digital data output from the ADC for the first time interval and stores the digital data in the memory device of the controller. When the pulsed preset signal 138 is received from the bias match, the controller accesses the digital data for the first time interval from the memory device. The digital data for the first time interval is embedded in a pulsed preset signal 138 and transmitted to the bias generator 1 via the communication cable 128. Similarly, in response to receiving the second pulse of the synchronization signal 728 for the second time interval, the controller of the bias generator 2 controls the ADC connected to the sensor 714 to convert the data sensed by the sensor 714 from analog to digital format for the second time interval and output the digital data for the second time interval. The controller of the bias generator 2 receives the digital data output for the second time interval from the ADC of the bias generator 2 and stores the digital data in the memory device of the controller. When the pulsed preset signal 138 is received from the bias match, the controller of the bias generator 2 accesses the digital data for the second time interval from the memory device of the bias generator 2. The digital data for the second time interval is embedded in the pulsed preset signal 138 and transmitted to the bias generator 1 via the communication cable 128.During the time intervals when no pulses of the synchronization signal 728 are received by the bias generator 2, the controller of the bias generator 2 does not control the ADC of the bias generator 2 to convert the data sensed by the sensor 714 from analog to digital format.

[0239] Similarly, in response to receiving the synchronization signal 726, the controller within the bias generator 1 controls the ADC of the bias generator 1 to collect data sensed by the sensor 712 in synchronization with the synchronization signal 726. The collected data is then transmitted to the TCP match via the communication cable 704 to send the collected data back to the pulse controller. For example, the synchronization signal 726 includes a series of pulses including a first pulse and a second pulse. In response to receiving the first pulse of the synchronization signal 726 for the first time interval, the controller of the bias generator 1 controls the ADC connected to the sensor 712 to convert the data sensed by the sensor 712 from analog format to digital format for the first time interval and output the digital data for the first time interval. The controller of the bias generator 1 receives the digital data output from the ADC for the first time interval and stores the digital data in the memory device of the controller. When the pulsed preset signal 138 is received from the bias generator 2, the controller accesses digital data for the first time interval from the memory device and embeds the digital data into the pulsed preset signal 138, which is transmitted to the TCP match via the communication cable 704. Similarly, in response to receiving the second pulse of the synchronization signal 726 for the second time interval, the controller of the bias generator 1 controls the ADC connected to the sensor 712 to convert the data sensed by the sensor 712 from analog to digital format for the second time interval and output the digital data for the second time interval. The controller of the bias generator 1 receives the digital data output for the second time interval from the ADC of the bias generator 1 and stores the digital data in the memory device of the controller. When the pulsed preset signal 138 is received from the bias generator 1, the controller of the bias generator 1 accesses digital data for the second time interval from the memory device of the bias generator 1 and embeds the digital data into the pulsed preset signal 138, which is transmitted to the TCP match via the communication cable 704.During the time intervals when no pulses of the synchronization signal 726 are received by the bias generator 1, the controller of the bias generator 1 does not control the ADC of the bias generator 1 to convert the data sensed by the sensor 712 from analog to digital format.

[0240] When the pulsed preset signal 138 is received from the bias generator 1, the match controller of the TCP match accesses the data sensed by the sensor 402 from the memory device of the match controller. The accessed data is embedded in the pulsed preset signal 138 by the TCP match and transmitted to the TCP generator via the communication cable 702.

[0241] In response to receiving the synchronization signal 724, the controller in the TCP generator controls the ADC of the TCP generator to collect data sensed by the sensor 710 in synchronization with the synchronization signal 724. The collected data is transmitted from the TCP generator to the pulse controller. For example, the synchronization signal 724 includes a series of pulses including a first pulse and a second pulse. In response to receiving the first pulse of the synchronization signal 724 for the first time interval, the controller of the TCP generator controls the ADC connected to the sensor 710 to convert the data sensed by the sensor 710 from analog to digital format for the first time interval and output digital data for the first time interval. The controller of the TCP generator receives the digital data output from the ADC for the first time interval and stores the digital data in the controller's memory device. When the pulsed preset signal 138 is received from the TCP generator, the controller of the TCP generator accesses the digital data for the first time interval from the memory device. The digital data for the first time interval is embedded within the pulsed preset signal 138 and transmitted to the pulse controller via the communication cable 118. Similarly, in response to receiving a second pulse of the synchronization signal 724 for the second time interval, the controller of the TCP generator controls the ADC of the TCP generator to convert the data sensed by the sensor 710 from analog to digital format for the second time interval and output the digital data for the second time interval. The controller of the TCP generator receives the digital data output from the ADC for the second time interval and stores the digital data in the memory device of the controller. When the pulsed preset signal 138 is received from the TCP match, the controller accesses the digital data for the second time interval from the memory device. The digital data for the second time interval is embedded within the pulsed preset signal 138 and transmitted to the pulse controller via the communication cable 118. During time intervals when a pulse of the synchronization signal 724 is not received by the TCP generator, the controller of the TCP generator does not control the ADC to convert the data sensed by the sensor 710 from analog to digital format.

[0242] In response to receiving data sensed by one or more of sensors 710, 402, 712, 714, and 404, the pulse controller controls one or more of the components, such as the TCP generator, bias generator 1, bias generator 2, TCP match, and bias match. For example, upon determining that the reflected power sensed by sensor 710 is high, the pulse controller controls the TCP generator to alter the power level of RF signal 102 (FIG. 1) to decrease the amount of power supplied by the TCP generator.

[0243] In one embodiment, the sensor 710 is located outside the TCP generator and connected to the output O1 of the TCP generator.

[0244] In one embodiment, the sensor 712 is located outside the bias generator 1 and connected to the output O3 of the bias generator 1.

[0245] In one embodiment, the sensor 714 is located outside the bias generator 2 and is connected to the output O4 of the bias generator 2.

[0246] In one embodiment, functions described herein as being performed by a controller are performed by a processor in the controller.

[0247] In one embodiment, system 700 does not include one or more of sensors 710 , 712 , and 714 .

[0248] Figure 8 is a diagram of an embodiment of a system 800 to illustrate that sensor data is transmitted from the sensors to the pulse controller over an Ethernet cable rather than via an EtherCAT train. System 800 is similar in structure and function to system 300 of Figure 3, except that system 800 includes sensors 402 and 404, a voltage sensor system 410, and an OES system 412. System 800 further includes an Ethernet cable 802 connecting the TCP match to the pulse controller, another Ethernet cable 804 connecting the bias match to the pulse controller, an Ethernet cable 806 connecting the voltage sensor system 410 to the pulse controller, and another Ethernet cable 808 connecting the OES system 412 to the pulse controller.

[0249] Transfer cable 414 In response to receiving the synchronization signal 416 via the Ethernet cable 802, the ADC connected to the sensor 402 converts the data sensed by the sensor 402 from analog format to digital format in synchronization with the pulse of the synchronization signal 416, outputs the digital measurement data, and provides the digital measurement data to the match controller of the TCP match. The match controller of the TCP match transmits the digital measurement data to the pulse controller via the Ethernet cable 802.

[0250] Similarly, upon receiving the synchronization signal 418 through the transmission cable 417, the ADC connected to the sensor 404 converts the data sensed by the sensor 404 from analog to digital form in synchronization with the pulse of the synchronization signal 418, and outputs the digital measurement data. bias The bias match controller sends the digital measurement data to the pulse controller via an Ethernet cable 804.

[0251] Also, in response to receiving the synchronization signal 426 via the transfer cable 420, the ADC of the voltage sensor system 410 converts the data sensed by the voltage sensor of the voltage sensor system 410 from analog format to digital format in synchronization with the pulse of the synchronization signal 426, outputs the digital measurement data, and transmits the digital measurement data to the controller of the voltage sensor system 410. The controller of the voltage sensor system 410 transmits the digital measurement data to the pulse controller via the Ethernet cable 806.

[0252] Similarly, upon receiving synchronization signal 428 via transfer cable 422, the ADC of OES system 412 converts data sensed by the OES of OES system 412 from analog format to digital format in synchronization with the pulse of synchronization signal 428, outputs digital measurement data, and sends the digital measurement data to the controller of OES system 412. The controller of OES system 412 sends the digital measurement data to the pulse controller via Ethernet cable 808.

[0253] In one embodiment, the TCP generator includes a sensor 710 (FIG. 7) and is connected to a pulse controller via an Ethernet cable. Upon receiving multiple pulses of a synchronization signal 724 (FIG. 7) via a transmission cable 716 (FIG. 7), the ADC of the TCP generator converts data sensed by the sensor 710 from analog to digital format in synchronization with the pulses and outputs digital measurement data. The TCP generator transmits the digital measurement data to the pulse controller via the Ethernet cable.

[0254] In one embodiment, bias generator 1 includes sensor 712 (FIG. 7) and is connected to a pulse controller via an Ethernet cable. Upon receiving multiple pulses of synchronization signal 726 (FIG. 7) via transfer cable 718 (FIG. 7), the ADC of bias generator 1 converts data sensed by sensor 712 from analog to digital format in synchronization with the pulses and outputs digital measurement data. Bias generator 1 transmits the digital measurement data to the pulse controller via the Ethernet cable.

[0255] In one embodiment, bias generator 2 includes sensor 714 (FIG. 7) and is connected to the pulse controller via an Ethernet cable. Upon receiving multiple pulses of synchronization signal 728 via transfer cable 720 (FIG. 7), the ADC of bias generator 2 converts data sensed by sensor 714 from analog to digital format in synchronization with the pulses and outputs digital measurement data. Bias generator 2 transmits the digital measurement data to the pulse controller via the Ethernet cable.

[0256] In one embodiment, a connecting cable is used in place of each of the Ethernet cables 802 and 804 .

[0257] In one embodiment, instead of the Ethernet cables for each sensor of the RF generator described herein, a connecting cable is used to transfer digital measurement data from the RF generator to the pulse controller.

[0258] FIG. 9 is a diagram of an embodiment of an RF generator 900 to illustrate components of the RF generator 900. The RF generator 900 is an example of a TCP generator, a bias generator 1, or a bias generator 2 (FIG. 1). The RF generator 900 includes a communication controller 902 and a digital signal processor (DSP) 904. The RF generator 900 further includes multiple parameter controllers. For example, the RF generator 900 includes a parameter controller for each state. For example, the RF generator 900 includes a parameter controller PCS0 for a state S0 of the RF signal 906 generated by the RF generator 900 and a parameter controller PCSn for a state Sn of the RF signal 906, where n is a positive integer. Examples of parameters include power and voltage. As another example, the RF generator 900 includes a frequency controller for each state. Illustratively, RF generator 900 includes a frequency controller FCS0 for state S0 of RF signal 906 and a parameter controller FCSn for state Sn of RF signal 906.

[0259] RF signal 906 is an example of RF signal 102, 104, or 106 (FIG. 1). For example, if RF generator 900 is a TCP generator, RF signal 906 is an example of RF signal 102, and if RF generator 900 is a bias generator 1, RF signal 906 is an example of RF signal 104.

[0260] The RF generator 900 includes a driver system 908, which includes one or more drivers connected to each other. An example of each driver is a transistor. The RF generator 900 includes a power supply 910, such as an electronic oscillator or RF oscillator, that generates a sinusoidal RF signal or a sinusoidal RF waveform. The RF generator 900 also includes a sensor 912 and an ADC 914. 914 Sensor 912 is an example of sensor 710, sensor 712, or sensor 714 (FIG. 7).

[0261] The DSP 904 is connected to the communication controller 902, the parameter controllers PCS0-PCSn, and the frequency controllers FCS0-FCSn. The DSP 904 is connected to a transfer cable 916. The transfer cable 916 is an example of the transfer cable 120, the transfer cable 122, or the transfer cable 124 (FIG. 1). The DSP 904 is connected to another transfer cable 918, which is an example of the transfer cable 716 (FIG. 7), the transfer cable 718 (FIG. 7), or the transfer cable 720 (FIG. 7).

[0262] The controllers PRS0 to PRSn and the frequency controllers FCS0 to FCSn are connected to a driver system 908, which is connected to a power supply 910. The output of the power supply 910 is connected to a sensor 912. The sensor 912 is connected to an ADC 914, which is connected to the DSP 904.

[0263] The communication controller 902 includes a port 920 and a port 922. The port 920 is connected to a communication cable 924, and the port 922 is connected to a communication cable 926. When the RF generator 900 is a TCP generator, the communication cable 924 is an example of the communication cable 118 (FIG. 1), and the communication cable 926 is an example of the communication cable 126 (FIG. 1). When the RF generator 900 is a bias generator 1, the communication cable 924 is an example of the communication cable 126 (FIG. 1), and the communication cable 926 is an example of the communication cable 128 (FIG. 1). When the RF generator 900 is a bias generator 1, the communication cable 924 is an example of the communication cable 704 (FIG. 7), and the communication cable 926 is an example of the communication cable 128 (FIG. 7). When the RF generator 900 is a bias generator 2, the communication controller 902 includes a port 920 and a port 922. The port 920 is connected to a communication cable 924, and the port 922 is connected to a communication cable 926. When the RF generator 900 is a TCP generator, the communication cable 924 is an example of the communication cable 118 (FIG. 1), and the communication cable 926 is an example of the communication cable 126 (FIG. 1). When the RF generator 900 is a bias generator 2, the communication controller 902 includes a port 920 and a port 922. ... cable 924 is an example of the communication cable 126 (FIG. 1), and the communication cable 926 is an example of the communication cable 1 922 , and communication cable 924 is an example of communication cable 128 (FIGS. 1 and 7).

[0264] The communications controller 902 receives the pulsed preset signal 138 via port 920 and determines whether the address in the pulsed preset signal 138 matches a pre-stored address of the RF generator 900. The pre-stored address is stored in one or more memory devices of the communications controller 902. A module controller or pulse controller (FIG. 1) embeds the address of the RF generator 900 in the pulsed preset signal 138. If the communications controller 902 determines that the address in the pulsed preset signal 138 matches the pre-stored address of the RF generator 900, the communications controller 902 extracts information about the duty cycle and variables of the RF signal 906 and sends the information about the duty cycle and variables to the DSP 904. The communications controller 902 also extracts information about the fraction of a cycle of the master clock signal 141 during which the multiple states of the RF signal 906 are generated and provides the information to the DSP 904.

[0265] The DSP 904 identifies, from the information regarding the duty cycle and the variable, information regarding the duty cycle and parameter level for each state of the parameter of the RF signal 906, and further identifies information regarding the duty cycle and frequency level for each state of the frequency of the RF signal 906. The DSP 904 transmits the duty cycle and parameter level for state S0 to parameter controller PRSO for storage in one or more memory devices of parameter controller PRSO, and transmits the duty cycle and parameter level for state Sn to parameter controller PRSn for storage in one or more memory devices of parameter controller PRSn. The DSP 904 also transmits the duty cycle and parameter level for state S0 to parameter controller PRSO for storage in one or more memory devices of frequency controller FCS0. Ru and The frequency controller FCSn transmits the duty cycle and frequency level for state Sn to frequency controller FCS0 and transmits the duty cycle and frequency level for state Sn to frequency controller FCSn for storage in one or more memory devices of frequency controller FCSn.

[0266] When a pulse of the synchronization signal 928 is received via the transmission cable 916, the DSP 904 transmits the pulse to the parameter controllers PRSO-PCSn and the frequency controllers FCS0-FCSn. The synchronization signal 928 is an example of the synchronization signal 140, 142, or 144 (FIG. 1). Upon receiving the pulse of the synchronization signal 928, the parameter controller PRSO generates a current signal for the time interval of the duty cycle of the state S0 based on the parameter level for the state S0 of the RF signal 906, and transmits the current signal to the driver system 908. Also, upon receiving the pulse of the synchronization signal 928, the frequency controller FCS0 generates a current signal for the time interval of the duty cycle of the state S0 based on the frequency level for the state S0 of the RF signal 906, and transmits the current signal to the driver system 908. Upon receiving the current signals for the state S0 from the controllers PCS0 and FCS0, the driver system 908 generates a current signal for the state S0 and transmits the current signal to the power supply 910. Upon receiving the current signal, the power supply 910 generates the parameters and frequency state S0 of the RF signal 906 .

[0267] Similarly, upon receiving a pulse of the synchronization signal 928, the parameter controller PRSn generates a current signal for the time interval of the duty cycle of the state Sn based on the parameter level for the state Sn of the RF signal 906, and transmits the current signal to the driver system 908. Also, upon receiving a pulse of the synchronization signal 928, the frequency controller FCSn generates a current signal for the time interval of the duty cycle of the state Sn based on the frequency level for the state Sn of the RF signal 906, and transmits the current signal to the driver system 908. Sn The synchronization signal 928 generates a current signal for the time interval of the duty cycle of the RF signal 906 and transmits the current signal to the driver system 908. Upon receiving the current signal for the state Sn from the controllers PCSn and FCSn, the driver system 908 generates a current signal for the state Sn and transmits the current signal to the power supply 910. Upon receiving the current signal, the power supply 910 generates the parameter and frequency state Sn of the RF signal 906. Similarly, for each additional pulse of the synchronization signal 928, the parameter and frequency states S0 through Sn of the RF signal 906 are generated by the power supply 910.

[0268] It should be noted that during time intervals when a pulse of the synchronization signal 928 is not received by the DSP 904, the states of the variables of the RF signal 906 are not generated by the power supply 910. For example, during time intervals when the synchronization signal 928 does not contain a pulse, the DSP 904 does not control the controllers PCS0-PCSn and the frequency controllers FCS0-FCSn to generate the states S0-Sn of the variables of the RF signal 906 ... 906 has a power level of 0 during time intervals when the synchronization signal 928 does not contain a pulse.

[0269] Based on information about the fraction of a cycle of the master clock signal 141 during which the states of the RF signal 906 are generated, the DSP 904 transmits different variable levels and different duty cycles to the controllers PCS0-PCSn and FCS0-FCSn. For example, if the DSP 904 determines that the count of the number of pulses of the synchronization signal 928 has been exceeded, the DSP 904 transmits a different variable and a different duty cycle to the controllers PCS0-PCSn and FCS0-FCSn than it transmitted before the count was exceeded. As another example, if the DSP 904 determines that the time interval for cycle 1 after receiving a pulse of the synchronization signal 928 has elapsed, the DSP 904 transmits a different variable and a different duty cycle to the controllers PCS0-PCSn and FCS0-FCSn than it transmitted before the time interval elapsed.

[0270] When the RF signal 906 is generated, the sensor 912 senses data, such as voltage, current, complex voltage-current sensor, or power, at the output of the power supply 910 and provides the measurement data to the ADC 914. The DSP 904 receives a synchronization signal 930 via a transmission cable 918 and transmits the synchronization signal 930 to the ADC 914. During the time intervals when a pulse of the synchronization signal 930 is received, the ADC 914 converts the measurement data from analog to digital format, outputs the digital measurement data, and transmits the digital measurement data to one or more memory devices of the DSP 904. During the time intervals when the synchronization signal 930 does not have a pulse, the ADC 914 does not convert the measurement data from analog to digital format, and no digital measurement data is output from the ADC 914. The synchronization signal 930 is an example of the synchronization signal 724, 726, or 728 (FIG. 7).

[0271] The pulsed preset signal 138 is 920 The pulsed preset signal 138 is received by the communication controller 902 at port 920 From port 922 While being transferred to the DSP 904, the communications controller 902 sends a request to the DSP 904 for the digital measurement data stored in one or more memory devices of the DSP 904. Upon receiving the request, the DSP 904 accesses the digital measurement data from one or more memory devices of the DSP 904 and sends the digital measurement data to the communications controller 902. The communications controller 902 embeds the digital measurement data in a pulsed preset signal 138 and transmits the digital measurement data to the port 904. 922 via communication cable 926 , and transmits a pulsed preset signal 138 to the

[0272] In an embodiment in which communications controller 902 includes port 920 but not port 922, pulsed preset signal 138 is received at port 920 and routed back to port 920 via communications controller 902. While pulsed preset signal 138 is routed back to port 920, a request for digital measurement data is generated by communications controller 902, and the received digital measurement data is embedded within pulsed preset signal 138.

[0273] In one embodiment, functions described herein as being performed by a communications controller are performed by a processor in the communications controller.

[0274] In embodiments where one or more Ethernet cables are used for point-to-point communication, the one or more Ethernet cables are connected to the DSP 904. In this embodiment, the RF generator 900 does not include a communication controller 902 used to generate the EtherCAT train, but does include a communication controller for generating Ethernet packets and for extracting information from the Ethernet packets.

[0275] In one embodiment, the DSP 904 is an example of a controller.

[0276] In one embodiment, the functions described herein as being performed by DSP 904, controllers PCS0-PCSn, and controllers FCS0-FCSn are performed by one or more controllers.

[0277] In one embodiment, there is a switch connected to the DSP 904, such as one or more transistors connected to each other. The switch connects the ADC 914 to the sensor 912. Upon receiving a pulse of the synchronization signal 928, the DSP 904 controls the switch to turn on. Turning on the switch allows the ADC 914 to acquire data from the sensor 912 and convert the data from analog to digital format. For example, the DSP 904 controls the switch to turn on for a certain period of time starting from the time the pulse of the synchronization signal 928 is received by the DSP 904. After the certain period of time, the DSP 904 controls the switch to turn off. Turning the switch off prevents the ADC 914 from receiving data sensed by the sensor 912 and converting the data from analog to digital format. As another example, the DSP 904 controls the switch to turn on for a time interval during which the pulse of the synchronization signal 928 has a logic level 1. At the time the pulse transitions to a logic level 0, the DSP 904 controls the switch to turn off.

[0278] 10 is a diagram of one embodiment of a controller 1000, which is an example of a pulse controller or module controller (FIG. 1). The controller 1000 includes a processor 1002, a memory device 1004, and a communication controller 1006. The processor 1002 is connected to the memory device 1004 and the communication controller 1006. The communication controller 1006 includes a port 1008 and another port 1010.

[0279] Port 1008 is connected to communication cable 1012, and port 1010 is connected to another communication cable 1014. Note that if controller 1000 is a module controller, communication controller 1006 does not include port 1008. Also, if communication controller 1006 is a module controller, communication cable 1014 is an example of communication cable 116 (FIG. 1). If communication controller 1006 is a pulse controller, communication cable 1012 is an example of communication cable 116, and communication cable 1014 is an example of communication cable 118 (FIG. 1). Processor 1002 is connected to transfer cable 1016, which is an example of transfer cable 120, 122, 124, 414, 417, 420, or 422 (FIG. 4), or 716, 718, or 720 (FIG. 7).

[0280] If the controller 1000 is a module controller, the communication controller 1006 The processor 1002 generates a preset signal 1020, such as the pulsed preset signal 138 (FIG. 1) or the factor control signal 415 (FIG. 4), and transmits the preset signal 1020 to the pulse controller via the communication cable 1014. For example, the processor 1002 receives information regarding the duty cycle and variables of the RF signals 102, 104, and 106 from a user via an input device and provides the information to the communication controller 1006. The communication controller 1006 embeds the information received from the processor 1002 into an EtherCAT train and transmits the EtherCAT train to the pulse controller via the communication cable 1014. The communication controller 1002 further embeds addresses of one or more components of the system 400 to which the EtherCAT train is transmitted. Examples of components of the system 400 include a TCP generator, a bias generator 1, a bias generator 2, a TCP match, and a bias match. Examples of input devices include a mouse, a keyboard, a touch screen, and a stylus. The input devices are connected to the processor 1002.

[0281] As another example, the processor 1002 receives a predetermined factor for the TCP match and a preset factor for the bias match from an input device, and generates an instruction for the match controller in the TCP match to change the factor to achieve the predetermined factor and an instruction for the match controller in the bias match to change the factor of the bias match to achieve the preset factor. The processor 1002 provides the instruction for the match controller in the TCP match to change the factor to achieve the predetermined factor and the instruction for the match controller in the bias match to change the factor of the bias match to achieve the preset factor to the communication controller 1006. The communication controller 1006 embeds the instruction received from the processor 1002 and the addresses of the components of the system 400 in an EtherCAT train. Examples of components of the system 400 to which an EtherCAT train, such as the factor control signal 415, is transmitted include the TCP match and the bias match. The communication controller 1006 transmits the EtherCAT train to the pulse controller via the communication cable 1014.

[0282] When the communication controller 1000 is a pulse controller, the communication controller 1000 1008 10, the communication controller 1000 receives the pulsed preset signal 138 or the factor control signal 415 from the module controller via the communication cable 1012. The communication controller 1000 transmits the pulsed preset signal 138 or the factor control signal 415 via the port 1010 and the communication cable 1014.

[0283] In one embodiment where the controller 1000 is a pulse controller and one or more Ethernet cables are used for point-to-point communication, the Ethernet cables are connected to the processor 1002. Also in this embodiment, the controller 1000 does not include a communication controller 1006 used to generate the EtherCAT train, but does include a communication controller for generating Ethernet packets and for extracting information from the Ethernet packets.

[0284] If the controller 1000 is a pulse controller, the processor 1002 generates a synchronization signal 1018 and transmits the synchronization signal 1018 via a transmission cable 1016. The synchronization signal 1018 is an example of synchronization signal 140, 142, 144, 416, 418, 426, or 428 (FIG. 4), or 724, 726, or 728 (FIG. 7).

[0285] In one embodiment, the communication controller 1000 includes a third port connected to a third communication cable over which the factor control signal 415 is transmitted.

[0286] In one embodiment, controller 1000 includes any number of processors and any number of memory devices, and the processors are coupled to the memory devices, and perform the same functions as those performed by processor 1002.

[0287] 11 is a diagram of one embodiment of a match 1100, which is an example of a TCP match or a bias match (FIG. 1). Match 1100 includes a communication controller 1102, a processor 1104, a memory device 1106, a driver system 1108, a motor system 1110, a network of circuit components 1112, an ADC 1114, and a sensor 1116. Processor 1104 and memory device 1106 are components of a match controller 1117 of match 1100. Sensor 1116 is an example of sensor 402 or 404 (FIG. 4). Communication controller 1102 includes a port 1118 and another port 1120.

[0288] The driver system 1108 includes one or more drivers connected to each other. The motor system 1110 includes one or more electric motors. Each motor is connected to a circuit component, such as a variable inductor or a variable capacitor, of the match 1100. The network 1112 includes circuit components, such as resistors, capacitors, or inductors, or a combination thereof.

[0289] The processor 1104 is connected to the memory device 1106 and the communication controller 1102. The processor 1104 is also connected to a driver system 1108, which is connected to a motor system 1110. The ADC 1114 is connected to the sensor 1116 and the processor 1104.

[0290] Processor 1104 is connected to transmission cable 1126. Transmission cable 1126 is an example of transmission cable 414 or 417 (FIG. 4). Port 1118 is connected to communication cable 1122, and port 1120 is connected to communication cable 1124. If match 1100 is a TCP match, communication cable 1122 is an example of communication cable 406, and communication cable 1124 is an example of communication cable 408 (FIG. 4). If match 1100 is a bias match, communication controller 1102 does not include port 1120. Also, if match 1100 is a bias match, communication cable 1122 is an example of communication cable 408.

[0291] The sensor 1116 is connected to the network 1112. For example, the sensor 1116 is connected to an input of the network 1112 or an output of the network 1112. For example, if the network 1112 includes a single branch circuit connected to a single RF generator, such as a TCP generator, the sensor 1116 is connected to an input of the signal branch circuit, and the input is between the RF generator and the single branch circuit. As another example, if the network 1112 includes a single branch circuit connected to a single RF generator, such as a TCP generator, the sensor 1116 is connected to an output of the signal branch circuit, and the output is between the single branch circuit and the plasma chamber 108 ( FIG. 1 ). As yet another example, if the network 1112 includes a first branch circuit connected to bias generator 1 and a second branch circuit connected to bias generator 2, the sensor 1116 is connected to the outputs of the first and second branch circuits, to the input of the first branch circuit, or to the input of the second branch circuit. The input of the first branch circuit is between the first branch circuit and bias generator 1, and the input of the second branch circuit is between the second branch circuit and bias generator 2. The first and second branches are connected to each other at their outputs, which are connected to the substrate support 110 (FIG. 1) via RF transmission line 139 (FIG. 1).

[0292] The communication controller 1102 receives a preset signal 1128, such as the pulsed preset signal 138 or the factor control signal 415, via the communication cable 1122 and the port 1118 and determines whether the address in the preset signal 1128 matches a pre-stored address of the match 1100. The pre-stored address is stored in one or more memory devices of the communication controller 1102. The module controller or pulse controller (FIG. 1) embeds the address of the match 1100 in the preset signal 1128. If the communication controller 1102 determines that the address in the preset signal 1128 matches the pre-stored address of the match 1100, the communication controller 1102 extracts instructions for implementing pre-fixed factors, such as instructions for implementing predetermined factors or instructions for implementing preset factors, from the preset signal 1128 and transmits the instructions to the processor 1104.

[0293] The processor 1104 identifies the pre-fixed factor from the instruction. The processor 1104 generates and transmits a control signal to execute the instruction to realize the pre-fixed factor and transmits the control signal to the driver system 1108. Upon receiving the control signal, the driver system 1108 generates a drive signal and transmits the drive signal to the motor system 1110. The motor of the motor system 1110 operates based on the drive signal. When the motor operates, the circuit components of the network 1112 are controlled to realize the pre-fixed factor. For example, when the motor operates, a plate of a variable capacitor moves relative to another plate of the variable capacitor to realize the pre-fixed capacitance.

[0294] If match 1100 is a TCP match, communication controller 1102 determines to send a preset signal 1128 to the bias match. The determination is made based on a comparison of the address of the bias match in preset signal 1128 with a pre-stored address of the bias match. The pre-stored address of the bias match is stored in one or more memory devices of communication controller 1102. Communication controller 1102 sends preset signal 1128 to the bias match via port 1120 and communication cable 1124.

[0295] The sensor 1116 measures voltage, current, complex voltage and current. Flow, Alternatively, it senses data such as power and provides the measurement data to the ADC 1114. 1104 receives a synchronization signal 1130 via the transfer cable 1126 and transmits the synchronization signal 1130 to the ADC 1114. During the time interval when a pulse of the synchronization signal 1130 is received, the ADC 1114 converts the measurement data from analog format to digital format, outputs the digital measurement data, and transmits the digital measurement data to the processor 1104 for storage in the memory device 1106. For example, the processor 1104 collects, e.g., stores or writes, the digital measurement data received from the ADC 1114 to the memory device 1106. Also, during the time interval when the synchronization signal 1130 does not have a pulse, the ADC 1114 does not convert the measurement data from analog format to digital format, and the digital measurement data is not output from the ADC 1114. The synchronization signal 1130 is an example of the synchronization signal 416 or 418 (FIG. 4).

[0296] The pulsed preset signal 1128 is 1118 The pulsed preset signal 1128 is received by the communication controller 1102 at port 1118 From port 1120While being transferred to the port, the communication controller 1102 sends a request to the processor 1104 for the digital measurement data stored in the memory device 1106. Upon receiving the request, the processor 1104 accesses the digital measurement data from the memory device 1106 and sends the digital measurement data to the communication controller 1102. The communication controller 1102 embeds the digital measurement data in a pulsed preset signal 1128 and transmits the digital measurement data to the port. 1120 via communication cable 1124 Pulsed preset signal 1128 Send.

[0297] In an embodiment in which communications controller 1102 includes port 1118 but not port 1120, pulsed preset signal 1128 is received at port 1118 and routed back to port 1118 via communications controller 1102. While pulsed preset signal 1128 is routed back to port 1118, a request for digital measurement data stored in memory device 1106 is generated by communications controller 1102. The digital measurement data is received by communications controller 1102 and embedded within pulsed preset signal 1128.

[0298] In embodiments where one or more Ethernet cables are used for point-to-point communication, the Ethernet cables are connected to the processor 1104. In this embodiment, the match 1100 does not include a communication controller 1102 used to generate the EtherCAT train, but does include a communication controller for generating Ethernet packets and for extracting information from the Ethernet packets.

[0299] In one embodiment, the sensor 1116 is located on the outside of the match 1110 .

[0300] In one embodiment, the processor 1104, the memory device 1106, the ADC 1114, and the sensor 1116 are components of a sensor system.

[0301] In one embodiment, there is a switch connected to the processor 1104, such as one or more transistors connected to each other. The switch connects the processor 1104 to the sensor 1116. Upon receiving a pulse of the synchronization signal 1130, the processor 1104 controls the switch to turn on. Turning on the switch allows the ADC 1114 to acquire data from the sensor 1116 and convert the data from analog to digital format. For example, the processor 1104 controls the switch to turn on for a certain period of time starting from the time the pulse of the synchronization signal 1130 is received by the processor 1104. After the certain period of time, the processor 1104 controls the switch to turn off. Turning off the switch prevents the ADC 1114 from receiving data sensed by the sensor 1116 and converting the data from analog to digital format. As another example, the processor 1104 controls the switch to turn on for a time interval during which the pulse of the synchronization signal 1130 has a logic level 1. At the time the pulse transitions to logic level 0, the processor 1104 controls the switch to turn it off.

[0302] FIG. 12 is a diagram of one embodiment of a sensor system 1200, which may be an OES system 412 (FIG. 4) or a voltage sensor system. 410 4. The sensor system 1200 includes a processor 1202, a memory device 1204, an ADC 1206, and a sensor 1208. The sensor 1208 may be an OES or voltage sensor system of the OES system 412. 410 The processor 1202 and memory device 1204 are components of a controller 1203 of the sensor system 1200.

[0303] The processor 1202 is connected to a transmission cable 1210, which is an example of the transmission cable 420 or 422 (FIG. 4). The processor 1202 is connected to a memory device 1204 and an ADC 1206, which is connected to the sensor 1208.

[0304] The sensor 1208 senses data such as voltage or intensity and provides the measurement data to the ADC 1206. The processor 1202 receives a synchronization signal 1212 via a transmission cable 1210 and transmits the synchronization signal 1212 to the ADC 1206. During the time interval in which the pulse of the synchronization signal 1212 is received, the ADC 1206 converts the measurement data from analog to digital format, outputs digital measurement data, and transmits the digital measurement data to the processor 1202. The processor 1202 receives the synchronization signal 1212 via a transmission cable 1210. 1210 12. During the time intervals when synchronization signal 1212 does not have a pulse, ADC 1206 does not convert the measurement data from analog to digital format, and no digital measurement data is output from ADC 1206. Synchronization signal 1212 is an example of synchronization signal 426 or 428 (FIG. 4).

[0305] In one embodiment, there is a switch connected to the processor 1202, such as one or more transistors connected to each other. The switch connects the processor 1202 to the sensor 1208. Upon receiving a pulse of the synchronization signal 1212, the processor 1202 controls the switch to turn on. Turning on the switch allows the ADC 1206 to acquire data from the sensor 1208 and convert the data from analog to digital format. For example, the processor 1202 controls the switch to turn on for a certain period of time starting from the time the pulse of the synchronization signal 1212 is received by the processor 1202. After the certain period of time, the processor 1202 controls the switch to turn off. Turning the switch off prevents the ADC 1206 from receiving data sensed by the sensor 1208 and converting the data from analog to digital format. As another example, the processor 1202 controls the switch to turn on for a time interval during which the pulse of the synchronization signal 1212 has a logic level 1. At the time the pulse transitions to logic level 0, the processor 1202 controls the switch to turn it off.

[0306] FIG. 13 shows a graph 1300 to illustrate a clock signal 1302. The clock signal 1302 is an example of the master clock signal 141 (FIG. 1). The graph 1300 plots the logic level of the clock signal 1302 on the y-axis and time t on the x-axis. The clock signal 1302 pulses from logic level 0 to logic level 1 at time t0 and remains at logic level 1 from time t0 to time t10. The clock signal 1302 pulses from logic level 1 to logic level 0 at time t10 for cycle 1 of the clock signal 1302 and remains at logic level 0 from time t10 to time t20. The clock signal 1302 pulses during cycle 2 of the clock signal 1302 in the same manner as during cycle 1 of the clock signal 1302. For example, clock signal 1302 pulses from logic level 0 to logic level 1 at time t20 and remains at logic level 1 from time t20 to time t30. Clock signal 1302 pulses from logic level 1 to logic level 0 at time t30. Clock signal 1302 remains at logic level 0 from time t30 to time t40, forming cycle 2 of clock signal 1302.

[0307] Note that clock signal 1302 differs from the synchronization signals described herein. For example, synchronization signal 202 (FIG. 2A) is periodic for one or more time intervals of each cycle of clock signal 130 and is not periodic for one or more remaining time intervals of the cycle. Illustratively, synchronization signal 202 pulses periodically for the time interval between times t0 and t16 of each cycle of clock signal 1302, and then stops pulsing for the remaining time interval between times t16 and t20 of the cycle. Clock signal 1302 is periodic in that it has one pulse during each cycle of clock signal 1302.

[0308] The embodiments described herein may be practiced with various computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network.

[0309] In some embodiments, the controller is part of a system, which may be part of the examples described above. Such systems include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as a wafer pedestal, gas flow system, etc.). These systems are integrated with electronics for controlling their operation before, during, and after semiconductor wafer or substrate processing. The electronics, sometimes referred to as a "controller," may control various components or subparts of one or more systems. The controller is programmed to control any of the processes disclosed herein, including process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, liquid delivery settings, position and motion settings, wafer transfer into and out of the tool, and wafer transfer into and out of other transport tools and / or load locks connected or interfaced with the system, depending on the processing requirements and / or type of system.

[0310] Broadly speaking, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define variables, factors, parameters, etc. for performing a particular process on, for, or on a semiconductor wafer or system. Program instructions, in some embodiments, are part of a recipe defined by a process engineer to accomplish one or more processing steps during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0311] The controller, in some embodiments, is part of or connected to a computer that is integrated into the system, connected to the system, or otherwise networked to the system, or a combination thereof. For example, the controller may be all or part of a "cloud," or fab host computer system, which allows remote access of wafer processing. The computer allows remote access to the system to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, examine trends or performance criteria from multiple manufacturing operations, change variables of the current process, set processing steps to track the current process, or start a new process.

[0312] In some embodiments, a remote computer (e.g., a server) provides the process recipe to the system over a network, which may include a local network or the Internet. The remote computer includes a user interface that allows for input or programming of variables and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify respective variables, factors, and / or parameters of the processing steps to be performed during one or more operations. It should be understood that the variables, factors, and / or parameters are specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, such as by including one or more individual controllers networked together and operating toward a common purpose, such as the processes and controls described herein. One example of a distributed controller for such purposes includes one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) and cooperatively controlling the process at the chamber.

[0313] In various embodiments, examples of systems to which the methods described herein may be applied include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0314] It is further noted that in some embodiments, the above-described operations apply to various types of plasma chambers, such as plasma chambers including inductively coupled plasma (ICP) reactors, capacitively coupled plasma (CCP) chambers, transformer-coupled plasma chambers, conductor tools, dielectric tools, and plasma chambers including electron cyclotron resonance (ECR) reactors. For example, one or more RF generators are connected to an inductor in an ICP reactor. Examples of inductor shapes include a solenoid, a dome-shaped coil, a flat coil, and the like. In a CCP plasma chamber, a top plate is used as the upper electrode instead of one or more RF coils.

[0315] As described above, depending on the process step or steps being performed by the tool, the host computer communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used to transport materials to and from tool locations and / or load ports of wafers within the semiconductor fabrication factory.

[0316] With the above embodiments in mind, it should be understood that some of the present embodiments employ various computer-implemented operations involving data stored in computer systems. These operations physically manipulate physical quantities. Any of the operations described herein that form part of the present embodiments are useful machine operations.

[0317] Additionally, some of the embodiments relate to hardware units or apparatus for performing these operations, which are specifically made for special-purpose computers. When defined as a special-purpose computer, the computer is operable for a special purpose, but also performs other processes, programs, or routines that do not belong to the special purpose.

[0318] In some embodiments, the operations may be processed by a computer selectively activated or configured by one or more computer programs stored in a computer memory or cache, or obtained over a computer network. If the data is obtained over a computer network, the data may be processed by other computers on the computer network, for example, in a cloud of computing resources.

[0319] One or more embodiments may also be fabricated as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit, such as a memory device, that stores data, which is subsequently read by a computer system. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium comprises a computer-readable tangible medium distributed over network-coupled computer systems so that the computer-readable code is stored and executed in a distributed fashion.

[0320] Although the method operations described above have been described in a particular order, it should be understood that in various embodiments, other housekeeping operations may be performed between operations, the method operations may be arranged to occur at slightly different times, may be distributed in a system that allows the method operations to occur at various intervals, or may be performed in an order different from that described above.

[0321] It is further noted that in one embodiment, one or more features from any of the above-described embodiments may be combined with one or more features of any other embodiment without departing from the scope described in the various embodiments described in this disclosure.

[0322] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. The present embodiments are therefore to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein. The present disclosure can also be realized in the following forms. [Form 1] 1. A method comprising: receiving, by a radio frequency (RF) generator, a first set of one or more variable levels and one or more duty cycles of an RF signal; receiving, by the RF generator, a synchronization signal from a pulse controller, the synchronization signal having a plurality of pulses; generating, during a clock cycle of a clock signal, a plurality of instances of a first plurality of states of the RF signal synchronously with the plurality of pulses of the synchronization signal; Including, each of the first plurality of states of the RF signal having a corresponding one of the one or more variable levels of the first set and a corresponding one of the one or more duty cycles of the first set; method. [Form 2] 2. The method of claim 1, during a time interval between two successive ones of the plurality of pulses of the synchronization signal, no pulse of the synchronization signal is received; The method further includes instantiating a single state of the RF signal during the time interval. [Form 3] 2. The method of claim 1, wherein the synchronization signal is different from the clock signal. [Form 4] 2. The method of claim 1, receiving a second set of one or more variable levels and one or more duty cycles of the RF signal; receiving a count of the number of pulses of the synchronization signal after which the RF signal includes the second set of one or more variable levels and one or more duty cycles; determining whether the count has been exceeded; generating a first instance of a second plurality of states of the RF signal in response to determining that the count has been exceeded during the clock cycle of the clock signal; further comprising each of the second plurality of states of the RF signal having a corresponding one of the one or more variable levels of the second set and a corresponding one of the one or more duty cycles of the second set; method. [Form 5] 2. The method of claim 1, wherein the first set of one or more variable levels and one or more duty cycles is received before receiving the synchronization signal. [Form 6] 2. The method of claim 1, wherein the frequency of the plurality of pulses is variable by the pulse controller. [Form 7] 2. The method of claim 1, wherein the plurality of states comprises two states, or three states, or four states. [Form 8] 2. The method of claim 1, wherein the one or more variable levels are one or more power levels. [Form 9] 2. The method of claim 1, wherein each of the one or more duty cycles is a corresponding one of the one or more variable levels. [Form 10] A pulse controller, a processor configured to transmit a first set of one or more variable levels and one or more duty cycles of a radio frequency (RF) signal to an RF generator; the processor is configured to transmit a synchronization signal having a plurality of pulses to the RF generator; transmitting the synchronization signal to the RF generator to enable the RF generator to generate, during a clock cycle of a clock signal, a plurality of instances of a first plurality of states of the RF signal in synchronization with the plurality of pulses of the synchronization signal, each of the first plurality of states of the RF signal having a corresponding one of the one or more variable levels of the first set and a corresponding one of the one or more duty cycles of the first set; a processor; a memory device coupled to said processor; a pulse controller. [Form 11] 11. The pulse controller of claim 10, wherein the processor is configured to generate a single logic level of the synchronization signal during a time interval between two consecutive ones of the plurality of pulses of the synchronization signal, the single logic level enabling the RF generator to generate an instance of a single state of the RF signal. [Form 12] 11. The pulse controller of claim 10, wherein the synchronization signal is different from the clock signal. [Form 13] 11. A pulse controller according to claim 10, wherein the one or more variable levels are one or more power levels. [Form 14] 1. A method comprising: measuring sensor data by a sensor of the sensor system; receiving, by the sensor system, a synchronization signal having a plurality of pulses; collecting, by the sensor system, portions of the sensor data synchronously with the plurality of pulses of the synchronization signal during clock cycles of a clock signal; transmitting said portion of said sensor data to a pulse controller; A method comprising: [Form 15] 15. The method of claim 14, wherein each of the plurality of pulses is generated during a corresponding one of a plurality of time periods, and each of the portions of sensor data is converted from analog to digital format for the corresponding one of the plurality of time periods. [Form 16] 16. The method of claim 15, wherein during the time interval between two successive ones of the pulses, a portion of the sensor data is not converted from the analog format to the digital format. [Form 17] 15. The method of claim 14, wherein a portion of the sensor data is not collected during a time interval between two successive ones of the pulses. [Form 18] 15. The method of claim 14, wherein the sensor system is disposed in an impedance matching circuit. [Form 19] 15. The method of claim 14, wherein the sensor system is disposed outside the impedance matching circuit. [Form 20] 15. The method of claim 14, wherein the sensor data is a voltage value, an intensity value, or a current value.

Claims

1. 1. A method comprising: receiving, by a radio frequency (RF) generator, a first set of RF signals having one or more variable levels and one or more duty cycles; receiving a second set of the RF signal having one or more variable levels and one or more duty cycles; receiving, by the RF generator, a synchronization signal from a pulse controller having a plurality of pulses; receiving a count of the number of pulses of the synchronization signal after which the RF signal includes the second set having one or more variable levels and one or more duty cycles; generating, during a clock cycle of a clock signal, a plurality of instances of a first plurality of states of the RF signal synchronously with the plurality of pulses of the synchronization signal; determining whether the count has been exceeded; generating a first instance of a second plurality of states of the RF signal in response to determining that the count has been exceeded during the clock cycle of the clock signal; Including, each of the first plurality of states of the RF signal having a corresponding one of the one or more variable levels of the first set and a corresponding one of the one or more duty cycles of the first set; each of the second plurality of states of the RF signal having a corresponding one of the one or more variable levels of the second set and a corresponding one of the one or more duty cycles of the second set; method.

2. 10. The method of claim 1, during a time interval between two successive ones of the plurality of pulses of the synchronization signal, no pulse of the synchronization signal is received; The method further includes instantiating a single state of the RF signal during the time interval.

3. The method of claim 1 , wherein the synchronization signal is different from the clock signal.

4. 2. The method of claim 1, wherein the first set of one or more variable levels and one or more duty cycles is received prior to receiving the synchronization signal.

5. 2. The method of claim 1, wherein the frequency of the plurality of pulses is variable by the pulse controller.

6. The method of claim 1 , wherein the first plurality of states comprises two states, or three states, or four states.

7. The method of claim 1 , wherein the one or more variable levels of the first set are one or more power levels.

8. 2. The method of claim 1, wherein each of the one or more duty cycles of the first set is the corresponding one of the one or more variable levels of the first set.

9. A pulse controller, a processor configured to transmit a first set of one or more variable levels and one or more duty cycles of a radio frequency (RF) signal to an RF generator; the processor is configured to transmit a second set of one or more variable levels and one or more duty cycles of the RF signal to the RF generator; the processor is configured to send a synchronization signal having a plurality of pulses to the RF generator; the processor is configured to transmit a count of the number of pulses of the synchronization signal after which the RF signal includes the second set having one or more variable levels and one or more duty cycles; transmitting the synchronization signal to the RF generator to enable the RF generator to generate, during a clock cycle of a clock signal, a plurality of instances of a first plurality of states of the RF signal in synchronization with the plurality of pulses of the synchronization signal, each of the first plurality of states of the RF signal having a corresponding one of the one or more variable levels of the first set and a corresponding one of the one or more duty cycles of the first set; transmitting the count to the RF generator to enable the RF generator to generate, during the clock cycle of the clock signal, a first instance of a second plurality of states of the RF signal, wherein an instance of the second plurality of states is generated when the count is exceeded, each of the second plurality of states of the RF signal having a corresponding one of the one or more variable levels of the second set and a corresponding one of the one or more duty cycles of the second set; a processor; a memory device coupled to said processor; a pulse controller.

10. 10. The pulse controller of claim 9, wherein the processor is configured to generate a single logic level of the synchronization signal during a time interval between two successive ones of the plurality of pulses of the synchronization signal, the single logic level enabling the RF generator to generate an instance of a single state of the RF signal.

11. 10. The pulse controller of claim 9, wherein the synchronization signal is different from the clock signal.

12. 10. The pulse controller of claim 9, wherein the one or more variable levels of the first set are one or more power levels.

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