Data double oversampling method, system, device and storage medium

Abstract

To provide a data double oversampling method, system, device, and storage medium for reducing costs by stably completing phase locking of recovery data within the time specified in a protocol.SOLUTION: A method includes the steps of: obtaining an initial sampling phase corresponding to each of two adjacent bits for two adjacent bits of a read code in a GPON frame and a phase label corresponding to each initial sampling phase; displacing the phase of each initial sampling and obtaining each sampling phase after the displacement; and depending on whether adjacent phase labels of a target hopping edge before and after the displacement are equal, and whether a first reference sampling phase is located on the target hopping edge, displacing each sampling phase after the displacement again, and obtaining an optimal sampling phase corresponding to the two adjacent bits so as to sample valid data.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to the field of electronic technology, and in particular to a data double oversampling method, system, device and storage medium. [Background technology]

[0002] Gigabit-Capable Passive Optical Network (GPON) technology has many advantages, including high bandwidth, high efficiency, wide coverage, and rich user interfaces. The GPON protocol has an uplink rate of 1.24416 Gbps and a downlink rate of 2.48832 Gbps. Currently, the data reception scheme of the receiving CDR (Clock Data Recovery) is a quadruple-oversampling scheme for the SERDES in a field-programmable gate array (FPGA). In this scheme, the transmitting side transmits data at the GPON uplink rate of 1.24416 Gbps, while the receiving SERDES samples at a linear rate of 4.97664 Gbps. The quadruple-oversampling method is used to sample the received data, first finding the correct sampling point and then tracking the sampling point drift, thereby achieving phase lock within the time specified by the protocol.

[0003] However, as FTTR (Fiber to the Room) is deployed in thousands of homes and user-side optical modems are typically connected to multiple ONUs (Optical Network Units), a scheme is needed to upgrade the uplink rate to 2.48832Gbps to transmit data. If the transmitting GPON transmits data at an uplink rate of 2.488Gbps, the clock frequency of the receiving SERDES cannot meet the requirement.

[0004] Therefore, there is an urgent need for a data sampling method for a scenario in which the sender transmits data at an uplink rate of 2.48832 Gbps. Summary of the Invention

[0005] The present invention provides a data double oversampling method, system, device and storage medium, the main purpose of which is to provide a data double oversampling method for a scenario in which transmission is performed at an uplink rate of 2.48832 Gbps.

[0006] According to a first aspect, an embodiment of the present invention provides a method for double oversampling data, comprising: S110, for two adjacent bits of a lead code in a GPON frame, obtain an initial sampling phase corresponding to each of the two adjacent bits and a phase label corresponding to each initial sampling phase, and the GPON frame includes the lead code and valid data; S120: shifting the phase of each initial sampling and acquiring the sampling phase after each shift; S130: according to whether the adjacent phase labels of the target hopping edge before and after the shift are equal and whether the first reference sampling phase is located on the target hopping edge, shift the sampling phase after each shift to obtain an optimal sampling phase corresponding to the two adjacent bits, where the optimal sampling phase is close to the middle phase of the corresponding read code, and the first reference sampling phase is a post-shift sampling phase that is adjacent to the target hopping edge and located after the target hopping edge; S140, sampling the valid data according to an optimal sampling phase corresponding to each bit of the read code.

[0007] Further, the step of again displacing the sampling phase after each displacement according to whether adjacent phase labels of the target hopping edge before and after the displacement are equal and whether the first reference sampling phase is located on the target hopping edge includes: determining whether the first reference sampling phase lies on the target hopping edge; If the first reference sampling phase is located on the target hopping edge, then again displacing the sampling phase after each displacement according to a first predetermined displacement rule; When the first reference sampling phase is not located on the target hopping edge, obtaining a first adjacent phase label of the target hopping edge according to the adjacent initial sampling phases of the target hopping edge and the phase labels corresponding to each initial sampling phase; Obtaining a second adjacent phase label of the target hopping edge according to a sampling phase after an adjacent displacement of the target hopping edge; if the first adjacent phase label and the second adjacent phase label are equal, then again shifting the sampling phase after each shift according to a second predetermined shift rule; If the first adjacent phase label and the second adjacent phase label are not equal, again displacing the sampling phase after each displacement according to a third predetermined displacement rule.

[0008] Furthermore, the first predetermined shift rule is to shift the sampling phase backward by 0.25 bits after each shift; the second predetermined shift rule is to shift the sampling phase forward by 0.125 bits after each shift; The third predetermined shift rule is to shift the sampling phase backward by 0.125 bits after each shift.

[0009] Furthermore, before obtaining a first adjacent phase label of the target hopping edge according to the adjacent initial sampling phases of the target hopping edge and the phase labels corresponding to each initial sampling phase, the method includes: Sampling corresponding bits through each initial sampling phase to obtain initial sampling data; performing an XOR on two adjacent initial sampling data; If the XOR value of the two adjacent initial sampling data is 1, the hopping edge between the initial sampling phases corresponding to the two adjacent initial sampling data is set as the target hopping edge.

[0010] Furthermore, the step of obtaining the optimal sampling phases corresponding to the two adjacent bits includes: an initial sampling phase adjacent to the hopping edge and located after the target hopping edge is set as a second reference sampling phase; obtaining final sampling phases after each shift of the sampling phase; The optimum sampling phase is a final sampling phase adjacent to a final reference phase, and the final reference phase is a final sampling phase corresponding to a result of displacing the second reference sampling phase.

[0011] Furthermore, the steps S110 to S130 are simultaneously executed at least once.

[0012] Furthermore, the step of shifting the phase of each initial sampling includes: This involves shifting each initial sampling phase forward by 0.25 bits.

[0013] According to a second aspect, an embodiment of the present invention provides a data double oversampling system, comprising: A receiving module for obtaining initial sampling phases and phase labels corresponding to two adjacent bits of a lead code in a GPON frame, the initial sampling phases corresponding to the two adjacent bits, and the phase labels corresponding to the initial sampling phases, the GPON frame including the lead code and valid data; a first displacement module for displacing the phase of each initial sampling and obtaining a sampling phase after each displacement; a second displacement module, which displaces the sampling phase after each displacement according to whether the adjacent phase labels of the target hopping edge before and after the displacement are equal and whether the first reference sampling phase is located on the target hopping edge, to obtain an optimal sampling phase corresponding to the two adjacent bits, wherein the optimal sampling phase is close to the middle phase of the corresponding read code, and the first reference sampling phase is a post-displacement sampling phase adjacent to the target hopping edge and located after the target hopping edge; a sampling module for sampling the valid data according to an optimal sampling phase corresponding to each bit of the read code.

[0014] According to a third aspect, an embodiment of the present invention provides a computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program executing on the processor performing steps of the data double oversampling method.

[0015] According to a fourth aspect, an embodiment of the present invention provides a computer storage medium having stored thereon a computer program, the computer program being adapted to perform the steps of the data double oversampling method when executed by a processor.

[0016] The data double oversampling method, system, device, and storage medium provided by the present invention shift the initial sampling phase of a read code bit twice to extract the optimal sampling phase. The double shift ensures that the optimal sampling phase is close to the middle phase of the corresponding read code, ensuring a sufficient window sampling margin. The higher the sampling accuracy, the higher the sampling precision. Effective data is sampled from the optimal sampling phase determined by the read code, and phase locking of the recovered data can be stably completed within the time specified by the protocol. This eliminates the need for hardware modifications, thereby reducing costs. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a flowchart of a data double oversampling method provided by an embodiment of the present invention; [Figure 2] FIG. 2 is a schematic diagram of initial sampling phases corresponding to two adjacent bits in an embodiment of the present invention. [Figure 3] 1 is a specific flowchart of a method for determining a displacement from an adjacent phase label according to an embodiment of the present invention; [Figure 4] FIG. 10 is a schematic diagram of a third initial sampling phase in the first interval segment of D2 in an embodiment of the present invention. [Figure 5] FIG. 10 is a schematic diagram of a third initial sampling phase in the second interval segment of D2 in an embodiment of the present invention. [Figure 6] FIG. 10 is a schematic diagram of a third initial sampling phase in the third section segment of D2 in an embodiment of the present invention. [Figure 7] FIG. 10 is a schematic diagram of a third initial sampling phase in the fourth interval segment of D2 in an embodiment of the present invention. [Figure 8] 1 is a structural schematic diagram of a data double oversampling system provided by an embodiment of the present invention; [Figure 9] 1 is a structural schematic diagram of a computer device provided by an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0018] The realization of the objects, functional features and advantages of the present invention will be explained in detail in conjunction with the embodiments with reference to the accompanying drawings.

[0023] Hereinafter, the embodiments of the present application will be described in detail, and examples of the embodiments are shown in the accompanying drawings, and the same or similar reference numerals throughout indicate the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are illustrative and are used only for the purpose of interpreting the present application, and do not limit the present application.

[0019] In order to help those skilled in the art better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, other embodiments obtained by those skilled in the art without any creative work are all included in the protection scope of the present application.

[0020] In the examples of this application, at least one means one or more, and plural means two or more. In the description of this application, terms such as "first," "second," "third," etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or order.

[0021] References herein to "one embodiment" or "some embodiments" or the like mean that one or more embodiments of the present application include the particular feature, structure, or characteristic described in connection with that example. Thus, in this specification, the terms "including," "comprising," "having," and variations thereof mean "including, but not limited to," unless otherwise emphasized.

[0022] In this embodiment, the target application scenario is to implement multiple optical network units under an optical modulator / demodulator, and in this embodiment, the transmitting side is the optical modulator / demodulator and the receiving side is the optical network unit. The optical modulator / demodulator transmits a GPON frame to the optical network unit according to the GPON protocol, and after receiving the GPON frame, the optical network unit performs a data double oversampling method to sample the GPON frame and obtain the transmitted data.

[0023] In this embodiment, the transmitting side transmits GPON frames at a rate of 2.48832 Gbps. If the receiving side samples the GPON frames at four times the frequency, the 6.6 Gbps clock frequency of the current FPGA SERDES cannot meet the requirements. Therefore, in this embodiment, the receiving side samples the GPON frames at twice the frequency. The GPON protocol uses burst interrupts and burst transmissions for uplink rate data. When the uplink rate data is upgraded to 2.48832 Gbps, the receiving side is required to stably complete phase locking of the recovered data within the time specified by the protocol.

[0024] SERDES is a communication system that includes a serializer and a deserializer, where the serializer is a device that converts parallel data into serial data, and the deserializer is a device that restores serial data to parallel data. In actual application scenarios, the receiving side realizes the corresponding data reception function through FPGA, and since FPGAs usually have built-in SERDES, the receiving side realizes data reception through the SERDES built into the FPGA.

[0025] When the sender communicates with the receiver, according to the GPON protocol, the sender sends a GPON frame through the serializer. When the receiver receives the GPON frame, according to the assigned time slot, the optical modem is in a non-illuminated state at this time. After the receiver receives the optical signal of the GPON frame, it converts the optical signal of the GPON frame into an electrical signal of the GPON frame and sends it to the deserializer.

[0026] FIG. 1 is a flowchart of a data double oversampling method provided by an embodiment of the present invention. As shown in FIG. 1, the method includes the following steps:

[0027] S110, for two adjacent bits of a lead code in a GPON frame, obtain initial sampling phases corresponding to the two adjacent bits and phase labels corresponding to each initial sampling phase, and the GPON frame includes the lead code and valid data; When the receiving side is in an idle state, the receiving side receives a GPON frame, where the GPON frame is the electrical signal of the GPON frame obtained by converting the optical signal of the GPON frame. The GPON frame includes two parts: a lead code and valid data. The function of the lead code is mainly to synchronize the bits of the transmitting side and the receiving side, and the valid data refers to the valid information contained in the GPON frame.

[0028] In order to easily explain this technical solution, this embodiment will take the case where the read code is 4'b1010 as an example, where 4 indicates the number of bits of the read code, b indicates that the read code is a binary number, and 1010 indicates the specific value of the read code. In this embodiment, the read code includes a total of four bits, and for any two adjacent bits among these four bits, such as "10", "01", etc., the case where "01" is the adjacent two bits will be taken as an example.

[0029] First, the initial sampling phases corresponding to the two adjacent bits are obtained. In this embodiment, sampling is performed at double frequency, i.e., double oversampling is performed for each bit of the read code. Therefore, each bit corresponds to two different initial sampling phases. Figure 2 is a schematic diagram of the initial sampling phases corresponding to two adjacent bits in this embodiment of the present invention. As shown in Figure 2, D1 and D2 in the figure represent two adjacent bits of the read code. In this embodiment, D1 is "0" and D2 is "1" as an example. The dotted lines indicated by s1 and s2 in the figure represent the two initial sampling phases of D1, referred to as the first and second initial sampling phases, respectively. The dotted lines indicated by s3 and s4 represent the two initial sampling phases of D2, referred to as the third and fourth initial sampling phases, respectively. s1, s2, s3, and s4 are the phase labels for the first, second, third, and fourth initial sampling phases, respectively. s1' in the figure represents the initial sampling phase for bits D2 and beyond.

[0030] S120, shifting the phase of each initial sampling, and obtaining the sampling phase after each shift; Next, each initial sampling phase is displaced to obtain each post-displacement sampling phase, and each initial sampling phase is displaced, the specific displacement direction and displacement magnitude are set according to actual circumstances and are not particularly limited in the embodiments of the present invention. Displacing each initial sampling phase means moving each initial sampling phase by a certain magnitude in a certain direction, and each initial sampling phase after the displacement is called a post-displacement sampling phase, and correspondingly, the post-displacement sampling phase includes a first post-displacement sampling phase, a second post-displacement sampling phase, a third post-displacement sampling phase and a fourth post-displacement sampling phase, where the first post-displacement sampling phase is obtained by displacing the first initial sampling phase, the second post-displacement sampling phase is obtained by displacing the second initial sampling phase, the third post-displacement sampling phase is obtained by displacing the third initial sampling phase, and the fourth post-displacement sampling phase is obtained by displacing the fourth initial sampling phase.

[0031] It is easy to understand that for the initial sampling phase and the corresponding post-displacement sampling phase, the phase label of the post-displacement sampling phase is not changed and is the same as the phase label of the initial sampling phase before displacement, that is, the first post-displacement sampling phase, the second post-displacement sampling phase, the third post-displacement sampling phase and the fourth post-displacement sampling phase are s1, s2, s3 and s4, respectively.

[0032] In this embodiment, displacing each initial sampling phase means moving each initial sampling phase forward by 0.25 bits, i.e., the first initial sampling phase, the second initial sampling phase, the third initial sampling phase and the fourth initial sampling phase are each moved forward by 0.25 bits.

[0033] In this embodiment, forward movement means moving forward in time based on timing, and backward movement means moving backward in time based on time. Referring to Figure 2, forward movement means moving to the left, and backward movement means moving to the right.

[0034] S130, according to whether the adjacent phase labels of the target hopping edge before and after the displacement are equal and whether the first reference sampling phase is located on the target hopping edge, the sampling phase after each displacement is displaced again to obtain an optimal sampling phase corresponding to the two adjacent bits, wherein the optimal sampling phase is close to the middle phase of the corresponding read code, and the first reference sampling phase is a post-displacement sampling phase adjacent to the target hopping edge and located after the target hopping edge; Next, it determines whether the adjacent phase labels of the target hopping edge before and after the shift are equal and whether the first reference sampling phase is located on the target hopping edge, and then shifts the sampling phase after each shift. Specifically, the target hopping edge refers to the hopping edge between D1 and D2. As can be seen from Figure 2, the hopping edge between the second initial sampling phase and the third initial sampling phase is the target hopping edge.

[0035] After determining the target hopping edge, a first reference sampling phase needs to be selected from the sampling phase after the first displacement, the sampling phase after the second displacement, the sampling phase after the third displacement, and the sampling phase after the fourth displacement according to the positional relationship between the target hopping edge and the sampling phase after the first displacement, the sampling phase after the second displacement, the sampling phase after the third displacement, and the sampling phase after the fourth displacement. A specific selection method is to select the displacement sampling phase adjacent to the target hopping edge and after the target hopping edge as the first reference sampling phase.

[0036] When the first reference sampling phase is at the target hopping edge, all the post-displacement sampling phases are at relatively special positions, and each post-displacement sampling phase is displaced again according to the processing rule for the special position.

[0037] Here, the term "the first reference sampling phase is at the target hopping edge" refers to the first reference sampling phase being at the target hopping edge, or the first reference sampling phase being in a predetermined interval before and after the target hopping edge, which can be specifically set according to actual conditions. The predetermined intervals are obtained by extending forward and backward from the target hopping edge, respectively, and the specific lengths of the predetermined intervals can be specifically set according to actual conditions. When the first reference sampling phase is in the predetermined interval, it means that the first reference sampling phase is at the target hopping edge, and conversely, it means that the first reference sampling phase is not located at the target hopping edge.

[0038] Since the two initial sampling phases adjacent to the target hopping edge are the second and third initial sampling phases, the adjacent phase labels of the target hopping edge before the displacement are s2 and s3. The position of the target hopping edge after the displacement remains unchanged, but the adjacent displacement of the target hopping edge may change depending on the relative position of the third initial sampling phase in D2. The adjacent sampling phases of the target hopping edge after the displacement may be the sampling phase after the second displacement and the sampling phase after the third displacement, or the sampling phase after the third displacement and the sampling phase after the fourth displacement, that is, the adjacent phase labels of the target hopping edge may be s2 and s3, or s3 and s4.

[0039] The displacement direction of the sampling phase after each displacement is determined based on whether the adjacent phase labels of the target hopping edge before and after the displacement are equal, i.e., whether the adjacent phase labels of the target hopping edge after the displacement have changed. That is, based on whether the adjacent phase labels of the target hopping edge after the displacement have changed, the sampling phase after the first displacement, the sampling phase after the second displacement, the sampling phase after the third displacement, and the sampling phase after the fourth displacement are displaced again to obtain the final sampling phases, i.e., the first final sampling phase, the second final sampling phase, the third final sampling phase, and the fourth final sampling phase.

[0040] In this embodiment, for the optimal sampling phase, several sampling phases are selected from the first final sampling phase, the second final sampling phase, the third final sampling phase, and the fourth final sampling phase as the optimal sampling phase, and the selected optimal sampling phase is close to the middle phase of the corresponding read code. The specific selection method can be determined according to the actual situation, and is not particularly limited in this embodiment.

[0041] For example, after two more shifts, the final sampling phase in the D1 read code corresponds to the first final sampling phase and the second final sampling phase. Taking the intermediate phase of the D1 read code as the reference, if the distance between the first final sampling phase and the intermediate phase is shorter than the distance between the second final sampling phase and the intermediate phase, the first final sampling phase becomes the optimal sampling phase of D1; if the distance between the second final sampling phase and the intermediate phase is shorter than the distance between the first final sampling phase and the intermediate phase, the second final sampling phase becomes the optimal sampling phase of D1.

[0042] The final sampling phase in the D2 read code corresponds to the third final sampling phase and the fourth final sampling phase. Taking the intermediate phase of the D2 read code as a reference, if the distance between the third final sampling phase and the intermediate phase is shorter than the distance between the fourth final sampling phase and the intermediate phase, then the third final sampling phase becomes the optimal sampling phase for D2; if the distance between the fourth final sampling phase and the intermediate phase is shorter than the distance between the third final sampling phase and the intermediate phase, then the fourth final sampling phase becomes the optimal sampling phase for D2.

[0043] The optimal sampling phase in this embodiment includes an optimal sampling phase corresponding to each bit of the read code. During the process of sampling the read code, generally, the more the sampling phase shifts, the closer the sampling phase is to the middle phase of the read code, ensuring a sufficient window sampling margin and the higher the sampling accuracy. In this embodiment, due to the influence of the number of read codes, the sampling phase can only be shifted a maximum of two times. The finally determined optimal sampling phase is close to the middle phase of the corresponding read code, ensuring a sufficient window sampling margin. The closer the sampling phase is to the middle, the higher the sampling accuracy and the better the sampling accuracy.

[0044] S140, sampling the valid data according to the optimal sampling phase corresponding to each bit of the read code.

[0045] Finally, the valid data of the GPON frame is sampled according to the optimal sampling phase corresponding to each bit of the lead code, and the data is locked within the time specified by the GPON protocol.

[0046] In the specific implementation process, the hardware device of this embodiment is the same as the existing hardware device that transmits data at an uplink rate of 1.24416 Gbps. When the uplink rate is upgraded to 2.48832 Gbps, the software code is directly modified to realize a scheme for transmitting data at an uplink rate of 2.48832 Gbps, and there is no need to change the hardware device, which reduces costs.

[0047] This embodiment provides a data double oversampling method, which shifts the initial sampling phase of the read code bit twice and finally extracts the optimal sampling phase. By shifting twice, the optimal sampling phase is close to the middle phase of the corresponding read code, ensuring a sufficient window sampling margin. The higher the sampling accuracy, the higher the sampling precision. From the optimal sampling phase determined by the read code, valid data can be sampled, and phase locking of the recovered data can be stably completed within the time specified by the protocol. There is no need to change the hardware, which reduces costs.

[0048] In some embodiments, FIG. 3 is a specific flowchart of a method for determining a displacement from an adjacent phase label according to an embodiment of the present invention. As shown in FIG. 3, in step S130, the step of re-displacing the sampling phase after each displacement according to whether the adjacent phase labels of the target hopping edge before and after the displacement are equal and whether the first reference sampling phase is located on the target hopping edge is: S131, determining whether the first reference sampling phase is located on the target hopping edge; if the first reference sampling phase is located on the target hopping edge, re-shifting the sampling phase after each shift according to a first predetermined shift rule; First, it is determined whether the first reference sampling phase is located at the target hopping edge. For the specific determination method, refer to the above embodiment. If the first reference sampling phase is located at the target hopping edge, the sampling phase is in a special position. This situation is handled separately. Specifically, the sampling phase is displaced again after each displacement according to a first predetermined displacement rule. The first predetermined displacement rule can be set according to the actual situation, and is not particularly limited in this embodiment.

[0049] Optionally, the first predetermined shifting rule is to shift the sampling phase backward by 0.25 bits after each shift. As an optional aspect, in this embodiment, when the first reference sampling phase is located at the target hopping edge, referring to FIG. 2 , the sampling phase after the third shift is the first reference sampling phase, and the sampling phase after the third shift is located at the target hopping edge. This means that the second and fourth initial sampling phases are all located at the middle phases of the corresponding read codes, i.e., the second initial sampling phase is located at the middle phase of D1, and the fourth initial sampling phase is located at the middle phase of D2. Since each initial sampling phase is shifted forward by 0.25 bits during the first shift, the optimal sampling phase is located at the middle phase of the corresponding read code simply by shifting it backward by 0.25 bits during the second shift. Therefore, when the first reference sampling phase is located at the target hopping edge, the sampling phase after each shift simply needs to be shifted backward by 0.25 bits during the second shift, eliminating the need to determine the adjacent phase labels before and after the shift of the target hopping edge.

[0050] S132, when the first reference sampling phase is not located at the target hopping edge, obtain a first adjacent phase label of the target hopping edge according to the adjacent initial sampling phases of the target hopping edge and the phase labels corresponding to each initial sampling phase; If the first reference sampling phase is not located at the target hopping edge, the first adjacent phase label is determined according to the adjacent initial phase and phase label of the target hopping edge. Taking FIG. 2 as an example, as can be seen from the description of the above embodiment, the first adjacent phase labels in this embodiment are s2 and s3.

[0051] S133, obtain a second adjacent phase label of the target hopping edge according to the sampling phase after the adjacent displacement of the target hopping edge; According to the sampling phase after the adjacent displacement of the target hopping edge, the second adjacent phase label of the target hopping edge is determined. Because the position of the third initial sampling phase in D2 is different, the second adjacent phase label of the target hopping edge is affected, and the second adjacent phase label changes according to the position of the third initial sampling phase.

[0052] In this embodiment, the positional relationship between the third initial sampling phase and D2 is analyzed separately, and finally summarized to arrive at the conclusion of displacement again. In this embodiment, the positional relationship between the third initial sampling phase and D2 is divided into the following four cases: Since the target hopping edge is located between the second initial sampling phase and the third initial sampling phase, and the first initial sampling phase after the target hopping edge is the third initial sampling phase, the phase is sampled based on the third initial sampling phase, and displacement is performed based on the reference sampling phase.

[0053] (1) The third initial sampling phase is located in the first section segment of D2, and the entire section in which D2 is located is 1 bit, with the first section segment ranging from 0 to 1 / 8 bit. Figure 4 is a schematic diagram of the third initial sampling phase in the first section segment of D2 in an embodiment of the present invention. As shown in Figure 4, when the third initial sampling phase is located in the 0 to 1 / 8 bit range, the adjacent sampling phases of the target hopping edge are the second and third initial sampling phases, and the first adjacent phase labels of the target phase are s2 and s3. After first shifting by 0.25 bits to the left, the sampling phase after the third shift is located in the 3 / 4 to 7 / 8 bit range of D1. The adjacent sampling phases of the target hopping edge are the sampling phase after the third shift and the sampling phase after the fourth shift, and the second adjacent phase labels of the target phase are s3 and s4.

[0054] (2) The third initial sampling phase is in the second section segment of D2, and the first section segment is 1 / 8 to 1 / 4 bit. Figure 5 is a schematic diagram of the third initial sampling phase in the second section segment of D2 in an embodiment of the present invention. As shown in Figure 5, when the third initial sampling phase is 1 / 8 to 1 / 4 bit, the adjacent sampling phases of the target hopping edge are the second and third initial sampling phases, and the first adjacent phase labels of the target phase are s2 and s3. After first shifting by 0.25 bit to the left, the sampling phase after the third shift is located at the 7 / 8 to 1 bit position of D1. The adjacent sampling phases of the target hopping edge are the sampling phase after the third shift and the sampling phase after the fourth shift, and the second adjacent phase labels of the target phase are s3 and s4.

[0055] (3), the third initial sampling phase is the third section segment of D2, and the third section segment is 1 / 4 to 3 / 8 bits. Figure 6 is a schematic diagram of the third initial sampling phase in the third section segment of D2 in an embodiment of the present invention. As shown in Figure 6, when the third initial sampling phase is 1 / 4 to 3 / 8 bits, the adjacent sampling phases of the target hopping edge are the second and third initial sampling phases, and the first adjacent phase labels of the target phase are s2 and s3. After first shifting by 0.25 bits to the left, the sampling phase after the third shift is located at 0 bit to 1 / 8 bit of D2, and the adjacent sampling phases of the target hopping edge are the sampling phase after the second shift and the sampling phase after the third shift, and the second adjacent phase labels of the target phase are s2 and s3.

[0056] (4) The third initial sampling phase is in the fourth section segment of D2, and the third section segment is 3 / 8 to 1 / 2 bits. Figure 7 is a schematic diagram of the third initial sampling phase in the fourth section segment of D2 in an embodiment of the present invention. As shown in Figure 7, when the third initial sampling phase is 3 / 8 to 1 / 2 bits, the adjacent sampling phases of the target hopping edge are the second and third initial sampling phases, and the first adjacent phase labels of the target phase are s2 and s3. After first shifting by 0.25 bits to the left, the sampling phase after the third shift is located between 1 / 8 bit and 1 / 4 bit of D2, and the adjacent sampling phases of the target hopping edge are the sampling phase after the second shift and the sampling phase after the third shift, and the second adjacent phase labels of the target phase are s2 and s3.

[0057] S134: if the first adjacent phase label and the second adjacent phase label are equal, the sampling phase after each displacement is displaced again according to a second predetermined displacement rule; if the first adjacent phase label and the second adjacent phase label are not equal, the sampling phase after each displacement is displaced again according to a third predetermined displacement rule.

[0058] From the above analysis, it can be seen that when the third initial sampling phase is between 1 / 4 and 1 / 2 bits of D2, the second adjacent sampling phase is s2 and s3, and the first adjacent phase label is equal to the second adjacent phase label. At this time, the sampling phase is displaced again after each displacement according to the second predetermined displacement rule. When the third initial sampling phase is between 0 and 1 / 4 bits of D2, the second adjacent sampling phase is s3 and s4, and the first adjacent phase label is not equal to the second adjacent phase label. At this time, the sampling phase is displaced again after each displacement according to the third predetermined displacement rule.

[0059] Optionally, the second predetermined shift rule is to shift the sampling phase forward by 0.125 bits after each shift, and the third predetermined shift rule is to shift the sampling phase backward by 0.125 bits after each shift.

[0060] In this embodiment, when the third initial sampling phase is between 0 and 1 / 4 bit of D2, the second adjacent sampling phase is s3 and s4, the first adjacent phase label and the second adjacent phase label are not equal, and the sampling phase after each shift is shifted backward by 0.125 bit; when the third initial sampling phase is between 1 / 4 and 1 / 2 bit of D2, the second adjacent sampling phase is s2 and s3, the first adjacent phase label and the second adjacent phase label are equal, and the sampling phase after each shift is shifted forward by 0.125 bit.

[0061] During the actual implementation, the initial sampling phase was shifted twice according to the above method. Simulation and actual testing were conducted, and the experimental results showed that phase locking could be completed within the time specified by the GPON protocol. The determined optimal sampling phase was then used to sample valid data.

[0062] In some embodiments, before obtaining a first adjacent phase label of the target hopping edge according to the adjacent initial sampling phases of the target hopping edge and a phase label corresponding to each initial sampling phase, the method includes: Sampling corresponding bits through each initial sampling phase to obtain initial sampling data; performing an XOR on two adjacent initial sampling data; If the XOR value of the two adjacent initial sampling data is 1, the hopping edge between the initial sampling phases corresponding to the two adjacent initial sampling data is set as the target hopping edge.

[0063] This embodiment further provides a method for determining a target hopping edge, which first samples corresponding bits through each initial sampling phase to obtain initial sampling data, including first, second, third and fourth initial sampling data, denoted as d1, d2, d3 and d4, respectively. Specifically, D1 is sampled using the first and second initial sampling phases to obtain the first and second initial sampling data, and D2 is sampled using the third and fourth initial sampling phases to obtain the third and fourth initial sampling data.

[0064] The result of XORing any two adjacent initial sampling data among the four initial sampling data is

number

[0065] In some embodiments, the step of obtaining optimal sampling phases corresponding to the two adjacent bits comprises: an initial sampling phase adjacent to the hopping edge and after the target hopping edge is a second reference sampling phase; obtaining final sampling phases after each shift of the sampling phase; The optimum sampling phase is a final sampling phase adjacent to a final reference phase, and the final reference phase is a final sampling phase corresponding to a result of displacing the second reference sampling phase.

[0066] In this embodiment, the sampling phase after each shift is shifted again to obtain a final sampling phase, which includes a first final sampling phase, a second final sampling phase, a third final sampling phase and a fourth final sampling phase.

[0067] Since the third initial sampling data is the first bit data after the target hopping edge, the third initial sampling phase is selected as the second reference sampling phase, and the second reference sampling phase corresponds to the third final sampling phase. The two final sampling phases adjacent to the third final sampling phase are selected as optimal sampling phases, i.e., the second final sampling phase and the fourth final sampling phase are selected as optimal sampling phases.

[0068] In some embodiments, steps S110 to S130 are simultaneously performed at least once.

[0069] Specifically, the above steps S110 to S130 are simultaneously executed at least once, and the data double oversampling method is simultaneously executed multiple times, i.e., the same steps are executed multiple times, so that even if an abnormal error occurs in one execution, it will not affect the results of other executions, and will not affect the finally determined optimal sampling phase, thereby avoiding the influence of the X state.

[0070] FIG. 8 is a structural schematic diagram of a data double oversampling system provided by an embodiment of the present invention. As shown in FIG. 8, the system includes: a receiving module 810, a first displacement module 820, a second displacement module 830, and a sampling module 840; The receiving module 810 obtains, for two adjacent bits of a lead code in a GPON frame, initial sampling phases corresponding to the two adjacent bits and phase labels corresponding to each initial sampling phase, and the GPON frame includes the lead code and valid data; The first displacement module 820 is used to displace the phase of each initial sampling and obtain the sampling phase after each displacement; the second displacement module 830 displaces the sampling phase after each displacement according to whether the adjacent phase labels of the target hopping edge before and after the displacement are equal and whether the first reference sampling phase is located on the target hopping edge, to obtain an optimal sampling phase corresponding to the two adjacent bits, where the optimal sampling phase is close to the middle phase of the corresponding read code, and the first reference sampling phase is a post-displacement sampling phase adjacent to the target hopping edge and located after the target hopping edge; The sampling module 840 is used to sample the valid data according to the optimal sampling phase corresponding to each bit of the read code.

[0071] Furthermore, the second displacement module includes a main judgment unit, a first displacement unit, a first adjacent unit, a second adjacent unit and a sub-judgment unit; the main determining unit is used to determine whether the first reference sampling phase is located on the target hopping edge; The first displacement unit is used to displace the sampling phase again after each displacement according to a first predetermined displacement rule when the first reference sampling phase is located on the target hopping edge; When the first reference sampling phase is not located at the target hopping edge, the first neighboring unit is used to obtain a first neighboring phase label of the target hopping edge according to the neighboring initial sampling phases of the target hopping edge and the phase labels corresponding to each initial sampling phase; The second neighbor unit is used to obtain a second neighbor phase label of the target hopping edge according to a sampling phase after an adjacent displacement of the target hopping edge; The determination unit is used to re-displace the sampling phase after each displacement according to a second predetermined displacement rule when the first adjacent phase label and the second adjacent phase label are equal, and to re-displace the sampling phase after each displacement according to a third predetermined displacement rule when the first adjacent phase label and the second adjacent phase label are not equal.

[0072] Furthermore, the first predetermined shift rule is to shift the sampling phase backward by 0.25 bits after each shift; the second predetermined shift rule is to shift the sampling phase forward by 0.125 bits after each shift; The third predetermined shift rule is to shift the sampling phase backward by 0.125 bits after each shift.

[0073] Furthermore, the data double oversampling system further comprises an initial module, an XOR module and a decision module; The initial module is used to sample corresponding bits during each initial sampling phase to obtain initial sampling data; The XOR module is used to perform XOR on two adjacent initial sampling data; The determination module is used to determine, when the XOR value of the two adjacent initial sampling data is 1, the hopping edge between the initial sampling phases corresponding to the two adjacent initial sampling data as the target hopping edge.

[0074] Furthermore, the second displacement module further comprises a reference unit, an acquisition unit and an optimization unit; the reference unit is adjacent to the hopping edge and is used to set an initial sampling phase after the target hopping edge as a second reference sampling phase; The acquisition unit is used to acquire each final sampling phase after the sampling phase after each displacement is again displaced, The optimization unit determines the final sampling phase adjacent to the final reference phase as the optimal sampling phase, and the final reference phase is the final sampling phase corresponding to the second reference sampling phase after the second reference sampling phase is displaced.

[0075] Furthermore, the first displacement module comprises a first displacement unit; The first displacement unit is used to displace each initial sampling phase forward by 0.25 bits.

[0076] The modules in the data double oversampling system can be implemented in whole or in part by software, hardware, or a combination thereof. The modules can be integrated into a processor in a computer system in the form of hardware, or can be independent of the processor, or can be stored in a memory in a computer system in the form of software, and the processor can call and execute the operations corresponding to the modules.

[0077] FIG. 9 is a structural schematic diagram of a computer device provided by an embodiment of the present invention. The computer device may be a server, and its internal structure is shown in FIG. The computer device includes a processor, memory, a network interface, and a database, all connected via a system bus. The processor of the computer device provides calculation and control capabilities. The memory of the computer device includes a computer storage medium and an internal memory. An operating system, a computer program, and a database are stored in the computer storage medium. The internal memory provides an environment for the operation of the operating system and the computer program in the computer storage medium. The database of the computer device stores data, such as lead codes and valid data, generated or acquired during the execution of the data double oversampling method. The network interface of the computer device is communicatively connected to an external terminal via a network. The data double oversampling method is implemented when the computer program is executed by the processor.

[0078] In one embodiment, a computer device is provided that includes a memory, a processor, and a computer program stored in the memory and operable on the processor, and when the processor executes the computer program, the steps of the data double oversampling method of the above embodiment are performed, or when the processor executes the computer program, the functions of each module / unit in the data double oversampling system embodiment are realized.

[0079] In one embodiment, a computer storage medium is provided that stores a computer program, which, when executed by a processor, performs the steps of the data double oversampling method in the above embodiment, or realizes the functions of each module / unit in the data double oversampling system embodiment.

[0080] Those skilled in the art will understand that the flow of implementing all or part of the methods in the above embodiments can be executed by associated hardware using a computer program, which is stored in a non-volatile computer-readable storage medium and, when executed, can include the flow of each of the above method embodiments. Herein, any reference to memory, storage, database, or other medium used in each embodiment provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of example and not limitation, RAM may include static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0081] For convenience and simplicity of explanation, the division of each functional unit or module has been described as an example. However, in actual applications, the above functions can be assigned to be performed by different functional units or modules as needed, i.e., it will be apparent to those skilled in the art that the internal structure of the device can be divided into different functional units or modules to perform all or part of the above functions.

[0082] The above embodiments are used to explain the technical solutions of the present invention, and are not intended to be limiting. The present invention has been described in detail with reference to the above embodiments. However, those skilled in the art may modify the technical solutions described in the above embodiments or make equivalent substitutions for some technical features. These modifications and substitutions will not deviate the essence of the relevant technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and all shall fall within the protection scope of the present invention.

Claims

1. 1. A data double oversampling method, comprising: S110: for two adjacent bits of a lead code in a GPON frame, obtain initial sampling phases corresponding to the two adjacent bits and phase labels corresponding to each initial sampling phase, and the GPON frame includes the lead code and valid data; S120: shifting the phase of each initial sampling and acquiring the sampling phase after each shift; S130: according to whether the adjacent phase labels of the target hopping edge before and after the shift are equal, and whether the first reference sampling phase, which is the sampling phase after the shift, is located on the target hopping edge, shift the sampling phase after each shift again to obtain the optimal sampling phase corresponding to the two adjacent bits, and the phase label corresponding to the first reference sampling phase is the same as the phase label corresponding to the sampling phase before the shift, which is adjacent to the target hopping edge and located after the target hopping edge; S140: sampling the valid data according to an optimal sampling phase corresponding to each bit of the read code; The step of again shifting the sampling phase after each shift according to whether adjacent phase labels of the target hopping edge before and after the shift are equal and whether the first reference sampling phase is located on the target hopping edge includes: determining whether the first reference sampling phase lies on the target hopping edge; if the first reference sampling phase is located on the target hopping edge, then again displacing the sampling phase after each displacement according to a first predetermined displacement rule; When the first reference sampling phase is not located on the target hopping edge, obtaining a first adjacent phase label of the target hopping edge according to the adjacent initial sampling phases of the target hopping edge and the phase labels corresponding to each initial sampling phase; Obtaining a second adjacent phase label of the target hopping edge according to a sampling phase after an adjacent displacement of the target hopping edge; if the first adjacent phase label and the second adjacent phase label are equal, then again shifting the sampling phase after each shift according to a second predetermined shift rule; if the first adjacent phase label and the second adjacent phase label are not equal, then again shifting the sampling phase after each shift according to a third predetermined shift rule; Before obtaining the first adjacent phase label of the target hopping edge according to the adjacent initial sampling phases of the target hopping edge and the phase labels corresponding to each initial sampling phase, the data double oversampling method includes: Sampling corresponding bits through each initial sampling phase to obtain initial sampling data; performing an XOR operation on two adjacent initial sampling data; If the XOR value of the two adjacent initial sampling data is 1, a hopping edge between the initial sampling phases corresponding to the two adjacent initial sampling data is set as the target hopping edge; The step of obtaining optimal sampling phases corresponding to two adjacent bits includes: an initial sampling phase adjacent to the hopping edge and located after the target hopping edge is set as a second reference sampling phase; obtaining final sampling phases after each shift of the sampling phase; a final sampling phase adjacent to a final reference phase is set as the optimum sampling phase, and a phase label corresponding to the final reference phase, which is the final sampling phase, is the same as a phase label corresponding to the second reference sampling phase; the target hopping edge is a hopping edge located between two adjacent bits; A data double oversampling method.

2. The step of shifting the phase of each initial sampling includes:

2. The method of claim 1, further comprising: shifting each initial sampling phase forward by 0.25 bits.

3. a receiving module for obtaining initial sampling phases and phase labels corresponding to two adjacent bits of a lead code in a GPON frame, the initial sampling phases corresponding to the two adjacent bits, the GPON frame including the lead code and valid data; a first shift module for shifting the phase of each initial sampling and obtaining a sampling phase after each shift; a second displacement module, which displaces each post-displacement sampling phase again according to whether the adjacent phase labels of the pre-displacement and post-displacement target hopping edges are equal and whether the post-displacement sampling phase, which is a first reference sampling phase, is located on the target hopping edge, to obtain an optimal sampling phase corresponding to the two adjacent bits, wherein the optimal sampling phase is close to the middle phase of the corresponding read code, and the phase label corresponding to the first reference sampling phase is the same as the phase label corresponding to the pre-displacement sampling phase, which is adjacent to the target hopping edge and located after the target hopping edge; a sampling module for sampling the valid data according to an optimal sampling phase corresponding to each bit of the read code; The second displacement module is Sampling corresponding bits through each initial sampling phase to obtain initial sampling data; XOR two adjacent initial sampling data; When the XOR value of the two adjacent initial sampling data is 1, a hopping edge between the initial sampling phases corresponding to the two adjacent initial sampling data is set as the target hopping edge; determining whether the first reference sampling phase lies on the target hopping edge; If the first reference sampling phase is located on the target hopping edge, then re-shift the sampling phase after each shift according to a first predetermined shift rule; When the first reference sampling phase is not located at the target hopping edge, obtain a first adjacent phase label of the target hopping edge according to the adjacent initial sampling phases of the target hopping edge and the phase labels corresponding to each initial sampling phase; Obtain a second adjacent phase label of the target hopping edge according to a sampling phase after an adjacent displacement of the target hopping edge; If the first adjacent phase label and the second adjacent phase label are equal, then again shift the sampling phase after each shift according to a second predetermined shift rule; if the first adjacent phase label and the second adjacent phase label are not equal, then again shift the sampling phase after each shift according to a third predetermined shift rule; an initial sampling phase adjacent to the hopping edge and located after the target hopping edge is a second reference sampling phase; The sampling phase after each displacement is displaced again to obtain each final sampling phase; a final sampling phase adjacent to a final reference phase is set as the optimal sampling phase, and a phase label corresponding to the final reference phase, which is the final sampling phase, is the same as a phase label corresponding to the second reference sampling phase; the target hopping edge is a hopping edge located between two adjacent bits; A data double oversampling system comprising:

4. 3. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer device performs the data double oversampling method according to claim 1 or 2 when the processor executes the computer program.

5. 3. A computer storage medium having stored thereon a computer program, the computer program being adapted to perform the steps of the method for double oversampling of data according to claim 1 or 2 when executed by a processor.

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