Optical semiconductor element and method for manufacturing the same

Abstract

An optical semiconductor element with improved efficiency relative to current, such as light-emitting efficiency or light-receiving sensitivity, and a method for manufacturing the optical semiconductor element are provided. The optical semiconductor device comprises a semiconductor laminate having at least one laminate structure including an active layer and a tunnel junction layer, a p-type cladding layer between the active layer and the tunnel junction layer, a first electron block layer between the active layer and the p-type cladding layer, and a second electron block layer between the p-type cladding layer and the tunnel junction layer, wherein the tunnel junction layer includes a p-type InGaAlAsP layer on the second electron block layer side and an n-type InGaAlAsP layer on the opposite side to the second electron block layer, the peak wavelength of the active layer is 1000 nm or more and 3000 nm or less, and the dopant concentration of the p-type cladding layer is 5.0×10 17 atoms / cm 3 Over 9.5 x 10 17 atoms / cm 3 and the thickness is 500 nm or less.

Description

[Technical Field]

[0001] The present invention relates to an optical semiconductor element and a method for manufacturing an optical semiconductor element. [Background technology]

[0002] Optical semiconductor elements that receive and emit light in the infrared region have been used in a wide range of applications, including infrared communications, proximity sensors in monitoring systems, and optical measurements in medical diagnostic equipment.

[0003] For example, Patent Document 1 discloses an infrared LED element with a peak emission wavelength of 1000 nm or more. This infrared LED element includes an n-type first cladding layer, an emission layer disposed on the first cladding layer, a p-type second cladding layer disposed on the emission layer, a first tunnel layer disposed on the second cladding layer and having a higher p-type dopant concentration than the second cladding layer, a second tunnel layer disposed on the first tunnel layer and having a higher n-type dopant concentration than the first cladding layer and forming a tunnel junction with the first tunnel layer, an n-type contact layer disposed on the second tunnel layer, a first electrode in contact with the first cladding layer directly or via a layer made of a conductive non-alloy material, and a second electrode in contact with the contact layer. The first cladding layer and emission layer of this infrared LED element are made of materials lattice-matchable to InP single crystal.

[0004] According to Patent Document 1, in this infrared LED element, by including Ga and As in one or both of the first tunnel layer and the second tunnel layer, it is possible to reduce the applied voltage (forward voltage) when injecting the same amount of current into the infrared LED element, compared to when both the first tunnel layer and the second tunnel layer are formed of InP. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2024-106499 Summary of the Invention [Problem to be solved by the invention]

[0006] When the optical semiconductor element is a semiconductor light-emitting element that emits light in the infrared region, further improvements in light-emitting efficiency are required. Also, when the optical semiconductor element is a semiconductor light-receiving element that receives light in the infrared region, further improvements in light-receiving sensitivity are required.

[0007] Therefore, the present invention provides an optical semiconductor element with improved efficiency relative to current, such as light-emitting efficiency or light-receiving sensitivity, and a method for manufacturing the optical semiconductor element. [Means for solving the problem]

[0008] In optical semiconductor devices, the mobility of a p-type semiconductor layer is approximately 1 / 20 of that of an n-type semiconductor layer, even with the same thickness. Therefore, to diffuse current laterally and increase the current reaching the active layer, it is necessary to increase the dopant concentration and ensure a sufficient thickness of the p-type semiconductor layer, specifically a thickness of 1000 nm or more. In fact, even when a tunnel junction is sandwiched between the second electrode and a p-type window layer or cladding layer, as in the aforementioned Patent Document 1, it was thought that a thickness of 1000 nm or more was required for the p-type semiconductor layer. However, the present inventors experimentally confirmed that, when a tunnel junction is sandwiched, a thin p-type cladding layer provided between the active layer and the tunnel junction layer with a relatively low dopant concentration can provide better device characteristics, leading to the completion of the present invention.

[0009] That is, the gist and configuration of the present invention are as follows. (1) A semiconductor laminate having at least one laminate structure including an active layer and a tunnel junction layer, a p-type cladding layer between the active layer and the tunnel junction layer, a first electron blocking layer between the active layer and the p-type cladding layer, and a second electron blocking layer between the p-type cladding layer and the tunnel junction layer, the tunnel junction layer includes a p-type InGaAlAsP layer on the second electron block layer side and an n-type InGaAlAsP layer on the opposite side to the second electron block layer, the peak wavelength of the active layer is 1000 nm or more and 3000 nm or less, The dopant concentration of the p-type cladding layer is 5.0×10 17 atoms / cm 3 Over 9.5 x 10 17 atoms / cm 3 and the thickness is 500 nm or less, Optical semiconductor element.

[0010] (2) The optical semiconductor element according to (1) above, wherein the second electron blocking layer has a thickness of 30 nm or more and 70 nm or less.

[0011] (3) The optical semiconductor element according to (1) or (2) above, wherein the first electron blocking layer is undoped and the second electron blocking layer is p-type doped.

[0012] (4) The optical semiconductor element according to any one of (1) to (3) above, wherein the semiconductor laminate is located between a first n-type electrode and a second n-type electrode.

[0013] (5) The optical semiconductor element according to any one of (1) to (4) above, wherein the semiconductor laminate has the laminate structure between a first n-type cladding layer and a second n-type cladding layer.

[0014] (6) The optical semiconductor device according to any one of (1) to (5) above, further comprising an undoped spacer layer between the first electron blocking layer and the p-type cladding layer.

[0015] (7) On the substrate, forming a semiconductor laminate having at least one laminate structure including an active layer and a tunnel junction layer, a p-type cladding layer between the active layer and the tunnel junction layer, a first electron blocking layer between the active layer and the p-type cladding layer, and a second electron blocking layer between the p-type cladding layer and the tunnel junction layer; the tunnel junction layer includes a p-type InGaAlAsP layer on the second electron block layer side and an n-type InGaAlAsP layer on the opposite side to the second electron block layer, the peak wavelength of the active layer is 1000 nm or more and 3000 nm or less, The dopant concentration of the p-type cladding layer is 5.0×10 17 atoms / cm 3 Over 9.5 x 10 17 atoms / cm 3 and the thickness is 500 nm or less, A method for manufacturing an optical semiconductor element.

[0016] (8) The method for manufacturing an optical semiconductor element described in (7) above, further comprising the step of forming a first n-type electrode and a second n-type electrode so that the semiconductor laminate is located between the first n-type electrode and the second n-type electrode.

[0017] (9) The method for manufacturing an optical semiconductor element according to claim 7, wherein the step of forming the semiconductor laminate further comprises the steps of forming a first n-type cladding layer before forming an active layer of the laminate structure, and forming a second n-type cladding layer after forming a tunnel junction layer of the laminate structure. [Effects of the Invention]

[0018] According to the present invention, it is possible to provide an optical semiconductor element and a method for manufacturing an optical semiconductor element in which efficiency relative to current, such as light-emitting efficiency or light-receiving sensitivity, is improved. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a cross-sectional view illustrating a first embodiment of an optical semiconductor element according to the present invention. [Figure 2] FIG. 3 is a cross-sectional view illustrating a second embodiment of an optical semiconductor element according to the present invention. [Figure 3] 5A to 5C are cross-sectional views illustrating an example of a method for manufacturing the second embodiment of the optical semiconductor element according to the present invention. [Figure 4] FIG. 4 is a schematic cross-sectional view illustrating an example of a manufacturing method following FIG. 3. [Figure 5] FIG. 5 is a schematic cross-sectional view illustrating an example of a manufacturing method following FIG. 4. [Figure 6] FIG. 4 is a cross-sectional view illustrating a third embodiment of an optical semiconductor element according to the present invention. [Figure 7] 10 is a graph showing changes in WPE when the dopant concentration of the p-type cladding layer is the same but the thickness is different in an example. DETAILED DESCRIPTION OF THE INVENTION

[0020] Prior to describing the embodiments according to the present invention, the following points will be explained in advance.

[0021] In this specification, "InGaAlAsP" refers to In, Ga, and Al whose composition ratios are a, b, and 1-ab, respectively, and As and P whose composition ratios are x and 1-x, respectively. a Ga b Al 1-a-b As x P 1-x This means that the In composition ratio a, Ga composition ratio b, and As composition ratio x of the InGaAlAsP composition ratio in this embodiment are determined from the wavelength observed in photoluminescence measurement performed on the surface of each layer when the layer is grown. Unless otherwise specified, the composition ratios a, b, and x are 0 to 1, and 0≦1−ab≦1, 0≦1−x≦1. Energy dispersive X-ray spectroscopy (EDS), for example, can be used as a method for determining the In composition ratio a, Ga composition ratio b, and As composition ratio x from the cross section of the optical semiconductor device.

[0022] In this specification, the peak wavelength means the emission peak wavelength at which the peak intensity is obtained in the emission spectrum when the optical semiconductor element is a semiconductor light-emitting element, or means the light-receiving peak wavelength at which the peak intensity is obtained in the light-receiving spectrum when the optical semiconductor element is a semiconductor light-receiving element.

[0023] In this specification, the composition wavelength refers to the wavelength of light corresponding to the band gap energy of each layer in a III-V compound semiconductor layer. The smaller the composition wavelength, the larger the band gap energy. Here, the first electron blocking layer and the second electron blocking layer are layers that have a smaller composition wavelength (larger band gap energy) than the active layer and the p-type cladding layer in order to block electrons.

[0024] In this specification, when a specific dopant such as Zn, Te, or Si is not intentionally added, it is referred to as "i" type or "undoped." An undoped layer may contain unavoidable dopants during the manufacturing process. Specifically, the dopant concentration is small and close to the lower limit of detection in SIMS (secondary ion mass spectrometry) analysis (for example, 4 × 10 16 / cm 3 In this specification, n-type and p-type dopant concentrations are treated as "undoped" when the film thickness is less than 40 nm. In this specification, the n-type and p-type dopant concentrations were measured by secondary ion mass spectrometry (SIMS, CAMECA IMS-4f manufactured by AMTEC). The analysis conditions were primary species: Cs+, primary energy: 14.5 keV, and secondary polarity: negative. The dopant concentration value of each layer in the SIMS profile is the average value excluding the edge (5 nm wide) that contacts other layers when the film thickness is greater than 40 nm, and is the maximum value (peak value) of the SIMS of the corresponding layer when the film thickness is 40 nm or less.

[0025] The III-V compound semiconductor of this embodiment contains at least one of Al, Ga, and In as a group III element, and at least P, As, and Sb as a group V element.

[0026] The thickness of each layer formed by epitaxial growth can be calculated from cross-sectional observation of the grown layer using a scanning electron microscope (SEM) or a transmission electron microscope (TEM). It is preferable to use an SEM when the film thickness is 10 nm or more, and a TEM when the film thickness is less than 10 nm.

[0027] In this specification, when two or more stacked structures are present, the peak wavelengths of the active layers of these stacked structures may be different from each other or may be similar to each other. When the peak wavelengths are different from each other, different roles can be assigned to each peak wavelength. In this specification, "peak wavelengths that are similar to each other" means that the peak wavelengths are positioned so that at least a portion of the full width at half maximum range in the spectrum overlaps, meaning that the wavelength difference is within the full width at half maximum value (e.g., within 100 nm). For example, when the emission peak wavelengths are the same or similar to each other, the emission spectra are combined, which is effective in improving the emission intensity. The above description was given in the case of a semiconductor light-emitting element, but the same applies to a semiconductor light-receiving element.

[0028] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, the aspect ratio of the substrate and each layer is exaggerated from the actual ratio for the sake of convenience. Hereinafter, III-V compound semiconductors composed of three or more elements may be described in a form in which the composition ratio of each element is omitted (for example, "InGaAlAsP").

[0029] The optical semiconductor device according to the present invention comprises a semiconductor stack having at least one stack structure including an active layer and a tunnel junction layer, a p-type cladding layer between the active layer and the tunnel junction layer, a first electron block layer between the active layer and the p-type cladding layer, and a second electron block layer between the p-type cladding layer and the tunnel junction layer. The layers described in the stack structure do not need to be in direct contact with each other, and other layers, such as spacer layers or intermediate layers, may be present between the layers. The semiconductor stack may also include layers other than the stack structure, such as spacer layers, intermediate layers, and layers such as n-type cladding layers or n-type contact layers. The tunnel junction layer includes a p-type InGaAlAsP layer on the second electron block layer side and an n-type InGaAlAsP layer on the opposite side from the second electron block layer. In other words, the order of the tunnel junction layer is such that the p-type InGaAlAsP layer is located on the inner side of the stack structure (the second electron block layer side), and the n-type InGaAlAsP layer is located on the outer side of the stack structure. The peak wavelength of the active layer in the semiconductor laminate is 1000 nm or more and 3000 nm or less. The dopant concentration of the p-type cladding layer is 5.0×10 17 atoms / cm 3 Over 9.5 x 10 17 atoms / cm 3 and the thickness is 500 nm or less.

[0030] First, a first embodiment of a semiconductor light-emitting device as an optical semiconductor device having a semiconductor laminate on a growth substrate will be described. Next, a second embodiment of a junction-type semiconductor light-emitting device obtained by bonding a support substrate and then removing the growth substrate will be described. In a third embodiment, a semiconductor light-emitting device having a semiconductor laminate having multiple laminate structures will be described. Finally, in a fourth embodiment, an embodiment of a semiconductor light-receiving device as an optical semiconductor device will be described. An optical semiconductor device can be a semiconductor light-emitting device or a semiconductor light-receiving device, but a semiconductor light-emitting device is preferable. Note that, as exemplified in the second embodiment, the order of the layers grown on the growth substrate and the order of the layers after the processing step involving removal of the growth substrate may be reversed. Therefore, the top and bottom of the overall laminate structure in the optical semiconductor device do not matter, and either the tunnel junction layer or the active layer may be at the top.

[0031] (First embodiment) Referring to FIG. 1 , an example of an optical semiconductor device 100, which is a first embodiment of an optical semiconductor device according to the present invention, will be described as a semiconductor light-emitting device, along with a manufacturing method. The optical semiconductor device 100 includes a growth substrate 105 and a semiconductor stack 120, which is composed of multiple semiconductor layers stacked on the growth substrate 105 and emits light when current is applied. The semiconductor stack 120 includes at least one stack structure 150 having, in this order, an active layer 124, a first electron blocking layer 125, a p-type cladding layer 127, a second electron blocking layer 128, and a tunnel junction layer 129. In this embodiment, the semiconductor stack 120 has one stack structure. The tunnel junction layer 129 includes, in this order, a p-type InGaAlAsP layer 1291 and an n-type InGaAlAsP layer 1292. The active layer 124 has an emission peak wavelength of 1000 nm or more and 3000 nm or less. The semiconductor laminate 120 is located between the first n-type electrode 191 and the second n-type electrode 195. Details of each component will be explained below.

[0032] In the first embodiment, a first n-type contact layer 121, a first n-type cladding layer 122, and a first spacer layer 123 are sequentially deposited on a growth substrate 105, and an active layer 124, a first electron blocking layer 125, a second spacer layer 126, a p-type cladding layer 127, a second electron blocking layer 128, and a tunnel junction layer 129 (a p-type tunnel junction layer 1291 and an n-type tunnel junction layer 1292) are sequentially deposited thereon as a stacked structure, and a second n-type cladding layer (sometimes referred to as a window layer) 130 and a second n-type contact layer 131 are sequentially deposited thereon, resulting in an optical semiconductor device 100 using the growth substrate 105 as a substrate as is. Note that the terms "sequentially deposited" and "sequentially formed" only refer to the order in which the listed layers are formed, and it is understood that other layers (such as a p-type intermediate layer or an n-type intermediate layer) not listed may be inserted between the layers. Furthermore, optical semiconductor device 100 has first n-type electrode 191 formed on the back surface of growth substrate 105 as a back surface electrode, and second n-type electrode 195 formed on second n-type contact layer 131 as an n-type ohmic electrode.

[0033] As another aspect of the first embodiment, the order of the layers may be reversed. For example, the second n-type contact layer 131 and the second n-type cladding layer 130 may be sequentially formed on the growth substrate 105, and the tunnel junction layer 129 (the n-type tunnel junction layer 1292 and the p-type tunnel junction layer 1291), the second electron blocking layer 128, the p-type cladding layer 127, the second spacer layer 126, the first electron blocking layer 125, and the active layer 124 may be sequentially formed thereon as a stacked structure, and the first spacer layer 123, the first n-type cladding layer 122, and the first n-type contact layer 121 may be sequentially formed thereon. A first n-type electrode 191 may be formed on the back surface of the growth substrate 105 as a back surface electrode, and a second n-type electrode 195 may be formed on the first n-type contact layer 121 as an n-type ohmic electrode. In this way, by providing a p-type layer between the active layer 124 and the tunnel junction layer 129 in a stacked structure in which the active layer 124 and the tunnel junction layer 129 are stacked, an npn-type configuration in which an n-type layer is located outside the stacked structure can be obtained without relying on the examples described above.

[0034] First, a description will be given of a substrate applicable to the optical semiconductor element 100. The substrate used in the present invention may be any substrate having a thickness sufficient to mechanically maintain the shape of the semiconductor laminate 120 including the active layer 124 and the tunnel junction layer 129, and may be the growth substrate 105 used for epitaxial growth when forming the semiconductor laminate 120 of the optical semiconductor element 100.

[0035] The growth substrate 105 can be a compound substrate such as GaAs, InP, InAs, GaSb, or InSb. The conductivity type of the growth substrate 105 may be n-type, p-type, or undoped, and various semiconductor layers may be provided appropriately depending on the conductivity type. For ease of explanation, the following description assumes that the growth substrate 105 is n-type doped. The thickness of the growth substrate 105 is preferably 100 μm or more and 1000 μm or less. Below, we will briefly explain examples of various semiconductor layers when the growth substrate 105 is n-type doped. When a substrate lattice-mismatched with the first n-type contact layer 121 is used as the growth substrate 105, a buffer layer to alleviate the lattice mismatch may be provided between the growth substrate 105 and the first n-type contact layer 121.

[0036] A first n-type contact layer 121 made of a III-V compound semiconductor layer may be provided on the growth substrate 105. The first n-type contact layer 121 has high conductivity and is advantageous for forming an electrode. The thickness of the first n-type contact layer 121 is preferably 10 nm or more and 500 nm or less. Dopants that can be used here include Si, Te, S, Ge, Sn, Se, etc., with Si being preferred. The dopant concentration of the first n-type contact layer 121 is preferably the same as or higher than the dopant concentration of the first n-type cladding layer 122 described next, and is preferably 1.0×10 17 / cm 3 Over 1.0 x 10 18 / cm 3 More preferably, it is:

[0037] A first n-type cladding layer 122 made of a III-V compound semiconductor layer may be provided on the first n-type contact layer 121, and its thickness is preferably 500 nm to 6000 nm. Examples of dopants that can be used here include Si, Te, S, Ge, Sn, and Se, with Si being preferred. When the thickness of the first n-type cladding layer 122 is 500 nm or greater, defects are less likely to propagate to the active layer 124, even if the lattice constants of the growth substrate 105 and the active layer 124 differ. Additionally, a thickness of 500 nm or greater ensures that a sufficient number of carriers are supplied to the active layer 124, increasing the light-emitting output. Furthermore, by limiting the thickness of the first n-type cladding layer 122 to 6000 nm or less, excessive growth that does not significantly improve the characteristics is suppressed, reducing raw material costs and contributing to improved productivity.

[0038] The dopant concentration of the first n-type cladding layer 122 is preferably the same as or lower than that of the first n-type contact layer 121, and is preferably 1.0×10 17 / cm 3 Over 1.0 x 10 18 / cm 3 It is more preferable to set the following:

[0039] A first spacer layer 123 may be provided between the first n-type cladding layer 122 and the active layer 124. The thickness of the first spacer layer 123 is preferably 10 nm or more and 200 nm or less. The first spacer layer 123 preferably has the same composition as the adjacent layer on the growth substrate side and is an undoped layer. This first spacer layer 123 reduces the amount of impurity diffusion from the doped layer to the undoped layer, for example, reducing the amount of n-type dopant diffusing from the first n-type cladding layer 122 to the active layer 124.

[0040] <Active layer> The active layer 124 is preferably undoped. Furthermore, while there are no particular limitations on the active layer 124 as long as its emission peak wavelength is between 1000 nm and 3000 nm, the active layer 124 preferably contains InGaAlAs or InGaAsP. While FIG. 1 exemplarily illustrates a quantum well structure in which the well layer of the active layer 124 is the well layer 124w and the barrier layer is the barrier layer 124b, the active layer 124 may have a single-layer structure. The well layer 124w and the barrier layer 124b may be different layers, or the composition difference may be adjusted to apply strain to the well layer 124w. Furthermore, the active layer 124 may be formed using, for example, InGaAlAs layers with different composition ratios. To improve optical output by suppressing crystal defects, the active layer 124 preferably has a multiple quantum well (MQW) structure as shown in FIG. 1. This multiple quantum well structure can be formed by alternating the well layer 124w and the barrier layer 124b. When a multiple quantum well structure is used, the number of combinations of well layers 124w and barrier layers 124b is preferably 3 to 40. That is, the number of combinations, including the first barrier layer, is preferably 3.5 to 40.5. Furthermore, the thickness of each well layer 124w is preferably 2 to 40 nm, and the thickness of each barrier layer 124b is preferably 5 to 50 nm. By adjusting the composition or composition ratio of the well layers 124w and the barrier layers 124b, the peak emission wavelength of the optical semiconductor device 100 can be adjusted to 1000 to 3000 nm. The peak emission wavelength of the optical semiconductor device 100 is preferably 1200 to 2500 nm, more preferably 1300 to less than 2000 nm, and even more preferably 1400 to 1600 nm.

[0041] <First electron blocking layer> A first electron blocking layer 125 is provided on the first active layer 124. The first electron blocking layer 125 is preferably undoped. The thickness of the first electron blocking layer 125 is preferably 5 nm or more and 50 nm or less, and more preferably 10 nm or more and 30 nm or less. Furthermore, the first electron blocking layer 125 is preferably lattice-matched with the active layer 124.

[0042] <<Second Spacer Layer>> A second spacer layer 126 may be provided on the first electron blocking layer 125. The second spacer layer 126 is preferably undoped and preferably has the same composition as the p-type cladding layer 127 described later. The thickness of the second spacer layer 126 depends on the degree of diffusion of the p-type dopant doped in the p-type cladding layer 127. When the p-type dopant doped in the p-type cladding layer 127 is Zn, since the diffusion is relatively large, the thickness of the second spacer layer 126 is preferably relatively thick so that the dopant does not diffuse into the active layer 124. In this case, the thickness of the second spacer layer 126 is preferably 100 nm or more and 400 nm or less, and more preferably 250 nm or more and 350 nm or less. On the other hand, when the p-type dopant doped in the p-type cladding layer 127 is C, since the diffusion is relatively small, the thickness of the second spacer layer 126 is preferably relatively small and may not be formed. In this case, the thickness of the second spacer layer 126 is preferably 0 nm or more and 300 nm or less, and more preferably 50 nm or more and 200 nm or less.

[0043] <p-type cladding layer> A p-type cladding layer 127 can be provided on the second spacer layer 126. Examples of the p-type cladding layer 127 include a p-type InP layer or a p-type InGaAlAs layer. Examples of the p-type dopant doped in the p-type cladding layer 127 include Mg, Zn, C, Be, etc., and Zn or C is preferred. The first electron blocking layer 125 and the second electron blocking layer 128 described later preferably have a smaller compositional wavelength than the p-type cladding layer 127. For example, when the compositional wavelength of the p-type cladding layer 127 is 920 nm, the compositional wavelengths of the first electron blocking layer 125 and the second electron blocking layer 128 can be set to 880 nm. The dopant concentration of the p-type cladding layer 127 is 5.0×10 17 atoms / cm 3 or more and 9.5×10 17 atoms / cm 3 or less, and 5.0×10 17 atoms / cm 3 or more and 8.5×10 17 atoms / cm [[ID=Preferably, the thickness is 5.0×10 atoms / cm or less, more preferably 5.0×10 atoms / cm or more and 8.0×10 atoms / cm or less, and even more preferably 5.0×10 atoms / cm or more and 7.5×10 atoms / cm or less. The thickness of the p-type cladding layer 127 is 500 nm or less, preferably 400 nm or less, preferably 300 nm or less, more preferably 150 nm or less, and even more preferably 100 nm or less. There is no particular lower limit to the thickness of the p-type cladding layer 127, but due to manufacturing constraints, it may be 1 nm or more, 5 nm or more, preferably 10 nm or more, and more preferably 20 nm or more. The inventors have proposed that a p-type cladding layer with a lower dopant concentration and thinner thickness than conventional layers improves current efficiency by increasing the dopant concentration of 1.0×10 18 atoms / cm 3 Unlike the p-cladding layer, for which a high dopant concentration and a thick film are considered ideal, in this structure having a tunnel junction layer and two electron blocking layers, sufficient current spreading can be obtained if holes can be supplied to the tunnel junction layer to the extent that it does not become a high-resistance layer, and it is expected that the light transmittance is improved by the low dopant concentration and thickness range that minimizes impurity scattering.

[0044] <Second electron blocking layer> A second electron blocking layer 128 is provided on the p-type cladding layer 127. The second electron blocking layer 128 is formed to prevent electrons overflowing from the first electron blocking layer 125 from reaching and interfering with the tunnel junction where the reverse current is flowing. The second electron blocking layer 128 is preferably p-doped. Examples of p-type dopants to be doped into the second electron blocking layer 128 include Mg, Zn, C, and Be, with Zn or C being preferred. The composition wavelengths of the first electron blocking layer 125 and the second electron blocking layer 128 are preferably shorter than those of the p-type cladding layer 127, and more preferably have the same composition. For example, when the first electron blocking layer 125 is undoped InAlAs, the second electron blocking layer 128 is preferably p-type InAlAs. The thickness of the second electron blocking layer 128 is preferably 30 nm to 70 nm, more preferably 40 nm to 60 nm, and even more preferably 45 nm to 55 nm.

[0045] Although not shown, a p-type intermediate layer may be provided between the second electron blocking layer 128 and the tunnel junction layer 129. The impurity concentration or composition wavelength of these layers is preferably between the impurity concentration and composition wavelength of the second electron blocking layer 128 and the impurity concentration and composition wavelength of the p-type tunnel junction layer 1291. The p-type intermediate layer may be a single layer or multiple layers. Providing the p-type intermediate layer facilitates carrier movement, thereby reducing the resistance when a reverse current flows in the tunnel junction layer 129, which will be described later. For example, p-type InGaAsP or p-type AlInGaAs can be used for the p-type intermediate layer.

[0046] <Tunnel junction layer> A tunnel junction layer 129 including a p-type tunnel junction layer 1291 and an n-type tunnel junction layer 1292 is provided on the second electron blocking layer 128. The n-type tunnel junction layer 1292 is deposited directly on the p-type tunnel junction layer 1291. The p-type tunnel junction layer 1291 and the n-type tunnel junction layer 1292 are p-type InGaAlAsP and n-type InGaAlAsP, respectively. Dopants that can be used for the p-type tunnel junction layer 1291 include Mg, Zn, C, and Be, with C being preferred. Using C as the dopant for the p-type tunnel junction layer 1291 can suppress dopant diffusion into adjacent epitaxial layers during growth compared to other dopants. Dopants that can be used for the n-type tunnel junction layer 1292 include Si, Te, S, Ge, Sn, and Se, with Si being preferred. By using Si as the dopant for the n-type tunnel junction layer 1292, the dopant diffusion phenomenon into the adjacent epitaxial layer during growth can be suppressed compared to other dopants.

[0047] The p-type tunnel junction layer 1291 and the n-type tunnel junction layer 1292 each have a dopant concentration of 1.0×10 19 atoms / cm 3 For example, when the dopant of the p-type tunnel junction layer 1291 is C, the dopant concentration according to SIMS analysis is 1.0×10 19 atoms / cm 3 It is preferable that the value is 5.0×10 or more. 19 atoms / cm 3 For example, when the dopant of the n-type tunnel junction layer 1292 is Te, the dopant concentration is 1.0×10 19 atoms / cm 3 It is preferable that the value is 3.0×10 or more. 19 atoms / cm 3 When the dopant of the n-type tunnel junction layer 1292 is Si, the dopant concentration is preferably 1.0×10 19 atoms / cm 3 It is preferable that the value is 1.5×10 or more.19 atoms / cm 3 The thickness of the p-type tunnel junction layer 1291 is preferably 5 nm or more and 50 nm or less, and more preferably 20 nm or more and 40 nm or less. The thickness of the n-type tunnel junction layer 1292 is preferably 5 nm or more and 30 nm or less, and more preferably 10 nm or more and 20 nm or less. The thickness and dopant concentrations of the p-type tunnel junction layer 1291 and the n-type tunnel junction layer 1292 may be the same or different. Furthermore, the impurity concentrations of the p-type tunnel junction layer 1291 and the n-type tunnel junction layer 1292 do not need to be uniform within the layers, and a concentration gradient may exist.

[0048] Although not shown, an n-type intermediate layer may be provided on the tunnel junction layer 129. The dopant concentration of the n-type intermediate layer is preferably lower than that of the n-type tunnel junction layer 1292 described above, and is preferably higher than that of the second n-type cladding layer 130 described below.

[0049] A second n-type cladding layer (window layer) 130 made of a III-V compound semiconductor layer may be provided on the n-type intermediate layer, and its thickness is preferably 500 nm to 2000 nm. A thickness of 500 nm or more for the second n-type cladding layer 130 allows current to spread over an appropriate range of the LED chip. This not only suppresses surface recombination but also reduces the ohmic resistance of the device, thereby improving light emission efficiency. Furthermore, a thickness of 500 nm or more for the second n-type cladding layer 130 prevents light from being emitted only directly below the electrode, enabling efficient light extraction. Examples of dopants that can be used here include Si, Te, S, Ge, Sn, and Se, with Si being preferred. The dopant concentration of the second n-type cladding layer 130 is 1.0×10 17 atoms / cm 3 Over 5.0 x 10 18 atoms / cm 3 Preferably, it is 3.0 x 10 or less. 17 atoms / cm 3 Over 3.0 x 10 18 atoms / cm 3 More preferably, it is:

[0050] A second n-type contact layer 131 made of a III-V compound semiconductor layer may be provided on the second n-type cladding layer 130, and its thickness is preferably 20 nm or more and 300 nm or less. The size of the second n-type contact layer 131 may be larger than the second n-type electrode 195 described later, but it is preferably formed only directly below the second n-type electrode 195. This is to minimize the amount of light absorbed by the second n-type contact layer 131. The second n-type contact layer 131 makes ohmic contact with the second n-type electrode 195 described later. The dopant concentration of the second n-type contact layer 131 is higher than the dopant concentration of the second n-type cladding layer 130, and is 1.0×10 18 atoms / cm 3 Over 3.0 x 10 19 atoms / cm 3 Preferably, it is 3.0 x 10 or less. 18 atoms / cm 3 Over 2.0 x 10 19 atoms / cm 3 More preferably, it is:

[0051] For convenience, the layers from the first n-type contact layer 121 to the second n-type cladding layer 130 will be collectively referred to as the semiconductor laminate 120.

[0052] It is preferable to provide a second n-type electrode 195 on at least a portion or the entire surface of the second n-type contact layer 131. Furthermore, it is preferable to provide a first n-type electrode 191 on the back surface of the growth substrate 105. It is preferable to position the growth substrate 105 and the semiconductor stack 120 between the first n-type electrode 191 and the second n-type electrode 195. Positioning the semiconductor stack 120 between the first n-type electrode 191 and the second n-type electrode 195 does not necessarily mean directly sandwiching the semiconductor stack 120 between the electrodes, but may also mean sandwiching the semiconductor stack 120 via a substrate or the like. Furthermore, a mesa may be formed in the semiconductor stack 120, and a portion of the first n-type contact layer 121 may be exposed and the first n-type electrode 191 may be provided thereon, thereby forming two electrodes on the top surface (flip-chip type). Here, the second n-type electrode 195 may include a wiring portion and a pad portion of an ohmic electrode. Although not shown, the pad portion may have a metal layer or solder for bonding. Known metal materials and formation methods can be used for the first n-type electrode 191 and the second n-type electrode 195. Examples of metal materials that can be used include Ti, Pt, Au, Ag, Al, Ge, and Ni.

[0053] An example of an embodiment of the manufacturing method of the optical semiconductor device 100 described above will be described below. The manufacturing method of the optical semiconductor device 100 includes a step of forming, on a growth substrate 105, a semiconductor stack 120 having at least one stack structure including an active layer 124 and a tunnel junction layer 129, a p-type cladding layer 127 between the active layer 124 and the tunnel junction layer 129, a first electron block layer 125 between the active layer 124 and the p-type cladding layer 127, and a second electron block layer 128 between the p-type cladding layer 127 and the tunnel junction layer 129. In this embodiment, the semiconductor stack 120 has one stack structure. The tunnel junction layer 129 includes a p-type InGaAlAsP layer 1291 on the second electron block layer 128 side and an n-type InGaAlAsP layer 1292 on the opposite side to the second electron block layer 128. The peak wavelength of the active layer 124 is 1000 nm or more and 3000 nm or less, and the dopant concentration of the p-type cladding layer 127 is 5.0×10 17 atoms / cm 3 Over 9.5 x 10 17 atoms / cm 3and a thickness of 500 nm or less. As an example, in an embodiment of this manufacturing method, when growth substrate 105 is n-type or undoped, optical semiconductor device 100 includes first n-type contact layer 121, first n-type cladding layer 122, and first spacer layer 123 grown, followed by sequential formation of active layer 124, first electron blocking layer 125, p-type cladding layer 127, second electron blocking layer 128, and tunnel junction layer 129 as a laminated structure. When forming tunnel junction layer 129, p-type InGaAlAsP layer 1291 is formed on second electron blocking layer 128, and n-type InGaAlAsP layer 1292 is formed directly on p-type InGaAlAsP layer 1291. If necessary, undoped second spacer layer 126 may be formed between first electron blocking layer 125 and p-type cladding layer 127 to suppress migration of dopants from p-type cladding layer 127 to the active layer. As mentioned above, the dopant concentration of the p-type cladding layer 127 is 5.0×10 17 atoms / cm 3 Over 9.5 x 10 17 atoms / cm 3 and the thickness is 500 nm or less.

[0054] One or more layers selected from a first n-type contact layer 131, an n-type cladding layer 122, and a first spacer layer 123 may be formed between the growth substrate 105 and the active layer 124, and one or more layers selected from a second n-type cladding layer (window layer) 130 and a second n-type contact layer 131 may be formed on the tunnel junction layer 129.

[0055] The semiconductor stack 120 is located between a second n-type electrode 195 on the second n-type contact layer 131 and a first n-type electrode 191 on the back surface of the growth substrate 105. The second n-type electrode 195 and the first n-type electrode 191 can be formed by, for example, vapor deposition.

[0056] Each semiconductor layer can be formed by epitaxial growth, for example, by a known thin film growth method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). For example, trimethylindium (TMIn) as an In source, trimethylgallium (TMGa) or triethylgallium (TEGa) as a Ga source, trimethylaluminum (TMAl) as an Al source, arsine (AsH) or tertiarybutylarsine (TBAs) as an As source, and phosphine (PH) or tertiarybutylphosphine (TBP) as a P source can be mixed in a predetermined ratio. These source gases can be vapor-phase grown using a carrier gas to form a desired thickness depending on the growth time. To dope each layer to p-type or n-type, a desired dopant source gas can be further added. For example, to dope Zn, DEZn (diethylzinc) gas or the like can be used. Incidentally, InAs is n-type even when undoped.

[0057] When a forward voltage is applied from the second n-type electrode 195 to the first n-type electrode 191, the forward voltage is applied to the active layer 124, causing the active layer 124 to emit light. At this time, a reverse voltage is applied to the tunnel junction (pn junction) in the tunnel junction layer 129. As a result, a current also flows in the reverse direction in the tunnel junction layer 129 due to the tunnel effect.

[0058] The optical semiconductor device 100 described above is a semiconductor light emitting device with excellent light emitting efficiency.

[0059] (Second embodiment) 2 to 5, an optical semiconductor element 200 according to a second embodiment of the present invention will be described. The optical semiconductor element 200 is a junction-type optical semiconductor element obtained by bonding a support substrate 280 and then removing a growth substrate 205. This optical semiconductor element 200 is also a semiconductor light-emitting element with excellent light-emitting efficiency. In principle, components identical to those of the optical semiconductor element 100 are designated by the same reference numerals, the last two of which are three digits, and redundant explanations will be omitted. The semiconductor stack 220 has one stack structure 250 including an active layer 224 and a tunnel junction layer 229, a p-type cladding layer 227 between the active layer 224 and the tunnel junction layer 229, a first electron blocking layer 225 between the active layer 224 and the p-type cladding layer 227, and a second electron blocking layer 228 between the p-type cladding layer 227 and the tunnel junction layer 229. Tunnel junction layer 229 includes a p-type InGaAlAsP layer 2291 on the second electron blocking layer 228 side and an n-type InGaAlAsP layer 2292 on the opposite side to second electron blocking layer 228. Semiconductor stack 220 is located between first n-type electrode 291 and second n-type electrode 295. Optical semiconductor device 200 includes at least support substrate 280, metal bonding layer 279 and metal reflective layer 271 provided on the surface of support substrate 280, power distribution unit 260 having transparent insulating layer 261 with a through-hole on metal reflective layer 271 and an ohmic electrode portion provided in the through-hole as second n-type electrode 295, semiconductor stack 220 provided on power distribution unit 260, and first n-type electrode 291 provided on a portion of semiconductor stack 220.

[0060] 2 includes, in order from the side opposite to the support substrate 280, a first n-type contact layer 221, a first n-type cladding layer 222, a first spacer layer 223, an active layer 224, a first electron blocking layer 225, a second spacer layer 226, a p-type cladding layer 227, a second electron blocking layer 228, a tunnel junction layer 229, and a second n-type cladding layer 230. The first n-type contact layer 221 is formed in the center of the upper surface of the semiconductor stack 220, and a first n-type electrode 291 is formed on at least the upper surface thereof. In addition, a back surface electrode 299 is formed on the back surface of the support substrate 280.

[0061] The support substrate 280, which is different from the growth substrate 205, is preferably cheaper and has higher thermal conductivity than the growth substrate, and examples thereof include compound substrates such as Si, Ge, and GaAs, as well as metal substrates using metals or alloys that can suppress the thermal expansion coefficient, such as copper alloys, molybdenum, tungsten, and Fe-Ni-Co alloys, and submount substrates in which metal is attached to a ceramic substrate such as AlN. From the standpoints of processability and cost, it is also preferable to use a Si substrate as the support substrate 280.

[0062] An example of an embodiment of the optical semiconductor element 200 and a manufacturing method thereof will be described in more detail below with reference to FIGS. 3 to 5. First, a growth substrate 205 is prepared. Then, referring to FIG. 3, a semiconductor laminate 220 is formed. At this time, the first n-type contact layer 221 on the growth substrate 205 may be used as an etching stop layer. In FIG. 2, the second n-type contact layer 231 is formed over the entire surface of the second n-type cladding layer 230, and then a portion of the second n-type contact layer 231 is etched away. However, the second n-type contact layer 231 may be left as is without etching. The contact portion after etching the second n-type contact layer 231 is referred to as a second n-type contact portion 232. The semiconductor laminate 220 is similar to the semiconductor laminate 120 described above.

[0063] The power distribution section 260 and the second n-type electrode 295 will be described with reference to FIG. 3 . The power distribution section 260 is formed on the second n-type cladding layer 230. The power distribution section 260 includes a transparent insulating film 261 with through-holes, a second n-type contact portion 232 provided in the through-hole, and an ohmic electrode portion serving as the second n-type electrode 295. Any specific method for forming the power distribution section 260 may be used; however, an example of a specific embodiment for forming the power distribution section 260 will be described below. Note that the figure shows four locations in the power distribution section 260 where the second n-type electrode 295 and the second n-type contact portion 232 are provided, but the number of locations may be one, two, three, five, or more. It is preferable that the locations be arranged in a dispersed island or stripe pattern so that the current between the first n-type electrode 291 and the second n-type electrode 295 is uniformly spread in the in-plane direction while avoiding the area directly below the first n-type electrode 291.

[0064] A resist mask is formed on the second n-type contact layer 231, and a second n-type electrode 295 is formed on the second n-type contact layer 231 in a region where the second n-type contact portion 232 is to be formed using a sputtering method or the like. The resist is removed using a solvent, and the second n-type electrode 295 is lifted off and removed from regions other than the second n-type contact portion 232. Thereafter, a mask is formed on the second n-type cladding layer 230, and the second n-type contact layer 231 is etched and removed from regions other than the second n-type contact portion 232 region where the second n-type electrode 295 is formed. Next, a transparent insulating film 261 is formed on the semiconductor stack 220 (on the second n-type cladding layer 230). A known method such as plasma CVD or sputtering can be used as the film formation method. Thereafter, a resist pattern on power distribution section 260 is formed on transparent insulating film 261 using a mask, and transparent insulating film 261 on second n-type electrode 295 is removed by etching until second n-type electrode 295 is exposed. The thickness of power distribution section 260 is preferably 500 nm or more and 1000 nm or less, and more preferably 600 nm or more and 800 nm or less.

[0065] Known metal materials and formation methods can be used for the second n-type electrode 295. Examples of metal materials that can be used include Ti, Pt, Au, Ag, Al, Ge, and Ni. For example, the second n-type electrode 295 can be formed as a laminate of Au / Ge / Au / Ni / Au, and an ohmic contact can be made by subsequent heat treatment.

[0066] - Formation of a metal reflective layer - As shown in FIG. 3, it is also preferable to form a metal reflective layer 271 on the power distribution unit 260. The metal reflective layer 271 can include multiple metal layers. The metal reflective layer 271 can be made of Au or Al, Pt, Ti, Ag, or the like. For example, the metal reflective layer 271 may be a single layer made of Au alone, or may include two or more Au metal layers. Here, the metal reflective layer 271 preferably contains 50 mass % or more of Au in its composition. To ensure reliable bonding with the metal bonding layer 279 in a subsequent process, it is preferable that the outermost layer of the metal reflective layer 271 (the surface opposite the semiconductor laminate 220) be an Au metal layer. The thickness of the metal reflective layer 271 is preferably 400 nm to 2200 nm, and more preferably 1500 nm to 2000 nm.

[0067] - Bonding to the supporting substrate - The bonding to the support substrate 280 will be described with reference to Fig. 4. The semiconductor stack 220 and the power distribution section 260 are bonded to the support substrate 280 via at least a metal bonding layer 279. By providing a metal reflective layer 271, the metal reflective layer 271 and the metal bonding layer 279 may be bonded to each other. The metal bonding layer 279 and the metal reflective layer 271 can be bonded to each other by arranging them opposite each other and bonding them by heat compression at a temperature of about 250°C to 500°C.

[0068] - Formation of a metal bonding layer - The metal bonding layer 279 can be formed using a metal such as Ti, Pt, or Au, or a metal that forms a eutectic alloy with Au (such as Sn), or solder, and is preferably formed by stacking these. The thickness of the metal bonding layer 279 is preferably 1000 nm or more and 2000 nm or less, and more preferably 1200 nm or more and 1800 nm or less. The outermost layer of the metal bonding layer 279 is made of Au metal, and the outermost layer of the metal reflective layer 271 is also made of Au, so that bonding between Au and Au can be achieved by Au-Au diffusion. The metal reflective layer 271 and the metal bonding layer 279 bonded together are referred to as bonding layer 270 (FIG. 5).

[0069] -Support substrate- The support substrate 280 may be a substrate of a different type from the growth substrate 205, and may be a submount substrate based on the semiconductor substrate, metal substrate, or ceramic substrate described above. Because the above-described bonding method is used, the support substrate 280 may be lattice-mismatched with the semiconductor layers formed in this embodiment. While the support substrate 280 may be insulating depending on the application, a conductive substrate is preferred. From the standpoints of processability and cost, a Si substrate is preferably used for the support substrate 280. By using a Si substrate, the thickness of the support substrate 280 can be significantly reduced compared to conventional substrates, making it suitable for implementation in combination with various semiconductor devices. Furthermore, Si substrates are advantageous in terms of heat dissipation compared to InAs or GaAs substrates.

[0070] -Removal of the growth substrate- The removal of the growth substrate 205 will be described with reference to FIG. 5. After the support substrate 280 is bonded, the growth substrate 205 is removed. When the growth substrate 205 is an InP substrate, the growth substrate 205 can be wet-etched using, for example, diluted hydrochloric acid. Here, the first n-type contact layer 221 may be used as an etching stop layer.

[0071] As shown in FIG. 2 , after removing the growth substrate 205, a first n-type electrode 291 is formed on the upper surface of the semiconductor laminate 220 (the surface opposite the support substrate 280). The first n-type electrode 291 preferably includes an ohmic electrode and a pad electrode on the ohmic electrode (not shown). The ohmic electrode can be formed using a metal such as Au, Ge, Ni, or Ti, a metal that forms a eutectic alloy with Au (e.g., Sn), or solder. The ohmic electrode can be formed by deposition using a common method such as vapor deposition. The thickness of the ohmic electrode is not limited, but can be, for example, 300 nm to 1300 nm. The thickness and metal of the pad electrode can be set as desired depending on the connection method (bump, solder, wire bond, etc.). After deposition of the ohmic electrode, heat treatment for ohmic contact is preferably performed. At this time, the first n-type contact layer 221 may be removed except for the portion connected to the first n-type electrode 291.

[0072] After forming the ohmic electrode, it is preferable to form a pad electrode on the ohmic electrode. The pad electrode can be formed using a metal such as Ti or Au, a metal that forms a eutectic alloy with Au (such as Sn), or solder. The pad electrode can be formed by a common method such as vapor deposition.

[0073] After forming the pad electrode, the upper surface of the semiconductor laminate 220 (for example, the surface of the first n-type cladding layer 222) other than the first n-type electrode 291 and its surrounding area may be roughened. This is because roughening the surface improves light extraction efficiency. The surface of the first n-type cladding layer 222 can be roughened by using a general method such as selective etching using a mask or wet etching. It is preferable that the first n-type electrode 291 and the second n-type electrode 295 are formed spaced apart from each other when viewed from above.

[0074] As shown in FIG. 2, a mesa shape may be formed in the semiconductor laminate 220 by removing a portion of the semiconductor laminate 220 using a dry etching method. The dry etching method is preferably reactive ion etching (RIE), and an inductively coupled plasma (ICP) can be used as the plasma source. Dry etching is performed on a street region having a certain width along the planned chip division lines when viewed from above. The width of the street region (street width) is the width necessary to perform chip division without adversely affecting the active layer, for example, 40 to 100 μm. The street region may be lattice-shaped, and the pad electrode formed above or the second n-type electrode 295 of the power distribution unit 260 is disposed in the area other than the street region when viewed from above. To expose the transparent insulating film 261 of the power distribution unit 260 in the street region, a mask (e.g., an SiO2 mask) is formed on the first n-type cladding layer 222. The mask has an etching rate during dry etching that is smaller than that of the semiconductor laminate 220 and is thick enough to remain until the etching of the street region is completed. Then, dry etching of the street region is performed. This dry etching is performed until the transparent insulating film 261 is exposed outside the mesa shape.

[0075] After the mesa is formed, it is preferable to form a protective film using plasma CVD or the like (not shown). Examples of the protective film used at this time include SiO2 and SiN. The SiO2 mask used in the mesa formation process may be used as part of the protective film. It is also preferable that the protective film does not cover the central portion of the top surface of the first n-type electrode 291. The thickness of the protective film is preferably 50 nm or more and 500 nm or less.

[0076] Furthermore, a back electrode 299 may be formed on the back surface of the support substrate 280 .

[0077] A mesa shape is formed by removing the semiconductor laminate 220 by mesa etching using dry etching or the like along the cutting line (dicing line) to be used for singulation, and then the support body consisting of the exposed power distribution section 260, metal reflective layer 271, metal bonding layer 279, support substrate 280, and back electrode 299 is cut by dicing to singulate into individual elements.

[0078] The above manufacturing method can obtain the optical semiconductor element 200 shown in Fig. 2. These embodiments are merely examples and are not limiting, and the semiconductor laminate 220 in Fig. 3 to Fig. 5 may be formed upside down on the growth substrate 205, with the second n-type cladding layer 230 on the light extraction side at the top in Fig. 2. Furthermore, in mesa etching, the side surfaces of the element may be sloped or vertical.

[0079] (Third embodiment) Next, with reference to FIG. 6 , an optical semiconductor device 300 according to a third embodiment of the present invention will be described, including a preferred configuration. This optical semiconductor device 300 is also a semiconductor light-emitting device with excellent luminous efficiency. The third embodiment is an embodiment in which an active layer and a tunnel junction layer are further formed on the tunnel junction layer of the first embodiment. In principle, components identical to those of the optical semiconductor device 100 are assigned the same reference numerals (the last two digits of the three-digit number) and redundant explanations will be omitted. The semiconductor stack 320 has two of the stack structures described above. The semiconductor stack 320 is located between a first n-type electrode 391 and a second n-type electrode 395.

[0080] Specifically, the optical semiconductor device 300 of FIG. 6 has a semiconductor laminate 320 in which a first n-type contact layer 321, a first n-type cladding layer 322, a first spacer layer 323, a first active layer 324, a first electron blocking layer 325, a second spacer layer 326, a first p-type cladding layer 327, a second electron blocking layer 328, a first tunnel junction layer 329, a second n-type cladding layer 342, a third spacer layer 343, a second active layer 344, a third electron blocking layer 345, a fourth spacer layer 346, a second p-type cladding layer 347, a fourth electron blocking layer 348, a second tunnel junction layer 349, a second n-type cladding layer 330, and a second n-type contact layer 331 are sequentially formed on a growth substrate 305. The first active layer 324, the first electron blocking layer 325, the second spacer layer 326, the first p-type cladding layer 327, the second electron blocking layer 328, and the first tunnel junction layer 329 are collectively referred to as a first stacked structure 350. Similarly, the second active layer 344, the third electron blocking layer 345, the fourth spacer layer 346, the second p-type cladding layer 347, the fourth electron blocking layer 348, and the second tunnel junction layer 349 are collectively referred to as a second stacked structure 351. In the semiconductor stacked body 320, the first n-type contact layer 321, the first n-type cladding layer 322, and the first spacer layer 323 are formed, and then the first stacked structure 350 and the second stacked structure 351 are stacked with the second n-type cladding layer 342 and the third spacer layer 343 interposed therebetween, and a second n-type cladding layer 330 and a second n-type contact layer 331 are further formed thereon. Furthermore, in optical semiconductor element 300, second n-type electrode 395 is formed as an n-type ohmic electrode on the top of semiconductor laminate 320, and first n-type electrode 391 is formed as a back surface electrode on the back surface of growth substrate 305. Furthermore, growth substrate 305 and semiconductor laminate 320 are preferably located between first n-type electrode 391 and second n-type electrode 395. Optical semiconductor element 300 has an emission peak wavelength of 1000 nm or more and 3000 nm or less.

[0081] Here, there is a correspondence between the semiconductor layers constituting the first stacked structure 350 and the semiconductor layers constituting the second stacked structure 351. Specifically, the first active layer 324 corresponds to the second active layer 344, the first electron blocking layer 325 corresponds to the third electron blocking layer 345, the second spacer layer 326 corresponds to the fourth spacer layer 346, the first p-type cladding layer 327 corresponds to the second p-type cladding layer 347, the second electron blocking layer 328 corresponds to the fourth electron blocking layer 348, and the first tunnel junction layer 329 corresponds to the second tunnel junction layer 349.

[0082] 6, the third embodiment may include the second n-type cladding layer 342. The second n-type cladding layer 342 prevents impurities doped in the first n-type tunnel junction layer 3292 from reaching the second active layer 344, and also supplies a sufficient amount of carriers to the second active layer 344, thereby increasing the light emission output. The thickness of the second n-type cladding layer 342 is preferably 50 nm or more and 1000 nm or less. The dopant concentration of the second n-type cladding layer 342 is 1.0×10 17 atoms / cm 3 Over 1.0 x 10 18 atoms / cm 3 The following is preferable: Dopants that can be used here include Si, Te, S, Ge, Sn, Se, and the like.

[0083] 6, the third embodiment may also include the third spacer layer 343. By providing the third spacer layer 343, when the second n-type cladding layer 342 and the second active layer 344 are not lattice-matched or have a difference in impurity concentration, the third spacer layer 343 can also function as a layer for relaxing strain or suppressing impurity diffusion. The thickness of the third spacer layer 343 is preferably 20 nm or more and 300 nm or less. The third spacer layer 343 is preferably an undoped layer.

[0084] (Fourth embodiment) The present invention is also applicable to semiconductor light-receiving elements, which are optical semiconductor elements, and a semiconductor light-receiving element according to a fourth embodiment of the present invention will be described. For example, the active layer 124 in the first embodiment can also be used as a layer that absorbs light and generates carriers for light reception (i.e., a light-absorbing layer) in the form of a light-receiving element. Even if the active layers 224, 334, and 344 in the second and third embodiments are each replaced with light-absorbing layers, a semiconductor light-receiving element with similarly excellent light-receiving sensitivity can be realized. By utilizing the mechanism by which light-emitting efficiency improves in relation to the spread of current from the electrodes in a semiconductor light-emitting element, a semiconductor light-receiving element having a first electron blocking layer and a second electron blocking layer between the active layer (light-absorbing layer) and the tunnel junction layer, a p-type cladding layer between the first electron blocking layer and the second electron blocking layer, and a dopant concentration of the p-type cladding layer of 5.0×10 17 atoms / cm 3 Over 9.5 x 10 17 atoms / cm 3 It is obvious that a thickness of 500 nm or less improves the light receiving efficiency in the semiconductor light receiving element in relation to the collection of the carrier flow (current) generated by light reception into the electrode. [Example]

[0085] Example 1 First, using MOCVD, a Si-doped first n-type InGaAs contact layer 221 (thickness: 20 nm), a Si-doped first n-type InP cladding layer 222 (thickness: 3500 nm), and an undoped InP first spacer layer 223 (thickness: 100 nm) were formed in this order on the (100) surface of a Si-doped n-type InP growth substrate 205 (thickness: 120 μm). Next, an active layer 224 (total thickness: 160 nm) with a multiple quantum well structure was formed, with a designed emission peak wavelength of 1480 nm. The active layer 224 with the multiple quantum well structure was formed by using undoped In 0.419 Ga 0.297 Al 0.284 As barrier layer 224b (thickness: 10 nm) and In 0.765 Ga 0.125 Al 0.110 After stacking 10 layers of As well layers 224w (thickness: 5 nm) alternately,0.419 Ga 0.297 Al 0.284 An As barrier layer 224b (thickness: 10 nm) was formed, making a total of 10.5 pairs including the last barrier layer 224b. On the active layer 224, an undoped InAlAs first electron blocking layer 225 (thickness: 20 nm), an undoped InP second spacer layer 226 (thickness: 300 nm), a Zn-doped p-type InP cladding layer 227 (thickness: 50 nm), a Zn-doped p-type InAlAs second electron blocking layer 228 (thickness: 50 nm), a Zn-doped p-type InGaAlAs intermediate layer (thickness: 20 nm), and a Zn-doped p-type InGaAsP intermediate layer (thickness: 20 nm) were formed, and a tunnel junction layer 229 was formed thereon.

[0086] The tunnel junction layer 229 was fabricated by forming a Si-doped n-type InGaAlAs tunnel junction layer 2292 (thickness: 18 nm) directly on a C-doped p-type InGaAlAs tunnel junction layer 2291 (thickness: 36 nm), thereby achieving a tunnel effect at the interface between them. The pressure during growth of the tunnel junction layer 229 was set to 50 Torr, and the ratio of group V elements to group III elements (V-III ratio) in the source gas used was set to 50. The layers from the active layer 224 to the tunnel junction layer 229 constitute a stacked structure 250.

[0087] A Si-doped n-type InGaAsP intermediate layer (thickness: 16 nm) was formed on the tunnel junction layer 229, and a Si-doped second n-type InP cladding layer 230 (thickness: 1000 nm) was formed thereon in this order to form a semiconductor laminate 220. Next, a Si-doped second n-type contact layer 231 (thickness: 100 nm) was formed on the entire surface of the second n-type InP cladding layer 230.

[0088] Table 1 below lists the composition and thickness of each layer before processing into devices, as well as the type of dopant and the dopant concentration determined by SIMS analysis, including dopant diffusion, after all epitaxial growth was completed and the substrate was removed from the MOCVD reactor. The source gases selected for forming each layer were trimethylindium (TMIn) as the In source, trimethylgallium (TMGa) as the Ga source, trimethylaluminum (TMAl) as the Al source, arsine (AsH3) as the As source, and phosphine (PH3) as the P source. Additionally, diethylzinc (DEZn) was used as the Zn dopant gas, carbon tetrabromide (CBr4) as the C dopant gas, and disilane (Si2H6) as the Si dopant gas.

[0089] The composition of each layer was measured using a BRUKER JV-QC3 XRD instrument. The composition of each layer was calculated by fitting using analytical software (Jordan Valley RADS). The thickness of each layer was calculated from cross-sectional observation of the grown layer using a SEM (scanning electron microscope) or TEM (transmission electron microscope).

[0090] [Table 1]

[0091] The following describes the steps for fabricating a device using a wafer on which epitaxial growth on the growth substrate 205 was completed. The surface of the formed second n-type contact layer 231 was covered with photoresist except for the area where the second n-type contact portion 232 was to be formed. A second n-type electrode 295 was formed using a vapor deposition method with Au (thickness: 10 nm), Ge (thickness: 30 nm), Au (thickness: 60 nm), Ni (thickness: 30 nm), and Au (thickness: 400 nm). The resist pattern, excluding the second n-type electrode 295 on the area where the second n-type contact portion 232 was to be formed, was then removed along with the metal film formed thereon. After contact annealing, a photomask was formed on the second n-type electrode 295. The second n-type contact layer 231 was then removed by wet etching using a tartaric acid-hydrogen peroxide mixture, leaving only the area of ​​the second n-type contact layer intended for the second n-type contact portion 232. A transparent insulating film 261 (thickness: 700 nm) made of SiO2 was formed on the entire surface of the second n-type cladding layer 230 by plasma CVD. The transparent insulating film 261 on the second n-type electrode 295 was removed by etching to form a power distribution section 260 in which the transparent insulating film 261 and the electrode section (the second n-type electrode 295 and the second n-type contact section 232) were arranged in parallel. Next, a metal reflective layer 271 (Al (film thickness: 10 nm / Au (film thickness: 650 nm) / Pt (film thickness: 100 nm) / Au (film thickness: 900 nm))) was formed on the power distribution section 260 by vapor deposition (FIG. 3).

[0092] Thereafter, a metal bonding layer 279 (Ti (film thickness: 650 nm) / Pt (film thickness: 20 nm) / Au (film thickness: 900 nm)) was formed on a support substrate (Si substrate) 280 by vapor deposition. Next, the metal reflective layer 271 and the metal bonding layer 279 were arranged facing each other and bonded by thermal compression bonding at 300°C (FIG. 4). Next, the growth substrate 205 was removed by wet etching using a diluted hydrochloric acid solution to expose the first n-type InGaAs contact layer 221 (FIG. 5).

[0093] A first n-type electrode 291 was formed on the first n-type InGaAs contact layer 221 using a vapor deposition method, with Au (thickness: 10 nm) / Ge (thickness: 30 nm) / Au (thickness: 60 nm) / Ni (thickness: 30 nm) / Au (thickness: 800 nm) / Ti (thickness: 100 nm) / Au (thickness: 1000 nm). A pad electrode (Ti (thickness: 150 nm) / Pt (thickness: 100 nm) / Au (thickness: 2500 nm)) was formed on the top ohmic electrode using a vapor deposition method. A resist-based lift-off method was used to form the electrode pattern. The first n-type InGaAs contact layer 221, excluding the region directly below the top ohmic electrode, was then removed by wet etching using a tartaric acid-hydrogen peroxide mixture.

[0094] Next, a resist mask was formed by photolithography to cover the street area along the planned chip dividing line as well as the upper surface ohmic electrode and pad electrode, and the upper surface of the light extraction surface of the first n-type cladding layer 222 other than the masked area was roughened by wet etching.

[0095] Next, SiO2 was formed over the entire surface by plasma CVD, and then a resist mask pattern was formed and etched to form an SiO2 mask that exposed street regions along the planned chip division lines. The width of the street region exposed by the mask pattern was 55 μm. A mesa was formed by dry etching (ICP-RIE), exposing the outer periphery of the power distribution section 260 in the street region and the side surface of the semiconductor laminate 220 (Figure 2).

[0096] After the mesa was formed, the SiO2 mask present in the center of the upper surface of the first n-type electrode 291 was removed, and then a SiN film (thickness: 190 μm) was formed as a protective film (not shown) on the entire surface (including the upper surface of the remaining SiO2 mask, the exposed side surfaces of the mesa, and the street region) by plasma CVD. Then, the SiN in the center of the upper surface of the first n-type electrode 291 was etched away using a resist mask pattern to expose the center of the upper surface of the first n-type electrode 291, and the resist was then removed. Next, the rear surface of the support substrate 280 was polished or etched to reduce the thickness of the semiconductor light-emitting element 200 to 150 μm. Next, a rear electrode 299 (Ti (thickness: 10 nm) / Pt (thickness: 50 nm) / Au (thickness: 200 nm)) was formed on the rear surface of the support substrate 280 by vapor deposition, and then subjected to RTA heat treatment at 300°C for 60 seconds. Finally, the semiconductor light emitting device 200 according to Example 1 was fabricated by separating the substrate into individual rectangular elements each having a chip size of 1080 μm×1080 μm using laser dicing.

[0097] (Comparative Example 1) In Example 1, the tunnel junction 229 was formed, but in this example, the tunnel junction 229 was not formed, the second electron blocking layer was not formed, and a p-type InP clad layer 227 (thickness: 2200 nm, dopant concentration: 7.0×10 17 atoms / cm 3 and thickness: 200 nm, dopant concentration: 1.50 × 10 18 atoms / cm 3 ), p-type InGaAsP intermediate layer (thickness: 50 nm, dopant concentration: 5.0 × 10 18 atoms / cm 3 ), p-type InGaAs contact layer (thickness: 100 nm, dopant concentration: 1.0 × 10 19 atoms / cm 3An optical semiconductor device of Comparative Example 1 was fabricated in the same manner as in Example 1, except that a second n-type contact layer 231 was formed on the substrate. Table 2 below shows the composition and film thickness of each layer, the type of dopant, and the dopant concentration determined by SIMS analysis, including dopant diffusion, before the device processing step was performed and the substrate was removed from the MOCVD apparatus. In Comparative Example 1, the second n-type contact layer 231 described above was replaced with a p-type contact layer (p-InGaAs), and therefore the second n-type electrode 295 was replaced with a p-type electrode and Ti (thickness: 10 nm) and Au (thickness: 530 nm) were deposited by vapor deposition. The semiconductor light-emitting device 200 of Comparative Example 1 was fabricated in the same manner as in Example 1, except that a second n-type contact layer 231 was formed on the substrate.

[0098] [Table 2]

[0099] Example 2 Optical semiconductor device 200 of Example 2 was fabricated in the same manner as Example 1, except that the thickness of p-type cladding layer 227 was changed as shown in Table 3.

[0100] Example 3 Optical semiconductor device 200 of Example 3 was fabricated in the same manner as Example 1, except that the thickness of p-type cladding layer 227 was changed as shown in Table 3.

[0101] Example 4 Optical semiconductor device 200 of Example 4 was fabricated in the same manner as in Example 1, except that the thickness and dopant concentration of p-type cladding layer 227 were changed as shown in Table 3.

[0102] Example 5 Optical semiconductor device 200 of Example 5 was fabricated in the same manner as in Example 1, except that the thickness of p-type cladding layer 227 was changed to 10 nm as shown in Table 3.

[0103] Example 6 Optical semiconductor device 200 of Example 4 was fabricated in the same manner as in Example 1, except that the thickness of p-type cladding layer 227 was changed to 1 nm as shown in Table 3.

[0104] (Comparative Example 2) Optical semiconductor device 200 of Comparative Example 2 was fabricated in the same manner as in Example 1, except that the thickness and dopant concentration of p-type cladding layer 227 and the thickness of second electron blocking layer 228 were changed as shown in Table 3.

[0105] (Comparative Example 3) Optical semiconductor element 200 of Comparative Example 3 was fabricated in the same manner as in Example 1, except that the thickness and dopant concentration of p-type cladding layer 227 and the thickness of second electron blocking layer 228 were changed as shown in Table 3.

[0106] Comparative Example 4 Optical semiconductor device 200 of Comparative Example 4 was fabricated in the same manner as in Example 1, except that the thickness of p-type cladding layer 227 was changed as shown in Table 3.

[0107] (Comparative Example 5) Optical semiconductor device 200 of Comparative Example 5 was fabricated in the same manner as in Example 1, except that the thickness of p-type cladding layer 227 was changed as shown in Table 3.

[0108] (Comparative Example 6) Optical semiconductor device 200 of Comparative Example 6 was fabricated in the same manner as in Example 1, except that the thickness and dopant concentration of p-type cladding layer 227 were changed as shown in Table 3.

[0109] (Comparative Example 7) Optical semiconductor device 200 of Comparative Example 7 was fabricated in the same manner as in Example 1, except that the thickness and dopant concentration of p-type cladding layer 227 were changed as shown in Table 3.

[0110] (Comparative Example 8) Optical semiconductor device 200 of Comparative Example 8 was fabricated in the same manner as in Example 1, except that the thickness of p-type cladding layer 227 was changed as shown in Table 3.

[0111] A current of 1 A was applied to the optical semiconductor devices obtained in Examples 1 to 4 and Comparative Examples 1 to 8 above using a prober, with the first n-type electrode serving as the negative electrode (-) and the second n-type electrode serving as the positive electrode (+) using a constant-current voltage source. The forward voltage Vf (V) and the on-axis light output Po (mW) received by a light-receiving element placed directly above the semiconductor light-emitting element were measured. The peak emission wavelength λp (nm) was also measured using an optical fiber spectrophotometer. The light output Po (mW), forward voltage Vf (V), luminous efficiency WPE (%), and peak emission wavelength λp (nm) are shown in Table 3 below. The luminous efficiency WPE (%) was calculated using the formula WPE (%) = Po (W) / {Vf (V) × 1 A} × 100.

[0112] [Table 3]

[0113] From the above results, it is found that the thickness of the p-type cladding layer 227 is 500 nm or less and the dopant concentration is 5.0×10 17 It can be seen that better luminous efficiency WPE can be obtained when the dopant concentration of the p-type cladding layer 228 is equal to or greater than 9.5×10 atoms / cm3 and equal to or less than 9.5×10 atoms / cm3. Furthermore, from Examples 1 to 3, Examples 5 and 6, and Comparative Examples 4, 5, and 8, when the dopant concentration of the p-type cladding layer 228 is the same (i.e., 7.0×10 atoms / cm3), the WPE is better when the thickness of the p-type cladding layer 228 is thinner than in Comparative Examples 4, 5, and 8, as shown in FIG. 7. Furthermore, from Examples 2 and 4, when the thickness of the p-type cladding layer 228 is the same, the WPE is better when the thickness is 5.0×10 17 atoms / cm 3 Over 9.5 x 10 17 atoms / cm 3 Within the range below, the higher the dopant concentration of the p-type cladding layer 228, the better the WPE. Furthermore, the semiconductor light-emitting devices of Examples 1 to 4 not only had better luminous efficiency than the comparative example, but also had good forward voltage. Since the p-type cladding layer 227 does not allow current to spread laterally, the conventional 18 atoms / cm 3It has been thought that a dopant concentration of about 9.5×10 is preferable, but in the case of the present invention having a tunnel junction layer, the dopant concentration is 9.5×10 17 atoms / cm 3 The luminous efficiency tended to be higher when the value was below 0.1. [Industrial Applicability]

[0114] According to the present invention, it is possible to provide an optical semiconductor element having excellent light-emitting efficiency or light-receiving sensitivity, and a method for manufacturing an optical semiconductor element. [Explanation of symbols]

[0115] 100, 200, 300 Optical semiconductor element 105, 205, 305 growth substrate 120, 220, 320 Semiconductor laminate 121, 221, 321 First n-type contact layer 122, 222, 322 First n-type cladding layer 123, 223, 323 First spacer layer 124, 224 active layer 124b, 224b Barrier layers of the active layers 124, 224 124w, 224w Active layer 124, 224 well layer 125, 225 First electron blocking layer 126, 226 Second spacer layer 127, 227 p-type cladding layer 128, 228 Second electron blocking layer 129, 229 Tunnel junction layer 1291, 2291 p-type tunnel junction layer 1292, 2292 n-type tunnel junction layer 130, 230 Second n-type cladding layer 131, 231 Second n-type contact layer 232 Second n-type contact 150, 250 laminated structure 191, 291, 391 1st n-type electrode 195, 295, 395 2nd n-type electrode 260 Power Distribution Department 261 Transparent insulating film 271 Metal reflective layer 279 Metal bonding layer 280 Support substrate 299 Back electrode 324 1st active layer 324b Barrier layer of the first active layer 324w Well layer of the first active layer 325 First electron blocking layer 326 Second spacer layer 327 1st p-type cladding layer 328 Second electron blocking layer 329 First tunnel junction layer 3291 1st p-type tunnel junction layer 3292 First n-type tunnel junction layer 342 Second n-type cladding layer 343 Third spacer layer 344 2nd active layer 344b Barrier layer of second active layer 344w Second active layer well layer 345 Third electron blocking layer 346 4th spacer layer 347 Second p-type cladding layer 348 4th electron blocking layer 349 Second tunnel junction layer 3491 Second p-type tunnel junction layer 3492 Second n-type tunnel junction layer 350 1st laminated structure 351 2nd laminated structure

Claims

1. a semiconductor laminate having at least one laminate structure including an active layer and a tunnel junction layer, a p-type cladding layer between the active layer and the tunnel junction layer, a first electron blocking layer between the active layer and the p-type cladding layer, and a second electron blocking layer between the p-type cladding layer and the tunnel junction layer; the tunnel junction layer includes a p-type InGaAlAsP layer on the second electron blocking layer side and an n-type InGaAlAsP layer on the opposite side to the second electron blocking layer, the peak wavelength of the active layer is 1000 nm or more and 3000 nm or less, The dopant concentration of the p-type cladding layer is 5.0×10 １７ atoms / cm ３ 9.5 x 10 １７ atoms / cm ３ and the thickness is 500 nm or less; Optical semiconductor element.

2. 2. The optical semiconductor device according to claim 1, wherein the second electron blocking layer has a thickness of 30 nm to 70 nm.

3. 2. The optical semiconductor device according to claim 1, wherein the first electron blocking layer is undoped, and the second electron blocking layer is p-type doped.

4. The optical semiconductor device according to claim 1 , wherein the semiconductor laminate is located between a first n-type electrode and a second n-type electrode.

5. The optical semiconductor element according to claim 1 , wherein the semiconductor laminate has the laminate structure between a first n-type cladding layer and a second n-type cladding layer.

6. The optical semiconductor device according to claim 1 , further comprising an undoped spacer layer between the first electron blocking layer and the p-type cladding layer.

7. On the board, forming a semiconductor laminate having at least one laminate structure including an active layer and a tunnel junction layer, a p-type cladding layer between the active layer and the tunnel junction layer, a first electron blocking layer between the active layer and the p-type cladding layer, and a second electron blocking layer between the p-type cladding layer and the tunnel junction layer; the tunnel junction layer includes a p-type InGaAlAsP layer on the second electron blocking layer side and an n-type InGaAlAsP layer on the opposite side to the second electron blocking layer, the peak wavelength of the active layer is 1000 nm or more and 3000 nm or less, The dopant concentration of the p-type cladding layer is 5.0×10 １７ atoms / cm ３ 9.5 x 10 １７ atoms / cm ３ and the thickness is 500 nm or less; A method for manufacturing an optical semiconductor element.

8. 8. The method for manufacturing an optical semiconductor element according to claim 7, further comprising the step of forming a first n-type electrode and a second n-type electrode such that the semiconductor laminate is located between the first n-type electrode and the second n-type electrode.

9. 8. The method for manufacturing an optical semiconductor element according to claim 7, wherein the step of forming the semiconductor laminate further comprises the steps of: forming a first n-type cladding layer before forming an active layer of the laminate structure; and forming a second n-type cladding layer after forming a tunnel junction layer of the laminate structure.

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