Baseline restoration technique for photon-counting computed tomography using active fiducials

Abstract

One embodiment is a circuit configuration for implementing a baseline restoration ("BLR") circuit for a photon counting computed tomography ("PCCT") signal chain, the circuit configuration comprising: a multi-level discriminator circuit for receiving a shaper voltage from the PCCT signal chain, the discriminator circuit outputting a digital signal indicative of one of a range of voltages within which the shaper voltage falls; a digital-to-analog converter ("DAC") connected to receive the digital signal output from the discriminator circuit, the DAC converting the received digital signal to a corresponding active reference voltage; and a feedback circuit for injecting a cancellation current at an input of the PCCT signal chain that is proportional to the difference between the shaper voltage and the active reference voltage.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Patent Application No. 63 / 187,329, filed May 11, 2021, entitled "BASELINE RESTORATION TECHNIQUE FOR PHOTON COUNTING COMPUTED TOMOGRAPHY USING ACTIVE REFERENCE," and U.S. Patent Application No. 17 / 725,242, filed April 20, 2022, entitled "BASELINE RESTORATION TECHNIQUE FOR PHOTON COUNTING COMPUTED TOMOGRAPHY USING ACTIVE REFERENCE," which are incorporated herein by reference in their entireties.

[0002] The present disclosure relates generally to the field of photon-counting computed tomography (PCCT), and more particularly to baseline reconstruction (BLR) techniques for PCCT using active fiducials. Summary of the Invention [Means for solving the problem]

[0003] 1. A circuit configuration for implementing a baseline restoration ("BLR") circuit for a photon counting computed tomography ("PCCT") signal chain, the circuit configuration comprising: a multi-level discriminator circuit for receiving a shaper voltage from the PCCT signal chain, the discriminator circuit outputting a digital signal indicative of one of a range of voltages within which the shaper voltage falls; a digital-to-analog converter ("DAC") connected to receive the digital signal output from the discriminator circuit, the DAC converting the received digital signal into a corresponding active reference voltage; a feedback circuit that injects a cancellation current at a particular node of the PCCT signal chain that is proportional to the difference between the shaper voltage and the active reference voltage.

[0004] For a more complete understanding of the present disclosure and its features and advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts and in which: [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a schematic block diagram of a typical PCCT signal chain including a linear BLR circuit, in accordance with certain embodiments. [Figure 2A] 2 is a graph showing the waveform of the BLR of the PCCT of FIG. 1 during low X-ray flux. [Figure 2B] 2 is a graph showing the waveform of the BLR of the PCCT of FIG. 1 during low X-ray flux. [Figure 3A] 2 is a graph showing the waveform of the BLR of the PCCT of FIG. 1 during high X-ray flux. [Figure 3B] 2 is a graph showing the waveform of the BLR of the PCCT of FIG. 1 during high X-ray flux. [Figure 4] The count curves of the PCCT signal chain in Figure 1 are shown with BLR enabled. [Figure 5] A comparison of the count curves and BLR of the PCCT signal chain in Figure 1 is shown for 0 nA leakage and 50 nA leakage. [Figure 6] The results of an experiment showing the undershoot effect of the BLR of the PCCT of FIG. 1 are shown. [Figure 7] FIG. 1 is a schematic block diagram illustrating a system for implementing an active reference in a BLR circuit, according to embodiments described herein. [Figure 8]8 is a chart illustrating exemplary active reference signals output from a digital-to-analog circuit (DAC) with specified shaper voltage (Vsh) ranges, each corresponding to the digital output of an exemplary five-level discriminator, in connection with the exemplary system shown in FIG. [Figure 9] 1 shows graphs of waveforms associated with a conventional BLR circuit in which a static reference is deployed. [Figure 10] 10 shows graphs of waveforms associated with a BLR circuit according to embodiments described herein in which a dynamic reference is deployed. [Figure 11] FIG. 1 is a block diagram of a computer system that may be used to implement all or a portion of a PCCT scanning system in accordance with features of certain embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0006] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between" when used in reference to a measurement range is inclusive of both ends of the measurement range. As used herein, the designation "A / B / C" means (A), (B), and / or (C).

[0007] This description uses the phrases "in an embodiment" or "in an embodiment," each of which may refer to one or more of the same or different embodiments. Furthermore, when used with respect to embodiments of the present disclosure, terms such as "comprising," "including," and "having" are synonymous. This disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side," and such descriptions are used for ease of discussion and are not intended to limit the application of the disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of ordinal adjectives such as "first," "second," and "third" to describe a common object merely indicates that various instances of the same object are being referenced and is not intended to imply that the objects so described must be in a given order, whether temporally, spatially, sequentially, or in any other manner.

[0008] In the following detailed description, references are made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0009] The following disclosure describes various exemplary embodiments and examples for implementing the features and functionality of the present disclosure. While specific components, arrangements, and / or features are described below in connection with various exemplary embodiments, these are merely examples used to simplify the disclosure and are not intended to be limiting. Of course, it will be understood that in the development of any actual embodiment, numerous implementation-specific decisions must be made to achieve the developer's particular goals, which may vary from implementation to implementation, including compliance with system, business, and / or legal constraints. Moreover, it will be understood that such a development effort may be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

[0010] Reference may be made herein to spatial relationships between various components and the spatial orientation of various aspects of components, as depicted in the accompanying drawings. However, as will be recognized by those skilled in the art after fully reading this disclosure, devices, components, members, apparatuses, etc. described herein may be positioned in any desired orientation. Accordingly, the use of terms such as "above," "below," "upper," "lower," "top," "bottom," or other similar terms describing spatial relationships between various components or describing the spatial orientation of aspects of such components should be understood to describe the relative relationships between the components or the spatial orientation of aspects of such components, respectively, as the components described herein may be oriented in any desired direction. When used to describe a range of dimensions or other characteristics (e.g., time, pressure, temperature, length, width, etc.) of elements, operations, and / or conditions, the phrase "between X and Y" represents a range that includes X and Y.

[0011] Furthermore, the present disclosure may repeat reference numerals and / or characters in the various examples. This repetition is for the purposes of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations being discussed. Example embodiments that can be used to implement the features and functionality of the present disclosure will now be described with more particular reference to the accompanying drawings.

[0012] In a conventional computed tomography (CT) scanning system, x-rays generated by an x-ray source pass through the object of interest and are converted by a scintillator into visible light that is captured by a detector implemented as a photodiode array. The photodiode array converts the light into an analog electrical signal, which is then converted to a digital signal using an analog-to-digital (A / D) converter. The digital signal output from the A / D converter is used to generate a grayscale image known as a CT scan.

[0013] Photon-counting CT (PCCT) imaging is a relatively new technology that may offer significant advantages and improvements over the existing CT imaging techniques described above. Photon-counting CT systems employ photon-counting detectors (PCDs), which include semiconductor layers to implement an array of detector pixels that register individual photon interactions with the PCD. By tracking the deposited energy of each interaction, the PCD's detector pixels record an approximate energy spectrum and light intensity, making photon-counting CT a spectral or energy-resolved CT technique. In contrast, traditional CT scanners use energy-integrating detectors (EIDs), which register the total energy from one or more photons as well as the electronic noise deposited in the pixel during a fixed period. Thus, EIDs record only light intensity, similar to black-and-white photography. In contrast, PCDs record both light intensity and spectral information, similar to color photography.

[0014] Photon-counting CT imaging replaces the three-step process described above with a more streamlined direct conversion of x-rays to electrical charge via a semiconductor layer comprising a photoconductive dielectric (PCD). Specifically, the semiconductor material used to implement the PCD efficiently converts each x-ray photon into a burst of electrical charge proportional to the x-ray's energy. Benefits of this technology include improved signal-to-noise, reduced x-ray dose to the patient due to higher contrast that can be achieved with the same x-ray dose, improved spatial resolution, and the ability to distinguish between multiple contrast agents and multiple types of materials / tissues through the use of several "energy bins."

[0015] When a photon interacts with a PCD, the height of the resulting electrical pulse is roughly proportional to the photon's energy. By comparing each pulse generated within a pixel with a suitable low-energy threshold, contributions from low-energy events (arising from both photon interactions and electronic noise) can be filtered out. As a result, PCDs have higher signal-to-noise and contrast-to-noise ratios compared to EIDs, allowing for improved image quality at the same x-ray exposure level or reduced patient x-ray dose for the same image quality.

[0016] The introduction of more energy thresholds above the low energy threshold allows for the division of PCD into several distinct energy bins. Each registered photon is assigned to a specific bin according to its energy, such that each pixel measures a histogram of the incident X-ray spectrum. This spectral information allows for the qualitative determination of the material composition of each pixel in the reconstructed CT image, as opposed to the estimated average linear attenuation coefficient obtained in conventional CT scans. In addition, the use of three or more energy bins allows for the differentiation between dense bone and calcification, relative to the heavier elements typically used as contrast agents, reducing the need for a reference scan prior to contrast injection, thereby further reducing the X-ray dose received by the patient.

[0017] 1 is a schematic block diagram illustrating a system 100 for implementing a typical PCCT signal chain according to embodiments described herein. A forward signal path 102 from a sensor 104 includes a charge-sensing amplifier (CSA) 106 and a pulse shaper (PS) 108, followed by a discriminator 110 and a counter 112. X-rays incident on the sensor 104 inject current pulses (or charge packets) into the forward signal path 102. The forward signal path 102 converts these current pulses into voltage pulses at the input of the discriminator 110. The discriminator 110 then quantizes the current pulses according to their energy, which is counted by the counter 112. The sensor 104 also contains a significant component of slowly varying leakage current. If left uncompensated, this leakage current passes through the forward signal chain and causes an offset at the input of the discriminator 110, distorting the measured spectrum. To counter this effect, a baseline restorer (BLR) 114 is introduced. The BLR 114 creates a slow negative feedback loop around the CSA 106 and PS 108 that adjusts the long-term value of the PS output to some desired voltage. It does this by injecting a slowly varying current at the CSA 106 input. The BLR circuit 114 includes a linear voltage gain stage 116 that is referenced to a desired baseline voltage Vbl. The voltage gain stage 116 is followed by a low-pass filter 118 and finally a transconductor 120. When implemented with a linear circuit, the BLR 114 adjusts the average shaper output voltage (shaper_out). When the flux rate is low, i.e., when the input current due to the x-ray flux is small compared to the leakage current, this is equivalent to adjusting the baseline voltage of the shaper 108 output.

[0018] Figures 2A and 2B show waveforms of a simple PCCT signal chain under low x-ray flux. In Figure 2A, waveforms 200, 202, and 204 correspond to the input current to the CSA (Iin), the stimulation current (Istim), and the BLR cancellation current (Iblr), respectively. Waveform 206 is the corresponding output voltage of the shaper (vshaper). Similarly, in Figure 2B, waveforms 208, 210, and 212 correspond to Iin, Istm, and Iblr, respectively, and waveform 214 is the corresponding vshaper. The plots in Figures 2A and 2B show a family of stimulators with different values ​​of leakage current, ranging from 35 nA to 5 nA. The BLR circuit regulates the average voltage of the shaper output voltage (vshaper) to 200 mV in all cases. All of the shaper voltage curves are indistinguishable by eye, and the baseline voltage settles to 200 mV as desired.

[0019] The problem, commonly referred to as "undershoot," occurs when the signal current due to the x-ray flux is significant relative to the leakage current. Specifically, undershoot occurs when the average of the signal current is high enough that its cancellation by the BLR circuit causes a significant negative shift in the baseline. BLR undershoot occurs because there is a net negative charge arriving at the input of the BLR circuit in the form of charge packets. To maintain a constant average shaper voltage (as in a linear BLR), the BLR circuit must apply a steady positive current that exactly opposes the average signal current. During gaps between events, this positive current causes BLR undershoot.

[0020] Figures 3A and 3B show waveforms 300-314, representing the flux rates of the corresponding waveforms 200-214 shown in Figures 2A and 2B, respectively. As shown in Figures 3A and 3B, the BLR circuit successfully cancels the leakage current, as evidenced by the shaper output voltage (vshaper) curves being on top of each other. However, due to the fact that the average stimulation current (Istim) includes a significant contribution from the signal current, the baseline of the shaper output voltage is less than 200 mV. The BLR circuit has no way to distinguish the leakage current from the signal current, so it cancels both. The resulting measured spectrum contains a shift to lower energy because each charge pulse (if distinguishable from the others) begins from a lower baseline.

[0021] The effect of undershoot can be observed in Figure 4, which shows, for each of the five counter bins of a typical frame of PCCT data, the actually generated events per bin (i.e., the "ground truth") in lines 400, 402, 404, 406, and 408, and the corresponding counter output in lines 410, 412, 414, 416, and 418. An increase in counts of approximately 1-2 megacounts per second (Mcps) relative to the ground truth can be observed in bins 0 and 1 (compare line 400 with line 410, and line 402 with line 412), serving as evidence that undershoot causes higher energy events to be falsely counted in lower energy bins.

[0022] Waveforms 500, 502, 504, 506, and 508 shown in Figure 5 demonstrate the effectiveness of the BLR in canceling leakage current. As shown in Figure 5, the difference between the counting results at 50 nA leakage current and 0 nA leakage current is negligible, and the undershoot effect is essentially the same in both cases.

[0023] Waveforms 600, 602, 604, 606, 608, and 610 shown in Figure 6 show the results of another experiment demonstrating the BLR undershoot effect. In particular, waveforms 600-610 shown in Figure 6 are the results of a series of simulations performed on the superposition of 10 Mcps, 50 kiloelectron volt (keV) periodic tones with realistic spectra at various flux rates. The output spectra were captured using a threshold sweep. The spectral flux was kept low so that the tones were clearly visible in the output spectrum. At a 1 nA flux, there is no observable difference in the spectrum whether the BLR is on (waveform 600) or off (waveform 602). At a 10 nA flux, there is a shift to lower energy in the observed tones when the BLR is on, as evidenced by the position of the peak in waveform 608. With the BLR off, the tones remain unchanged. When leakage current is applied, the tone shifts dramatically higher with the BLR off (waveform 610), while remaining at the same energy level with the BLR on (waveform 608). The results are summarized in Table 1 below. [Table 1]

[0024] Although undershoot is undesirable, the benefits of using a BLR to cancel leakage current far outweigh the cost. The undershoot effect is a deterministic response to flux changes. There is an opportunity to correct this in post-processing. The leakage current can change over many frames, even if the flux remains constant. Furthermore, the leakage current can vary from pixel to pixel or with sensor aging or temperature. Therefore, canceling the leakage current is far more important than avoiding the undershoot effect. Therefore, using a BLR loop is desirable, and the BLR loop must have sufficient loop gain to cancel most of the leakage current.

[0025] What is needed is a method to suppress the response of a BLR circuit during a signal event without affecting either the forward signal path or accurate control of the baseline voltage during periods of low signal activity. In conventional methods, the pulse shaper voltage is compared to a reference voltage set to the desired baseline voltage. A feedback loop forces the shaper voltage to equal the reference voltage when no signal current is present. However, during a signal event, the feedback loop integrates the positive signal, creating a negative offset on the shaper voltage.

[0026] According to a feature of the embodiments described herein, the discriminator output is used as a digital signal to drive a digital-to-analog converter (DAC) with a specific transfer function that models the detected pulse shape. The DAC outputs a voltage equal to the highest discriminator threshold that was exceeded. The resulting DAC output is a tightly quantized continuous-time waveform that roughly tracks the pulse shaper voltage. This allows the BLR circuit to focus on canceling leakage current as intended, without having to cancel signal charge.

[0027] 7 is a schematic block diagram illustrating a system 700 for implementing an active reference in a BLR circuit, according to embodiments described herein. Similar to system 100 (FIG. 1), in system 700, a forward signal path 702 from a sensor 704 includes a charge-sensing amplifier (CSA) 706 and a pulse shaper (PS) 708, followed by a discriminator 710 and a counter 712. X-rays incident on the sensor 704 inject current pulses (or charge packets) into the forward signal path 702. The forward signal path 702 converts these current pulses into voltage pulses at the input of the discriminator 710. The discriminator 710 then quantizes the current pulses according to their energy, which is counted by the counter 712. For reasons detailed above, system 700 includes a BLR 714, which (also described above) creates a slow negative feedback loop around CSA 706 and PS 708 that regulates the long-term value of the PS output to some desired voltage. This is done by injecting a slowly varying current at the CSA 706 input. The BLR circuit 714 includes a linear voltage gain stage 716 followed by a low-pass filter 718 and a transconductor 720. According to a feature of embodiments described herein, instead of being referenced to a static baseline voltage Vbl, the voltage gain stage 716 is referenced to a dynamic / active reference output from a digital-to-analog converter (DAC) 722, whose input is tied to the output of the discriminator 710. As described above, the DAC 722 implements a transfer function that models the detected pulse shape. In particular, the DAC 722 outputs a voltage equal to the highest discriminator threshold that was exceeded.

[0028] It will be appreciated that the feedback from the BLR circuitry may be applied to the input of the PCCT signal chain as shown, or may be applied to an intermediate node such as the output of the CSA 106.

[0029] It will be appreciated that the BLR 714 can be modified to function as a delta modulator by replacing the linear gain stage 716 with a comparator. In this configuration, the low pass filter 718 functions as an integrator in the delta modulator.

[0030] 8 is a chart 800 illustrating exemplary active reference signals output from the DAC 710 for specified shaper voltage (Vsh) ranges, each corresponding to the digital output of an exemplary five-level discriminator. For example, referring to line 802, when Vsh is less than a first threshold voltage Vth0, the discriminator output is 00000, and the active reference signal input from the DAC to the gain stage is equal to the desired baseline voltage Vbl. Referring to line 804, when Vsh is equal to or greater than Vth0 and less than a second threshold voltage Vth1, the discriminator output is 00001, and the active reference signal output from the DAC to the gain stage is Vth0. Referring to line 806, when Vsh is equal to or greater than Vth1 and less than a third reference voltage Vth2, the discriminator output is 00011, and the active reference signal input from the DAC to the gain stage is Vth1. Referring to line 808, when Vsh is greater than or equal to Vth2 and less than a fourth reference voltage Vth3, the discriminator output is 00111, and the active reference signal input from the DAC to the gain stage is Vth2. Referring to line 810, when Vsh is greater than or equal to Vth3 and less than a fifth threshold voltage Vth4, the discriminator output is 01111, and the active reference signal input from the DAC to the gain stage is Vth3. Finally, referring to line 812, when Vsh is greater than or equal to Vth4, the discriminator output is 11111, and the active reference signal input from the DAC to the gain stage is Vth4.

[0031] As mentioned above, the example depicted in Figure 8 is for a five-level discriminator. However, the techniques described herein can be extended to more or fewer levels as desired without departing from the spirit or scope of the teachings. Vth[0:4] is the discriminator level to which the shaper voltage Vsh is compared on the forward signal path. Vbl is the desired baseline voltage. The DAC outputs one of Vbl, Vth[0:4] depending on the instantaneous discriminator digital output.

[0032] The resulting DAC output is a tightly quantized continuous-time waveform that roughly tracks the pulse shaper voltage, which frees the BLR circuit from having to cancel signal charge and allows it to focus on canceling leakage current as intended.

[0033] Figures 9 and 10 show waveforms related to a conventional BLR circuit with a static reference deployed (as shown in FIG. 1) and a BLR circuit according to an embodiment described herein with a dynamic reference deployed (as shown in FIG. 7). Specifically, in FIG. 9, waveform 900 depicts a static reference signal and waveform 902 depicts a shaper voltage signal. In FIG. 10, waveform 1000 depicts a dynamic reference signal generated according to an embodiment described herein and waveform 1002 depicts a shaper voltage signal. A balanced BLR circuit ensures that the integral of the difference between the shaper voltage (Vsh) and the reference voltage (Vref) is zero. In graphical terms, this means that the area under the curve defined by Vsh - Vref has as much negative area (Vsh < Vref, corresponding to area 904) as positive area (Vsh > Vref, corresponding to area 906). In FIG. 9, a large positive peak of Vsh accumulates a large positive area. To balance this with an equal negative area, Vsh must be shifted negatively with respect to Vref. In FIG. 10, the dynamic reference reduces the positive area accumulated by Vsh - Vref. As a result, Vsh does not need to shift as much to balance the positive area (including area 1004) and negative area (including area 1006) of Vsh - Vref. Thus, as shown in FIGS. 9 and 10, compared to the conventional method (FIG. 9) with a static reference, the BLR circuit of the embodiment described herein with a dynamic reference voltage integrates far fewer signal events, thereby reducing baseline undershoot.

[0034] 11 is a block diagram illustrating an exemplary system 1100 that may be configured to implement at least a portion of the techniques according to embodiments described herein, and more particularly, as shown in the figures described above. As shown in FIG. 11, the system 1100 may include at least one processor 1102, e.g., a hardware processor 1102, coupled to a memory device 1104 through a system bus 1106. Thus, the system may store program code and / or data in the memory device 1104. The processor 1102 may also execute program code accessed from the memory device 1104 via the system bus 1106. In one aspect, the system may be implemented as a computer suitable for storing and / or executing program code. However, it should be understood that the system 1100 may be implemented in the form of any system including a processor and memory capable of performing the functions described in this disclosure.

[0035] In some embodiments, the processor 1102 may execute software or algorithms to perform activities as discussed herein, particularly activities related to the embodiments described herein. The processor 1102 may include any combination of hardware, software, or firmware providing programmable logic, including, by way of non-limiting example, a microprocessor, a DSP, a field programmable gate array (FPGA), a programmable logic array (PLA), an integrated circuit (IC), an application specific IC (ASIC), or a virtual machine processor. The processor 1102 may be communicatively coupled to the memory device 1104, for example, in a direct memory access (DMA) configuration, such that the processor 1102 can read from or write to the memory device 1104.

[0036] In general, memory device 1104 may include any suitable volatile or non-volatile memory technology, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash, read-only memory (ROM), optical media, virtual memory area, magnetic or tape memory, or any other suitable technology. Unless otherwise specified, any of the memory devices discussed herein should be construed as encompassed by the broad term “memory.” Information measured, processed, tracked, or transmitted to or from any of the components of system 1100 may be provided in any database, register, control list, cache, or storage structure, all of which may be referenced in any suitable time frame. Any such storage options may be included in the broad term “memory” as used herein. Similarly, any of the potential processing elements, modules, and machines described herein should be construed as encompassed by the broad term “processor.” Each of the elements shown in the figures herein may include suitable interfaces for receiving, sending, and / or otherwise communicating data or information in a network environment so that they can communicate, for example, with systems having similar or identical hardware as other ones of the elements.

[0037] In certain exemplary implementations, mechanisms for implementing the embodiments outlined herein may be implemented by logic encoded in one or more tangible media, which may include embedded logic provided in non-transitory media, such as ASICs, DSP instructions, software executed by a processor (potentially including object code and source code), or other similar machines. In some of these examples, a memory element, such as memory element 1104 shown in FIG. 11, can store data or information used in the operations described herein. This includes memory elements that can store software, logic, code, or processor instructions that are executed to perform the activities described herein. A processor can execute any type of instruction associated with data or information to achieve the operations detailed herein. In one example, a processor, such as processor 1102 shown in FIG. 11, can transform an element or article (e.g., data) from one state or thing to another. In another example, the activities outlined herein may be implemented in fixed logic or programmable logic (e.g., software / computer instructions executed by a processor), and the elements identified herein may be any type of programmable processor, programmable digital logic (e.g., FPGA, DSP, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), or ASIC, including digital logic, software, code, electronic instructions, or any suitable combination thereof.

[0038] The memory element 1104 may include one or more physical memory devices, such as, for example, a local memory 1108 and one or more bulk storage devices 1110. Local memory may refer to RAM or other non-persistent memory devices typically used during the actual execution of program code. A bulk storage device may be implemented as a hard drive or other persistent data storage device. The processing system 1100 may also include one or more cache memories (not shown) that provide temporary storage of at least some program code to reduce the number of times the program code must be retrieved from the bulk storage device 1110 during execution.

[0039] 11 , memory element 1104 may store energy bin event counting module 1120. In various embodiments, module 1120 may be stored in local memory 1108, in one or more bulk storage devices 1110, or remotely from local memory and bulk storage devices. It should be understood that system 1100 may further execute an operating system (not shown in FIG. 11 ) that may facilitate execution of module 1120. Module 1120, implemented in the form of executable program code and / or data, may be read, written, and / or executed by system 1100, for example, by processor 1102. In response to reading from, writing to, and / or executing module 1120, system 1100 may be configured to perform one or more operations or method steps described herein.

[0040] Input / output (I / O) devices, depicted as input device(s) 1112 and output device(s) 1114, may optionally be coupled to the system. Examples of input devices include, but are not limited to, a keyboard, a pointing device such as a mouse, etc. Examples of output devices include, but are not limited to, a monitor or display, a speaker, etc. In some implementations, the system may include a device driver (not shown) for the output device(s) 1114. The input and / or output devices 1112, 1114 may be coupled to the system 1100 directly or through an intervening I / O controller. Additionally, sensors 1115 may be coupled to the system 1100 directly or through an intervening controller and / or driver.

[0041] In one embodiment, the input and output devices may be implemented as a combined input / output device (shown in FIG. 11 by the dashed line surrounding input device 1112 and output device 1114). One example of such a combination device is a touch-sensitive display, sometimes referred to as a "touchscreen display" or simply a "touchscreen." In such an embodiment, input to the device may be provided by the movement of a physical object, such as a stylus or a user's finger, on or near the touchscreen display.

[0042] A network adapter 1116 may also optionally be coupled to system 1100 to enable coupling to other systems, computer systems, remote network devices, and / or remote storage devices through intervening private or public networks. The network adapter may comprise a data receiver for receiving data transmitted to system 1100 by such systems, devices, and / or networks, and a data transmitter for transmitting data from system 1100 to such systems, devices, and / or networks. Modems, cable modems, and Ethernet cards are examples of different types of network adapters that may be used with system 1100.

[0043] Example 1 provides a circuit configuration for implementing a baseline restoration ("BLR") circuit for a photon-counting computed tomography ("PCCT") signal chain, the circuit configuration including: a multi-level discriminator circuit for receiving a shaper voltage from the PCCT signal chain, the discriminator circuit outputting a digital signal indicative of one of a range of voltages within which the shaper voltage falls; a digital-to-analog converter ("DAC") connected to receive the digital signal output from the discriminator circuit, the DAC converting the received digital signal to a corresponding active reference voltage; and a feedback circuit for injecting a cancellation current at a particular node of the PCCT signal chain that is proportional to the difference between the shaper voltage and the active reference voltage.

[0044] Example 2 provides the circuit configuration described in Example 1, in which the difference between the shaper voltage and the active reference voltage is calculated by a linear amplifier.

[0045] Example 3 provides the circuit configuration of Example 2, in which the signal output from the linear amplifier is applied to the input of a low-pass filter.

[0046] Example 4 provides the circuit configuration of Example 3, further comprising: a transconductor connected to receive the filtered voltage signal output from the low-pass filter, convert the filtered voltage signal into a current signal, and feed back the current signal to an input of the PCCT signal chain.

[0047] A fifth embodiment provides the circuit configuration according to any one of the second to fourth embodiments, in which the low-pass filter functions as an integrator.

[0048] A sixth embodiment provides the circuit configuration according to any one of the first to fifth embodiments, in which the BLR circuit is a delta modulator.

[0049] A seventh embodiment provides the circuit configuration according to any one of the first to sixth embodiments, wherein the difference between the shaper voltage and the active reference voltage is calculated by a comparator.

[0050] Example 8 provides the circuit configuration of Example 7, in which the output of the comparator is applied to the input of a low-pass filter.

[0051] A ninth embodiment provides the circuit configuration according to any one of the sixth to eighth embodiments, wherein the BLR circuit is clocked.

[0052] Example 10 provides the circuit configuration described in Example 9, in which chopper stabilization is applied to null the offset of the comparator.

[0053] Example 11 provides the circuit configuration of any one of Examples 1 to 10, wherein the cancellation current is injected at the input of the PCCT signal chain.

[0054] Example 12 provides a method for implementing baseline restoration ("BLR") in connection with a photocounting computed tomography ("PCCT") signal chain, the method including receiving a shaper voltage from the PCCT signal chain, generating a digital signal indicative of one of a range of voltages within which the shaper voltage falls, converting the received digital signal to a corresponding active reference voltage, and injecting a cancellation current at the input of the PCCT signal chain that is proportional to the difference between the shaper voltage and the active reference voltage.

[0055] Example 13 provides the method according to example 12, wherein the difference between the shaper voltage and the active reference voltage is calculated by a linear amplifier.

[0056] Example 14 provides the method of example 12 or 13, further comprising applying the signal output from the linear amplifier to an input of a low-pass filter.

[0057] Example 15 provides the method of any one of Examples 12 to 14, further including: filtering the comparator voltage; converting the filtered comparator voltage into a current signal; and feeding back the current signal to an input of the PCCT signal chain.

[0058] Example 16 provides the method of example 15, where the filtering, converting, and feeding effectively functions as a delta modulator.

[0059] Example 17 provides the method according to any one of Examples 14 to 16, wherein the low-pass filter functions as an integrator.

[0060] Example 18 provides the method according to any one of Examples 12 to 17, wherein the difference between the shaper voltage and the active reference voltage is calculated by a comparator.

[0061] Example 19 provides the method according to example 18, wherein the signal output from the comparator is applied to the input of a low-pass filter.

[0062] Example 20 provides the method of any one of Examples 16-19, further comprising clocking a circuit for implementing the BLR.

[0063] Example 21 provides the method of any one of Examples 12 to 20, further comprising applying chopper stabilization to null the offset of the input comparator.

[0064] Example 22 provides the method of any one of examples 12-21, wherein the cancellation current is injected at the input of the PCCT signal chain.

[0065] Example 23 provides an apparatus for performing baseline restoration ("BLR") for a photon-counting computed tomography ("PCCT") signal chain, comprising: a first circuit configuration for receiving a shaper voltage from the PCCT signal chain and outputting a digital signal indicative of a detected level of the shaper voltage; a second circuit configuration for converting the digital signal output from the first circuit configuration to an active reference voltage; and a third circuit configuration for injecting a cancellation current at the input of the PCCT signal chain that is proportional to the difference between the shaper voltage and the active reference voltage, wherein the third circuit configuration comprises at least one of a linear amplifier and a comparator for outputting the difference between the shaper voltage and the active reference voltage.

[0066] Example 24 provides the apparatus of example 23, wherein the signal output from the linear amplifier is applied to the input of a low pass filter.

[0067] Example 25 is the apparatus described in Example 24, further comprising a transconductor connected to receive the filtered voltage signal output from the low pass filter, convert the filtered voltage signal into a current signal, and feed back the current signal to the input of the PCCT signal chain.

[0068] Example 26 provides the apparatus of example 24 or 25, wherein the low pass filter functions as an integrator.

[0069] Example 27 provides the apparatus of any one of Examples 23 to 26, wherein the BLR is implemented using a delta modulator.

[0070] It should be noted that all specifications, dimensions, and relationships (e.g., numbers of elements, operations, steps, etc.) outlined herein are provided for illustrative and instructional purposes only. Such information may vary widely without departing from the spirit of the disclosure or the scope of the appended claims. The specifications apply to one non-limiting example only, and therefore, they should be construed as such. In the foregoing description, exemplary embodiments have been described with reference to particular component arrangements. Various modifications and changes can be made to such embodiments without departing from the scope of the appended claims. Accordingly, the description and drawings should be regarded in an illustrative sense, and not a restrictive sense.

[0071] It should be noted that in many of the examples provided herein, interactions may be described in terms of two, three, four, or more electrical components. However, this is done for purposes of clarity and illustrative purposes only. It should be recognized that systems may be integrated in any suitable manner. According to similar design alternatives, any of the illustrated components, modules, and elements of the figures may be combined into a variety of possible configurations, all of which are clearly within the broad scope of this specification. In certain cases, it may be easier to describe one or more of the functionality of a given sequence of flows by referring to only a limited number of electrical elements. It should be understood that the illustrated electrical circuits and their teachings can be readily extended to accommodate more components and more complex / sophisticated arrangements and configurations. Thus, the examples provided should not limit the scope or inhibit the broad teachings of the electrical circuits as they may be applied to countless other architectures.

[0072] It should also be noted that, in this specification, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in "an embodiment," "an example embodiment," "one embodiment," "another embodiment," "some embodiments," "various embodiments," "other embodiments," "alternative embodiments," etc. are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may, or may not necessarily, be combined in the same embodiment.

[0073] It should also be noted that the functions associated with the circuit architecture represent only some of the possible circuit architecture functions that may be performed by or within the system depicted in the figures. Some of these operations may be omitted or removed as desired, or these operations may be significantly modified or changed without departing from the scope of the present disclosure. Furthermore, the timing of these operations may be significantly changed. The foregoing operational flow is provided for purposes of illustration and discussion. Substantial flexibility is provided by the embodiments described herein in that any suitable arrangement, timeline, configuration, and timing mechanism may be provided without departing from the teachings of the present disclosure.

[0074] Numerous other changes, substitutions, variations, alterations, and modifications may be ascertainable by those skilled in the art, and the present disclosure is intended to encompass all such changes, substitutions, variations, alterations, and modifications as fall within the scope of the appended claims.

[0075] It should be noted that all optional features of the devices and systems described above may be implemented in connection with any method or process described herein, and the example details may be used anywhere in one or more embodiments.

[0076] The "means for" in these (above) examples includes, but is not limited to, the use of any suitable components discussed herein in conjunction with any suitable software, circuitry, hubs, computer code, logic, algorithms, hardware, controllers, interfaces, links, buses, communication paths, etc.

[0077] It should be noted that with the examples provided above, as well as many other examples provided herein, interactions can be described with respect to two, three, or four network elements. However, this is done for purposes of clarity and example only. In certain cases, it may be easier to describe one or more of the functionality of a given set of flows by referring to only a limited number of network elements. It should be understood that the topologies shown in and described with reference to the accompanying figures (and their teachings) are readily expandable and can accommodate many components and more complex / sophisticated arrangements and configurations. Thus, the examples provided should not limit the scope or inhibit the broad teachings of the topologies shown as they may be applied to countless other architectures.

[0078] It is also important to note that the steps of the foregoing flow diagrams illustrate only some of the possible signaling scenarios and patterns that may be performed by or within the communications system shown in the figures. Some of these steps may be deleted or eliminated, as desired, or these steps may be significantly modified or altered without departing from the scope of this disclosure. In addition, many of these operations are described as being performed simultaneously or in parallel with one or more additional operations. However, the timing of these operations may be significantly altered. The foregoing operational flows are provided for purposes of illustration and discussion. Substantial flexibility is provided by the communications system shown in the figures, in that any suitable arrangement, timeline, configuration, and timing mechanism may be provided without departing from the teachings of this disclosure.

[0079] While the present disclosure has been described in detail with reference to particular arrangements and configurations, these example configurations and arrangements may be varied considerably without departing from the scope of the present disclosure. For example, while the present disclosure has been described with reference to particular communication exchanges, the embodiments described herein may be applicable to other architectures.

[0080] Numerous other changes, substitutions, variations, alterations, and modifications may be ascertainable by those skilled in the art, and the present disclosure is intended to encompass all such changes, substitutions, variations, alterations, and modifications as fall within the scope of the appended claims. In order to aid the United States Patent and Trademark Office (USPTO) and, additionally, the reader of any patent issued on this application, in interpreting the claims appended hereto, Applicant hereby expressly disclaims: (a) that any of the appended claims, as existing on the filing date hereof, are intended to invoke 35 U.S.C. § 142, paragraph 6, unless the terms "means for" or "step for" are specifically used in a particular claim; and (b) that no reference herein intends to limit the present disclosure in any manner not otherwise reflected in the appended claims. [Explanation of symbols]

[0081] 100 systems 102 forward signal path 104 Sensors 106 Charge Sensitive Amplifier (CSA) 108 Pulse Shaper (PS) 110 Discriminator 112 counters 114 Baseline Restorer (BLR) 116 Linear Voltage Gain Stage 118 Low-pass filter 120 Transconductor

Claims

1. 1. A circuit configuration for implementing baseline restoration (BLR) for a photon-counting computed tomography (PCCT) signal chain, the circuit configuration comprising: a multi-level discriminator circuit configured to receive a shaper voltage from the PCCT signal chain, the multi-level discriminator circuit outputting a digital signal indicative of one of a range of voltages within which the shaper voltage falls; a digital-to-analog converter (DAC) connected to receive the digital signal output from the multi-level discriminator circuit, the DAC configured to convert the received digital signal into a corresponding active reference voltage; a feedback circuit configured to inject a cancellation current at a particular node of the PCCT signal chain that is proportional to a difference between the shaper voltage and the active reference voltage.

2. 2. The circuit configuration of claim 1, wherein the difference between the shaper voltage and the active reference voltage is calculated by a linear amplifier.

3. 3. The circuit arrangement of claim 2, wherein the signal output from the linear amplifier is applied to the input of a low pass filter.

4. 4. The circuit configuration of claim 3, further comprising a transconductor connected to receive the filtered voltage signal output from the low pass filter, convert the filtered voltage signal to a current signal, and feed back the current signal to an input of the PCCT signal chain.

5. 2. The circuitry of claim 1, wherein the circuitry forms a BLR circuit that is a delta modulator.

6. The circuit configuration of claim 5 , wherein the BLR circuit is clocked.

7. 2. The circuit arrangement of claim 1, wherein the difference between the shaper voltage and the active reference voltage is calculated by a comparator, the output of which is applied to an input of a low pass filter.

8. 8. The circuit arrangement of claim 7, wherein chopper stabilization is applied to null the offset of the comparator.

9. 1. A method for implementing baseline restoration (BLR) for a photon-counting computed tomography (PCCT) signal chain, the method comprising: receiving a shaper voltage from the PCCT signal chain; generating a digital signal indicative of one of a range of voltages within which the shaper voltage falls; converting said digital signal to a corresponding active reference voltage; injecting a cancellation current at the input of the PCCT signal chain proportional to the difference between the shaper voltage and the active reference voltage.

10. 10. The method of claim 9, wherein the difference between the shaper voltage and the active reference voltage is calculated by a linear amplifier.

11. 10. The method of claim 9, further comprising applying the signal output from the linear amplifier to an input of a low pass filter, the low pass filter acting as an integrator.

12. filtering the comparator voltage; converting the filtered comparator voltage into a current signal; 10. The method of claim 9, further comprising: feeding back the current signal to an input of the PCCT signal chain.

13. The method of claim 12 , wherein the filtering, the conversion, and the feedback effectively function as a delta modulator.

14. 10. The method of claim 9, wherein the difference between the shaper voltage and the active reference voltage is calculated by a comparator.

15. 10. The method of claim 9, further comprising clocking a circuit for implementing the BLR.

16. 10. The method of claim 9, further comprising applying chopper stabilization to null the offset of the input comparator.

17. 1. An apparatus for baseline restoration (BLR) for a photon-counting computed tomography (PCCT) signal chain, the apparatus comprising: a first circuit configuration configured to receive a shaper voltage from the PCCT signal chain and further configured to output a digital signal indicative of a detected level of the shaper voltage; a second circuitry configured to convert the digital signal output from the first circuitry to an active reference voltage; and a third circuit configuration configured to inject a cancellation current at an input of the PCCT signal chain that is proportional to a difference between the shaper voltage and the active reference voltage, the third circuit configuration comprising at least one of a linear amplifier and a comparator configured to output the difference between the shaper voltage and the active reference voltage.

18. 18. The apparatus of claim 17, wherein the signal output from the linear amplifier is applied to the input of a low pass filter.

19. 20. The apparatus of claim 17, further comprising a transconductor connected to receive the filtered voltage signal output from the low pass filter, convert the filtered voltage signal to a current signal, and feed back the current signal to the input of the PCCT signal chain.

20. 18. The apparatus of claim 17, wherein the output of the comparator is applied to the input of a low pass filter and chopper stabilization is applied to null the offset of the comparator.

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