Three-dimensional memory devices and methods for forming same - Patent Application 20070122997

Abstract

In a particular embodiment, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure is formed including interleaved first and second dielectric layers. A channel structure is formed extending through the first and second dielectric layers in a first region of the stack structure. All of the second dielectric layers in the first region of the stack structure and a portion of the second dielectric layer in the second region are replaced with a conductive layer. Word line pickup structures are formed at different depths extending through remaining portions of the first and second dielectric layers in a second region of the stack structure, whereby the word line pickup structures are electrically connected to the conductive layers in the second region of the stack structure, respectively.

Description

[Technical Field]

[0001] The present disclosure relates to three-dimensional (3D) memory devices and methods for fabricating the same. [Background technology]

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as memory cell feature sizes approach lower limits, planar processes and fabrication techniques become difficult and costly. As a result, memory densities for planar memory cells approach upper limits.

[0003] 3D memory architectures can address the density limitations of planar memory cells and include a memory array and peripheral devices for controlling signals to and from the memory array. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent Application Serial No. 16 / 881,168 [Patent Document 2] U.S. Patent Application No. 16 / 881,339 Summary of the Invention [Means for solving the problem]

[0005] In one embodiment, a method for forming a 3D memory device is disclosed. A stack structure including interleaved first and second dielectric layers is formed. A channel structure extending through the first and second dielectric layers in a first region of the stack structure is formed. All of the second dielectric layers in the first region of the stack structure and a portion of the second dielectric layer in the second region are replaced with a conductive layer. Word line pickup structures are formed at different depths and extend through remaining portions of the first and second dielectric layers in a second region of the stack structure, thereby electrically connecting the word line pickup structures to the conductive layers in the second region of the stack structure, respectively.

[0006] In some implementations, a dummy channel structure extending through the first dielectric layer and the second dielectric layer in the second region of the stack structure is formed in the same process that forms the channel structure.

[0007] In some implementations, for the purpose of replacement, a slit extending through the first and second dielectric layers and across the first and second regions of the stack structure is formed prior to forming the word line pickup structure.

[0008] In some implementations, to perform the replacement, the slits in the second region of the stack structure are covered, and in the first region of the stack structure, all of the second dielectric layer in the first region of the stack structure is removed through the slits, the slits in the second region of the stack structure are opened, a portion of the second dielectric layer in the second region of the stack structure is removed through the slits in the second region of the stack structure, and a conductive layer is deposited through the slits in the first and second regions of the stack structure.

[0009] In some implementations, to perform the replacement, the slits in a first region of the stack structure are covered, and in a second region of the stack structure, a portion of the second dielectric layer in the second region of the stack structure is removed through the slits and the slits in the first region of the stack structure are opened, the slits in the second region of the stack structure are covered, all of the second dielectric layer in the first region of the stack structure is removed through the slits in the first region of the stack structure, the slits in the second region of the stack structure are opened, and a conductive layer is deposited through the slits in the first and second regions of the stack structure.

[0010] In some implementations, a first spacer is formed in the slit before forming the word line pickup structure.

[0011] In some implementations, to form wordline pickup structures, wordline pickup openings extending through the remaining portions of the first dielectric layer and the second dielectric layer in the second region of the stack structure are formed at different depths to expose the remaining portions of the second dielectric layer in the second region of the stack structure, portions of the remaining portions of the second dielectric layer in the second region of the stack structure are respectively replaced with interconnect lines through the wordline pickup openings, and the interconnect lines respectively contact the conductive layers in the second region of the stack structure, and vertical contacts in the wordline pickup openings are respectively formed in contact with the interconnect lines.

[0012] In some implementations, to form the word line pickup structure, second spacers are formed on the sidewalls and bottom of each of the word line pickup openings, the second spacers on the bottom of the word line pickup openings are removed to expose respective portions of the remaining portions of the second dielectric layer, and fillers are formed in the word line pickup openings after forming the respective vertical contacts.

[0013] In some implementations, to replace portions of the second dielectric layer with interconnect lines, exposed portions of the remaining portion of the second dielectric layer are etched through the word line pickup openings to expose respective conductive layers in the second region of the stack structure, and respective interconnect lines are deposited through the word line pickup openings to contact the exposed respective conductive layers in the second region of the stack structure.

[0014] In some implementations, a high-k gate dielectric layer is deposited to replace all of the second dielectric layer and portions of the second dielectric layer with a conductive layer, whereby the conductive layers are each surrounded by the high-k gate dielectric layer. In some implementations, to replace portions of the second dielectric layer with interconnect lines, exposed portions of the remaining portions of the second dielectric layer are etched to expose the respective high-k gate dielectric layer, the exposed high-k gate dielectric layer is etched to expose the respective conductive layer, and respective interconnect lines are deposited to contact the exposed respective conductive layer.

[0015] In another aspect, a 3D memory device includes a first stack structure including alternating conductive layers and a first dielectric layer, a second stack structure including alternating second dielectric layers and the first dielectric layer, a dummy channel structure extending through the first stack structure, and word line pickup structures extending into the second stack structure at different depths, each of the word line pickup structures including a vertical contact and an interconnect line in contact with the vertical contact and a respective one of the conductive layers in the first stack structure.

[0016] In some implementations, a dummy channel structure extending through the first dielectric layer and the second dielectric layer in the second region of the stack structure is formed in the same process that forms the channel structure.

[0017] In some implementations, to form a wordline pickup structure, wordline pickup openings extending through the first dielectric layer and the second dielectric layer in the second region of the stack structure are formed at different depths to expose the second dielectric layer in the second region of the stack structure, portions of the second dielectric layer in the second region of the stack structure are respectively replaced with interconnect lines through the wordline pickup openings, and vertical contacts in the wordline pickup openings are respectively formed in contact with the interconnect lines.

[0018] In some implementations, to form the word line pickup structure, second spacers are formed on the sidewalls and bottom of each of the word line pickup openings, the second spacers on the bottom of the word line pickup openings are removed to expose respective portions of the second dielectric layer, and fillers are formed in the word line pickup openings after forming the respective vertical contacts.

[0019] In some implementations, exposed portions of the remaining portion of the second dielectric layer are etched through the word line pickup openings to replace portions of the second dielectric layer with interconnect lines, and respective interconnect lines are deposited through the word line pickup openings.

[0020] In some implementations, a slit extending through the first and second dielectric layers and across the first and second regions of the stack structure is formed after forming the word line pickup structure to replace all of the second dielectric layer and portions of the second dielectric layer with a conductive layer.

[0021] In some implementations, to replace all of the second dielectric layers and portions of the second dielectric layers with a conductive layer, the slits in the second region of the stack structure are covered; in the first region of the stack structure, all of the second dielectric layers in the first region of the stack structure are removed through the slits, the slits in the second region of the stack structure are opened, portions of the second dielectric layers in the second region of the stack structure are removed through the slits in the second region of the stack structure to expose the interconnect lines of the word line pickup structures; and a conductive layer is deposited through the slits in the first region and the second region of the stack structure to respectively contact the interconnect lines of the word line pickup structures in the second region of the stack structure.

[0022] In some implementations, to replace all of the second dielectric layer and portions of the second dielectric layer with a conductive layer, the slits in the first region of the stack structure are covered, and in the second region of the stack structure, portions of the second dielectric layer in the second region of the stack structure are removed through the slits to expose the interconnect lines of the word line pickup structure, the slits in the first region of the stack structure are opened, the slits in the second region of the stack structure are covered, all of the second dielectric layer in the first region of the stack structure is removed through the slits in the first region of the stack structure, the slits in the second region of the stack structure are opened, and a conductive layer is deposited through the slits in the first region and the second region of the stack structure to respectively contact the interconnect lines of the word line pickup structure in the second region of the stack structure.

[0023] In some implementations, a first spacer is formed in the slit before forming the word line pickup structure.

[0024] In some implementations, a high-k gate dielectric layer, a memory layer, and a channel layer are formed sequentially to form a channel structure.

[0025] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure and to enable those skilled in the art to make and use the disclosure. [Brief explanation of the drawings]

[0026] [Figure 1] 1 is a plan view of a 3D memory device having word line pickup structures according to some embodiments of the present disclosure. [Figure 2] 1 is a top perspective view of a 3D memory device having word line pickup structures according to some embodiments of the present disclosure. FIG. [Figure 3] FIG. 1 is an enlarged top perspective view of a 3D memory device having word line pickup structures according to some embodiments of the present disclosure. [Figure 4] 1 is a cross-sectional side view of a 3D memory device having word line pickup structures according to some embodiments of the present disclosure. [Figure 5] 1 is a cross-sectional side view of a 3D memory device having word line pickup structures according to some embodiments of the present disclosure. [Figure 6A] 1 is an enlarged cross-sectional side view of a 3D memory device having word line pickup structures according to some embodiments of the present disclosure. [Figure 6B] FIG. 10 is an enlarged cross-sectional side view of another 3D memory device having word line pickup structures in accordance with some aspects of the present disclosure. [Figure 7A] 1A-1C illustrate a fabrication process for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 7B] 1A-1C illustrate a fabrication process for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 7C]1A-1C illustrate a fabrication process for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 7D] 1A-1C illustrate a fabrication process for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 7E] 1A-1C illustrate a fabrication process for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 7F] 1A-1C illustrate a fabrication process for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 7G] 1A-1C illustrate a fabrication process for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 7H] 1A-1C illustrate a fabrication process for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 7I] 1A-1C illustrate a fabrication process for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 7J] 1A-1C illustrate a fabrication process for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 7K] 1A-1C illustrate a fabrication process for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 7L] 1A-1C illustrate a fabrication process for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 7M] 1A-1C illustrate a fabrication process for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 7N] 1A-1C illustrate a fabrication process for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 7O] 1A-1C illustrate a fabrication process for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 7P] 1A-1C illustrate a fabrication process for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 8A] 10A-10C illustrate a fabrication process for forming another 3D memory device having word line pickup structures in accordance with some aspects of the present disclosure. [Figure 8B] 10A-10C illustrate a fabrication process for forming another 3D memory device having word line pickup structures in accordance with some aspects of the present disclosure. [Figure 8C] 10A-10C illustrate a fabrication process for forming another 3D memory device having word line pickup structures in accordance with some aspects of the present disclosure. [Figure 9] 1 is a flowchart of a method for forming a 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 10A] 1 is a flowchart of a method for gate replacement according to some aspects of the present disclosure. [Figure 10B] 10 is a flowchart of a method for another gate replacement according to some aspects of the present disclosure. [Figure 11A] 10A-10C illustrate a fabrication process for forming yet another 3D memory device having word line pickup structures in accordance with some aspects of the present disclosure. [Figure 11B] 10A-10C illustrate a fabrication process for forming yet another 3D memory device having word line pickup structures in accordance with some aspects of the present disclosure. [Figure 11C] 10A-10C illustrate a fabrication process for forming yet another 3D memory device having word line pickup structures in accordance with some aspects of the present disclosure. [Figure 11D] 10A-10C illustrate a fabrication process for forming yet another 3D memory device having word line pickup structures in accordance with some aspects of the present disclosure. [Figure 11E] 10A-10C illustrate a fabrication process for forming yet another 3D memory device having word line pickup structures in accordance with some aspects of the present disclosure. [Figure 11F] 10A-10C illustrate a fabrication process for forming yet another 3D memory device having word line pickup structures in accordance with some aspects of the present disclosure. [Figure 11G] 10A-10C illustrate a fabrication process for forming yet another 3D memory device having word line pickup structures in accordance with some aspects of the present disclosure. [Figure 11H] 10A-10C illustrate a fabrication process for forming yet another 3D memory device having word line pickup structures in accordance with some aspects of the present disclosure. [Figure 11I] 10A-10C illustrate a fabrication process for forming yet another 3D memory device having word line pickup structures in accordance with some aspects of the present disclosure. [Figure 11J] 10A-10C illustrate a fabrication process for forming yet another 3D memory device having word line pickup structures in accordance with some aspects of the present disclosure. [Figure 11K] 10A-10C illustrate a fabrication process for forming yet another 3D memory device having word line pickup structures in accordance with some aspects of the present disclosure. [Figure 11L] 10A-10C illustrate a fabrication process for forming yet another 3D memory device having word line pickup structures in accordance with some aspects of the present disclosure. [Figure 12]10 is a flowchart of a method for forming another 3D memory device having word line pick-up structures according to some aspects of the present disclosure. [Figure 13] 1 is a block diagram of an exemplary system having a 3D memory device in accordance with some aspects of the present disclosure. [Figure 14A] 1 is a diagram of an exemplary memory card having a 3D memory device according to some aspects of the present disclosure. [Figure 14B] 1 is a diagram of an exemplary solid-state drive (SSD) having a 3D memory device according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0027] The present disclosure will be described with reference to the accompanying drawings.

[0028] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Accordingly, other configurations and arrangements can be used without departing from the scope of the present disclosure. The present disclosure can also be used in a variety of other applications. The functional and structural features as described in the present disclosure can be combined, adjusted, and modified with each other and in manners not specifically shown in the drawings, whereby these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0029] Generally, terminology can be understood, at least in part, from contextual usage. For example, the term "one or more," as used herein, can be used in a singular sense to describe any feature, structure, or characteristic, or in a plural sense to describe a combination of features, structures, or characteristics, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" can be understood to convey singular usage or plural usage, again, depending, at least in part, on the context. Additionally, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but instead may allow for the existence of additional factors not necessarily explicitly recited, again, depending, at least in part, on the context.

[0030] It should be readily understood that the meanings of "on," "above," and "over" in this disclosure should be interpreted in the broadest manner, such that "on" not only means "directly on" something, but can also include meaning "on" something with intermediate features or layers between them, and that "above" or "over" can not only mean "above" or "over" something, but can also include meaning it is "above" or "over" something (i.e., directly on) with no intermediate features or layers between them.

[0031] Additionally, spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0032] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself can be patterned. Materials added onto the substrate can be patterned or left unpatterned. Moreover, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0033] As used herein, the term "layer" refers to a portion of material that includes a region having a predetermined thickness. A layer can extend throughout an underlying or overlying structure, or can have an extension that is less than the extension of the underlying or overlying structure. Furthermore, a layer can be a homogeneous or heterogeneous region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be positioned between any pair of horizontal planes between (or at) the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer and can include one or more layers therein and / or have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (with interconnect lines and / or vertical contacts formed therein) and one or more dielectric layers.

[0034] In some 3D memory devices (e.g., 3D NAND memory devices), memory cells for storing data are vertically stacked through stack structures (e.g., memory stacks) in vertical channel structures. 3D memory devices typically include a staircase structure formed on one or more sides (edges) of (or at the center of) the stacked storage structures for purposes such as word line pickup / fan-out using word line contacts mounted on different steps / levels of the staircase structure. Dummy channel structures are typically formed through the memory stacks in regions outside the core array region in which the channel structures of the 3D NAND memory device are formed (e.g., the staircase region with the staircase structure) to provide mechanical support for the stack structure, particularly during a gate replacement process that temporarily removes some layers of the stack structure through slit openings across the core array region and staircase region of the stack structure.

[0035] The integration of various structures (e.g., dummy channel structures, word line contacts, staircase structures, slit openings, etc.) becomes increasingly challenging from both a device design perspective and a fabrication process perspective as the memory cell density of 3D NAND memory devices continues to increase.

[0036] To address one or more of the above-mentioned problems, the present disclosure introduces a solution for achieving word line pick-up / fan-out functionality without using staircase structures and word line contacts. The present disclosure can use a relatively simple single process for fabricating word line pick-up structures to replace the relatively complex multiple processes for fabricating staircase structures and word line contacts. That is, the two structures (staircase structures and word line contacts) and their separate processes can be integrated into a single word line pick structure in one process, thereby reducing manufacturing costs and simplifying the process. Moreover, by replacing the staircase structures and word line contacts with word line pick structures, the scope of the gate replacement process can be reduced, and at least some of the dummy channel structures can be eliminated as well, further reducing costs and simplifying the process.

[0037] 1 illustrates a plan view of a 3D memory device 100 having word line pickup structures 106 according to some embodiments of the present disclosure. In some implementations, the 3D memory device 100 is a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings. It is noted that x- and y-axes are included in FIG. 1 to illustrate two orthogonal (perpendicular) directions in the wafer plane. The x-direction is the word line direction of the 3D memory device 100, and the y-direction is the bit line direction of the 3D memory device 100.

[0038] 1, the 3D memory device 100 may include one or more blocks 102 arranged in the y-direction (bit line direction) separated by parallel slit structures 108 (e.g., gate line slits (GLS)). In some implementations in which the 3D memory device 100 is a NAND flash memory device, each block 102 is the smallest erasable unit of the NAND flash memory device. Each block 102 may further include multiple fingers 104 in the y-direction separated by some of the slit structures 108 having "H" cuts 109.

[0039] As shown in FIG. 1 , the 3D memory device 100 can be divided into at least a core array region 101 and a word line pickup region 103, where the core array region 101 has an array of channel structures 110 formed therein and the word line pickup region 103 has word line pickup structures 106 formed therein. The core array region 101 and the word line pickup region 103 are arranged in the x-direction (word line direction) according to some implementations. While one core array region 101 and one word line pickup region 103 are illustrated in FIG. 1 , it is understood that multiple core array regions 101 and / or multiple word line pickup regions 103 can be included in the 3D memory device 100, for example, one word line pickup region 103 can be included between two core array regions 101 in the x-direction in other examples. It is also understood that FIG. 1 merely illustrates the portion of the core array region 101 adjacent to the word line pickup region 103.

[0040] As described in more detail below, the wordline pickup region 103 can include conductive portions 105 and dielectric portions 107 arranged in the y-direction. As shown in FIG. 1 , the wordline pickup structures 106 are disposed in the dielectric portions 107, while dummy channel structures 112, according to some implementations, are disposed in the conductive portions 105 of the wordline pickup region 103 to provide mechanical support and / or load balancing. In some implementations (e.g., as shown in FIG. 1 ), the dummy channel structures 112 are also disposed in the dielectric portions 107 of the wordline pickup region 103, e.g., disposed between the wordline pickup structures 106 in the x-direction. In some implementations, the dummy channel structures 112 are not disposed in the dielectric portions 107 of the wordline pickup region 103, i.e., are disposed only in the conductive portions 105 of the wordline pickup region 103. 1, each finger 104 of the 3D memory device 100 may include a row of word line pickup structures 106 disposed in a dielectric portion 107 of the word line pickup region 103. It is understood that the layout and arrangement of the word line pickup structures 106, as well as the shape of each word line pickup structure 106, may vary in different examples.

[0041] FIG. 2 illustrates a top perspective view of a 3D memory device 100 having word line pickup structures 106 according to some embodiments of the present disclosure. FIG. 3 illustrates an enlarged top perspective view of a 3D memory device 100 having word line pickup structures 106 according to some embodiments of the present disclosure. As shown in FIGS. 2 and 3 , the stack structure 201 can be formed on a substrate 203, which can include silicon (e.g., monocrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some implementations, the substrate 203 includes monocrystalline silicon (which is part of the wafer on which the 3D memory device 100 is fabricated), either at its native thickness or thinned. In some implementations, the substrate 203 includes, for example, polysilicon, which is a semiconductor layer that replaces part of the wafer on which the 3D memory device 100 is fabricated. It is noted that x-, y-, and z-axes are included in FIGS. 2 and 3 to further illustrate the spatial relationships of components in the 3D memory device 100. The substrate 203 of the 3D memory device 100 includes two lateral surfaces extending laterally in the x-y plane: a top surface at the front side of the wafer on which the stack structure 201 may be formed, and a bottom surface at the back side opposite the front side of the wafer. The z-axis is perpendicular to both the x- and y-axes. As used herein, whether one component (e.g., a layer or device) is "on," "above," or "below" another component (e.g., a layer or device) of the 3D memory device 100 is determined in the z-direction (a vertical direction that is perpendicular to the x-y plane) with respect to the substrate 203 of the 3D memory device 100 when the substrate 203 is positioned within the lowest plane of the 3D memory device 100 in the z-direction. The same concepts for describing spatial relationships apply throughout this disclosure.

[0042] 3 , the stack structure 201 can include vertically interleaved first and second material layers 302 and 304, where the second material layer 304 is different from the first material layer 302. The first and second material layers 302 and 304 can alternate vertically (z-direction). In some implementations, the stack structure 201 can include multiple material layer pairs stacked vertically in the z-direction, where each of the multiple material layer pairs includes a first material layer 302 and a second material layer 304. The number of material layer pairs in the stack structure 201 can determine the number of memory cells in the 3D memory device 100.

[0043] In some implementations, the 3D memory device 100 is a NAND flash memory device, and the stack structure 201 is a stacked storage structure through which a NAND memory string is formed. As shown in FIG. 3 , the second material layer 304 can have different materials in different regions / portions of the 3D memory device 100. Thus, for ease of explanation in this disclosure, the stack structure 201 can be viewed as having multiple stack structures with different materials for the second material layer 304. In some implementations, the conductive portions 105 of the core array region 101 and the word line pickup region 103 include conductive stack structures with interleaved conductive layers and first dielectric layers. That is, the second material layer 304 of the stack structure 201 can be a conductive layer in the conductive portions 105 of the core array region 101 and the word line pickup region 103. In some implementations, the dielectric portions 107 of the word line pickup region 103 include a dielectric stack structure with interleaved second and first dielectric layers. That is, the second material layer 304 of the stack structure 201 can be a second dielectric layer in the dielectric portion 107 of the word line pick-up region 103. The first material layer 302 of the stack structure can be the same (first dielectric layer) in the conductive stack structure and the dielectric stack structure across the core array region 101 and the word line pick-up region 103. As described in detail below with respect to the fabrication process, forming the stack structure 201 with different materials for the second material layer 304 in different regions / portions can be achieved by controlling different degrees and extents of the gate replacement process in different regions / portions.For example, stack structure 201 may have undergone a complete gate replacement process in core array region 101, replacing all of the second dielectric layers with conductive layers, but a partial gate replacement process in word line pickup region 103, replacing some of the second dielectric layers with conductive layers in conductive portion 105 and leaving the remaining portions of the second dielectric layers in dielectric portion 107.

[0044] In some implementations, each conductive layer in the conductive stack structure in the core array region 101 and the conductive portion 105 of the wordline pickup region 103 functions as a gate line for a NAND memory string (in the form of a channel structure 110) in the core array region 101, and also functions as a word line, which extends laterally from the gate line and terminates in the conductive portion 105 of the wordline pickup region 103 for wordline pick-up / fan-out through the wordline pickup structure 106. The word lines (i.e., conductive layers) at different depths / levels of the conductive stack structure extend laterally in the conductive portion 105 of the core array region 101 and the wordline pick-up region 103, respectively, but according to some implementations, are discontinuous (e.g., replaced by a second dielectric layer) in the dielectric portion 107 of the wordline pick-up region 103.

[0045] The conductive layer may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof. The dielectric layer may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The first and second dielectric layers may have different dielectric materials (e.g., silicon oxide and silicon nitride). In some implementations, the conductive layer includes a metal such as tungsten, the first dielectric layer includes silicon oxide, and the second dielectric layer includes silicon nitride. For example, the first material layer 302 of the stack structure 201 may include silicon oxide over the core array region 101 and the word line pickup region 103, and the second material layer 304 of the stack structure 201 may include tungsten in the conductive portion 105 of the core array region 101 and the word line pickup region 103, and silicon nitride in the dielectric portion 107 of the word line pickup region 103.

[0046] 2 and 3 , according to some implementations, the height of the stack structures 201 (e.g., the conductive stack structures and the dielectric stack structures) is uniform in the core array region 101 and the word line pick-up region 103. Unlike some 3D memory devices that include one or more staircase structures in the staircase region (corresponding to the word line pick-up region 103 for word line pick-up / fan-out), which have uniform height of the stack structures in the staircase region, the 3D memory device 100 can eliminate the staircase structures while still achieving word line pick-up / fan-out functionality using the word line pick-up structures 106, as described in detail below.

[0047] 4 illustrates a cross-sectional side view of a 3D memory device 100 having word line pickup structures 106 according to some embodiments of the present disclosure. The cross section can be along the AA direction at the dielectric portion 107 of the word line pickup region 103 in FIG. 1. As shown in FIG. 4, the word line pickup structures 106 extend vertically into the stack structure 201 (the dielectric stack structure within the dielectric portion 107 of the word line pickup region 103) to different depths in the z direction, according to some implementations. The top surfaces of different word line pickup structures 106 can be coplanar with each other, while the bottom surfaces of different word line pickup structures 106 can extend to different levels, for example, to different second material layers 304 of the stack structure 201.

[0048] In some implementations, the word line pickup structure 106 includes a vertical contact 202, a contact spacer 204 surrounding the vertical contact 202, and an interconnect line 206 below and in contact with the vertical contact 202. The vertical contact 202 and the interconnect line 206 can include a conductive material, including, but not limited to, W, Co, Cu, Al, TiN, polysilicon, doped silicon, silicide, or any combination thereof. The contact spacer 204 can include a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some implementations, the vertical contact 202 and the interconnect line 206 include TiN / W, and the contact spacer 204 includes silicon oxide.

[0049] FIG. 5 illustrates a cross-sectional side view of a 3D memory device 100 having word line pickup structures 106 according to some embodiments of the present disclosure. One cross section can be along the BB direction in the core array region 101 in FIG. 1 , and another cross section can be along the CC direction in the word line pickup region 103 in FIG. 1 . As shown in FIG. 5 , the 3D memory device 100 can include channel structures 110 in the core array region 101. Each channel structure 110 can extend vertically through the interleaved conductive layers 502 (word lines, e.g., tungsten) and first dielectric layers 503 (e.g., silicon oxide) of the conductive stack structure of the stack structure 201 into the substrate 203. The 3D memory device 100 can also include dummy channel structures 112 in the conductive portion 105 of the word line pickup region 103. Each dummy channel structure 112 may extend vertically through the interleaved conductive layers 502 and the first dielectric layer 503 of the conductive stack structure of the stack structure 201 and into the substrate 203. The 3D memory device 100 may further include a slit structure 108 that crosses the core array region 101 and the core array region 101. Each slit structure 108 may similarly extend vertically through the interleaved conductive layers 502 and the first dielectric layer 503 of the conductive stack structure of the stack structure 201 and into the substrate 203.

[0050] As shown in FIG. 5 , the slit structure 108 can include slit spacers 509 that separate the conductive layers 502 (word lines) between different blocks 102. In some implementations, the slit structure 108 is an insulating structure that does not include any contacts therein (i.e., does not function as a source contact) and therefore does not introduce parasitic capacitance and leakage current through the conductive layers 502 (word lines). In some implementations, the slit structure 108 is a front-side source contact that further includes a conductive portion (e.g., comprising W, polysilicon, and / or TiN) surrounded by the slit spacers 509. As described in detail below, during a gate replacement process, the slits in which the slit structure 108 is formed can serve as pathways and starting points for forming the conductive layers 502. As a result, the slit structure 108 is surrounded by the conductive layers 502 in either the core array region 101 or the conductive portions 105 of the word line pickup region 103.

[0051] As shown in FIG. 5 , in some implementations, the 3D memory device 300 further includes a plurality of drain select gate (DSG) channel structures 507 above and respectively in contact with upper ends of the channel structures 110. The 3D memory device 300 may further include, for example, a DSG layer 504 including a semiconductor layer (e.g., a polysilicon layer) over the stack structure 201 in the core array region 101, but not within the word line pickup region 105, as shown in FIG. 5 . Each DSG channel structure 507 may extend vertically through the DSG layer 504 to contact an upper end of a corresponding channel structure 110. In some implementations, the 3D memory device 300 further includes a stop layer 511 (e.g., a silicon nitride layer) over the DSG layer 504. The DSG channel structure 507 may include a semiconductor layer (e.g., polysilicon) and a spacer surrounding the semiconductor layer. In some implementations, the 3D memory device 300 includes a DSG stack including one or more DSG layers and one or more dielectric layers (e.g., silicon oxide layers) stacked in an alternating arrangement above the stack structure 201.

[0052] As shown in FIG. 5 , the 3D memory device 100 may further include a local contact layer above the stop layer 511 and the stack structure 201. In some implementations, the local contact layer includes various local contacts (e.g., channel contacts 506 (also known as bit line contacts)) above and in contact with the DSG structure 507 in the core array region 101. The local contact layer may further include one or more interlayer dielectric (ILD) layers (also known as “inter-metal dielectric (IMD) layers”), and the local contacts may be formed in the one or more interlayer dielectric (ILD) layers. The channel contacts 506 in the local contact layer may include a conductive material, including, but not limited to, W, Co, Cu, Al, a silicide, or any combination thereof. The ILD layers in the local contact layer may include a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof.

[0053] Instead of having a staircase structure and word line contacts resting on different levels / stairs of the staircase structure, the 3D memory device 100 may include a stack structure 201 having a uniform height and word line pickup structures 106 in the dielectric portion 107 of the word line pickup region 103 for word line pickup / fan-out. As shown in FIG. 5 , the interconnect line 206 of each word line pickup structure 106 in the dielectric portion 107 may extend laterally in the y-direction (bit line direction) to contact a corresponding conductive layer 502 (word line) in the conductive portion 105 at the same level of the stack structure 201. Because the interconnect line 206 contacts the vertical contact 202 of the word line pickup structure 106, each word line pickup structure 106 is electrically connected to a corresponding conductive layer 502 (word line) across the conductive portion 105 in the word line pickup region 103 and the core array region 101, according to some implementations. In other words, the word line pickup structures 106 can extend vertically through the stack structure 201 at different depths so as to be electrically connected to the word lines at different levels to achieve word line pickup / fan-out.

[0054] As described in detail below, during the gate replacement process, some of the second dielectric layers 505 (e.g., silicon nitride) remain intact, thereby forming the dielectric stack structure of the stack structure 201 in the dielectric portion 107 of the wordline pick-up region 103, and the wordline pick-up structure 106 is formed by etching the first and second dielectric layers 503 and 505 in the dielectric portion 107 of the wordline pick-up region 103. As a result, the wordline pick-up structure 106 extends into the interleaved first and second dielectric layers 503 and 505 of the dielectric stack structure and is surrounded by the first and second dielectric layers 503 and 505 in the dielectric portion 107 of the wordline pick-up region 103. The bottom of each wordline pickup region 103 may be aligned with a corresponding second dielectric layer 505, as opposed to a first dielectric layer 503, which may be partially replaced by an interconnect line 206 to form an electrical connection between the vertical contact 202 of the wordline pickup region 103 and the corresponding conductive layer 502 (word line). Thus, in some implementations, the interconnect line 206 is sandwiched between two first dielectric layers 503, as opposed to two second dielectric layers 505, in the dielectric stack structure within the dielectric portion 107 of the wordline pickup region 103.

[0055] 5 , due to a relatively large critical dimension compared to word line contacts in some 3D memory devices caused by its fabrication process, as described in detail below, the word line pickup structure 106 further includes a filler 508 surrounded by the vertical contact 202. That is, the word line pickup opening may not be completely filled by the contact spacer 204 and the vertical contact 202, and the remaining space of the word line pickup opening can be filled with a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof, as the filler 508.

[0056] As shown in the enlarged view of FIG. 6A , in some implementations, the channel structure 110 includes a channel hole portion filled with a semiconductor layer (e.g., as the channel layer 604) and a composite dielectric layer (e.g., as the memory layer 602). In some implementations, the channel layer 604 includes silicon (e.g., amorphous silicon, polysilicon, or single-crystal silicon). For example, the channel layer 604 can include polysilicon. In some implementations, the memory layer 602 is a composite layer including a tunneling layer 610, a storage layer 608 (also known as a “charge trap layer”), and a blocking layer 606. The remaining space of the channel hole portion can be partially or completely filled with a filler including a dielectric material (e.g., silicon oxide) and / or an air gap. The channel structure 110 can have a cylindrical shape (e.g., a pillar shape). According to some implementations, the filler, channel layer 604, tunneling layer 610 of memory layer 602, storage layer 608, and blocking layer 606 are arranged radially from the center toward the outer surface of the pillar in that order. The tunneling layer 610 can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 608 can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer 606 can include silicon oxide, silicon oxynitride, or any combination thereof. In one example, the memory layer 602 can include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0057] 6A , the 3D memory device 100 can further include a high-k gate dielectric layer 612 sandwiched between adjacent conductive layers 502 and first dielectric layers 503 in the conductive stack structures in the core array region 101 and the conductive portions 105 of the word line pick-up region 103, respectively. As described in detail below with respect to the fabrication process, the high-k gate dielectric layer 612 can be formed before the formation of the conductive layer 502, such that the conductive layer 502 can be formed surrounded by the high-k gate dielectric layer 612. A portion of the high-k gate dielectric layer 612 laterally between the memory layer 602 and the conductive layer 502 of the channel structure 110 can serve as a gate dielectric for the memory cell. The high-k gate dielectric layer 612 may include a high-k dielectric material such as aluminum oxide (AlO), hafnium oxide (HfO), zirconium oxide (ZrO), or any combination thereof.

[0058] As shown in FIG. 6A , compared to other high-k gate dielectric layers 612, a portion of the high-k gate dielectric layer 612 surrounding the conductive layer 502 (part of the word line) in contact with the interconnect line 206 of the word line pickup structure 106 has been removed to expose the conductive layer 502, thereby allowing the interconnect line 206 to be electrically connected to the conductive layer 502.

[0059] It is understood that the high-k gate dielectric layer 612 can be formed at different locations within the 3D memory device 100, for example, as shown in FIG. 6B . As shown in the expanded view of FIG. 6B , in some implementations, the channel structure 110 includes a channel hole portion filled with a semiconductor layer (e.g., as the channel layer 604) and a composite dielectric layer (e.g., as the memory layer 602 and the high-k gate dielectric layer 612). In some implementations, the channel layer 604 includes silicon (e.g., amorphous silicon, polysilicon, or single-crystalline silicon). For example, the channel layer 604 can include polysilicon. In some implementations, the memory layer 602 is a composite layer including a tunneling layer 610, a storage layer 608 (also known as a “charge trap layer”), and a blocking layer 606. Unlike the example of FIG. 6A , the channel structure 110 of FIG. 6B may further include a high-k gate dielectric layer 612 laterally between the blocking layer 606 of the memory layer 602 and the conductive stack structure of the stack structure 201. The remaining space of the channel structure 110 may be partially or completely filled with a filler including a dielectric material (e.g., silicon oxide) and / or an air gap. The channel structure 110 may have a cylindrical shape (e.g., a pillar shape). According to some implementations, the filler, the channel layer 604, the tunneling layer 610 of the memory layer 602, the storage layer 608, and the blocking layer 606, and the high-k gate dielectric layer 612 are radially arranged in this order from the center to the outer surface of the pillar. The tunneling layer 610 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 608 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer 606 can include silicon oxide, silicon oxynitride, or any combination thereof. In one example, the memory layer 602 can include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.The high-k gate dielectric layer 612 may include aluminum oxide (AlO), hafnium oxide (HfO), zirconium oxide (ZrO), or any combination thereof. In one example, the high-k gate dielectric layer 612 may include AlO.

[0060] 6A , the high-k gate dielectric layer 612 is disposed surrounding only the memory layer 602 of the channel structure 110, but is not sandwiched between adjacent conductive layers 502 and first dielectric layers 503 in the conductive stack structure in the core array region 101 and the conductive portions 105 of the word line pick-up region 103. As described in detail below with respect to the fabrication process, the high-k gate dielectric layer 612, as opposed to the conductive layer 502, can be formed before the formation of the memory layer 602, such that the memory layer 602 can be formed surrounded by the high-k gate dielectric layer 612 instead of the conductive layer 502.

[0061] In some implementations, the dummy channel structures 112 have the same structure as the channel structures 110, as described above with respect to FIGS. 6A and 6B, because they are formed in the same fabrication process. However, the dummy channel structures 112 cannot perform the same memory function as the channel structures 110. This is because, at least according to some implementations, the dummy channel structures 112 are not in contact with any DSG channel structures 507 or any local contacts (e.g., channel contacts 506) in the local contact layer to pick up / fan out the dummy channel structures 112, as shown in FIG. 5. It is understood that in some examples, the dummy channel structures 112 and the channel structures 110 can have different structures and can be formed in different fabrication processes. For example, the dummy channel structures 112 can be filled with a dielectric material without a semiconductor material (as the channel layer 604). Nevertheless, both the dummy channel structure 112 and the channel structure 110 are capable of performing a mechanical support function for the stack structure 201, particularly during the gate replacement process, as described in detail below with respect to the fabrication process.

[0062] FIG. 13 illustrates a block diagram of an exemplary system 1300 having a 3D memory device according to some aspects of the present disclosure. The system 1300 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG. 13 , the system 1300 may include a host 1308 and a memory system 1302, which has one or more 3D memory devices 1304 and a memory controller 1306. The host 1308 may be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)) of the electronic device. The host 1308 may be configured to transmit data to or receive data from the 3D memory device 1304.

[0063] The 3D memory devices 1304 can be any 3D memory device disclosed herein (e.g., the 3D memory devices 100 depicted in FIGS. 1-5, 6A, and 6B, etc.). In some implementations, each 3D memory device 1304 includes NAND flash memory. Consistent with the scope of the present disclosure, word line pickup structures can replace staircase structures and word line contacts to achieve word line pickup / fan-out functions, thereby reducing manufacturing costs and simplifying the fabrication process.

[0064] The memory controller 1306 (also known as a controller circuit) is coupled to the 3D memory device 1304 and the host 1308 and, according to some implementations, is configured to control the 3D memory device 1304. For example, the memory controller 1306 can be configured to operate multiple channel structures via word lines. The memory controller 1306 can manage data stored in the 3D memory device 1304 and communicate with the host 1308. In some implementations, the memory controller 1306 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, CompactFlash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, the memory controller 1306 is designed to operate in high-duty-cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage and enterprise storage arrays for mobile devices (e.g., smartphones, tablets, laptop computers, etc.). The memory controller 1306 can be configured to control operations (e.g., read operations, erase operations, program operations, etc.) of the 3D memory device 1304. The memory controller 1306 can also be configured to manage various functions related to data stored or to be stored in the 3D memory device 1304 (including, but not limited to, bad block management, garbage collection, logical address-to-physical address translation, wear leveling, etc.). In some implementations, the memory controller 1306 is further configured to process error correcting codes (ECC) on data read from or written to the 3D memory device 1304.Any other suitable functions may be similarly performed by memory controller 1306, for example, to form 3D memory device 1304. Memory controller 1306 may communicate with an external device (e.g., host 1308) according to a particular communication protocol. For example, memory controller 1306 may communicate with an external device through at least one of a variety of interface protocols (e.g., USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI-express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.).

[0065] The memory controller 1306 and the one or more 3D memory devices 1304 can be integrated into various types of storage devices, for example, can be included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package, etc.). That is, the memory system 1302 can be implemented and packaged into different types of end electronics products. In one example, as shown in FIG. 14A , the memory controller 1306 and the single 3D memory device 1304 can be integrated into a memory card 1402. The memory card 1402 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a Memory Stick, a MultiMediaCard (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1402 can further include a memory card connector 1404 that electrically couples the memory card 1402 with a host (e.g., the host 1308 of FIG. 13). 14B, the memory controller 1306 and the multiple 3D memory devices 1304 can be integrated into an SSD 1406. The SSD 1406 can further include an SSD connector 1408 that electrically couples the SSD 1406 with a host (e.g., the host 1308 of FIG. 13). In some implementations, the storage capacity and / or operating speed of the SSD 1406 is greater than that of the memory card 1402.

[0066] 7A-7P illustrate a fabrication process for forming a 3D memory device having word line pickup structures according to some embodiments of the present disclosure. 8A-8C illustrate a fabrication process for forming another 3D memory device having word line pickup structures according to some embodiments of the present disclosure. 9 illustrates a flowchart of a method 900 for forming an exemplary 3D memory device having word line pickup structures according to some implementations of the present disclosure. Examples of 3D memory devices depicted in FIGS. 7A-7P, 8A-8C, and 9 include the 3D memory devices 100 depicted in FIGS. 1-5, 6A, and 6B. 7A-7P, 8A-8C, and 9 will be described together. It is understood that the operations illustrated in method 900 are not exhaustive and that other operations can similarly be performed before, after, or during any of the illustrated operations. Additionally, some of the operations may be performed simultaneously or in a different order than that shown in FIG.

[0067] 9 , the method 900 begins at operation 902, where a stack structure is formed including alternating first and second dielectric layers. The first dielectric layer may include silicon oxide, and the second dielectric layer may include silicon nitride. In some implementations, the first and second dielectric layers are alternately deposited above a substrate to form the stack structure. The substrate may be a silicon substrate.

[0068] 7A , a stack structure 704 including multiple pairs of first and second dielectric layers 706 and 708 (also known as stack sacrificial layers) is formed above a silicon substrate 702. According to some implementations, the stack structure 704 includes vertically interleaved first and second dielectric layers 706 and 708. The first and second dielectric layers 706 and 708 can be alternately deposited above the silicon substrate 702 to form the stack structure 704. In some implementations, each first dielectric layer 706 includes a layer of silicon oxide, and each second dielectric layer 708 includes a layer of silicon nitride. The stack structure 704 can be formed by one or more thin film deposition processes, including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0069] The method 900 proceeds to operation 904, as illustrated in FIG. 9 , where a channel structure extending through the first and second dielectric layers is formed in a first region of the stack structure. In some implementations, to form the channel structure, a channel hole extending vertically through the stack structure is formed, and a memory layer and a channel layer are sequentially formed on sidewalls of the channel hole. In some implementations, to form the channel structure, a channel hole extending vertically through the stack structure is formed, and a high-k gate dielectric layer, a memory layer, and a channel layer are sequentially formed on sidewalls of the channel hole. In some implementations, a dummy channel structure extending through the first and second dielectric layers is formed in a second region of the stack structure in the same process that forms the channel structure. That is, the channel structure and the dummy channel structure can be simultaneously formed through the first and second dielectric layers in the first and second regions of the stack structure, respectively.

[0070] As shown in FIG. 7B , channel structures 714 can be formed in a core array region 701 of a stack structure 704 (e.g., corresponding to the core array region 101 of the stack structure 201 of FIGS. 1-3 ). To form each channel structure 714, a channel hole portion 710 (which is an opening extending vertically through the stack structure 704) can first be formed in the core array region 701, as shown in FIG. 7A . In some implementations, multiple openings are formed, such that each opening provides a location for growing an individual channel structure 714 in a later process. In some implementations, the fabrication process for forming the channel hole portion 710 of the channel structure 714 includes wet etching and / or dry etching (e.g., deep ion reactive etching (DRIE)).

[0071] 7B , the memory layer (including the blocking layer, storage layer, and tunneling layer) and the channel layer are sequentially formed in this order along the sidewalls and bottom surface of the channel hole portion 710, for example, corresponding to the example shown in FIG. 6A . In some implementations, the memory layer is first deposited along the sidewalls and bottom surface of the channel hole portion 710, and then the semiconductor channel layer is deposited on top of the memory layer. The blocking layer, storage layer, and tunneling layer can then be deposited in this order using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.) to form the memory layer. The channel layer can then be formed by depositing a semiconductor material (e.g., polysilicon, etc.) on the tunneling layer of the memory layer using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). In some implementations, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a "SONO" structure) are subsequently deposited to form the memory layer and the channel layer of the channel structure 714.

[0072] In some implementations, the high-k gate dielectric layer is formed before the formation of the memory layer. That is, the high-k gate dielectric layer, the memory layer (including the blocking layer, the storage layer, and the tunneling layer), and the channel layer can be sequentially formed in this order along the sidewalls and bottom surface of the channel hole portion 710, for example, corresponding to the example shown in FIG. 6B . In some implementations, the high-k gate dielectric layer is first deposited along the sidewalls and bottom surface of the channel hole portion 710, then the memory layer is deposited on the high-k gate dielectric layer, and then the semiconductor channel layer is deposited on the memory layer. The high-k gate dielectric layer can be formed by depositing a high-k dielectric material (e.g., aluminum oxide) using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). A blocking layer, a storage layer, and a tunneling layer may then be deposited in that order on the high-k gate dielectric layer using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.) to form the memory layer. A channel layer may then be formed by depositing a semiconductor material (e.g., polysilicon, etc.) on the tunneling layer of the memory layer using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). In some implementations, an aluminum oxide layer, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a "SONO" structure) are then deposited to form the high-k gate dielectric layer, memory layer, and channel layer of the channel structure 714.

[0073] In some implementations, as shown in Figure 7B, dummy channel structures 716 can be formed in the word line pickup region 703 of the stack structure 704 (e.g., corresponding to the word line pickup region 103 of the stack structure 201 of Figures 1-3) in the same process that forms the channel structures 714. To form each dummy channel structure 716, as shown in Figure 7A, a dummy channel hole portion 712 (which is another opening extending vertically through the stack structure 704) can be formed in the word line pickup region 703 simultaneously with the channel hole portion 710 by the same wet and / or dry etching (e.g., DRIE, etc.). 7B, a dummy channel structure 716 can then be formed simultaneously with the channel structure 714 by the same thin film deposition process (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) that deposits the memory layer (including the blocking layer, storage layer, and tunneling layer) and the channel layer, or the high-k gate dielectric layer, the memory layer (including the blocking layer, storage layer, and tunneling layer), and the channel layer. It will be understood that in some examples, the dummy channel structure 716 can be formed in a process separate from the channel structure 714.

[0074] As shown in FIG. 7C , a DSG layer 718 and a stop layer 721 are formed over the core array region 701 of the stack structure 704. The DSG layer 718 may include a semiconductor layer (e.g., a polysilicon layer, etc.), and the stop layer 721 may include a silicon nitride layer. The DSG layer 718 and the stop layer 721 may be sequentially deposited over the core array region 701 of the stack structure 704 (but not over the word line pickup region 703) using one or more thin film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). A DSG channel structure 719 may be formed extending vertically through the DSG layer 718 and the stop layer 721 to contact the upper ends of the channel structures 714 (but not the dummy channel structures 716), as shown in FIG. 7C . To form the DSG channel structure 719, a DSG hole portion can be etched through the DSG layer 718 and the stop layer 721 to expose the upper end of the channel structure 714, respectively, and a spacer (e.g., having silicon oxide) and a semiconductor layer (e.g., having polysilicon) can be sequentially deposited into the DSG hole portion using one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof) to fill the DSG hole portion.

[0075] 9 , where all of the second dielectric layer in the first region of the stack structure and a portion of the second dielectric layer in the second region are replaced with a conductive layer, e.g., by a gate replacement process. The conductive layer may include a metal. FIG. 10A is a flowchart of the method 906 for gate replacement according to some aspects of the present disclosure. In operation 1002, a slit is formed through the first and second dielectric layers and across the first and second regions of the stack structure. In some implementations, the slit also extends vertically through the local contact layer.

[0076] 7D , the slits 720 are openings that extend vertically through the stop layer 721, the DSG layer 718, and the first and second dielectric layers 706 and 708 (also known as stack sacrificial layers) of the stack structure 704 to the silicon substrate 702. The slits 720 can also extend laterally across the core array region 701 and the word line pick-up region 703 in the x-direction (word line direction), for example, corresponding to the slit structure 108 of FIG. 1. In some implementations, the fabrication process for forming the slits 720 includes wet etching and / or dry etching (e.g., DRIE, etc.) of the first and second dielectric layers 706 and 708. The etching process through the stack structure 704 may not stop at the top surface of the silicon substrate 702, but may continue to etch away portions of the silicon substrate 702 to ensure that the slit 720 extends vertically all the way through all of the first dielectric layers 706 and second dielectric layers 708 of the stack structure 704.

[0077] In operation 1004, the slits in the first region of the stack structure are covered. As shown in FIG. 7E , a portion of the slits 720 in the core array region 701 is covered by a sacrificial layer 724. In some implementations, a sacrificial layer 724 (e.g., a polysilicon layer or a carbon layer, etc.) different from the first dielectric layer 706 and the second dielectric layer 708 is deposited into the slits 720 using one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof) to at least partially fill the slits 720 (covering the exposed first dielectric layer 706 and second dielectric layer 708 in the slits 720). The sacrificial layer 724 can then be patterned using lithography and wet etching and / or dry etching to remove a portion of the sacrificial layer 724 in the word line pickup region 703, leaving only a portion of the sacrificial layer 724 in the core array region 701 and covering only a portion of the slits 720 in the core array region 701.

[0078] In operation 1006, portions of the second dielectric layer in the second region of the stack structure are removed through the slits in the second region of the stack structure. As shown in FIG. 7E , portions of the second dielectric layer 708 in the conductive portion 729 of the word line pickup region 703 are removed by wet etching to form lateral recesses 726, leaving remaining portions of the second dielectric layer 708 in the dielectric portion 727 of the word line pickup region 703 intact. In some implementations, portions of the second dielectric layer 708 are wet etched by applying a wet etchant through portions of the slits 720 in the word line pickup region 703 that are not covered by the sacrificial layer 724, generating lateral recesses 726 interleaved between the first dielectric layer 706. The wet etchant can include phosphoric acid for etching the second dielectric layer 708, which includes silicon nitride. In some implementations, the etch rate and / or etch time are controlled to remove only a portion of the second dielectric layer 708 in the conductive portion 729, leaving the remaining portion of the second dielectric layer 708 intact in the dielectric portion 727. By controlling the etch time, the wet etchant does not travel all the way to completely remove the second dielectric layer 708 in the word line pickup region 703, thereby defining two portions in the word line pickup region 703: the dielectric portion 709 and the dielectric portion 727, where the second dielectric layer 708 has been removed and where the second dielectric layer 708 remains. As shown in FIG. 7E , in operation 1006, all of the second dielectric layer 708 remains intact in the core array region 701 because some of the slits 720 in the core array region 701 are covered by a sacrificial layer 724 that is resistant to the etchant used to remove the second dielectric layer 708.

[0079] In operation 1008, the slits in the first region of the stack structure are opened. As shown in FIG. 7F, a portion of the slits 720 in the core array region 701 is again opened by removing the sacrificial layer 724 (shown in FIG. 7E), exposing the first dielectric layer 706 and the second dielectric layer 708 (shown in FIG. 7E). In some implementations, the sacrificial layer 724 is selectively etched away from the portion of the slits 720 in the core array region 701, for example, using potassium hydroxide (KOH) to etch the sacrificial layer 724 with polysilicon, opening the portion of the slits 720 in the core array region 701.

[0080] In operation 1010, the slits in the second region of the stack structure are covered. As shown in FIG. 7F , the lateral recesses 726 (shown in FIG. 7E ) and portions of the slits 720 in the word line pickup region 703 are covered by a sacrificial layer 728. In some implementations, a sacrificial layer 728 (e.g., a polysilicon layer or a carbon layer, etc.) different from the first and second dielectric layers 706 and 708 is deposited into the lateral recesses 726 and the slits 720 using one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof, etc.) to at least partially fill the slits 720 (covering the exposed first and second dielectric layers 706 and 708). The sacrificial layer 728 may then be patterned using lithography and wet and / or dry etching to remove a portion of the sacrificial layer 728 in the core array region 701, leaving only a portion of the sacrificial layer 728 in the word line pickup region 703, covering only the lateral recesses 726 and portions of the slits 720 in the word line pickup region 703, but not in the core array region 701. It will be understood that the lateral recesses 726 may be considered part of the slits 720 in the word line pickup region 703. Thus, even if only the lateral recesses 726 are completely or partially filled by the sacrificial layer 728 (e.g., as shown in FIG. 7F ), the portions of the slits 720 in the word line pickup region 703 may still be considered to be covered.

[0081] In operation 1012, all of the second dielectric layers in the first region of the stack structure are removed through the slits in the first region of the stack structure. As shown in FIG. 7F, all of the second dielectric layers 708 in the core array region 701 (as shown in FIG. 7E) are completely removed by wet etching, forming lateral recesses 730. In some implementations, the second dielectric layers 708 are wet etched by applying a wet etchant through portions of the slits 720 in the core array region 701 that are not covered by the sacrificial layer 728, generating lateral recesses 730 interleaved between the first dielectric layers 706. The wet etchant can include phosphoric acid to etch the second dielectric layers 708 that include silicon nitride. In some implementations, the etch rate and / or etch time are controlled to ensure that all of the second dielectric layers 708 in the core array region 701 are completely etched away. As shown in FIG. 7F, in operation 1012, the remaining portion of the second dielectric layer 708 in the dielectric portion 727 of the word line pickup region 703 remains untouched because a portion of the slit 720 in the word line pickup region 703 is covered by a sacrificial layer 728 that is resistant to the etchant used to remove the second dielectric layer 708.

[0082] In operation 1014, the slits in the second region of the stack structure are opened. As shown in FIG. 7G, a portion of the slits 720 in the word line pickup region 703 is again opened by removing the sacrificial layer 728 (shown in FIG. 7F), exposing remaining portions of the first dielectric layer 706 and the second dielectric layer 708 in the word line pickup region 703. In some implementations, the sacrificial layer 728 is selectively etched away from the portion of the slits 720 in the word line pickup region 703, for example, using KOH to etch the polysilicon-containing sacrificial layer 728, opening the portion of the slits 720 (and the lateral recesses 726) in the word line pickup region 703.

[0083] In operation 1016, a conductive layer is deposited through the slits in the first and second regions of the stack structure. As shown in FIG. 7H, a conductive layer 732 is deposited through the slits 720 and into the lateral recesses 730 and 726 (shown in FIG. 7G) in the conductive portions 729 of the core array region 701 and the word line pickup region 703. In some implementations in which a high-k gate dielectric layer is not formed in the channel structure 714, the high-k gate dielectric layer 733 is deposited into the lateral recesses 726 and 730 before the conductive layer 732, and the conductive layer 732 is deposited on top of the high-k gate dielectric layer 733, thereby being surrounded by the high-k gate dielectric layer 733 (e.g., corresponding to the example shown in FIG. 6A). In some implementations in which a high-k gate dielectric layer is formed in the channel structure 714, the high-k gate dielectric layer is not deposited into the lateral recesses 726 and 730 before the conductive layer 732, and the conductive layer 732 is deposited on top of, and thereby surrounded by, the first dielectric layer 706 (e.g., corresponding to the example shown in FIG. 6B ). The conductive layer 732 (e.g., a metal layer, etc.) can be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.).

[0084] As described above, removal of the second dielectric layer 708 (comprising a stack sacrificial layer, e.g., silicon nitride) can be performed separately in the core array region 101 and the word line pickup region 103 by partially covering the slits 720 in the core array region 101 or the word line pickup region 103, allowing the second dielectric layer 708 to be removed in different areas (e.g., completely removed in the core array region 101 and partially removed in the word line pickup region 103). In the gate replacement process described above with respect to FIG. 10A , removal of the second dielectric layer 708 is performed first in the word line pickup region 703 and then in the core array region 701. It is understood that in an alternative gate replacement process, removal of the second dielectric layer 708 can be performed first in the core array region 701 and then in the word line pickup region 703, for example, as shown in FIGS. 8A-8C and 10B . 10B is a flowchart of a method 906 for another gate replacement according to some embodiments of the present disclosure. In operation 1002, a slit is formed through the first and second dielectric layers, extending across the first and second regions of the stack structure. In some implementations, the slit also extends vertically through the local contact layer.

[0085] 7D , the slits 720 are openings that extend vertically through the stop layer 721, the DSG layer 718, and the first and second dielectric layers 706 and 708 of the stack structure 704 down to the silicon substrate 702. The slits 720 can also extend laterally across the core array region 701 and the word line pickup region 703 in the x-direction (word line direction), corresponding to, for example, the slit structure 108 of FIG. 1 . In some implementations, the fabrication process for forming the slits 720 includes wet etching and / or dry etching (e.g., DRIE, etc.) of the first and second dielectric layers 706 and 708. The etching process through the stack structure 704 can not stop at the top surface of the silicon substrate 702 and can continue to etch away portions of the silicon substrate 702 to ensure that the slits 720 extend vertically all the way through all of the first and second dielectric layers 706 and 708 of the stack structure 704.

[0086] In operation 1005, the slits in the second region of the stack structure are covered. As shown in FIG. 8A , a portion of the slits 720 in the word line pickup region 703 is covered by a sacrificial layer 802. In some implementations, a sacrificial layer 802 (e.g., a polysilicon layer or a carbon layer, etc.) different from the first dielectric layer 706 and the second dielectric layer 708 is deposited into the slits 720 using one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof) to at least partially fill the slits 720 (covering the exposed first dielectric layer 706 and second dielectric layer 708 in the slits 720). The sacrificial layer 802 can then be patterned using lithography and wet etching and / or dry etching to remove a portion of the sacrificial layer 802 in the core array region 701, leaving only a portion of the sacrificial layer 802 in the word line pickup region 703 and covering only a portion of the slits 720 in the word line pickup region 703.

[0087] In operation 1007, all of the second dielectric layers in the first region of the stack structure are removed through the slits in the first region of the stack structure. As shown in FIG. 8B, all of the second dielectric layers 708 in the core array region 701 (as shown in FIG. 8A) are completely removed by wet etching to form lateral recesses 730. In some implementations, the second dielectric layers 708 are wet etched by applying a wet etchant through portions of the slits 720 in the core array region 701 that are not covered by the sacrificial layer 802, generating lateral recesses 730 interleaved between the first dielectric layers 706. The wet etchant may include phosphoric acid to etch the second dielectric layers 708 that include silicon nitride. In some implementations, the etch rate and / or etch time are controlled to ensure that all of the second dielectric layers 708 in the core array region 701 are completely etched away. As shown in FIG. 8B, the second dielectric layer 708 in the word line pickup region 703 remains untouched in operation 1007 because a portion of the slit 720 in the word line pickup region 703 is covered by a sacrificial layer 802 that is resistant to the etchant used to remove the second dielectric layer 708.

[0088] In operation 1009, the slits in the second region of the stack structure are opened. As shown in FIG. 8C, a portion of the slits 720 in the word line pickup region 703 is again opened by removing the sacrificial layer 802 (shown in FIG. 8B), exposing the first dielectric layer 706 and the second dielectric layer 708 in the word line pickup region 703. In some implementations, the sacrificial layer 802 is selectively etched away from the portion of the slits 720 in the word line pickup region 703, for example, using KOH to etch the sacrificial layer 802 with polysilicon, opening the portion of the slits 720 in the word line pickup region 703.

[0089] In operation 1013, portions of the second dielectric layer in the second region of the stack structure are removed through the slits in the second region of the stack structure. As shown in FIG. 8C , portions of the second dielectric layer 708 in the conductive portion 729 of the word line pickup region 703 are removed by wet etching to form lateral recesses 726, leaving remaining portions of the second dielectric layer 708 in the dielectric portion 727 of the word line pickup region 703 intact. In some implementations, portions of the second dielectric layer 708 are wet etched by applying a wet etchant through portions of the slits 720 in the word line pickup region 703 to create lateral recesses 726 interleaved between the first dielectric layer 706. The wet etchant can include phosphoric acid for etching the second dielectric layer 708, which includes silicon nitride. In some implementations, the etch rate and / or etch time are controlled to remove only a portion of the second dielectric layer 708 in the conductive portion 729, leaving the remaining portion of the second dielectric layer 708 intact in the dielectric portion 727. By controlling the etch time, the wet etchant does not travel all the way to completely remove the second dielectric layer 708 in the word line pickup region 703, thereby defining two portions in the word line pickup region 703: the conductive portion 729 and the dielectric portion 727, where the second dielectric layer 708 has been removed and where the second dielectric layer 708 remains. As shown in FIG. 8C , because all of the second dielectric layer 708 in the core array region 701 has already been removed in operation 1007, some of the slits 720 in the core array region 701 may not need to be covered in operation 1013.

[0090] In operation 1016, a conductive layer is deposited through the slits in the first and second regions of the stack structure. As shown in FIG. 7H , a conductive layer 732 is deposited through the slits 720 and into the lateral recesses 730 and 726 (shown in FIG. 8C ) in the conductive portions 729 of the core array region 701 and the word line pickup region 703. In some implementations where a high-k gate dielectric layer is not formed in the channel structure 714, a high-k gate dielectric layer 733 is deposited into the lateral recesses 726 and 730 before the conductive layer 732, such that the conductive layer 732 is deposited on and surrounded by the high-k gate dielectric layer 733 (e.g., corresponding to the example shown in FIG. 6A ). In some implementations in which a high-k gate dielectric layer is formed in the channel structure 714, the high-k gate dielectric layer is not deposited into the lateral recesses 726 and 730 before the conductive layer 732, such that the conductive layer 732 is deposited on top of and surrounded by the first dielectric layer 706 (e.g., corresponding to the example shown in FIG. 6B ). The conductive layer 732 (e.g., a metal layer, etc.) can be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.).

[0091] 10A and 10B , the stack structure 704 can be redefined into two stack structures: a conductive stack structure including the interleaved conductive layers 732 and first dielectric layers 706 in the core array region 701 and in the conductive portion 729 of the word line pickup region 703, and a dielectric stack structure including the interleaved first dielectric layers 706 and remaining portions of the second dielectric layers 708 in the dielectric portion 727 of the word line pickup region 703. That is, all of the second dielectric layers 708 in the core array region 701 and a portion of the second dielectric layers 708 in the word line pickup region 703 of the stack structure 704 are replaced with conductive layers 732, according to some implementations. Moreover, in some examples, because the dielectric stack structure in the dielectric portion 727 of the word line pickup region 703 remains intact during the gate replacement process (without removing remaining portions of the second dielectric layer 708 therein), the dummy channel structure 716 may not need to be formed in the dielectric portion 727 of the word line pickup region 703 to provide mechanical support when removing the second dielectric layer 708.

[0092] Referring back to FIG. 9, method 900 proceeds to operation 908, as illustrated in FIG. 9, where word line pickup structures are formed at different depths that extend through remaining portions of the first and second dielectric layers in the second region of the stack structure, thereby electrically connecting the word line pickup structures to the conductive layers, respectively, in the second region of the stack structure.

[0093] In some implementations, a first spacer is formed in the slit before forming the word line pickup structure. As shown in FIG. 7I, a slit spacer 737 is formed in the slit 720 (shown in FIG. 7H) to form a slit structure 734 that extends vertically through the interleaved conductive layers 732 and the first dielectric layer 706 of the stack structure 704 and laterally across the conductive portions 729 of the core array region 701 and the word line pickup region 703. The slit spacer 737 can be formed by depositing a dielectric into the slit 720 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). In some implementations, a conductive material (e.g., as a source contact) is deposited into the slit 720 after the slit spacer 737 as part of the slit structure 734.

[0094] In some implementations, to form a wordline pickup structure, wordline pickup openings extending through the remaining portions of the first and second dielectric layers in the second region of the stack structure are formed to different depths, exposing the remaining portions of the second dielectric layer in the second region of the stack structure. As shown in FIG. 7J , an opening 736 extends vertically through multiple pairs of the first and second dielectric layers 706 and 708 of the dielectric stack structure in the dielectric portion 727 of the wordline pickup region 703. In some implementations, multiple openings 736 are formed, extending through different numbers of pairs of the first and second dielectric layers 706 and 708 in the dielectric portion 727 and stopping at different depths, for example, corresponding to the example shown in FIG. 4 . The openings 736 can be formed using a chopping process. As used herein, a “chopping” process is a process of increasing the depth of one or more openings extending through a dielectric stack structure including alternating first and second dielectric layers by multiple etching cycles. Each etching cycle can include one or more dry etching and / or wet etching processes that etch one pair of the first and second dielectric layers (i.e., reduce the depth by one dielectric layer pair). The purpose of the chopping process is to create multiple openings 736 at different depths. Therefore, depending on the number of openings 736, a certain number of chopping processes may be required, along with multiple chopping masks. It is understood that the number of chopping masks, the sequence of the chopping masks, the design of each chopping mask (e.g., the number and pattern of openings), and / or the depth reduced by each chopping process (e.g., the number of etching cycles) can affect the specific depth of each opening 736 after the chopping process.A detailed description of the chopping process can be found in U.S. Patent Application No. 16 / 881,168, filed May 22, 2022, and U.S. Patent Application No. 16 / 881,339, filed May 22, 2022, both of which are incorporated by reference in their entirety into this specification.

[0095] It will be appreciated that the chopping process can be readily performed through a dielectric stack structure including alternating first and second dielectric layers (e.g., silicon oxide and silicon nitride) as opposed to a conductive stack structure including alternating conductive and dielectric layers (e.g., metal and silicon oxide) due to the etching properties of the different materials. Thus, the dielectric stack structure remaining after the gate replacement process in the dielectric portion 727 of the word line pickup region 703 is suitable, according to some implementations, for forming openings 736 for word line pickup structures at different depths using the chopping process.

[0096] In some implementations, to form the word line pickup structure, second spacers are formed on the sidewalls and bottom of each of the word line pickup openings. As shown in FIG. 7K , contact spacers 738 are formed on the sidewalls and bottom surfaces of the openings 736, thereby covering the first dielectric layer 706 and the second dielectric layer 708 exposed from the sidewalls of the openings 736. In some implementations, the contact spacers 738 are formed by depositing a dielectric material (e.g., silicon oxide) on the sidewalls and bottom surfaces of the openings 736 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0097] In some implementations, to form the wordline pickup structures, the second spacers over the bottoms of the wordline pickup openings are removed, exposing portions of the remaining second dielectric layer. As shown in FIG. 7L , portions of the contact spacers 738 over the bottom surfaces of the openings 736 are removed (e.g., by dry etching) to expose portions of the second dielectric layer 708 in the dielectric portion 727 of the wordline pickup region 703. In some implementations, the etch rate, direction, and / or duration of the RIE are controlled to etch only the portions of the contact spacers 738 over the bottom surfaces of the openings 736 (but not over the sidewall portions) (i.e., to “punch” through the contact spacers 738 in the z-direction, exposing only the corresponding second dielectric layer 708 from the bottom and not the other second dielectric layer 708 from the sidewall portions).

[0098] In some implementations, to form wordline pickup structures, portions of the remaining portions of the second dielectric layer in the second region of the stack structure are respectively replaced with interconnect lines through the wordline pickup openings, whereby the interconnect lines respectively contact the conductive layers in the second region of the stack structure. In some implementations, to replace portions of the second dielectric layer with the interconnect lines, exposed portions of the remaining portions of the second dielectric layer are etched through the wordline pickup openings to expose the respective conductive layers in the second region of the stack structure, and the respective interconnect lines are deposited through the wordline pickup openings to contact the exposed respective conductive layers in the second region of the stack structure.

[0099] As shown in FIG. 7M , a portion of the second dielectric layer 708 exposed from the bottom of the opening 736 is removed by wet etching to form a lateral recess 740, leaving intact the remaining portion of the second dielectric layer 708 at the same level in the dielectric portion 727 of the word line pickup region 703 and other second dielectric layers 708 at other levels. The lateral recess 740 can expose a corresponding conductive layer 732 at the same level in the conductive portion 729 of the word line pickup region 703. In some implementations, the portion of the second dielectric layer 708 is wet etched by applying a wet etchant through the opening 736 to create the lateral recess 740 sandwiched between the two first dielectric layers 706. The wet etchant can include phosphoric acid for etching the second dielectric layer 708 including silicon nitride. In some implementations, the etch rate and / or etch time are controlled to remove only a portion of the second dielectric layer 708 sufficient to expose the corresponding conductive layer 732 at the same level in the conductive portion 729. By controlling the etch time, the wet etchant does not travel all the way to completely remove the second dielectric layer 708 in the dielectric portion 727. As a result, a dummy channel structure 716 may not need to be formed in the dielectric portion 727 of the word line pick-up region 703 to provide mechanical support when removing the second dielectric layer 708. As shown in FIG. 7M , the second dielectric layer 708 at other levels remains untouched in the dielectric portion 727 because the sidewalls of the opening 736 are still covered by contact spacers 738 (e.g., silicon oxide) that are resistant to the etchant for removing the second dielectric layer 708 (e.g., silicon nitride).

[0100] In some implementations where a high-k gate dielectric layer 733 is formed surrounding the conductive layer 732, as opposed to in the channel structure 714, when the exposed portion of the second dielectric layer 708 is etched from the opening 736, the corresponding high-k gate dielectric layer 733 surrounding the corresponding conductive layer 732 at the same level is exposed, as illustrated in FIG. 7N . The exposed portion of the corresponding high-k gate dielectric layer 733 can then be etched (e.g., using a wet etch) to expose the corresponding conductive layer 732 at the same level. It is understood that in some examples where the high-k gate dielectric layer 733 is formed in the channel structure 714, as opposed to surrounding the conductive layer 732, etching of the second dielectric layer 708 can directly expose the corresponding conductive layer 732 at the same level, so etching of the high-k gate dielectric layer 733 can be skipped.

[0101] 7O , an interconnect line 743 is formed by depositing a conductive layer through the opening 736 to fill the lateral recess 740. The conductive layer (e.g., a metal layer, etc.) can be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). The deposition rate and / or duration can be controlled to ensure that the interconnect line 743 can contact the exposed corresponding conductive layer 732 at the same level as the lateral recess 740. In other words, the second dielectric layer 708 exposed from the bottom of the corresponding opening 736 can partially replace the corresponding interconnect line 743 in the dielectric portion 727 of the word line pickup region 703, while other second dielectric layers 708 at other levels in the dielectric portion 727 remain untouched.

[0102] In some implementations, vertical contacts are formed in the word line pickup openings in contact with the interconnect lines, respectively, to form word line pickup structures. As shown in FIG. 7O , vertical contacts 742 are formed on the sidewalls of opening 736 and in contact with interconnect lines 743. Vertical contacts 742 can be formed in the same process that forms interconnect lines 743 by depositing a conductive layer not only into lateral recesses 740 but also on the sidewalls and bottom surfaces of opening 736 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0103] In some implementations, to form the word line pickup structure, after forming each vertical contact, a filler is formed in the word line pickup opening. As shown in FIG. 7P, a filler 744 is formed in the opening 736 (shown in FIG. 7O) to completely or partially fill the opening 736. The filler 744 (e.g., a dielectric layer, etc.) can be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). Excess portions of the conductive layer and the dielectric layer to form the vertical contact 742 and the filler 744 can be removed using chemical mechanical polishing (CMP).

[0104] As described above, the fabrication process for forming a 3D memory device with word line pickup structures involves two major processes: gate replacement and word line pickup structure formation. In method 900, the gate replacement process is performed before the word line pickup structure formation process. It is understood that in other examples, the gate replacement process can be performed after the word line pickup structure formation process. For example, FIGS. 11A-11L illustrate another fabrication process for forming a 3D memory device with word line pickup structures according to some aspects of the present disclosure. FIG. 12 illustrates a flowchart of another method 1200 for forming an exemplary 3D memory device with word line pickup structures according to some implementations of the present disclosure. Examples of 3D memory devices depicted in FIGS. 11A-11L and 12 include the 3D memory devices 100 depicted in FIGS. 1-5, 6A, and 6B. FIGS. 11A-11L and 12 will be described together. It is understood that the operations shown in method 1200 are not exhaustive and that other operations may similarly be performed before, after, or between any of the illustrated operations. Furthermore, some of the operations may be performed simultaneously or in a different order than that shown in FIG.

[0105] 12 , method 1200 begins at operation 1202, where a stack structure is formed including alternating first and second dielectric layers. The first dielectric layer can include silicon oxide, and the second dielectric layer can include silicon nitride. In some implementations, the first and second dielectric layers are alternately deposited above a substrate to form the stack structure. The substrate can be a silicon substrate.

[0106] 11A , a stack structure 704 including multiple pairs of first and second dielectric layers 706 and 708 (also known as stack sacrificial layers) is formed above a silicon substrate 702. The stack structure 704, according to some implementations, includes vertically interleaved first and second dielectric layers 706 and 708. The first and second dielectric layers 706 and 708 can be alternately deposited above the silicon substrate 702 to form the stack structure 704. In some implementations, each first dielectric layer 706 includes a layer of silicon oxide, and each second dielectric layer 708 includes a layer of silicon nitride. The stack structure 704 can be formed by one or more thin film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof).

[0107] 12 , the method 1200 proceeds to operation 1204, where a channel structure extending through the first and second dielectric layers is formed in a first region of the stack structure. In some implementations, to form the channel structure, a channel hole extending vertically through the stack structure is formed, and a high-k gate dielectric layer, a memory layer, and a channel layer are sequentially formed on sidewalls of the channel hole. In some implementations, a dummy channel structure extending through the first and second dielectric layers is formed in a second region of the stack structure in the same process that forms the channel structure. That is, the channel structure and the dummy channel structure can be simultaneously formed through the first and second dielectric layers in the first and second regions of the stack structure, respectively.

[0108] 11A , the channel structures 1102 can be formed in a core array region 701 of the stack structure 704 (e.g., corresponding to the core array region 101 of the stack structure 201 of FIGS. 1-3 ). To form each channel structure 1102, a channel hole portion (which is an opening extending vertically through the stack structure 704) can first be formed in the core array region 701. In some implementations, multiple openings are formed, such that each opening becomes a location for growing an individual channel structure 1102 in a later process. In some implementations, the fabrication process for forming the channel hole portion of the channel structures 1102 includes wet etching and / or dry etching (e.g., DRIE, etc.).

[0109] 11A, a high-k gate dielectric layer, a memory layer (including a blocking layer, a storage layer, and a tunneling layer), and a channel layer can be sequentially formed in this order along the sidewalls and bottom surface of the channel hole, for example, corresponding to the example shown in FIG. 6B. In some implementations, the high-k gate dielectric layer is first deposited along the sidewalls and bottom surface of the channel hole, then the memory layer is deposited on the high-k gate dielectric layer, and then the semiconductor channel is deposited on the memory layer. The high-k gate dielectric layer can be formed by depositing a high-k dielectric material (e.g., aluminum oxide, etc.) using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). The blocking layer, the storage layer, and the tunneling layer can then be deposited in this order on the high-k gate dielectric layer using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to form the memory layer. A channel layer can then be formed by depositing a semiconductor material (e.g., polysilicon, etc.) over the tunneling layer of the memory layer using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). In some implementations, an aluminum oxide layer, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a "SONO" structure) are subsequently deposited to form the high-k gate dielectric layer, memory layer, and channel layer of the channel structure 1102.

[0110] 11A , dummy channel structures 1104 can be formed in the word line pickup region 703 of the stack structure 704 (e.g., corresponding to the word line pickup region 103 of the stack structure 201 of FIGS. 1-3 ) in the same process that forms the channel structure 1102. To form each dummy channel structure 1104, a dummy channel hole portion (which is a separate opening extending vertically through the stack structure 704) can be formed in the word line pickup region 703 simultaneously with the channel hole portion for the channel structure 1102 by the same wet etching and / or dry etching (e.g., DRIE, etc.). As shown in FIG. 11A , the dummy channel structures 1104 can then be formed simultaneously with the channel structure 1102 by the same thin film deposition process (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) that deposits the high-k gate dielectric layer, the memory layer (including the blocking layer, the storage layer, and the tunneling layer), and the channel layer. It is understood that in some examples, the dummy channel structures 1104 may be formed in a separate process from the channel structures 1102 .

[0111] 11A, a DSG layer 718 and a stop layer 721 are formed over the core array region 701 of the stack structure 704. The DSG layer 718 may include a semiconductor layer (e.g., a polysilicon layer, etc.), and the stop layer 721 may include a silicon nitride layer. The DSG layer 718 and the stop layer 721 may be sequentially deposited over the core array region 701 of the stack structure 704 (but not over the word line pickup region 703) using one or more thin film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). A DSG channel structure 719 may be formed extending vertically through the DSG layer 718 and the stop layer 721 to contact the upper ends of the channel structures 1102 (but not the dummy channel structures 1104), as shown in FIG. 11A. To form the DSG channel structure 719, a DSG hole portion can be etched through the DSG layer 718 and the stop layer 721 to expose the upper end of the channel structure 1102, and a spacer (e.g., having silicon oxide) and a semiconductor layer (e.g., having polysilicon) can be sequentially deposited into the DSG hole portion using one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof) to fill the DSG hole portion.

[0112] The method 1200 proceeds to operation 1206, as illustrated in FIG. 12, where word line pickup structures are formed to different depths that extend through the first and second dielectric layers in a second region of the stack structure.

[0113] In some implementations, to form the wordline pickup structure, wordline pickup openings extending through the first and second dielectric layers in the second region of the stack structure are formed to different depths, exposing the second dielectric layer in the second region of the stack structure. As shown in FIG. 11B , opening 1106 extends vertically through multiple pairs of first and second dielectric layers 706 and 708 of stack structure 704 in wordline pickup region 703. In some implementations, multiple openings 1106 are formed, extending through different numbers of pairs of first and second dielectric layers 706 and 708 in wordline pickup region 703 and stopping at different depths, for example, corresponding to the example shown in FIG. 4 . Opening 1106 can be formed using the same chopping process as described in detail above for opening 736.

[0114] In some implementations, to form the word line pickup structure, second spacers are formed on the sidewalls and bottom of each of the word line pickup openings. As shown in FIG. 11C , contact spacers 1108 are formed on the sidewalls and bottom surfaces of the opening 1106, thereby covering the first dielectric layer 706 and the second dielectric layer 708 exposed from the sidewalls of the opening 1106. In some implementations, the contact spacers 1108 are formed by depositing a dielectric material (e.g., silicon oxide) on the sidewalls and bottom surfaces of the opening 1106 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0115] In some implementations, to form the wordline pickup structures, the second spacers over the bottoms of the wordline pickup openings are removed, exposing respective portions of the second dielectric layer. As shown in FIG. 11D , portions of the contact spacers 1108 over the bottom surfaces of the openings 1106 are removed (e.g., by dry etching) to expose portions of the second dielectric layer 708 in the wordline pickup regions 703. In some implementations, the etch rate, direction, and / or duration of the RIE are controlled to etch only the portions of the contact spacers 1108 over the bottom surfaces of the openings 1106 (but not over the sidewall portions) (i.e., to “punch” through the contact spacers 1108 in the z-direction, exposing only the corresponding second dielectric layer 708 from the bottom and not the other second dielectric layer 708 from the sidewall portions).

[0116] In some implementations, portions of the second dielectric layer in the second region of the stack structure are respectively replaced with interconnect lines through the word line pickup openings to form word line pickup structures. In some implementations, exposed portions of remaining portions of the second dielectric layer are etched through the word line pickup openings to replace the portions of the second dielectric layer with the interconnect lines, and respective interconnect lines are deposited through the word line pickup openings.

[0117] As shown in FIG. 11E , a portion of the second dielectric layer 708 exposed from the bottom of the opening 1106 is removed by wet etching, forming a lateral recess 1110 and leaving the remaining portions of the second dielectric layer 708 at the same level and other second dielectric layers 708 at other levels intact in the word line pickup region 703. In some implementations, the portion of the second dielectric layer 708 is wet etched by applying a wet etchant through the opening 1106 to create the lateral recess 1110 sandwiched between the two first dielectric layers 706. The wet etchant can include phosphoric acid to etch the second dielectric layer 708 including silicon nitride. In some implementations, the etch rate and / or etch time are controlled to remove only a portion of the second dielectric layer 708. By controlling the etch time, the wet etchant does not travel all the way to completely remove the second dielectric layer 708 in the word line pickup region 703. As shown in FIG. 11E, the second dielectric layer 708 at other levels remains untouched because the sidewalls of the opening 1106 are still covered by contact spacers 1108 (e.g., silicon oxide) that are resistant to the etchant used to remove the second dielectric layer 708 (e.g., silicon nitride).

[0118] 11F, an interconnect line 1113 is formed by depositing a conductive layer through the opening 736 to fill the lateral recess 740. The conductive layer (e.g., a metal layer, etc.) can be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). In other words, the second dielectric layer 708 exposed from the bottom of the corresponding opening 1106 can be partially replaced with the corresponding interconnect line 1113 in the word line pickup region 703, while other second dielectric layers 708 at other levels remain untouched.

[0119] In some implementations, vertical contacts are formed in the word line pickup openings in contact with the interconnect lines to form word line pickup structures. As shown in FIG. 11F , vertical contacts 1112 are formed on the sidewalls of opening 1106 and in contact with interconnect lines 1113. Vertical contacts 1112 can be formed in the same process that forms interconnect lines 1113 by depositing a conductive layer not only into lateral recesses 1110 but also on the sidewalls and bottom surfaces of opening 1106 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0120] In some implementations, to form the word line pickup structure, after forming each vertical contact, a filler is formed in the word line pickup opening. As shown in FIG. 11G, a filler 1114 is formed in the opening 1106 (shown in FIG. 11F) to completely or partially fill the opening 1106. The filler 1114 (e.g., a dielectric layer, etc.) can be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). Excess portions of the conductive layer and the dielectric layer to form the vertical contact 1112 and the filler 1114 can be removed using CMP.

[0121] 12, the method 1200 proceeds to operation 1208, where all of the second dielectric layers in the first region of the stack structure and portions of the second dielectric layers in the second region are replaced with conductive layers, e.g., by a gate replacement process, such that the conductive layers are electrically connected to the word line pickup structures, respectively, in the second region of the stack structure. The conductive layers may include metal.

[0122] In some implementations, to perform a gate replacement process, slits extending through the first and second dielectric layers and across the first and second regions of the stack structure are formed after forming the word line pickup structures. In some implementations, the slits similarly extend vertically through the local contact layers. As illustrated in FIG. 11H , the slits 1116 are openings that extend vertically through the stop layer 721, the DSG layer 718, and the first and second dielectric layers 706 and 708 of the stack structure 704 to the silicon substrate 702. The slits 1116 can also extend laterally across the core array region 701 and the word line pickup region 703 in the x-direction (word line direction), for example, corresponding to the slit structures 108 of FIG. 1 . In some implementations, the fabrication process for forming the slits 1116 includes wet etching and / or dry etching (e.g., DRIE, etc.) of the first and second dielectric layers 706 and 708. The etching process through the stack structure 704 may not stop at the top surface of the silicon substrate 702, but may continue to etch away portions of the silicon substrate 702 to ensure that the slit 1116 extends vertically all the way through all of the first dielectric layers 706 and second dielectric layers 708 of the stack structure 704.

[0123] In some implementations, the slit in the second region of the stack structure is covered to perform the gate replacement process. As shown in FIG. 11I, a portion of the slit 1116 in the word line pickup region 703 is covered by a sacrificial layer 1120. In some implementations, a sacrificial layer 1120 (e.g., a polysilicon layer or a carbon layer, etc.) different from the first dielectric layer 706 and the second dielectric layer 708 is deposited into the slit 1116 using one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof) to at least partially fill the slit 1116 (covering the exposed first dielectric layer 706 and second dielectric layer 708 in the slit 1116). The sacrificial layer 1120 can then be patterned using lithography and wet and / or dry etching to remove a portion of the sacrificial layer 1120 in the core array region 701, leaving only a portion of the sacrificial layer 1120 in the word line pickup region 703, and covering only a portion of the slits 1116 in the word line pickup region 703.

[0124] In some implementations, to perform the gate replacement process, all of the second dielectric layers in the first region of the stack structure are removed through the slits in the first region of the stack structure. As illustrated in FIG. 11I, all of the second dielectric layers 708 in the core array region 701 (as shown in FIG. 11H) are completely removed by wet etching to form lateral recesses 1122. In some implementations, the second dielectric layers 708 are wet etched by applying a wet etchant through portions of the slits 1116 in the core array region 701 that are not covered by the sacrificial layer 1120, generating lateral recesses 1122 interleaved between the first dielectric layers 706. The wet etchant can include phosphoric acid to etch the second dielectric layers 708 that include silicon nitride. In some implementations, the etch rate and / or etch time are controlled to ensure that all of the second dielectric layers 708 in the core array region 701 are completely etched away. As shown in FIG. 11I, the second dielectric layer 708 in the word line pickup region 703 remains intact because a portion of the slit 1116 in the word line pickup region 703 is covered by a sacrificial layer 1120 that is resistant to the etchant used to remove the second dielectric layer 708.

[0125] In some implementations, a slit in a second region of the stack structure is opened to perform a gate replacement process. As shown in FIG. 11J, a portion of the slit 1116 in the word line pickup region 703 is again opened by removing the sacrificial layer 1120 (shown in FIG. 11I), exposing the first dielectric layer 706 and the second dielectric layer 708 in the word line pickup region 703. In some implementations, the sacrificial layer 1120 is selectively etched away from the portion of the slit 1116 in the word line pickup region 703, for example, using KOH to etch the sacrificial layer 1120 with polysilicon, opening the portion of the slit 1116 in the word line pickup region 703.

[0126] In some implementations, to perform the gate replacement process, portions of the second dielectric layer in the second region of the stack structure are removed through the slits in the second region of the stack structure to expose the interconnect lines of the word line pickup structure. As shown in FIG. 11J , portions of the second dielectric layer 708 in the conductive portion 729 of the word line pickup region 703 are removed by wet etching to form lateral recesses 1124, leaving the remaining portions of the second dielectric layer 708 in the dielectric portion 727 of the word line pickup region 703 intact. In some implementations, portions of the second dielectric layer 708 are wet etched by applying a wet etchant through portions of the slits 1116 in the word line pickup region 703 to create lateral recesses 1124 interleaved between the first dielectric layer 706. The wet etchant can include phosphoric acid to etch the second dielectric layer 708, which includes silicon nitride. In some implementations, the etch rate and / or etch time are controlled to remove only a portion of the second dielectric layer 708 in the conductive portion 729, leaving the remaining portion of the second dielectric layer 708 intact in the dielectric portion 727. By controlling the etch time, the wet etchant does not travel all the way to completely remove the second dielectric layer 708 in the word line pickup region 703, thereby defining two portions in the word line pickup region 703: the conductive portion 729 and the dielectric portion 727, where the second dielectric layer 708 has been removed and where the second dielectric layer 708 remains in the dielectric portion 727. On the other hand, the etch rate and / or etch time are also controlled to ensure that the interconnect line 1113 is exposed by a corresponding lateral recess 1124 at the same level. That is, the remaining portion of the second dielectric layer 708 at the same level as the interconnect line 1113 can be removed sufficiently to expose the interconnect line 1113 from the corresponding lateral recess 1124 and slit 1116 .As shown in FIG. 11J, because all of the second dielectric layer 708 in the core array region 701 has already been removed, some of the slits 1116 in the core array region 701 may not need to be covered when removing some of the second dielectric layer 708 in the word line pickup region 703.

[0127] In some implementations, to perform the gate replacement process, a conductive layer is deposited through the slits in the first and second regions of the stack structure to respectively contact the interconnect lines of the word line pickup structures in the second region of the stack structure. As shown in FIG. 11K, a conductive layer 1126 is deposited through the slits 1116 into the lateral recesses 1122 and 1124 (shown in FIG. 11J) in the conductive portions 729 of the core array region 701 and the word line pickup region 703. It is understood that a high-k gate dielectric layer may already be formed in the channel structure 1102 and not be deposited into the lateral recesses 1122 and 1124 before the conductive layer 1126, whereby the conductive layer 1126 is deposited on and surrounded by the first dielectric layer 706 (e.g., corresponding to the example shown in FIG. 6B). The conductive layer 1126 (e.g., a metal layer, etc.) can be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). The deposition rate and / or duration can be controlled to ensure that the conductive layer 1126 at the same level as the interconnect lines 1113 is in contact with the interconnect lines 1113 in the word line pick-up region 703.

[0128] After the gate replacement process described above, the stack structure 704 can be redefined into two stack structures: a conductive stack structure including the interleaved conductive layers 732 and first dielectric layers 706 in the core array region 701 and in the conductive portion 729 of the word line pickup region 703, and a dielectric stack structure including the interleaved first dielectric layers 706 and remaining portions of the second dielectric layers 708 in the dielectric portion 727 of the word line pickup region 703. That is, all of the second dielectric layers 708 in the core array region 701 and a portion of the second dielectric layers 708 in the word line pickup region 703 of the stack structure 704 are replaced with conductive layers 732, according to some implementations. Moreover, in some examples, because the dielectric stack structure in the dielectric portion 727 of the word line pickup region 703 remains intact during the gate replacement process (without removing remaining portions of the second dielectric layer 708 therein), the dummy channel structure 716 may not need to be formed in the dielectric portion 727 of the word line pickup region 703 to provide mechanical support when removing the second dielectric layer 708.

[0129] In some implementations, after forming the word line pickup structures and after the gate replacement process, first spacers are formed in the slits. As shown in FIG. 11L, slit spacers 1127 are formed in the slits 1116 (shown in FIG. 11K) to form slit structures 1128 that extend vertically through the interleaved conductive layers 732 and the first dielectric layer 706 of the stack structure 704 and laterally across the conductive portions 729 of the core array region 701 and the word line pickup region 703. The slit spacers 1127 can be formed by depositing a dielectric into the slits 1116 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). In some implementations, a conductive material (e.g., as a source contact) is deposited into the slits 1116 after the slit spacers 1127 as part of the slit structures 1128.

[0130] 10A and 10B, during the gate replacement process, removal of the second dielectric layer 708 can be performed first in the core array region 701 and then in the word line pickup region 703 (e.g., as shown in FIGS. 11I and 11J), or vice versa. Thus, the operations described with respect to FIGS. 11I and 11J can be replaced with similar operations described with respect to FIGS. 7E-7G, such that the gate replacement process can be performed after the word line pickup structure formation process, and during the gate replacement process, removal of the second dielectric layer 708 can be performed first in the word line pickup region 703 and then in the core array region 701. In some implementations, to perform the gate replacement process, the slit in a first region of the stack structure is covered, in a second region of the stack structure, a portion of the second dielectric layer in the second region of the stack structure is removed through the slit, the slit in the first region of the stack structure is opened, the slit in the second region of the stack structure is covered, all of the second dielectric layer in the first region of the stack structure is removed through the slit in the first region of the stack structure, the slit in the second region of the stack structure is opened, and a conductive layer is deposited through the slit in the first region and the second region of the stack structure.

[0131] The foregoing descriptions of specific implementations may be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

[0132] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0133] 100 3D memory devices 101 Core Array Region 102 blocks 103 Word Line Pickup Area 104 Finger 105 Conductive part 106 Word Line Pickup Structure 107 Dielectric part 108 Slit Structure 109 "H" cut 110 Channel Structure 112 Dummy Channel Structure 201 Stack Structure 202 Vertical Contact 203 Substrate 204 Contact spacer 206 Interconnection Lines 300 3D memory devices 302 first material layer 304 Second material layer 502 Conductive layer 503 First Dielectric Layer 504 DSG layer 505 Second Dielectric Layer 506 Channel Contact 507 Drain Select Gate (DSG) Channel Structure 508 Filler 509 Slit Spacer 511 Stop Layer 602 Memory Layer 604 Channel Layer 606 Blocking Layer 608 Storage Tier 610 Tunneling Layer 612 High-k gate dielectric layers 701 Core Array Region 702 Silicon substrate 703 Word Line Pickup Area 704 Stack Structure 706 First Dielectric Layer 708 Second Dielectric Layer 709 Dielectric part 710 Channel hole part 712 Dummy channel hole part 714 Channel Structure 716 Dummy Channel Structure 718 DSG layer 719 DSG Channel Structure 720 slit 721 Stop Layer 724 Sacrificial Layer 726 Lateral recess 727 Dielectric part 728 Sacrificial Layer 729 Conductive part 730 Lateral recess 732 Conductive Layer 733 High-k gate dielectric layer 734 Slit Structure 736 Opening 737 Slit Spacer 738 Contact Spacer 740 Lateral recess 742 Vertical Contact 743 Interconnection Line 744 Filler 802 Sacrificial Layer 1102 Channel Structure 1104 Dummy Channel Structure 1106 Opening 1108 Contact spacer 1110 Lateral recess 1112 Vertical Contact 1113 Interconnection Line 1114 Filler 1116 Slit 1120 Sacrificial Layer 1122 Lateral recess 1124 Lateral recess 1126 Conductive layer 1127 Slit Spacer 1128 Slit structure 1300 System 1302 Memory System 1304 3D Memory Device 1306 Memory Controller 1308 Host 1402 memory card 1404 memory card connector 1406 SSD 1408 SSD Connector

Claims

1. 1. A method for forming a three-dimensional (3D) memory device, the method comprising: forming a stack structure including alternating first and second dielectric layers; forming a channel structure extending through the first dielectric layer and the second dielectric layer in a first region of the stack structure; replacing all of the second dielectric layers in the first region and a portion of the second dielectric layers in the second region of the stack structure with a conductive layer; forming word line pickup structures at different depths that extend through remaining portions of the first and second dielectric layers in the second region of the stack structure, whereby the word line pickup structures are each electrically connected to the conductive layer in the second region of the stack structure; Including, The method, wherein the conductive layer formed by substitution in the first region and the conductive layer formed by substitution in the second region are electrically connected to each other.

2. 2. The method of claim 1, further comprising forming a dummy channel structure extending through the first dielectric layer and the second dielectric layer in the second region of the stack structure in the same process of forming the channel structure.

3. The method of claim 1, wherein the replacing step includes forming a slit extending through the first dielectric layer and the second dielectric layer and across the first region and the second region of the stack structure before forming the word line pickup structure.

4. The replacing step comprises: covering the slit in the second region of the stack structure; removing all of the second dielectric layer in the first region of the stack structure through the slit in the first region of the stack structure; opening the slit in the second region of the stack structure; removing the portion of the second dielectric layer in the second region of the stack structure through the slit in the second region of the stack structure; depositing the conductive layer through the slits in the first region and the second region of the stack structure; The method of claim 3 further comprising:

5. The replacing step comprises: covering the slit in the first region of the stack structure; removing the portion of the second dielectric layer in the second region of the stack structure through the slit in the second region of the stack structure; opening the slit in the first region of the stack structure; covering the slit in the second region of the stack structure; removing all of the second dielectric layer in the first region of the stack structure through the slit in the first region of the stack structure; opening the slit in the second region of the stack structure; depositing the conductive layer through the slits in the first region and the second region of the stack structure; The method of claim 3 further comprising:

6. 4. The method of claim 3, further comprising forming a first spacer in the slit before forming the word line pickup structure.

7. forming the word line pickup structure includes: forming word line pick-up openings at different depths that extend through the remaining portions of the first and second dielectric layers in the second region of the stack structure to expose the remaining portions of the second dielectric layer in the second region of the stack structure, respectively; replacing a portion of the remaining portion of the second dielectric layer in the second region of the stack structure with an interconnect line through the word line pickup opening, whereby the interconnect line contacts the conductive layer in the second region of the stack structure; forming vertical contacts in the word line pick-up openings in contact with the interconnect lines, respectively; The method of claim 1 , comprising:

8. forming the word line pickup structure includes: forming second spacers on the sidewalls and bottom of each of the word line pick-up openings; removing the second spacers on the bottoms of the word line pick-up openings to expose the portions of each of the remaining portions of the second dielectric layer; forming a filler in the word line pick-up opening after forming each of the vertical contacts; The method of claim 7 further comprising:

9. replacing the portion of the second dielectric layer with the interconnect line; etching the exposed portions of the remaining portion of the second dielectric layer through the word line pick-up openings to expose the respective conductive layers in the second region of the stack structure; depositing respective interconnect lines through the word line pick-up openings so as to contact the respective exposed conductive layers in the second region of the stack structure; The method of claim 8, comprising:

10. The step of replacing all of the second dielectric layers in the first region and the portion of the second dielectric layers in the second region with the conductive layer comprises depositing a high dielectric constant (high-k) gate dielectric layer, whereby the conductive layers are each surrounded by the high-k gate dielectric layer; replacing the portion of the second dielectric layer with the interconnect line; etching the exposed portions of the remaining portions of the second dielectric layer to expose the respective high-k gate dielectric layer; etching the exposed high-k gate dielectric layer to expose each of the conductive layers; depositing each of the interconnect lines so as to contact the exposed respective conductive layers; 10. The method of claim 9, further comprising:

11. 1. A method for forming a three-dimensional (3D) memory device, comprising: forming a stack structure including alternating first and second dielectric layers; forming a channel structure extending through the first dielectric layer and the second dielectric layer in a first region of the stack structure; forming word line pickup structures to different depths that extend through the first and second dielectric layers in a second region of the stack structure; replacing all of the second dielectric layers in the first region of the stack structure and portions of the second dielectric layers in the second region with conductive layers, whereby the conductive layers are electrically connected to the word line pickup structures in the second region of the stack structure, respectively; Including, The method, wherein the conductive layer formed by substitution in the first region and the conductive layer formed by substitution in the second region are electrically connected to each other.

12. 12. The method of claim 11, further comprising forming a dummy channel structure extending through the first dielectric layer and the second dielectric layer in the second region of the stack structure in the same process of forming the channel structure.

13. forming the word line pickup structure includes: forming word line pick-up openings at different depths that extend through the first dielectric layer and the second dielectric layer in the second region of the stack structure to expose the second dielectric layer in the second region of the stack structure, respectively; respectively replacing a portion of the second dielectric layer in the second region of the stack structure with an interconnect line through the word line pickup opening; forming vertical contacts in the word line pick-up openings in contact with the interconnect lines, respectively; The method of claim 11 , comprising:

14. forming the word line pickup structure includes: forming second spacers on the sidewalls and bottom of each of the word line pick-up openings; removing the second spacers on the bottoms of the word line pick-up openings to expose the portions of each of the second dielectric layers; forming a filler in the word line pick-up opening after forming each of the vertical contacts; 14. The method of claim 13, further comprising:

15. replacing the portion of the second dielectric layer with the interconnect line; etching the exposed portion of the second dielectric layer through the word line pick-up opening; depositing each of the interconnect lines through the word line pick-up openings; 15. The method of claim 14, comprising:

16. The method of claim 13, wherein the step of replacing all of the second dielectric layers in the first region and the portion of the second dielectric layers in the second region with the conductive layer includes, after forming the word line pickup structure, forming a slit through the first dielectric layer and the second dielectric layer and extending across the first region and the second region of the stack structure.

17. The step of replacing all of the second dielectric layers in the first region and the portion of the second dielectric layers in the second region with the conductive layer includes: covering the slit in the second region of the stack structure; removing all of the second dielectric layer in the first region of the stack structure through the slit in the first region of the stack structure; opening the slit in the second region of the stack structure; removing the portion of the second dielectric layer in the second region of the stack structure through the slit in the second region of the stack structure to expose the interconnect line of the word line pickup structure; depositing the conductive layer through the slits in the first and second regions of the stack structure so as to respectively contact the interconnect lines of the word line pickup structure in the second region of the stack structure; 17. The method of claim 16, further comprising:

18. The step of replacing all of the second dielectric layers in the first region and the portion of the second dielectric layers in the second region with the conductive layer includes: covering the slit in the first region of the stack structure; removing the portion of the second dielectric layer in the second region of the stack structure through the slit in the second region of the stack structure to expose the interconnect line of the word line pickup structure; opening the slit in the first region of the stack structure; covering the slit in the second region of the stack structure; removing all of the second dielectric layer in the first region of the stack structure through the slit in the first region of the stack structure; opening the slit in the second region of the stack structure; depositing the conductive layer through the slits in the first and second regions of the stack structure so as to respectively contact the interconnect lines of the word line pickup structure in the second region of the stack structure; 17. The method of claim 16, further comprising:

19. The method described in claim 16, further comprising the step of forming a first spacer in the slit after the step of replacing all of the second dielectric layer in the first region and the portion of the second dielectric layer in the second region with the conductive layer.

20. 12. The method of claim 11, wherein forming the channel structure comprises sequentially forming a high-k gate dielectric layer, a memory layer, and a channel layer.

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