Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device capable of suppressing a withstanding voltage.SOLUTION: A charge balance CB of an n-type region 21 and a p-type region 22 which are adjacent to a parallel pn-layer each other 20, becomes a p-rich on a front surface side of a substrate in a boundary of a reference condition range 23 containing a depth position Z0 of 1 / 2 of a thickness Lsj of the parallel pn-layer each other 20, becomes an n-rich on a back surface side of the substrate while increasing at a predetermined first inclination D+ as directed to the front surface side of the substrate, and becomes small at a predetermined second inclination D- as directed to the back surface side of the substrate. A charge amount of the p-type region 22 of the parallel pn-layer each other 20 is larger than that of the p-type region 22 of a reference condition on the front surface side of the substrate in the boundary of the reference condition range 23, and is smaller than the charge amount of the p-type region 22 of the reference condition on the back surface side of the substrate. An absolute value of the first inclination D+ is larger than an absolute value of the second inclination D- in the range of the n-rich.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a silicon carbide semiconductor device. and a method for manufacturing a silicon carbide semiconductor device Regarding. [Background technology]

[0002] Conventionally, semiconductor devices with a super junction (SJ) structure have been known, in which the drift layer is a parallel pn layer formed by alternately and repeatedly arranging n-type and p-type regions adjacent to each other in a direction parallel to the main surface of the substrate. It has been disclosed that in a semiconductor device with an SJ structure using silicon (Si) as the semiconductor material, the breakdown voltage margin can be widened by providing a gradient in the depth direction to the charge balance between the adjacent n-type and p-type regions of the parallel pn layer (by changing the charge balance in the depth direction) (see, for example, Non-Patent Document 1 below).

[0003] Non-Patent Document 1 below discloses that a trench-filling epitaxial method is used to form an SJ structure by forming a trench (hereinafter referred to as an SJ trench) in an n-type epitaxial layer, leaving a portion that will become the n-type region of the parallel pn layer, and filling the SJ trench with a p-type epitaxial layer that will become the p-type region of the parallel pn layer, and by making the SJ trench have a tapered cross-sectional shape that narrows as it becomes deeper, a gradient is created in the depth direction in the charge balance between the adjacent n-type and p-type regions of the parallel pn layer.

[0004] Charge balance is an index showing the degree of balance between the amount of charge, which is expressed as the product of the carrier concentration (impurity concentration) and width of the n-type region of the parallel pn layer, and the amount of charge, which is expressed as the product of the carrier concentration and width of the p-type region. To impart a gradient in the depth direction to the charge balance between the adjacent n-type and p-type regions of the parallel pn layer, there are two methods: one is to change the impurity concentration of the p-type region (or n-type region) of the parallel pn layer in the depth direction, and the other is to change the widths of the n-type and p-type regions of the parallel pn layer in the depth direction, as in Non-Patent Document 1 below.

[0005] Another known method for forming an SJ structure is a multistage epitaxial method in which an n-type epitaxial layer is divided into multiple stages (multiple times) and epitaxially grown in multiple stages, and an ion implantation mask with openings at predetermined locations is formed on the n-type epitaxial layer for each stage, and p-type impurities are ion-implanted using this ion implantation mask as a mask, thereby selectively forming regions that will become p-type regions of the parallel p-n layer so that regions that will become n-type regions of the parallel p-n layer remain in each of the n-type epitaxial layers epitaxially grown in multiple stages.

[0006] A conventional silicon carbide semiconductor device with an SJ structure is a vertical semiconductor device with a planar gate structure, in which the thickness of the gate insulating film is made relatively thick directly below the center of the gate electrode, and the impurity concentrations of the n-type and p-type regions of the parallel pn layer are made relatively high to reduce the on-resistance, and the impurity concentrations of the n-type and p-type regions of the parallel pn layer are made relatively low directly below the p-type base region to maintain the element breakdown voltage (see, for example, Patent Document 1 below).

[0007] Another conventional silicon carbide semiconductor device with an SJ structure has been proposed, in which the SJ trench in which the n-type region of the parallel pn layer is embedded has a tapered cross-sectional shape that narrows as it becomes deeper, and the p-type region of the parallel pn layer is formed by multiple ion implantations at different angles obliquely into the sidewall of the SJ trench, and the impurity concentration of the p-type region decreases at a constant gradient toward the drain region, thereby maintaining a uniform charge balance in the depth direction between the adjacent n-type and p-type regions of the parallel pn layer and maintaining a high maximum breakdown voltage (see, for example, Patent Document 2 below). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-018877 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-019146 [Non-patent literature]

[0009] [Non-Patent Document 1] T. Tamaki and eight others, "Vertical charge imbalance effect on 600V-class trench-filling superjunction power MOSFETs," 2011 IEEE 23rd International Symposium on Power Semiconductor Devices & ICs (2011 ISPSD), USA, IEEE: Institute of Electrical and Electronics Engineers, May 2011, pp. 308-311. Summary of the Invention [Problem to be solved by the invention]

[0010] However, in conventional methods for manufacturing silicon carbide semiconductor devices, whether the parallel pn layer is formed using a trench-filling epitaxial method or a multilevel epitaxial method, the width of the p-type region (or n-type region) of the parallel pn layer is likely to deviate from the design value (optimal value). In the multilevel epitaxial method, dimensional deviations are likely to occur due to the accuracy of the openings in the ion implantation mask, and in particular, when the p-type region of the parallel pn layer is formed by ion implantation of aluminum (Al), the width of the p-type region can be narrowed by up to about 1 μm from the design value.

[0011] The more the width of the p-type region (or n-type region) of the parallel p-n layer deviates from the standard condition, the greater the decrease in breakdown voltage. The standard condition is the condition of charge balance between the adjacent n-type and p-type regions of the parallel p-n layer that, in terms of design, provides the highest breakdown voltage. For example, when the widths of the n-type and p-type regions of the parallel p-n layer are approximately uniform in the depth direction, the charge balance (equilibrium) between the adjacent n-type and p-type regions of the parallel p-n layer is generally maintained. "Approximately uniform width" means that the width is the same within a range that includes tolerances due to process variations.

[0012] The present invention provides a silicon carbide semiconductor device capable of suppressing a decrease in breakdown voltage in order to solve the above-mentioned problems associated with the prior art. and a method for manufacturing a silicon carbide semiconductor device The purpose is to provide the following. [Means for solving the problem]

[0013] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features: A parallel pn layer is provided within a semiconductor substrate made of silicon carbide, in which first conductivity type regions and second conductivity type regions are alternately and repeatedly arranged in a first direction parallel to a first main surface of the semiconductor substrate; A predetermined element structure is provided between the first main surface and the parallel pn layer; A first electrode is provided on the first main surface and electrically connected to the element structure; and A second electrode is provided on a second main surface of the semiconductor substrate.

[0014] The charge balance between the first conductivity type region and the second conductivity type region adjacent to each other in the parallel pn layer has the following six characteristics. ,before In a depth range of a predetermined width symmetrical with respect to a depth position of 1 / 2 the thickness of the parallel pn layer, Uniform in the thickness direction The second feature is that the amount of charge in the second conductivity type region on the first main surface side is greater than the amount of charge in the first conductivity type region under the standard conditions, and is also greater than the amount of charge in the second conductivity type region under the standard conditions.

[0015] A third feature is that the charge amount in the second conductivity type region relatively increases at a predetermined first gradient as the distance from the standard condition portion to the first main surface side increases. A fourth feature is that the charge amount in the first conductivity type region is greater than the charge amount in the second conductivity type region on the second main surface side of the standard condition portion. A fifth feature is that the charge amount in the second conductivity type region on the second main surface side of the standard condition portion is less than the charge amount in the second conductivity type region under the standard condition. A sixth feature is that the charge amount in the second conductivity type region relatively decreases at a predetermined second gradient as the distance from the standard condition portion to the second main surface side increases.

[0016] In addition, in the silicon carbide semiconductor device according to the present invention, an absolute value of the first gradient is greater than an absolute value of the second gradient.

[0017] Furthermore, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the charge balance is defined as CB, and the carrier concentration, width and charge amount of the first conductivity type region are defined as N d , W n and Q n The carrier concentration, width and charge amount of the second conductivity type region are set to N a , W p and Q p When the above formula (1) is satisfied, the charge balance has an upper limit of +160% on the first principal surface side of the standard condition portion, and a lower limit of −30% on the second principal surface side of the standard condition portion.

[0018]

number

[0019] Furthermore, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, a first charge balance (CB1 +) and a second charge balance (CB1 - ) is characterized by satisfying the following formula (2).

[0020]

number

[0021] In addition, in the silicon carbide semiconductor device according to the present invention, the standard conditions are charge balance conditions that provide the highest breakdown voltage.

[0022] In addition, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the first conductivity type region has a uniform impurity concentration in a depth direction, and the second conductivity type region has an impurity concentration distribution that varies in a depth direction with the same gradients as the first gradient and the second gradient of the charge balance distribution.

[0023] In addition, the silicon carbide semiconductor device according to the present invention further includes a buffer region of a first conductivity type provided between the second main surface and the parallel pn layer, the buffer region having a lower impurity concentration than the first conductivity type region, and a boundary between the buffer region and the first conductivity type region. Bottom of The charge balance at the boundary between the buffer region and the first conductivity type region is at a depth position closer to the first main surface than the boundary between the buffer region and the first conductivity type region.

[0024] Further, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the charge balance is determined by measuring the depth of the boundary between the buffer region and the first conductivity type region from the depth position of the boundary between the buffer region and the second conductivity type region. Bottom of It is characterized by being uniform in the depth direction up to the depth position of the boundary with

[0025] Further, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, the charge balance is determined by measuring the depth of the boundary between the buffer region and the first conductivity type region from the depth position of the boundary between the buffer region and the second conductivity type region. Bottom of The thickness of the insulating layer increases at a predetermined third gradient toward the second main surface up to a depth position of the boundary between the insulating layer and the insulating layer.

[0026] Further, in the silicon carbide semiconductor device according to the present invention, in the above-described invention, a depth of the boundary between the buffer region and the first conductivity type region is determined based on a depth position of the boundary between the buffer region and the second conductivity type region. Bottom of the buffer region and the second conductivity type region in a portion up to a depth position of the boundary between the buffer region and the second conductivity type region Bottom of A fourth charge balance (CB2 - ) at a depth position on the second main surface side by a third distance equal to the fourth distance from a depth position of an end of the parallel pn layer on the first main surface side, and a third charge balance (CB2 + ) is characterized by satisfying the following equation (3).

[0027]

number

[0028] In the silicon carbide semiconductor device according to the present invention, the impurity concentration of the first conductivity type region is uniform in a depth direction, and the impurity concentration of the second conductivity type region varies in a depth direction at the same gradients as the first gradient and the second gradient of the charge balance distribution, and the impurity concentration of the buffer region and the second conductivity type region varies in a depth direction at a gradient equal to the first gradient and the second gradient of the charge balance distribution, and the impurity concentration of the buffer region and the second conductivity type region varies in a depth direction at a gradient equal to the first gradient and the second gradient of the charge balance distribution, and the impurity concentration of the first conductivity type region varies in a depth direction at a gradient equal to the first gradient and the second gradient of the charge balance distribution, and the impurity concentration of ... second conductivity type region varies in a depth direction at a gradient equal to the first gradient and the second gradient of the charge balance distribution, and the impurity concentration of the buffer region and the second conductivity type region varies in a depth direction at a gradient equal to the first gradient and the second gradient of the charge balance distribution, and Bottom of It is characterized by having a uniform impurity concentration distribution in the depth direction up to the depth position of the boundary with the

[0029] In the silicon carbide semiconductor device according to the present invention, in the above-described invention, the first conductivity type region has a uniform impurity concentration in a depth direction, and the second conductivity type region has an impurity concentration distribution that varies in a depth direction with gradients that are the same as the first gradient, the second gradient, and the third gradient of the charge balance distribution.

[0030] Furthermore, in order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention is the above-mentioned method for manufacturing a silicon carbide semiconductor device, and has the following features: a multistage epitaxial process is performed in which a first conductivity type epitaxial layer is epitaxially grown in multiple stages, and each time the first conductivity type epitaxial layer is epitaxially grown in multiple stages, a second conductivity type impurity is ion-implanted into the first conductivity type epitaxial layer to form a second conductivity type diffusion region that becomes the second conductivity type region, and portions of the first conductivity type epitaxial layer excluding the second conductivity type diffusion region remain as the first conductivity type region, thereby forming the parallel p-n layer; and second conductivity type diffusion regions with different impurity concentrations are formed by the ion implantation in each of the plurality of first conductivity type epitaxial layers that are epitaxially grown in multiple stages, so that the second conductivity type region of the parallel p-n layer has the impurity concentration distribution.

[0031] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, in the multistage epitaxial step, a lowest layer of the plurality of first conductivity type epitaxial layers that are epitaxially grown in multiple stages is epitaxially grown with an impurity concentration of the buffer region, and a portion of the lowest layer excluding the second conductivity type diffusion region is left as the buffer region.

[0032] Furthermore, in order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention is the above-mentioned method for manufacturing a silicon carbide semiconductor device, and has the following features: The trench-filling epitaxial step for forming the parallel pn layer includes first to third steps. In the first step, a first-conductivity-type epitaxial layer is epitaxially grown. In the second step, a trench is formed in the first-conductivity-type epitaxial layer, leaving a portion of the first-conductivity-type epitaxial layer that will become the first-conductivity-type region. In the third step, the trench is filled with a second-conductivity-type epitaxial layer that will become the second-conductivity-type region. In the third step, an impurity concentration is changed during epitaxial growth of the second-conductivity-type epitaxial layer, so that the second-conductivity-type region of the parallel pn layer has the impurity concentration distribution.

[0033] Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the first step is semiconductor a second impurity concentration layer of the first conductivity type region; semiconductor The first conductive type epitaxial layer is formed by epitaxially growing the first layer and the second layer in this order. semiconductor The trench is formed to terminate inside the layer, leaving portions of the first conductivity type epitaxial layer that will become the buffer region and the first conductivity type region. [Effects of the Invention]

[0034] Silicon carbide semiconductor device according to the present invention and a method for manufacturing a silicon carbide semiconductor device This provides the effect of suppressing a decrease in breakdown voltage due to a change in the width of the second conductivity type region of the parallel pn layer. [Brief explanation of the drawings]

[0035] [Figure 1] 1 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to an embodiment; [Figure 2] 2 is a cross-sectional view showing any adjacent n-type and p-type regions of the parallel pn layer of FIG. 1. FIG. [Figure 3] 3 is a distribution diagram showing the charge balance distribution in the depth direction of the n-type region and p-type region adjacent to each other in the parallel pn layer of FIG. 2. FIG. [Figure 4] 1. FIG. 4 is a cross-sectional view showing another example of any mutually adjacent n-type region and p-type region of the parallel pn layer of FIG. [Figure 5] 5 is a distribution diagram showing the charge balance distribution in the depth direction of the n-type region and p-type region adjacent to each other in the parallel pn layer of FIG. 4. FIG. [Figure 6] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 7] 7 is a distribution diagram showing an example of charge balance distribution in the depth direction of the n-type region and p-type region adjacent to each other in the parallel pn layer of FIG. 6. FIG. [Figure 8] FIG. 10 is a characteristic diagram showing the relationship between the breakdown voltage and the width of the p-type region of the parallel pn layer in an embodiment. [Figure 9] FIG. 10 is a characteristic diagram showing the relationship between the breakdown voltage and the width of the p-type region of the parallel pn layer in a conventional example. [Figure 10] FIG. 10 is a characteristic diagram showing the relationship between the yield rate and the width of the p-type region of the parallel pn layer in the example and the conventional example. DETAILED DESCRIPTION OF THE INVENTION

[0036] A silicon carbide semiconductor device according to the present invention will be described below with reference to the accompanying drawings. and a method for manufacturing a silicon carbide semiconductor device Preferred embodiments of the present invention will be described in detail. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - prefixed with n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with that prefix, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0037] (Embodiment) The structure of a silicon carbide semiconductor device according to an embodiment will be described using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor having an insulated gate with a three-layer structure of metal-oxide film-semiconductor) as an example. FIG. 1 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment. FIG. 1 shows some unit cells among a plurality of unit cells (components of an element) of the same structure arranged in an active region.

[0038] 1 is a vertical MOSFET with an SJ structure, in which an active region of a silicon carbide (SiC) semiconductor substrate (semiconductor chip) 30 has a typical trench gate structure (device structure) on the front surface (first main surface) side, and a drift layer (drift region) 2 serves as a parallel pn layer 20. The active region is a region through which a main current flows when the MOSFET is in an on-state, and is located at the center of the semiconductor substrate 30. An edge termination region (not shown) is a region between the active region and an edge of the semiconductor substrate 30, and surrounds the periphery of the active region.

[0039] The edge termination region has the function of maintaining a breakdown voltage by mitigating the electric field on the front surface side of the semiconductor substrate 30 in the drift layer 2 in the active region. The breakdown voltage is the limit voltage at which the leakage current does not increase excessively and the device does not malfunction or break down. The edge termination region contains breakdown voltage structures such as a field limiting ring (FLR) and a junction termination extension (JTE) structure.

[0040] The semiconductor substrate 30 is made of silicon carbide. + The semiconductor substrate 30 is formed by depositing epitaxial layers 32 to 34, which will become the drift layer 2, the n-type current diffusion region 3, and the p-type base region 4, in this order on the front surface of the starting substrate 31. The main surface of the semiconductor substrate 30 on the side of the p-type epitaxial layer 34 is the front surface, and the n + The main surface (n + The back surface of the starting substrate 31 is referred to as the back surface (second main surface). +The starting substrate 31 is n + The drift layer 2 (n-type epitaxial layer (first conductivity type epitaxial layer) 32) is connected to the p-type base region 4 and the n-type drain region 1. + Between the n-type drain region 1 + The gate electrode 1 contacts the drain region 1.

[0041] At least n + The surface region on the side of the n-type source region 5 (the front surface side of the semiconductor substrate 30) is the parallel pn layer 20. The parallel pn layer 20 has an SJ structure in which n-type regions (first conductivity type regions) 21 and p-type regions (second conductivity type regions) 22 are alternately and repeatedly arranged adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 30. + The portion between the first and second drain regions 1 may be an n-type buffer region 2a (an n-type region that does not have an SJ structure). The impurity concentration of the n-type buffer region 2a is equal to or lower than the impurity concentration of the n-type region 21 of the parallel pn layer 20.

[0042] The thickness Lsj of the parallel pn layer 20 is determined by the thickness of the p-type region 22 of the parallel pn layer 20. When the n-type buffer region 2a is provided, the p-type region 22 of the parallel pn layer 20 is located n-thicker than the n-type region 21 in the depth direction Z. + The p-type regions 22 may reach a deep position on the side of the p-type drain region 1 (the back surface side of the semiconductor substrate 30). In this case, an n-type region 22 is formed between adjacent p-type regions 22 of the parallel pn layer 20. + An n-type buffer region 2a extends a predetermined length from the side of the p-type drain region 1. The portions of the n-type buffer region 2a between the adjacent p-type regions 22 function as parallel pn layers 20.

[0043] The widths (widths in the first direction X) W of the n-type region 21 and the p-type region 22 of the parallel pn layer 20 n ,W pis approximately uniform in the depth direction Z. The impurity concentration of n-type region 21 of parallel pn layer 20 is approximately uniform in the depth direction Z. The impurity concentration of p-type region 22 of parallel pn layer 20 varies in the depth direction Z with the same impurity concentration distribution as the charge balance distribution between adjacent n-type region 21 and p-type region 22 of parallel pn layer 20. The effect of this embodiment can be further enhanced by making the impurity concentration of p-type region 22 higher than that of n-type region 21. The charge balance distribution between adjacent n-type region 21 and p-type region 22 of parallel pn layer 20 will be described later.

[0044] The charge balance is determined by the carrier concentration (impurity concentration) and the width W n The charge amount expressed by the product of the carrier concentration and width W of the p-type region 22 p The width and impurity concentration are approximately uniform, meaning that the width and impurity concentration are the same within the range including tolerances due to process variations. The carrier concentration and width W of the n-type region 21 and the p-type region 22 of the parallel pn layer 20 are n ,W p are set appropriately and may be approximately the same or different.

[0045] Although not shown, the parallel pn layer 20 may have a layout in which the n-type regions 21 and the p-type regions 22 extend in a stripe pattern in a second direction Y that is parallel to the front surface of the semiconductor substrate 30 and perpendicular to the first direction X, as viewed from the front surface side of the semiconductor substrate 30. Alternatively, the parallel pn layer 20 may have a layout in which the p-type regions 22 are arranged in a matrix pattern (dot pattern) and the n-type regions 21 are arranged in a lattice pattern surrounding the peripheries of the plurality of p-type regions 22, as viewed from the front surface side of the semiconductor substrate 30.

[0046] The trench gate structure has a p-type base region 4, an n + Type source region 5, p ++The p-type base region 4 is formed by the n-type contact region 6, the gate trench 7, the gate insulating film 8, and the gate electrode 9. The p-type base region 4 is provided between the front surface of the semiconductor substrate 30 and the drift layer 2. The p-type base region 4 is formed by the n-type epitaxial layer 34. + Type source region 5 and p ++ This is the area excluding the contact region 6. + Type source region 5 and p ++ The p-type contact regions 6 are selectively provided between the front surface of the semiconductor substrate 30 and the p-type base region 4, respectively.

[0047] n + Type source region 5 and p ++ The p-type contact region 6 is in contact with the p-type base region 4 and is exposed on the front surface of the semiconductor substrate 30. The exposure on the front surface of the semiconductor substrate 30 means that the n-type contact region 6 is exposed on the front surface of the semiconductor substrate 30. + Type source region 5 and p ++ The contact region 6 contacts a source electrode (first electrode) 14, which will be described later, on the front surface of the semiconductor substrate 30. ++ The p-type contact region 6 may not be provided. ++ Instead of the p-type contact region 6, the p-type base region 4 is exposed on the front surface of the semiconductor substrate 30.

[0048] Between the p-type base region 4 and the parallel pn layer 20 (drift layer 2), an n-type current diffusion region 3 and a p + The n-type regions 11 and 12 are selectively provided. The n-type current diffusion region 3 is formed by the p-type epitaxial layer 33. + This is the part excluding the mold regions 11 and 12. + The n-type regions 11 and 12 are diffusion regions formed by ion implantation inside the n-type epitaxial layer 33. The n-type current diffusion region 3 and the p + The n-type regions 11 and 12 are located closer to the bottom of the gate trench 7 than the n-type regions 11 and 12. + The trench reaches a deep position on the drain region 1 side.

[0049] The n-type current diffusion region 3 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The n-type current diffusion region 3 is formed between adjacent gate trenches 7. + The n-type current diffusion region 3 contacts the n-type regions 11 and 12, the p-type base region 4, and the n-type region 21 of the parallel p-n layer 20, and extends in the first direction X to reach the sidewall of the gate trench 7. The impurity concentration of the n-type current diffusion region 3 is equal to or higher than the impurity concentration of the n-type region 21 of the parallel p-n layer 20.

[0050] p + The gate regions 11 and 12 are electrically connected to the source electrode 14 and are depleted when the MOSFET is turned off, thereby reducing the electric field near the bottom of the gate trench 7. + The p-type region 11 is disposed apart from the p-type base region 4 and faces the bottom surface of the gate trench 7 in the depth direction Z. + The mold region 11 is p + It is connected to the mold region 12. + The n-type region 11 faces the n-type current diffusion region 3 in the depth direction Z. + The n-type region 11 may contact the n-type current diffusion region 3 in the depth direction Z.

[0051] p + The p-type region 12 is in contact with the p-type base region 4 between the adjacent gate trenches 7, and + The gate trench 7 is provided apart from the mold region 11. + The p-type region 12 faces the p-type region 22 in the depth direction Z. + The n-type region 12 may be in contact with the p-type region 22 facing the n-type region 12 in the depth direction Z. + The gate trenches 7 extend through the p-type source region 5 and the p-type base region 4 to reach the n-type current diffusion region 3. The gate trenches 7 extend in a stripe shape in a direction parallel to the front surface of the semiconductor substrate 30 (here, the second direction Y).

[0052] A gate electrode 9 is provided inside the gate trench 7 via a gate insulating film 8. The gate trench 7, gate insulating film 8, and gate electrode 9 constitute a MOS gate with a trench gate structure. An interlayer insulating film 13 is provided on the entire front surface of the semiconductor substrate 30 and covers the gate electrode 9. A source electrode 14 is provided in a contact hole of the interlayer insulating film 13, and is connected to the n + Type source region 5 and p ++ The drain electrode (second electrode) 15 is electrically connected to the contact region 6. The drain electrode (second electrode) 15 is provided on the entire back surface of the semiconductor substrate 30.

[0053] The charge balance distribution between the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20 will now be described. FIG. 2 is a cross-sectional view showing any adjacent n-type region and p-type region of the parallel pn layer of FIG. 1. FIG. 2 shows the width W in the first direction X of the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20. n ,W p The part between the centers (both the n-type region 21 and the p-type region 22) has a width W n ,W p 3 shows a half portion of the parallel pn layer shown in FIG. 2 (the same applies to FIG. 4 described later). FIG. 3 is a distribution diagram showing the charge balance distribution in the depth direction of the adjacent n-type region and p-type region of the parallel pn layer shown in FIG. 2.

[0054] The distribution of charge balance CB in Figure 3 applies to all adjacent n-type regions 21 and p-type regions 22 in parallel p-n layer 20. The horizontal axis of Figure 3 represents the depth [au (arbitrary unit)] from the front surface of semiconductor substrate 30. The vertical axis of Figure 3 represents the charge balance CB [%] between adjacent n-type regions 21 and p-type regions 22 in parallel p-n layer 20, with the charge balance CB on the plus (+) side in the p-rich range and the minus (-) side in the n-rich range. The conditions for charge balance CB, the horizontal axis, and the vertical axis in Figure 3 also apply to Figure 5, which will be described later.

[0055] The charge balance CB between the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20 is determined by dividing the n + The source region 5 side (the front surface side of the semiconductor substrate 30) is p-rich (positive value in FIG. 3), and the n + The n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20 are n-rich (negative values ​​in FIG. 3) at the center position Z0.

[0056] The charge amount of the p-type region 22 of the parallel pn layer 20 is determined as follows: + The charge amount of the p-type region 22 on the n-type source region 5 side is larger than that of the p-type region 22 under standard conditions. + The charge amount of the p-type region 22 on the drain region 1 side is less than that under standard conditions. "P-rich" means that the charge amount of the p-type region 22 is greater than that of the n-type region 21 at the portion adjacent to the n-type region 21. "N-rich" means that the charge amount of the n-type region 21 is greater than that of the p-type region 22 at the portion adjacent to the p-type region 22.

[0057] The standard condition is a condition of charge balance between the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20 that can obtain the highest breakdown voltage in design, and corresponds to the charge balance CB0 in FIG. 3. Specifically, the standard condition is, for example, a condition under which the charge balance (equilibrium) between the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20 is roughly maintained (see ( 1 The charge balance CB calculated by the formula is 0%, and ( 1 The charge balance CB calculated by the formula (1) may be an n-rich condition in which the charge balance CB is equal to or greater than -15% and less than 0%.

[0058] The parallel pn layer 20 may be under standard conditions in a predetermined thickness range 23 (hereinafter referred to as standard condition range) including the center position Z0 in the depth direction Z. The standard condition range 23 is thinner than the thickness Lsj of the parallel pn layer 20 and has a predetermined width L0 that is symmetrical in the depth direction Z with respect to the center position Z0. The standard condition range 23 is a range from the center position Z0 to the n + The distance from the center position Z0 to the end 23a on the side of the source region 5 and the distance from the center position Z0 to the end + The distance to the end 23b on the side of the type drain region 1 is approximately the same (1 / 2 of the width L0). "Approximately the same distance" means that the distance is the same within a range including tolerances due to process variations.

[0059] The charge balance CB between the adjacent n-type region 21 and p-type region 22 of the parallel pn layer 20 is adjusted by varying the impurity concentration of the p-type region 22 in a predetermined impurity concentration distribution in the depth direction Z. As described above, the widths W of the n-type region 21 and p-type region 22 of the parallel pn layer 20 are n ,W p is approximately uniform in the depth direction Z, and the impurity concentration of the n-type region 21 is approximately uniform in the depth direction Z, so the impurity concentration distribution of the p-type region 22 of the parallel pn layer 20 becomes the distribution of the charge balance CB between the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20.

[0060] For example, as will be described later, the parallel pn layer 20 is formed by epitaxially growing the n-type epitaxial layer 32, which will become the drift layer 2, in multiple stages (multiple times) and ion-implanting p-type impurities (second-conductivity-type impurities) into the n-type epitaxial layer of each stage (corresponding to n-type epitaxial layers (first-conductivity-type epitaxial layers) 49 to 41 in FIG. 6, which will be described later), so that a predetermined impurity concentration distribution of the p-type region 22 is formed in the depth direction Z, thereby selectively forming portions (second-conductivity-type diffusion regions) which will become the p-type region 22 with different impurity concentrations, and forming portions of the n-type epitaxial layer 32 which are not ion-implanted and remain n-type as the n-type region 21.

[0061] In this case, of the multiple epitaxial layers of approximately the same thickness epitaxially grown in multiple stages as the n-type epitaxial layer 32, at least the epitaxial layer in the middle stage (one stage if the total number of stages is odd, or two stages if the total number of stages is even) may be set to the standard condition range 23. To increase the width L0 of the standard condition range 23, the epitaxial layers adjacent to the upper and lower stages of the middle epitaxial layer may be set to the standard condition range 23 by the same number of stages. "Approximately the same thickness" means that the thickness is the same within a range that includes tolerances due to process variations.

[0062] Specifically, the charge balance CB [%] between the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20 is determined by the charge amount Q of the n-type region 21 of the parallel pn layer 20. n and the charge amount Q of the p-type region 22 p Based on the following ( 1 ) is calculated using the formula below ( 1 ) In the formula, N a ,W p are the carrier concentration (hole concentration) and the width in the first direction X of the p-type region 22 of the parallel pn layer 20, respectively. d ,W n are the carrier concentration (electron concentration) and the width in the first direction X of the n-type region of the parallel pn layer 20, respectively.

[0063]

number

[0064] the above( 1 ) formula, the charge balance CB [%] between the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20 is calculated based on the central position Z0 (or the n + The depth position Z3 of the end 23a on the source region 5 side is + It becomes a positive value on the type source region 5 side (p-rich range), and n + A predetermined first gradient D +(The amount of charge in the p-type region 22 is greater than the amount of charge in the p-type region 22 under the standard conditions).

[0065] the above( 1 ) formula, the charge balance CB [%] between the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20 is calculated based on the central position Z0 (or the n + The depth position Z4) of the end 23b on the side of the drain region 1 + The value is negative on the n-rich region of the drain region 1, and + A predetermined second gradient D - (The charge amount in the p-type region 22 is smaller than the charge amount in the p-type region 22 under the standard conditions).

[0066] The charge balance CB between the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20 is determined by the + The upper limit value (n of the parallel pn layer 20) on the side of the type source region 5 (p-rich range) + The positive value at the depth position Z1 of the end 20a on the source region 5 side is set to +160%, and the positive value at the depth position Z2 of the end 20a on the source region 5 side is set to +160%. + The lower limit (n of the parallel pn layer 20) on the side of the drain region 1 (n-rich range) + In the charge balance CB between the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20, the first gradient D of the p-rich range is preferably set to -30%. + The absolute value of the second gradient D of the n-rich range - It is desirable that the absolute value of |D + |>|D - |).

[0067] The first gradient D between the adjacent n-type region 21 and p-type region 22 of the parallel pn layer 20 + The charge balance CB (positive value) increases as the center position Z0 increases. +The second gradient D between the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20 may be increased linearly (FIG. 3) or may be increased stepwise (not shown). - The charge balance CB (negative value) decreases as the center position Z0 increases. + The thickness may decrease linearly toward the source / drain region 1 (FIG. 3) or may decrease stepwise (not shown).

[0068] In addition, in the charge balance CB between the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20, the first distance h1 from the center position Z0 (depth position Z3 in the case of the standard condition range 23) + Just n + A predetermined depth position Z5 on the mold source region 5 side + First charge balance CB1 in the p-rich range + and the first distance h1 from the center position Z0 (depth position Z4 when the standard condition range 23 is met). + The second distance h1 is approximately the same as - Just n + A predetermined depth position Z5 on the side of the mold drain region 1 - Second charge balance CB1 in the n-rich range - and the next ( 2 ) equation should be satisfied.

[0069]

number

[0070] Another example of a silicon carbide semiconductor device 10 according to an embodiment will now be described. Fig. 4 is a cross-sectional view showing another example of any mutually adjacent n-type region and p-type region of the parallel p-n layer of Fig. 1. Fig. 5 is a distribution diagram showing the charge balance distribution in the depth direction Z of the mutually adjacent n-type region and p-type region of the parallel p-n layer of Fig. 4. Fig. 5 shows the charge balance distribution in the depth direction Z of the mutually adjacent n-type region 21 and p-type region 22 of the parallel p-n layer 20 when the impurity concentration of the n-type buffer region 2a is lower than the impurity concentration of the n-type region 21 of the parallel p-n layer 20.

[0071] When the impurity concentration of the n-type buffer region 2a is substantially the same as the impurity concentration of the n-type region 21 of the parallel pn layer 20, the charge balance distribution in the depth direction Z between the adjacent n-type region 21 and p-type region 22 of the parallel pn layer 20 will be as shown in FIG. 3 above. "Substantially the same impurity concentration" means that the impurity concentrations are the same within a range that includes tolerances due to process variations. When the impurity concentration of the n-type buffer region 2a is lower than the impurity concentration of the n-type region 21 of the parallel pn layer 20, the charge balance distribution in the depth direction Z between the adjacent n-type region 21 and p-type region 22 of the parallel pn layer 20 will satisfy the following two differences in addition to the above-mentioned conditions.

[0072] The first difference is that the charge balance CB between the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20 is at a depth position Z6 - This is the most n-rich point. 1 ) formula, the charge balance CB [%] between the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20 is calculated from the center position Z0 (depth position Z4 in the case of the standard condition range 23) to + A predetermined second gradient D - At the depth position Z6 of the boundary 20c between the n-type buffer region 2a and the n-type region 21 of the parallel pn layer 20, - The minimum value is

[0073] The charge balance CB between the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20 may be constant in the depth direction Z in a portion 24 where the n-type buffer region 2a and the p-type region 22 of the parallel pn layer 20 are adjacent to each other in the first direction X (not shown). + A predetermined third gradient D buf The portion 24 where the n-type buffer region 2a and the p-type region 22 of the parallel pn layer 20 are adjacent to each other in the first direction X is a portion 24 at a depth position Z6 of the boundary 20c between the n-type buffer region 2a and the n-type region 21 of the parallel pn layer 20. - From the parallel pn layer 20,+ The end 20b of the n-type drain region 1 (the n-type buffer region 2a and the p-type region 22 of the parallel pn layer 20) Bottom of The n-rich range extends to the depth position Z2 (boundary with the

[0074] The second difference is that the charge balance CB between the n-type region 21 and the p-type region 22 adjacent to each other in the parallel pn layer 20 is as follows: 3 Specifically, in the n-rich range in the portion 24 where the n-type buffer region 2a and the p-type region 22 of the parallel pn layer 20 are adjacent to each other in the first direction X, there is a region at a predetermined depth position Z7 - 4th charge balance CB2 - The third gradient D buf The charge balance distribution of the thickness L of this portion 24 is formed. - Approximately the same thickness as L + Only the n of the parallel pn layer 20 + The depth position Z1 to n of the end 20a on the source region 5 side + Depth position Z6 on the side of the mold drain region 1 + Up to the p-rich range, at a predetermined depth position Z7 + Third charge balance CB2 + The first gradient D + A charge balance distribution of

[0075] In a portion 24 where the n-type buffer region 2 a and the p-type region 22 of the parallel pn layer 20 are adjacent to each other in the first direction X, + A predetermined fourth distance h2 from the depth position Z2 of the end 20b on the side of the drain region 1 - Just n + Depth position Z7 on the mold source region 5 side - The fourth charge balance CB2 - and n of the parallel pn layer 20 + A fourth distance h2 from the depth position Z1 of the end 20a on the source region 5 side - The third distance h2 is approximately the same as + Just n + Depth position Z7 on the side of the mold drain region 1 + The third ,1 Charge Balance CB2 +and the next ( 3 ) formula is satisfied. + ,Z5 + and the third charge balance CB2 + ,CB1 + The charge balance distribution is at depth position Z6 + The same first gradient D + and continues.

[0076]

number

[0077] From the center position Z0 (depth position Z3 in the case of the standard condition range 23), + A third distance h2 from the depth position Z1 of the end 20a on the source region 5 side + Just n + Depth position Z6 on the side of the mold drain region 1 + In the p-rich range up to the predetermined depth position Z5 as in Figure 3 + In the above ( 2 ) The first charge balance CB1 satisfies the formula + The first gradient D + The charge balance distribution is formed as follows: from the center position Z0 (depth position Z4 in the case of the standard condition range 23) to the depth position Z6 of the boundary 20c between the n-type buffer region 2a and the n-type region 21 of the parallel pn layer 20. - Up to the n-rich range, at a predetermined depth position Z5 - As in Figure 3, 2 ) The second charge balance CB1 satisfies the formula - The second gradient D - A charge balance distribution of

[0078] A method for manufacturing the silicon carbide semiconductor device 10 according to the embodiment will be described. Fig. 6 is a cross-sectional view showing a state during the manufacturing process of the silicon carbide semiconductor device according to the embodiment. First, n + n-type drain region 1 +Drift layer 2 including parallel pn layer 20 is formed on the front surface of starting substrate (semiconductor wafer) 31. At this time, a multi-stage epitaxial method is used to divide n-type epitaxial layer 32, which will become drift layer 2, into multiple stages and epitaxially grow the n-type epitaxial layer 32 in multiple stages. Each time the n-type epitaxial layer 32 is epitaxially grown, p-type impurities such as aluminum (Al) are ion-implanted into the n-type epitaxial layer 32, thereby selectively forming portions that will become p-type regions 22 of parallel pn layer 20.

[0079] The portions of the n-type epitaxial layer 32 that are not ion-implanted and remain n-type between adjacent p-type regions 22 become the n-type regions 21 of the parallel pn layer 20. FIG. 6 shows a case where the n-type epitaxial layer 32 that becomes the drift layer 2 is epitaxially grown in multiple stages, for example, divided into nine stages. + The n-type epitaxial layer 32 is provided with the parallel pn layer 20 and the n-type source region 5 side. + The entire area between the starting substrate 31 and the substrate 30 may be left as the n-type buffer region 2a without ion implantation. The following describes an example in which the n-type buffer region 2a is provided.

[0080] The lowest n-type epitaxial layer 49, which will become the n-type epitaxial layer 32, is formed with the impurity concentration and thickness Lbuf of the n-type buffer region 2a. P-type impurities such as aluminum are ion-implanted into the surface region of this n-type epitaxial layer 49 to selectively form portions that will become p-type regions 22. The portions that will become p-type regions 22 and the portions of the surface region of the n-type epitaxial layer 49 that remain n-type without being ion-implanted between the p-type regions 22 form the lowest portion SJ9 that constitutes the parallel pn layer 20. The portions of the n-type epitaxial layer 49 excluding the p-type regions 22 become n-type buffer regions 2a, and the n-type buffer regions 2a reach the surface of the n-type epitaxial layer 49 between adjacent p-type regions 22 in the lowest portion SJ9.

[0081] The remaining eight n-type epitaxial layers 48-41, which will become n-type epitaxial layer 32, are epitaxially grown in sequence on n-type epitaxial layer 49 at the impurity concentration of n-type region 21 of parallel pn layer 20. The total thickness of portion SJ9 and the eight n-type epitaxial layers 48-41 is thickness Lsj of parallel pn layer 20. In n-type epitaxial layers 48-41, p-type impurities such as aluminum are ion-implanted under different conditions to selectively form portions that will become p-type region 22, so that a predetermined impurity concentration distribution of p-type region 22 is formed in depth direction Z across n-type epitaxial layers 49-41 that are continuous in depth direction Z.

[0082] The portions of the n-type epitaxial layers 48-41 that are not ion-implanted and remain n-type between adjacent p-type regions 22 become n-type regions 21 of the parallel p-n layer 20. As a result, portions SJ8-SJ1 that constitute the parallel p-n layer 20 are formed in the eight stages of the n-type epitaxial layers 48-41. The impurity concentration of the p-type regions 22 of portions SJ9-SJ1 is adjusted so that the charge balance CB between the adjacent n-type regions 21 and p-type regions 22 of the parallel p-n layer 20 satisfies the above-mentioned condition (see FIG. 3 and the above ( 2 ) equation, or Figure 5 and the above ( 3 7 is a distribution diagram showing an example of charge balance distribution in the depth direction of the n-type region and p-type region adjacent to each other in the parallel pn layer of FIG.

[0083] FIG. 7 shows the results of a simulation of the charge balance CB between adjacent n-type region 21 and p-type region 22 of parallel pn layer 20 when the impurity concentration of n-type buffer region 2a is lower than the impurity concentration of n-type region 21 of parallel pn layer 20 (see FIG. 5) and when middle portion SJ5 is set to standard condition range 23 (hereinafter referred to as Example). For comparison, FIG. 7 also shows the charge balance distribution in the depth direction of adjacent n-type and p-type regions of the parallel pn layer of a conventional example. The conventional example differs from the Example in that the impurity concentration in the p-type region of the parallel pn layer is approximately uniform in the depth direction, there is no gradient in the charge balance distribution in the depth direction between adjacent n-type and p-type regions of the parallel pn layer, and all portions SJ are under standard conditions (conditions for charge balance CB0 in FIG. 3).

[0084] In this example, the portions SJ9 to SJ1 were formed to a thickness of 0.65 μm, and the thickness Lsj of the parallel pn layer 20 was set to 5.85 μm (=0.65 μm×9). The impurity concentrations of the n-type region 21 and the p-type region 22 of the parallel pn layer 20 under standard conditions were set to 3×10 16 / cm 3 and 6×10 16 / cm 3 That is, the impurity concentration of the n-type region 21 of the parallel pn layer 20 is uniformly set to 3×10 16 / cm 3 The impurity concentration of the p-type region 22 in the middle portion SJ5 in the standard condition range 23 is 6×10 16 / cm 3 The thickness Lbuf and impurity concentration of the n-type buffer region 2a are 4.4 μm and 1.8×10 16 / cm 3 It was decided.

[0085] In this embodiment, the breakdown voltage was set to 1200 V. In this case, as shown in FIG. 7, the charge balance CB between the adjacent n-type region 21 and p-type region 22 of parallel pn layer 20 can be achieved by adjusting the impurity concentration of p-type region 22 in portions SJ9 and SJ1. For example, the upper portions SJ1 and SJ2 can be approximately +150% p-rich, the lower portions SJ3 and SJ4 can be approximately +70% p-rich, the middle portion SJ5 can be set to standard conditions, the lower portions SJ6 and SJ7 can be approximately -30% n-rich, the lower portion SJ8 can be approximately -50% n-rich, and the lower portion SJ9 can be approximately -5% n-rich. The numbers "1" to "9" listed as the SJ stage numbers on the horizontal axis of FIG. 7 correspond to portions SJ1 to SJ9, respectively.

[0086] The width W of the n-type region 21 and the p-type region 22 of the parallel pn layer 20 n ,W p is uniform in the depth direction Z, and the impurity concentration of the n-type region 21 of the parallel pn layer 20 is uniform in the depth direction Z. Therefore, by adjusting the impurity concentration of the p-type region 22 of the portions SJ9 to SJ1, the charge balance CB between the n-type region 21 and the p-type region 22 adjacent to each other of the parallel pn layer 20 can be adjusted to be lower than that of the portion under standard conditions (portion SJ5). + The source region 5 side is p-rich, and the n + The first gradient D + and is larger than the part SJ5 + The n-rich region is located on the n-type drain region side. + The second gradient D - (See Figures 3 and 5.)

[0087] Next, an n-type epitaxial layer 33 that will become the n-type current diffusion region 3 is epitaxially grown on the n-type epitaxial layer 32 (on the portion SJ1). Next, p +The n-type regions 11 and 12 are selectively formed. The portion of the n-type epitaxial layer 33 that is not ion-implanted and remains n-type becomes the n-type current diffusion region 3. The n-type epitaxial layer 33 may be epitaxially grown with an impurity concentration lower than that of the n-type current diffusion region 3, and the n-type current diffusion region 3 may be formed in the n-type epitaxial layer 33 by ion implantation.

[0088] Next, a p-type epitaxial layer 34 that will become the p-type base region 4 is epitaxially grown on the n-type epitaxial layer 33. + A semiconductor substrate (semiconductor wafer) 30 is fabricated in which epitaxial layers 32 to 34 are stacked in order on a p-type starting substrate 31, and the epitaxial layer 32 includes a parallel pn layer 20. Next, n ions are implanted into the surface region of the p-type epitaxial layer 34. + Type source region 5 and p ++ The n-type contact region 6 is selectively formed on the p-type epitaxial layer 34. + Type source region 5 and p ++ The portion excluding the contact region 6 becomes the p-type base region 4 .

[0089] Next, a heat treatment (hereinafter referred to as activation annealing) is performed to activate the impurities ion-implanted into the epitaxial layers 32 to 34. Next, the semiconductor substrate 30 is + The p-type source region 5 and the p-type base region 4 are penetrated into the n-type current diffusion region 3. + A gate trench 7 is formed facing the mold region 11. Next, a gate insulating film 8, a gate electrode 9, an interlayer insulating film 13, a source electrode 14, and a drain electrode 15 are formed by a general method. Thereafter, the semiconductor wafer (semiconductor substrate 30) is diced (cut) into individual chips, thereby completing the silicon carbide semiconductor device 10 shown in FIGS. 1 to 3.

[0090] In the method for manufacturing silicon carbide semiconductor device 10 according to the embodiment described above, a trench-filling epitaxial method may be used instead of the multistage epitaxial method to form parallel pn layer 20. When the trench-filling epitaxial method is used, a trench (SJ trench) is formed in n-type epitaxial layer (first conductivity type epitaxial layer) 32 to leave a portion that will become n-type region 21, and this SJ trench is filled with a p-type epitaxial layer (second conductivity type epitaxial layer) that will become p-type region 22, thereby forming parallel pn layer 20.

[0091] The p-type region 22 embedded in the SJ trench can be made to have a predetermined impurity concentration distribution by appropriately changing the impurity concentration during epitaxial growth of the p-type epitaxial layer that will become the p-type region 22. When the impurity concentration of the n-type buffer region 2a is to be lower than the impurity concentration of the n-type region 21 of the parallel pn layer 20, an n-type epitaxial layer 32 having a two-layer structure including a portion (first semiconductor layer) that will become the n-type buffer region 2a and a portion (second semiconductor layer) that will become the n-type region 21 of the parallel pn layer 20 is formed, and an SJ trench that terminates inside the portion that will become the n-type buffer region 2a is formed.

[0092] As described above, according to the embodiment, the charge balance between the adjacent n-type and p-type regions of the parallel pn layer is determined by setting the depth position of 1 / 2 the thickness of the parallel pn layer as the center position, and setting the standard condition at this center position or a depth range of a predetermined width including the center position. + The source region side is p-rich and n + The first gradient increases toward the source region side, and the n + The drain region side is n-rich and n + The second gradient decreases toward the drain region side. This makes it possible to suppress a decrease in breakdown voltage due to a change in the width of the p-type region of the parallel pn layer, and to widen the process margin for dimensional deviations in the width of the p-type region of the parallel pn layer.

[0093] Furthermore, according to the embodiment, charge balance between the adjacent n-type and p-type regions of the parallel pn layer can be achieved by adjusting the impurity concentration distribution in the depth direction of the p-type region of the parallel pn layer. Therefore, to achieve a predetermined impurity concentration distribution in the depth direction of the p-type region of the parallel pn layer, the ion implantation conditions for forming the p-type region when forming the parallel pn layer using a multistage epitaxial method can be appropriately changed, or the growth conditions during epitaxial growth of the p-type epitaxial layer embedded in the SJ trench when forming the parallel pn layer using a trench-filling epitaxial method can be appropriately changed. Therefore, according to the embodiment, it is possible to easily apply the present invention to existing manufacturing lines.

[0094] (Experimental example) The width W of the p-type region 22 of the parallel pn layer 20 of the silicon carbide semiconductor device 10 according to the embodiment p The process margin of the above example was verified. FIG. 8 is a characteristic diagram showing the relationship between the breakdown voltage of the example and the width of the p-type region of the parallel pn layer. FIG. 9 is a characteristic diagram showing the relationship between the breakdown voltage of the conventional example and the width of the p-type region of the parallel pn layer. FIG. 10 is a characteristic diagram showing the relationship between the yield rate of the example and the conventional example and the width of the p-type region of the parallel pn layer. The breakdown voltage of the above example (see FIGS. 6 and 7) was verified by comparing the width W of the p-type region 22 of the parallel pn layer 20. p The results of the simulation performed multiple times under multiple different conditions are shown in Figure 8. The set breakdown voltage in this example was 1200V.

[0095] 8, the vertical axis represents breakdown voltage (BV), and the horizontal axis represents the width W of the p-type region 22 of the parallel pn layer 20. p Standard conditions (ΔW p =0%) and the ratio of increase / decrease from ΔW p (%) and "ΔW p = (Width W of p-type region 22 under simulation conditions) p -Width W of p-type region 22 under standard conditions p ) / Width W of the p-type region 22 under standard conditions p In Figure 8, ΔW p <0% and ΔW pIn the case of >0%, the width Wp of the p-type region 22 of the parallel pn layer 20 under the standard conditions is p When the width is narrowed and when the width is widened.

[0096] For comparison, the results of the breakdown voltage of the above-mentioned conventional example (see FIG. 7) are shown in FIG. 9. That is, FIG. 9 shows the case where the charge balance between the n-type region and the p-type region adjacent to each other in the parallel pn layer is uniform in the depth direction under standard conditions. Here, the standard conditions are as described above ( 1 The charge balance CB calculated by the formula ) was set to an n-rich condition of about -15%. The set withstand voltage and simulation conditions of the conventional example were the same as those of the example. The horizontal axis of FIG. 9 is ΔW p The horizontal axis (%) and vertical axis BV(V) are the same as the horizontal axis and vertical axis in Fig. 8. The results of simulating the yield rates of these examples and the conventional example are shown in Fig. 10.

[0097] From the results shown in FIGS. 8 and 9, in the example, the width W p The ratio of decrease from standard condition ΔW p It was confirmed that the decrease in breakdown voltage can be alleviated compared to the conventional example when the difference is in the range of -20% or more (compare the areas surrounded by the frames 51 and 52 in Figs. 8 and 9). + ,D - By adding p The decrease in breakdown voltage due to the change in the width W p It was confirmed that the process margin for dimensional deviation can be widened.

[0098] From the results shown in FIG. 10, in the example, the width W p The ratio of decrease from standard condition ΔW p It was confirmed that the yield rate could be increased to about 80% when the width W of the p-type region 22 of the parallel pn layer 20 was within the range of -20% to 10%. pThe ratio of decrease from standard condition ΔW p It was confirmed that even if the breakdown voltage BV was -30%, the yield rate could be more than doubled compared to conventional examples. Here, a product was considered to be good if the breakdown voltage BV was 1200V or higher and the drain-source current Idss was less than 1mA. The upper limit of the drain-source current Idss is the current value when the breakdown voltage is 1200V.

[0099] Even when the impurity concentration of the n-type buffer region 2a is approximately the same as the impurity concentration of the n-type region 21 of the parallel pn layer 20 (see FIG. 3), substantially the same results as in the example are obtained.

[0100] The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention is not limited to MOSFETs, and can be applied to MOS-type semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) in which the drift layer is a parallel pn layer. The present invention also applies when the conductivity types (n-type, p-type) are reversed. [Industrial Applicability]

[0101] As described above, the silicon carbide semiconductor device according to the present invention and a method for manufacturing a silicon carbide semiconductor device This is useful for power semiconductor devices with an SJ structure used in power converters and power supplies for various industrial machines, and is particularly suitable for forming the p-type region of a parallel pn layer by ion implantation when forming the parallel pn layer using a multi-stage epitaxial method. [Explanation of symbols]

[0102] 1n + Type drain region 2 Drift layer 2a n-type buffer region 3 n-type current diffusion region 4 p-type base region 5n + Type Source Area 6 p ++ Mold contact area 7 Gate Trench 8 Gate insulating film 9 Gate electrode 10 Silicon carbide semiconductor device 11,12 pages + type area 13 Interlayer insulating film 14 Source electrode 15 Drain electrode 20 parallel pn layers 20a Parallel pn layer n + End of the mold source region 20b Parallel pn layer n + End of mold drain region 20c Boundary between n-type buffer region and n-type region of parallel pn layer 21 n-type region of parallel pn layer 22 p-type region of parallel pn layer 23 Standard Condition Range 23a Standard Condition Range n + End of the mold source region 23b Standard Condition Range n + End of mold drain region 24 A portion where the n-type buffer region and the p-type region of the parallel pn layer are adjacent to each other in the first direction X 30 Semiconductor substrate 31n + Starting substrate 32, 33, 41-49 n-type epitaxial layer 34 p-type epitaxial layer D + ,D - ,D buf Charge balance gradient between adjacent n-type and p-type regions in a parallel pn layer h1 + ,h1 - ,h2 + ,h2 - Depth distance Lsj Parallel pn layer thickness Lbuf Thickness of n-type buffer region L0 Standard condition range width L + Thickness within a specified range L -The thickness of the portion where the n-type buffer region and the p-type region of the parallel pn layer are adjacent in the first direction X W n Width of the n-type region of the parallel pn layer W p Width of the p-type region of the parallel pn layer X: Direction parallel to the front surface of the semiconductor substrate (first direction) Y: A direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction (second direction) Z depth direction Z0: Depth position of 1 / 2 the thickness of the parallel pn layer Z1 n of parallel pn layer + Depth position of the end of the mold source region Z2 n of parallel pn layer + Depth position of the end of the mold drain region Z3 Standard condition range n + Depth position of the end of the mold source region Z4 Standard condition range n + Depth position of the end of the mold drain region Z5 + ,Z5 - ,Z6 + ,Z7 + ,Z7 - Predetermined depth position Z6 - Depth position of the boundary between the n-type buffer region and the n-type region of the parallel pn layer

Claims

1. a parallel pn layer provided inside a semiconductor substrate made of silicon carbide, in which first conductivity type regions and second conductivity type regions are alternately and repeatedly arranged in a first direction parallel to a first main surface of the semiconductor substrate; a predetermined element structure provided between the first major surface and the parallel pn layer; a first electrode provided on the first main surface and electrically connected to the element structure; a second electrode provided on a second main surface of the semiconductor substrate; Equipped with The charge balance between the first conductivity type region and the second conductivity type region adjacent to each other in the parallel pn layer is a standard condition that is uniform in the thickness direction within a depth range of a predetermined width that is symmetrical with respect to a depth position that is 1 / 2 of the thickness of the parallel pn layer, a charge amount of the second conductivity type region on the first main surface side of the portion under the standard conditions is larger than a charge amount of the first conductivity type region and is also larger than a charge amount of the second conductivity type region under the standard conditions, the amount of charge in the second conductivity type region increases relatively at a predetermined first gradient as the distance from the standard condition portion to the first main surface side increases, the charge amount of the first conductivity type region is greater than the charge amount of the second conductivity type region on the second main surface side than in the portion under the standard conditions, the amount of charge in the second conductivity type region on the second main surface side of the portion under the standard conditions is smaller than the amount of charge in the second conductivity type region under the standard conditions, a second conductivity type region having a second gradient of charge amount that decreases relatively with increasing distance from the standard condition portion toward the second main surface;

2. The silicon carbide semiconductor device according to claim 1 , wherein an absolute value of the first gradient is greater than an absolute value of the second gradient.

3. The charge balance is CB, and the carrier concentration, width, and charge amount of the first conductivity type region are N d , W n and Q n and the carrier concentration, width and charge amount of the second conductivity type region are N a , W p and Q p When this is done, the following equation (1) is satisfied:

3. The silicon carbide semiconductor device according to claim 1, wherein the charge balance has an upper limit of +160% on the first main surface side of the standard condition portion and a lower limit of −30% on the second main surface side of the standard condition portion. [Equation 1]

4. A first charge balance (CB1 + ) and a second charge balance (CB1 - 4. The silicon carbide semiconductor device according to claim 1, wherein ρ and ρ satisfy the following formula (2): [Equation 2]

5. 5. The silicon carbide semiconductor device according to claim 1, wherein the standard conditions are the charge balance conditions that provide the highest breakdown voltage.

6. the impurity concentration of the first conductivity type region is uniform in a depth direction; 6. The silicon carbide semiconductor device according to claim 1, wherein the second conductivity type region has an impurity concentration distribution that changes in a depth direction with the same gradient as the first gradient and the second gradient of the charge balance distribution.

7. a buffer region of a first conductivity type provided between the second main surface and the parallel pn layer and having an impurity concentration lower than that of the first conductivity type region; a boundary between the buffer region and the first conductivity type region is located at a depth closer to the first main surface than a boundary between the buffer region and a bottom surface of the second conductivity type region, 6. The silicon carbide semiconductor device according to claim 1, wherein the charge balance at the boundary between the buffer region and the first conductivity type region is at a minimum value.

8. 8. The silicon carbide semiconductor device according to claim 7, wherein the charge balance is uniform in a depth direction from a depth position of a boundary between the buffer region and the first conductivity type region to a depth position of a boundary between the buffer region and a bottom surface of the second conductivity type region.

9. 8. The silicon carbide semiconductor device according to claim 7, wherein the charge balance increases at a predetermined third gradient from a depth position of a boundary between the buffer region and the first conductivity type region to a depth position of a boundary between the buffer region and a bottom surface of the second conductivity type region toward the second main surface.

10. In a portion from a depth position of the boundary between the buffer region and the first conductivity type region to a depth position of the boundary between the buffer region and a bottom surface of the second conductivity type region, a fourth charge balance (CB2 - )and, A third charge balance (CB2 + 10. The silicon carbide semiconductor device according to claim 8, wherein Θ and Θ satisfy the following formula (3): [Equation 3]

11. the impurity concentration of the first conductivity type region is uniform in a depth direction; 9. The silicon carbide semiconductor device according to claim 8, wherein the second conductivity type region has an impurity concentration distribution that changes in a depth direction at gradients that are the same as the first gradient and the second gradient of the charge balance distribution, and that is uniform in the depth direction from a depth position of a boundary between the buffer region and the first conductivity type region to a depth position of a boundary between the buffer region and a bottom surface of the second conductivity type region.

12. the impurity concentration of the first conductivity type region is uniform in a depth direction; 10. The silicon carbide semiconductor device according to claim 9, wherein the second conductivity type region has an impurity concentration distribution that changes in a depth direction at gradients that are the same as the first gradient, the second gradient, and the third gradient of the charge balance distribution.

13. 13. The method for manufacturing a silicon carbide semiconductor device according to claim 11 or 12, a multi-stage epitaxial process in which a first conductivity type epitaxial layer is divided into multiple stages and epitaxially grown, and each time a second conductivity type impurity is ion-implanted into the first conductivity type epitaxial layer to form a second conductivity type diffusion region that becomes the second conductivity type region, and a portion of the first conductivity type epitaxial layer other than the second conductivity type diffusion region remains as the first conductivity type region, thereby forming the parallel pn layer; a second conductivity type diffusion region having a different impurity concentration by the ion implantation, in each of a plurality of the first conductivity type epitaxial layers that are epitaxially grown in multiple stages, and the second conductivity type region of the parallel pn layer has the impurity concentration distribution.

14. 14. The method for manufacturing a silicon carbide semiconductor device according to claim 13, wherein, in the multistage epitaxial step, a lowest layer of the plurality of first conductivity type epitaxial layers that are epitaxially grown in multiple stages is epitaxially grown with an impurity concentration of the buffer region, and a portion of the lowest layer excluding the second conductivity type diffusion region is left as the buffer region.

15. 13. The method for manufacturing a silicon carbide semiconductor device according to claim 11 or 12, a first step of epitaxially growing a first conductivity type epitaxial layer; a second step of forming a trench in the first conductivity type epitaxial layer to leave a portion of the first conductivity type epitaxial layer that will become the first conductivity type region; a third step of filling the trench with a second conductivity type epitaxial layer that becomes the second conductivity type region, thereby forming the parallel pn layer; the third step comprises changing an impurity concentration during epitaxial growth of the second conductivity type epitaxial layer, so that the second conductivity type region of the parallel pn layer has the impurity concentration distribution.

16. In the first step, a first semiconductor layer having an impurity concentration of the buffer region and a second semiconductor layer having an impurity concentration of the first conductivity type region are epitaxially grown in order to form the first conductivity type epitaxial layer; 16. The method for manufacturing a silicon carbide semiconductor device according to claim 15, wherein in the second step, the trench is formed terminating inside the first semiconductor layer, leaving portions of the first conductivity type epitaxial layer that will become the buffer region and the first conductivity type region.

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