Adaptive fast response LDO circuit and its chip

Abstract

We provide an adaptive, fast-response LDO circuit and its chip. The adaptive fast-response LDO circuit includes a bandgap reference circuit, an error amplifier, a power tube, a feedback resistor network, and an adaptive acceleration circuit. The current of the power tube is mirrored by the power tube's current adaptive acceleration circuit, which adaptively accelerates the charging and discharging of the differential circuit's tail current in the error amplifier based on the load fluctuations of the LDO circuit. Furthermore, before stabilizing the balance state of the LDO circuit, the unbalanced state of the two differential inputs of the error amplifier is utilized to rapidly charge and discharge the differential circuit's tail current and the gate of the power tube in a very short time, thereby significantly shortening the response time of the LDO circuit and improving the response speed of integrated circuit chips. Furthermore, the circuit meets the high performance requirements of electronic devices, such as on-time, switching time, and off-time.

Description

[Technical Field]

[0001] The present invention relates to an adaptive, fast-response low-dropout regulator (LDO) circuit in the field of analog integrated circuit technology, and to an integrated circuit chip including this LDO circuit. [Background technology]

[0002] With the development of communication technology, higher requirements are being placed on the performance of electronic devices, such as on-time, switching time, and off-time. Therefore, analog integrated circuits need to have faster response times, and power supply bias circuits that provide DC operating points for analog integrated circuits are of utmost importance. LDO circuits, as commonly used power supply bias circuits, are also facing urgent demands for shorter response times.

[0003] Chinese Invention Patent No. ZL201710905386.4 proposes a fast-response LDO circuit that uses a Class AB driver circuit to generate high-current drive with very low static power consumption, accelerating the establishment of the control end signal for the power tube and accelerating loop adjustment. Chinese Patent Application No. 201711004540.7 also proposes an LDO circuit that uses a transient response circuit to quickly respond to changes in output voltage and quickly adjust the drive voltage of the power device, improving the transient characteristics and AC accuracy of the LDO circuit. However, the drawback of these two LDO circuits is that increasing the number of circuit stages and feedback capacitance can affect the loop stability of the circuit and even degrade the performance of the original LDO circuit. Furthermore, the inability to quickly adjust the circuit in real time in response to load changes limits their application range. Summary of the Invention [Problem to be solved by the invention]

[0004] The main technical problem that the present invention aims to solve is to provide an adaptive, fast-response LDO circuit.

[0005] Another technical problem that the present invention aims to solve is to provide an integrated circuit chip including the above LDO circuit and a corresponding electronic terminal.

[0006] To achieve the above object, the present invention adopts the following technical solutions.

[0007] According to a first aspect of an embodiment of the present invention, there is provided an adaptive fast response LDO circuit including a bandgap reference circuit, an error amplifier, a power tube, a feedback resistor network, and an adaptive accelerated response circuit. The output terminal of the bandgap reference circuit is connected to the common input terminal of the error amplifier, the inverting input terminal of the error amplifier is connected to the feedback resistor network, and the output terminal of the error amplifier is connected to the gate of the power tube. The error amplifier and the power tube are each connected to the adaptive accelerated response circuit, and the drain of the power tube is connected to the feedback resistor network. The adaptive acceleration response circuit comprises an acceleration charging circuit, an adaptive acceleration charging / discharging circuit, and an acceleration discharging circuit, the acceleration charging circuit being connected to two current output terminals of a differential circuit inside the error amplifier and a tail current terminal of the differential circuit, the adaptive acceleration charging / discharging circuit being connected to the gate of the power tube and the tail current terminal of the differential circuit respectively, and the acceleration discharging circuit being connected to a first node, a second node, and the gate of the power tube respectively. The accelerated charging circuit includes a first NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, and a second NMOS tube, wherein the gate of the first NMOS tube is connected to a current output terminal corresponding to the reference voltage terminal of the differential circuit, the drain of the first NMOS tube is connected to the drain and gate of the first PMOS tube, respectively, the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the drain of the second PMOS tube is connected to the drain and gate of the third PMOS tube and the drain of the second NMOS tube, respectively, the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube, the drain of the fourth PMOS tube is connected to the tail current terminal of the differential circuit, and the gate of the second NMOS tube is connected to a current output terminal corresponding to the feedback terminal of the differential circuit.

[0010] Preferably, the first NMOS tube, the first PMOS tube, and the second PMOS tube mirror the current at the in-phase input terminal at a predetermined ratio to obtain a first current, and the second NMOS tube mirrors the current at the inverting input terminal at a predetermined ratio to obtain a second current. When the second current is greater than the first current, a first differential secondary current obtained from the difference between the second current and the first current is output to the third PMOS tube, and the first differential secondary current is mirrored by the fourth PMOS tube and then output to the differential circuit as a tail current.

[0011] Preferably, the accelerated charging circuit further includes a third NMOS tube, a fourth NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, and an eighth PMOS tube. The gate of the third NMOS tube is connected to a current output terminal corresponding to the reference voltage terminal of the differential circuit, and the drain of the third NMOS tube is connected to the drain of the sixth PMOS tube and the drain and gate of the seventh PMOS tube, respectively. The gate of the seventh PMOS tube is connected to the gate of the eighth PMOS tube, and the drain of the eighth PMOS tube is connected to the tail current terminal of the differential circuit. The gate of the fourth NMOS tube is connected to a current output terminal corresponding to the feedback terminal of the differential circuit, the drain of the fourth NMOS tube is connected to the drain and gate of the fifth PMOS tube, and the gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube.

[0012] Preferably, the third NMOS tube mirrors the current at the in-phase input terminal at a predetermined ratio to obtain a fifth current, and the fourth NMOS tube, the fifth PMOS tube, and the sixth PMOS tube mirror the current at the inverting input terminal at a predetermined ratio to obtain a sixth current. If the sixth current is greater than the fifth current, a second differential sub-current is obtained from the difference between the sixth current and the fifth current, and the second differential sub-current is output to the seventh PMOS tube. The second differential sub-current is mirrored by the eighth PMOS tube and then output to the differential circuit as a tail current.

[0013] Preferably, the adaptive acceleration charge / discharge circuit includes a ninth PMOS tube, the gate of which is connected to the gate of the power tube, and the drain of which is connected to the tail current end of the differential circuit.

[0014] Preferably, the accelerated discharge circuit comprises a fifth NMOS tube, a sixth NMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a twelfth PMOS tube, and a thirteenth PMOS tube. The gate of the fifth NMOS tube is connected to a first node, and the drain of the fifth NMOS tube is connected to the gate and drain of the tenth PMOS tube, respectively. The gate of the sixth NMOS tube is connected to a second node, and the drain of the sixth NMOS tube is connected to the drain of the eleventh PMOS tube and the gate and drain of the seventh NMOS tube, respectively. The gate of the eleventh PMOS tube is connected to the gate of the tenth PMOS tube, and the gate of the seventh NMOS tube is connected to the gate of the eighth NMOS tube. The drain of the eighth NMOS tube is connected to the gate and drain of the twelfth PMOS tube, respectively; the gate of the twelfth PMOS tube is connected to the gate of the thirteenth PMOS tube; and the drain of the thirteenth PMOS tube is connected to the gate of the power tube.

[0015] Preferably, the fifth NMOS tube, the tenth PMOS tube, and the eleventh PMOS tube mirror the current at the common-mode input terminal at a predetermined ratio to obtain a third current, and the sixth NMOS tube mirrors the current at the inverting input terminal at a predetermined ratio to obtain a fourth current. A second differential current obtained from the difference between the third current and the fourth current is output to the seventh NMOS tube, and the second differential current is mirrored by the seventh NMOS tube, the eighth NMOS tube, the twelfth PMOS tube, and the thirteenth PMOS tube before being output to the gate of the power tube.

[0016] Preferably, the adaptive acceleration response circuit obtains a first differential current and a second differential current based on the currents of the two differential input terminals inside the error amplifier, mirrors them at a predetermined ratio, and then accelerates discharging or charging by outputting them to the gate of the power tube and as the tail current of the differential circuit inside the error amplifier, where the first differential current is a first differential secondary current or a superposition of the first differential secondary current and the second differential secondary current.

[0017] Preferably, the adaptive acceleration response circuit mirrors the current of the power tube at a predetermined ratio, and then outputs the mirrored current as a tail current of the differential circuit. The LDO circuit Accelerate discharge or charge based on load changes.

[0018] According to a second aspect of an embodiment of the present invention, there is provided an integrated circuit chip including the adaptive fast response LDO circuit described above. [Effects of the Invention]

[0019] The adaptive fast-response LDO circuit provided by the present invention adds an adaptive acceleration circuit to a conventional LDO circuit. By mirroring the current of the power tube at a predetermined ratio, the circuit can adaptively accelerate the charging and discharging of the tail current of the differential circuit inside the error amplifier based on the load fluctuation of the LDO circuit. Furthermore, by taking advantage of the fact that the two differential inputs of the error amplifier are in an unbalanced state before the circuit balance stabilizes, the tail current of the differential circuit and the gate of the power tube can be rapidly charged and discharged in a very short time, significantly shortening the response time of the LDO circuit and improving the response speed of integrated circuit chips. Furthermore, the circuit meets the high performance requirements of electronic devices, such as on-time, switching time, and off-time. [Brief explanation of the drawings]

[0020] [Figure 1] 1 is a circuit diagram of an adaptive fast-response LDO circuit provided by the present invention. [Figure 2] 1 is a circuit diagram of an accelerated charging circuit in an adaptive fast response LDO circuit provided by the present invention. [Figure 3] 1 is a circuit diagram of an adaptive charge / discharge circuit in an adaptive fast-response LDO circuit provided by the present invention. [Figure 4] 1 is a circuit diagram of an accelerated discharge circuit in an adaptive fast-response LDO circuit provided by the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] The technical contents of the present invention will be described in more detail below with reference to the accompanying drawings and specific embodiments.

[0022] As shown in FIG. 1 , an embodiment of the present invention provides an adaptive fast-response LDO circuit 101, which includes a bandgap reference circuit 102, an error amplifier 201, a power tube 202, a feedback resistor network 203, and an adaptive acceleration response circuit 204, in order to shorten the response time of the LDO circuit, improve the fast response of the integrated circuit chip, and meet the high performance requirements of electronic devices, such as on-time, switching time, and off-time. The output terminal of the bandgap reference circuit 102 is connected to the common input terminal of the error amplifier 201, and the inverting input terminal of the error amplifier 201 is connected to the feedback resistor network 203. The output terminal of the error amplifier 201 is connected to the gate of the power tube 202, and the error amplifier 201 and the power tube 202 are respectively connected to the adaptive acceleration response circuit 204. The drain of the power tube 202 is connected to the feedback resistor network 203, thereby forming the output terminal of the adaptive fast-response LDO circuit 101 for connecting to the output load 103. A power supply voltage VDD is connected to the bandgap reference circuit 102, the error amplifier 201 and the power tube 202, and the feedback resistor network 203 is connected to ground.

[0023] Here, the basic structure of a typical LDO circuit is composed of a bandgap reference circuit 102, an error amplifier 201, a power tube 202, and a feedback resistor network 203. The bandgap reference circuit 102 generates a reference voltage Vref and a bias current, which are supplied as an input reference voltage to the error amplifier 201. The error amplifier 201, the power tube 202, and the feedback resistor network 203 form a negative feedback loop, which realizes voltage clamping. The feedback resistor network 203 is composed of resistors Rf1 and Rf2 connected in series.

[0024] The formula for the output voltage Vout of this typical LDO circuit is as follows:

number

[0025] In the above equation, (Rf1+Rf2) / Rf2 is the gain coefficient of the LDO circuit, and its magnitude is determined by the proportional relationship between the resistors Rf1 and Rf2, and the output voltage Vout is determined by both the reference voltage and the gain coefficient. It can be easily understood that the adaptive fast-response LDO circuit 101 provided in the embodiment of the present invention shortens the response time of the LDO circuit by adding the adaptive accelerated response circuit 204 to a general LDO circuit.

[0026] Before the adaptive fast-response LDO circuit stabilizes and reaches a balanced state, the adaptive accelerated response circuit 204 utilizes the imbalance between the two differential inputs of the error amplifier 201 to obtain a first differential current and a second differential current based on the currents at the two differential inputs. The first and second differential currents are then mirrored at a predetermined ratio and output as the gate and tail currents of the power tube 202 to the differential circuit to accelerate charging or discharging, thereby achieving an accelerated response of the LDO circuit. The current of the power tube 202 is also mirrored at a predetermined ratio and output as the tail current of the differential circuit to further improve the response speed of the circuit and accelerate charging or discharging based on load fluctuations.

[0027] Here, the two differential inputs are the in-phase input and the inverting input of error amplifier 201, respectively. As shown in FIG. 2, the gate of PMOS tube 10 in the differential circuit is connected to the output of bandgap reference circuit 102 and serves as the in-phase input of error amplifier 201 to receive reference voltage Vref. The drain of PMOS tube 10 in the differential circuit is connected to the drain of NMOS tube 30 to receive the current of PMOS tube 10. The gate of NMOS tube 30 serves as the current output corresponding to the reference voltage terminal of the differential circuit to output the current of PMOS tube 10. The gate of PMOS tube 20 in the differential circuit is connected to the inverting input of error amplifier 201 to connect feedback resistor network 203 and receive feedback voltage Vfdbk. The drain of PMOS tube 20 in the differential circuit is connected to the drain of NMOS tube 40 to receive the current at the gate of PMOS tube 20. The gate of NMOS tube 40 serves as the current output of the feedback terminal of the differential circuit to output the current of PMOS tube 20. The sources of the PMOS tube 10 and the PMOS tube 20 of the differential circuit are connected together as the tail current end of the differential circuit, and before the operating point of the LDO circuit stabilizes, the tail current end of the LDO circuit superimposes a first differential current supplied from the adaptive acceleration response circuit 204.

[0028] As shown in FIGS. 1 to 4, the adaptive accelerated response circuit includes an accelerated charging circuit 301, an adaptive accelerated charging / discharging circuit 302, and an accelerated discharging circuit 303. The accelerated charging circuit 301 is connected to two current output terminals (i.e., a current output terminal corresponding to a reference voltage terminal and a current output terminal corresponding to a feedback terminal) of a differential circuit inside the error amplifier 201 and its tail current terminal. The adaptive accelerated charging / discharging circuit 302 is connected to the gate of the power tube 202 and the tail current terminal of the differential circuit, respectively. The accelerated discharging circuit 303 is connected to a first node Vn1, a second node Vn2, and the gate of the power tube 202, respectively. Here, the first node Vn1 is connected to the drain of the PMOS tube 10 in the differential circuit to output the current of the PMOS tube 10. The second node Vn2 is connected to the drain of the PMOS tube 20 in the differential circuit to output the current of the PMOS tube 20.

[0029] Before the adaptive fast-response LDO circuit stabilizes and reaches a balanced state, the accelerated charging circuit 301 utilizes the unbalanced state of the two differential inputs of the error amplifier 201 to obtain a first differential current based on the current values ​​of the two differential inputs. After mirroring the first differential current at a predetermined ratio, the accelerated charging circuit 301 outputs the first differential current as a tail current corresponding to the differential circuit. The accelerated charging circuit 301 can adopt two structures. The first accelerated charging circuit 301 utilizes the unbalanced state of the two differential inputs of the error amplifier 201 to obtain a first differential secondary current based on the current values ​​of the two differential inputs. The second accelerated charging circuit 301 utilizes the unbalanced state of the two differential inputs of the error amplifier 201 to obtain a first differential secondary current and a second differential secondary current based on the current values ​​of the two differential inputs. Therefore, in one embodiment of the present invention, the accelerated charging circuit 301 can obtain a first differential secondary current corresponding to the current values ​​of the two differential inputs. Alternatively, in other embodiments of the present invention, the first differential current may be a superposition of the first differential secondary current and the second differential secondary current, where superposition does not mean an addition of currents but an effective superposition, i.e., the superposition of the function performed by the first differential secondary current with the function performed by the second differential secondary current.

[0030] 2, in one embodiment of the present invention, the accelerated charging circuit 301 includes a first NMOS tube 401, a first PMOS tube 402, a second PMOS tube 403, a third PMOS tube 404, a fourth PMOS tube 405, and a second NMOS tube 406. The gate of the first NMOS tube 401 is connected to a current output terminal (the gate of the NMOS tube 30) corresponding to the reference voltage terminal of the differential circuit inside the error amplifier 201, the drain of the first NMOS tube 401 is connected to the drain and gate of the first PMOS tube 402, respectively, and the gate of the first PMOS tube 402 is connected to the gate of the second PMOS tube 403. The drain of the second PMOS tube 403 is connected to the drain and gate of the third PMOS tube 404 and the drain of the second NMOS tube 406, respectively, and the gate of the third PMOS tube 404 is connected to the gate of the fourth PMOS tube 405. The drain of the fourth PMOS tube 405 is connected to the tail current terminal of the differential circuit, and the gate of the second NMOS tube 406 is connected to the current output terminal (the gate of the NMOS tube 40) corresponding to the feedback terminal of the differential circuit. The sources of the first PMOS tube 402, the second PMOS tube 403, the third PMOS tube 404, and the fourth PMOS tube 405 are connected to the power supply voltage VDD, and the sources of the first NMOS tube 401 and the second NMOS tube 406 are grounded.

[0031] The first NMOS tube 401 and the NMOS tube 30, and the first PMOS tube 402 and the second PMOS tube 403, respectively, form a current mirror circuit. The first NMOS tube 401 mirrors the current at the in-phase input terminal at a predetermined ratio and then transfers it to the first PMOS tube 402. The second PMOS tube 403 continues mirroring at a predetermined ratio to obtain a first current having a predetermined ratio with the current at the in-phase input terminal. The second NMOS tube 406 mirrors the current at the inverting input terminal at a predetermined ratio to obtain a second current. Before the adaptive fast-response LDO circuit 101 stabilizes and reaches a balanced state, the currents corresponding to the two differential input terminals are different, i.e., the current at the in-phase input terminal is different from the current at the inverting input terminal. When the second current is greater than the first current, the first differential current obtained by the difference between the second current and the first current is greater than zero, i.e., a first differential secondary current can be output to the third PMOS tube 404. When the second current is smaller than the first current, the first differential current is zero, and the current of the third PMOS tube 404 is zero. The first differential current output to the third PMOS tube 404 is mirrored at a predetermined ratio by the fourth PMOS tube 405 and then output to the differential circuit as a tail current. Therefore, when the two differential input terminals of the adaptive fast response LDO circuit 101 begin to establish a response in an unstable state (the currents corresponding to the two differential input terminals are different), the tail current has a large charging current, and the adaptive fast response LDO circuit 101 establishes a response in a very short time and completes a fast response from the unstable state to a stable state. Once the circuit reaches a stable balanced state, the voltages at the two differential inputs become equal or nearly equal, and the tail current of the differential circuit returns to its normal value. Therefore, after the adaptive fast-response LDO circuit 101 stabilizes, the tail current of the differential circuit returns to its balanced state value and no longer consumes current. Therefore, the accelerated charging circuit 301 only affects the circuit before it reaches a stable balanced state, and does not affect the circuit once it reaches a stable balanced state.

[0032] 2, in another embodiment of the present invention, the accelerated charging circuit 301 is configured by adding another accelerated charging circuit configured by a third NMOS tube 407, a fourth NMOS tube 408, a fifth PMOS tube 409, a sixth PMOS tube 410, a seventh PMOS tube 411, and an eighth PMOS tube 412 to the accelerated charging circuit configured by the MOS tubes 401 to 406. Here, the connections of the components of the added accelerated charging circuit are as follows: The gate of the third NMOS tube 407 is connected to the current output terminal (the gate of the NMOS tube 30) corresponding to the reference voltage terminal of the differential circuit inside the error amplifier 201, and the drain of the third NMOS tube 407 is connected to the drain of the sixth PMOS tube 410 and the drain and gate of the seventh PMOS tube 411, respectively. The gate of the seventh PMOS tube 411 is connected to the gate of the eighth PMOS tube 412, and the drain of the eighth PMOS tube 412 is connected to the tail current terminal of the differential circuit. The gate of the fourth NMOS tube 408 is connected to the current output terminal (the gate of NMOS tube 40) corresponding to the feedback terminal of the differential circuit, the drain of the fourth NMOS tube 408 is connected to the drain and gate of the fifth PMOS tube 409, and the gate of the fifth PMOS tube 409 is connected to the gate of the sixth PMOS tube 410. The sources of the fifth PMOS tube 409, the sixth PMOS tube 410, the seventh PMOS tube 411, and the eighth PMOS tube 412 are connected to the power supply voltage VDD, and the sources of the third NMOS tube 407 and the fourth NMOS tube 408 are grounded.

[0033] The accelerated charging circuit 301, consisting of MOS tubes 407-412, is essentially the same as the accelerated charging circuit 301 consisting of MOS tubes 401-406. As long as there is an imbalance between the two inputs of the differential circuit, the method of increasing the tail current to accelerate charging can be used to accelerate the response of the adaptive fast-response LDO circuit 101 and cover a wider range of application scenarios. Specifically, the third NMOS tube 407 mirrors the current at the in-phase input at a predetermined ratio to obtain a fifth current, while the fourth NMOS tube 408, the fifth PMOS tube 409, and the sixth PMOS tube 410 mirror the current at the inverting input at a predetermined ratio to obtain a sixth current. Before the adaptive fast-response LDO circuit 101 stabilizes and reaches a balanced state, the currents corresponding to the two differential inputs are different, i.e., the current at the in-phase input is different from the current at the inverting input. When the sixth current is greater than the fifth current, the second differential secondary current obtained from the difference between the sixth current and the fifth current is greater than 0, that is, the second differential secondary current can be output to the seventh PMOS tube 411. By mirroring this second differential secondary current through the eighth PMOS tube 412 and outputting it as a tail current to the differential circuit, the adaptive fast response LDO circuit 101 has a large charging current in the tail current when it begins to establish a response in an unstable state at the two differential input terminals (when the currents corresponding to the two differential input terminals are different). Furthermore, by establishing the adaptive fast response LDO circuit 101 in a very short time, it quickly transitions from an unstable state to a stable state. After the circuit reaches a stable balanced state, the voltages at the two differential input terminals become equal or nearly equal, and the tail current of the differential circuit returns to its normal value. Therefore, after the adaptive fast response LDO circuit 101 stabilizes, the tail current of the differential circuit returns to its balanced state value and no longer consumes current. Therefore, the accelerated charging circuit 301 only affects the circuit before it reaches a stable balanced state, and does not affect the circuit's stable balanced state.

[0034] 2 shows not only the structure of the accelerated charging circuit 301 but also the specific structure of the error amplifier 201. To make it easier to understand the principle of the accelerated charging circuit 301, only some of the MOS tubes are labeled. Those skilled in the art will understand that the other unlabeled MOS tubes also form part of the differential circuit inside the error amplifier.

[0035] 3, an adaptive accelerated charge / discharge circuit 302 is added to the accelerated charge circuit 301 and error amplifier 201 shown in FIG. 2. This adaptive accelerated charge / discharge circuit 302 includes a ninth PMOS tube 501. The gate of the ninth PMOS tube 501 is connected to the gate of the power tube 202, the drain of the ninth PMOS tube 501 is connected to the tail current end of the differential circuit, and the source of the ninth PMOS tube 501 is connected to the power supply voltage VDD.

[0036] The adaptive fast-response LDO circuit 101 further improves its response speed by adding a ninth PMOS tube 501 to increase the tail current of the differential circuit. When the adaptive fast-response LDO circuit 101 transitions from an unstable state to a stable state or from a stable state to another stable state, the load current changes, causing the current through the power tube 202 to change, and the current through the power tube becomes approximately equal to the load current. Therefore, the ninth PMOS tube 501 mirrors the current through the power tube 202 as the tail current of the differential circuit at a predetermined ratio, so that the tail current remains synchronized with load fluctuations. This allows the adaptive acceleration charge / discharge circuit 302 to adaptively adjust the magnitude of the tail current when the load changes, enabling self-adaptive charging and discharging. This allows the circuit to reach a stable state in a shorter time, achieving the goal of the adaptive fast-response LDO circuit 101 adaptively accelerating its response to load changes. Here, the magnitude of the current ratio of the ninth PMOS tube 501 mirroring the power tube 202 is adjusted based on the premise of meeting the power consumption, and the accelerated charging circuit and the accelerated discharging circuit are combined to make the circuit reach a stable state in a shorter time.

[0037] 4, an accelerated discharge circuit 303 is added to the adaptive accelerated charge / discharge circuit 302, the accelerated charge circuit 301, and the error amplifier 201 shown in FIG. The accelerated discharge circuit 303 includes a fifth NMOS tube 601, a sixth NMOS tube 602, a tenth PMOS tube 603, an eleventh PMOS tube 604, a seventh NMOS tube 605, an eighth NMOS tube 606, a twelfth PMOS tube 607, and a thirteenth PMOS tube 608. The gate of the fifth NMOS tube 601 is connected to the first node Vn1, and the drain of the fifth NMOS tube 601 is connected to the gate and drain of the tenth PMOS tube 603, respectively. The gate of the sixth NMOS tube 602 is connected to the second node Vn2, and the drain of the sixth NMOS tube 602 is connected to the drain of the eleventh PMOS tube 604 and the gate and drain of the seventh NMOS tube 605. The gate of the eleventh PMOS tube 604 is connected to the gate of the tenth PMOS tube 603, and the gate of the seventh NMOS tube 605 is connected to the gate of the eighth NMOS tube 606. The drain of the eighth NMOS tube 606 is connected to the gate and drain of the twelfth PMOS tube 607, and the gate of the twelfth PMOS tube 607 is connected to the gate of the thirteenth PMOS tube 608. The drain of the thirteenth PMOS tube 608 is connected to the gate of the power tube 202, and the sources of the tenth PMOS tube 603, the eleventh PMOS tube 604, the twelfth PMOS tube 607, and the thirteenth PMOS tube 608 are each connected to the power supply voltage VDD. The sources of the fifth NMOS tube 601, the sixth NMOS tube 602, the seventh NMOS tube 605, and the eighth NMOS tube 606 are each grounded.

[0038] The fifth NMOS tube 601, the tenth PMOS tube 603, and the eleventh PMOS tube 604 mirror the current at the common-mode input terminal at a predetermined ratio to obtain a third current. The sixth NMOS tube 602 mirrors the current at the inverting input terminal at a predetermined ratio to obtain a fourth current. Before the adaptive fast-response LDO circuit 101 stabilizes and reaches a balanced state, the currents at the two differential input terminals are different. A second differential current is obtained from the difference between the third current and the fourth current. The second differential current is output to the seventh NMOS tube 605, and is then mirrored at a predetermined ratio by the seventh NMOS tube 605, the eighth NMOS tube 606, the twelfth PMOS tube 607, and the thirteenth PMOS tube 608, before being output to the gate of the power tube 202. Therefore, adaptive fast response LDO circuit 101 accelerates the response of the circuit by controlling the gate of power tube 202 during the transition from high voltage to low voltage, thereby controlling the gate voltage of power tube 202 to accelerate charging in a very short time, allowing adaptive fast response LDO circuit 101 to quickly reach a stable state. Furthermore, once the circuit stabilizes and reaches a balanced state, the currents at the two differential input terminals return to their balanced state values ​​and no longer consume current. Therefore, accelerated discharge circuit 303 only affects the circuit before it stabilizes and reaches a balanced state, and does not affect the balanced state once the circuit has stabilized.

[0039] The current mirroring ratio between the accelerated charging circuit 301 and the accelerated discharging circuit 303 is determined based on the response speed actually required for the adaptive fast response LDO circuit 101, the size of the MOS tube in the differential circuit, and the magnitude of the current required for stable circuit operation. An optimal current mirroring ratio is selected to achieve an optimal response effect and prevent overshoot or insufficient acceleration response in the adaptive fast response LDO circuit 101.

[0040] The adaptive fast-response LDO circuit provided by the embodiment of the present invention can be used in an integrated circuit chip, and the specific structure of the LDO circuit in the integrated circuit chip will not be described in detail herein.

[0041] The adaptive fast-response LDO circuit provided by the embodiment of the present invention can also be used as an important component of an analog integrated circuit in electronic terminals, including mobile phones, laptops, tablet PCs, and in-vehicle PCs. The technical solution provided by the present invention can also be applied to other analog integrated circuit applications, such as communication base stations.

[0042] To summarize, the LDO circuit provided by the embodiment of the present invention adds an adaptive acceleration response circuit to an existing LDO circuit, on the one hand, realizing proportional mirroring of the current in the power tube and adaptively accelerating the charging and discharging of the tail current of the differential circuit inside the error amplifier based on the LDO load fluctuation. On the other hand, before the circuit reaches a stable balanced state, the unbalanced state of the two differential inputs of the error amplifier is used to charge and discharge the tail current of the differential circuit and the gate of the power tube in a very short time, thereby significantly shortening the response time of the LDO circuit and accelerating the response speed of the integrated circuit chip, thereby meeting the high performance requirements of electronic devices, such as on time, switching time, and off time.

[0043] The adaptive fast response LDO circuit and its chip provided by the embodiments of the present invention have been described in detail above. Any insubstantial modifications and substitutions made by those skilled in the art based on the present invention will fall within the scope of protection claimed by the present invention.

Claims

1. An adaptive fast response LDO circuit, comprising: a bandgap reference circuit, an error amplifier, a power tube, a feedback resistor network, and an adaptive accelerated response circuit; an output terminal of the bandgap reference circuit is connected to a common input terminal of the error amplifier, an inverting input terminal of the error amplifier is connected to the feedback resistor network, an output terminal of the error amplifier is connected to a gate of the power tube, the error amplifier and the power tube are each connected to the adaptive acceleration response circuit, and a drain of the power tube is connected to the feedback resistor network; the adaptive acceleration response circuit comprises an acceleration charging circuit, an adaptive acceleration charging / discharging circuit, and an acceleration discharging circuit; The acceleration charging circuit is connected to two current output terminals of a differential circuit in the error amplifier and a tail current terminal of the differential circuit, the adaptive acceleration charging / discharging circuit is connected to the gate of the power tube and the tail current terminal of the differential circuit respectively, and the acceleration discharging circuit is connected to a first node, a second node and the gate of the power tube respectively; the accelerated charging circuit comprises a first NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, and a second NMOS tube; an adaptive fast-response LDO circuit, characterized in that: the gate of the first NMOS tube is connected to a current output terminal corresponding to a reference voltage terminal of the differential circuit; the drain of the first NMOS tube is connected to the drain and gate of the first PMOS tube, respectively; the gate of the first PMOS tube is connected to the gate of the second PMOS tube; the drain of the second PMOS tube is connected to the drain and gate of the third PMOS tube and the drain of the second NMOS tube, respectively; the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube; the drain of the fourth PMOS tube is connected to a tail current terminal of the differential circuit; and the gate of the second NMOS tube is connected to a current output terminal corresponding to a feedback terminal of the differential circuit.

2. 2. The adaptive fast-response LDO circuit according to claim 1, wherein the first NMOS tube, the first PMOS tube, and the second PMOS tube mirror the current at the common-mode input terminal at a predetermined ratio to obtain a first current, the second NMOS tube mirrors the current at the inverting input terminal at a predetermined ratio to obtain a second current, and when the second current is greater than the first current, a first differential sub-current obtained from the difference between the second current and the first current is output to the third PMOS tube, and the first differential sub-current is mirrored by the fourth PMOS tube and then output to the differential circuit as a tail current.

3. the accelerated charging circuit further comprises a third NMOS tube, a fourth NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, and an eighth PMOS tube; 3. The adaptive fast-response LDO circuit according to claim 2, wherein the gate of the third NMOS tube is connected to the current output terminal corresponding to the reference voltage terminal of the differential circuit, the drain of the third NMOS tube is connected to the drain of the sixth PMOS tube, the drain and gate of the seventh PMOS tube, respectively, the gate of the seventh PMOS tube is connected to the gate of the eighth PMOS tube, the drain of the eighth PMOS tube is connected to the tail current terminal of the differential circuit, the gate of the fourth NMOS tube is connected to the current output terminal corresponding to the feedback terminal of the differential circuit, the drain of the fourth NMOS tube is connected to the drain and gate of the fifth PMOS tube, and the gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube.

4. 4. The adaptive fast-response LDO circuit according to claim 3, wherein the third NMOS tube mirrors the current at the common-mode input terminal at a predetermined ratio to obtain a fifth current; the fourth NMOS tube, the fifth PMOS tube, and the sixth PMOS tube mirror the current at the inverting input terminal at a predetermined ratio to obtain a sixth current; when the sixth current is greater than the fifth current, a second differential sub-current is obtained from the difference between the sixth current and the fifth current, and the second differential sub-current is output to the seventh PMOS tube; and the second differential sub-current is mirrored by the eighth PMOS tube and then output to the differential circuit as a tail current.

5. the adaptive accelerated charge / discharge circuit comprises a ninth PMOS tube; 5. The adaptive fast-response LDO circuit of claim 4, wherein the gate of the ninth PMOS tube is connected to the gate of the power tube, and the drain of the ninth PMOS tube is connected to the tail current end of the differential circuit.

6. the accelerated discharge circuit comprises a fifth NMOS tube, a sixth NMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a twelfth PMOS tube, and a thirteenth PMOS tube; 6. The adaptive fast-response LDO circuit of claim 5, wherein the gate of the fifth NMOS tube is connected to a first node, the drain of the fifth NMOS tube is connected to the gate and drain of the tenth PMOS tube, respectively, the gate of the sixth NMOS tube is connected to a second node, the drain of the sixth NMOS tube is connected to the drain of the eleventh PMOS tube, the gate and drain of the seventh NMOS tube, respectively, the gate of the eleventh PMOS tube is connected to the gate of the tenth PMOS tube, the gate of the seventh NMOS tube is connected to the gate of the eighth NMOS tube, the drain of the eighth NMOS tube is connected to the gate and drain of the twelfth PMOS tube, respectively, the gate of the twelfth PMOS tube is connected to the gate of the thirteenth PMOS tube, and the drain of the thirteenth PMOS tube is connected to the gate of the power tube.

7. 7. The adaptive fast-response LDO circuit according to claim 6, wherein the fifth NMOS tube, the tenth PMOS tube, and the eleventh PMOS tube mirror the current of the common-mode input terminal at a predetermined ratio to obtain a third current, the sixth NMOS tube mirrors the current of the inverting input terminal at a predetermined ratio to obtain a fourth current, and outputs a second differential current obtained from the difference between the third current and the fourth current to the seventh NMOS tube, and the second differential current is mirrored by the seventh NMOS tube, the eighth NMOS tube, the twelfth PMOS tube, and the thirteenth PMOS tube, and then output to the gate of the power tube.

8. The adaptive fast-response LDO circuit according to any one of claims 1 to 7, characterized in that the adaptive accelerated response circuit obtains a first differential current and a second differential current based on the currents of the two differential input terminals inside the error amplifier, mirrors them at a predetermined ratio, and then accelerates discharging or charging by outputting them to the gate of the power tube and outputting them as a tail current of the differential circuit inside the error amplifier, and the first differential current is a first differential sub-current or a superposition of the first differential sub-current and the second differential sub-current.

9. The adaptive fast response LDO circuit according to any one of claims 1 to 7, characterized in that the adaptive accelerated response circuit mirrors the current of the power tube at a predetermined ratio, and then accelerates discharging or charging based on load fluctuations of the LDO circuit as a tail current of a differential circuit inside the error amplifier.

10. An integrated circuit chip comprising the adaptive fast response LDO circuit according to any one of claims 1 to 9.

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