Semiconductor device manufacturing method and semiconductor device

Abstract

To improve the performance of semiconductor devices.SOLUTION: A source pad SE, which is connected to the source of the MOSFET of a semiconductor chip 10 and is positioned lower than a lead 30S in cross-sectional view, is electrically connected to a lead 30S for the source via a conductive member 50 bonded to the source pad SE and the wire (conductive member) 12 bonded to this conductive member 50.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a manufacturing technique for semiconductor devices, and relates to a technique that is effective when applied to, for example, power semiconductor devices incorporated in power control circuits. [Background technology]

[0002] Japanese Patent Application Laid-Open Publication No. 2018-73970 (Patent Document 1) describes a semiconductor device having a semiconductor chip equipped with a MOSFET, a die pad on which the semiconductor chip is mounted, a lead positioned higher than the die pad, and a wire electrically connecting the source pad of the semiconductor chip to the lead.

[0003] Furthermore, Japanese Patent Laid-Open Publication No. 2009-147103 (Patent Document 2) describes a semiconductor device in which aluminum ribbons are bonded to a plurality of locations on the source pad of a semiconductor chip using a wedge tool, which is a bonding tool. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-73970 [Patent Document 2] Japanese Patent Application Laid-Open No. 2009-147103 Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, there has been a demand for lower on-resistance (i.e., higher current) in semiconductor devices (especially the current path between the source pad and source lead, which serves as the output). To achieve low on-resistance, as in the above-mentioned patent documents, possible approaches include: 1) connecting the source pad and source lead via multiple conductive members; 2) increasing the diameter of the source conductive member connecting the source pad and source lead; or 3) connecting the source conductive member to the source pad at multiple locations. Furthermore, the inventors' investigations have found that the on-resistance can be further improved by adjusting the position at which the source conductive member is bonded to the source pad.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A method for manufacturing a semiconductor device according to one embodiment includes: (a) preparing a lead frame having a die pad and a first lead positioned above the die pad; (b) after step (a), mounting a semiconductor chip having a source pad electrically connected to a source of a MOSFET on the first surface of the die pad; (c) after step (b), bonding a first conductive member to the source pad using a first bonder; (d) after step (c), bonding a second conductive member to the first conductive member and the first lead using a second bonder; and (e) after step (d), encapsulating the semiconductor chip, the first conductive member, and the second conductive member with resin so that the second surface of the die pad is exposed. Here, the first bonder includes a cutter capable of cutting the first conductive member, a guide capable of feeding the first conductive member, and a wedge tool positioned adjacent to the cutter and capable of pressing the first conductive member. In the step (c), the first bonder is positioned so that the guide of the first bonder is positioned farther from the first lead than the wedge tool of the first bonder. The step (c) includes the steps of: (c1) bonding a first portion of the first conductive member to a first pad bonding portion of the source pad; and (c2) after the step (c1), bonding a second portion of the first conductive member to a second pad bonding portion of the source pad positioned farther from the first lead than the first pad bonding portion of the source pad. [Effects of the Invention]

[0008] According to the above embodiment, the performance of the semiconductor device can be improved. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is an explanatory diagram schematically illustrating an example of a circuit included in the semiconductor device according to the embodiment; [Figure 2]2 is a cross-sectional view of a main part showing an example of an element structure of the field effect transistor shown in FIG. 1. FIG. [Figure 3] FIG. 2 is a top view of the semiconductor device shown in FIG. [Figure 4] FIG. 4 is a bottom view of the semiconductor device shown in FIG. [Figure 5] 4 is a perspective plan view showing the internal structure of the semiconductor device with the sealing body shown in FIG. 3 removed. [Figure 6] FIG. 6 is a cross-sectional view taken along line AA in FIG. 5. [Figure 7] 7 is an enlarged cross-sectional view of the periphery of the connection portion between the source pad and the wire shown in FIG. 6. FIG. [Figure 8] FIG. 8 is an enlarged cross-sectional view showing a study example for FIG. 7. [Figure 9] FIG. 10 is an explanatory diagram schematically showing the planar positional relationship between a source pad and a plurality of connection portions; [Figure 10] FIG. 10 is an explanatory diagram showing a modified example of FIG. 9. [Figure 11] FIG. 11 is an explanatory diagram showing an outline of the manufacturing process of the semiconductor device described with reference to FIGS. 1 to 10. [Figure 12] 12 is an enlarged plan view showing a part of the lead frame prepared in the lead frame preparation step shown in FIG. [Figure 13] 13 is an enlarged plan view showing a state in which a semiconductor chip is mounted on the die pad shown in FIG. 12. [Figure 14] 14 is an enlarged plan view showing a state in which a conductive member is bonded onto a source pad of the semiconductor chip shown in FIG. 13. FIG. [Figure 15] 12 is an enlarged cross-sectional view showing a state in which a first ribbon is bonded to a first pad bonding portion of a source pad using a wedge bonder in the on-pad conductive member bonding step shown in FIG. 11. FIG. [Figure 16] FIG. 16 is an enlarged cross-sectional view showing the state in which the wedge bonder is moved from above the first pad bonding portion, following FIG. 15. [Figure 17] 17 is an enlarged cross-sectional view showing the state in which the first ribbon is bonded to the second pad bonding portion of the source pad, following FIG. 16. FIG. [Figure 18]FIG. 18 is an enlarged cross-sectional view showing the state in which the first ribbon is cut, following FIG. 17. [Figure 19] 10 is an enlarged cross-sectional view showing a state in which a second ribbon is bonded to a first ribbon joint portion of a first ribbon using a wedge bonder. FIG. [Figure 20] 19. FIG. 20 is an enlarged cross-sectional view showing the state in which the wedge bonder is moved from above the first ribbon joint portion, following FIG. [Figure 21] 21 is an enlarged cross-sectional view showing the state in which the second ribbon is joined to the second ribbon joint portion of the first ribbon, following FIG. 20. FIG. [Figure 22] 22 is an enlarged cross-sectional view showing the state in which the second ribbon is cut, following FIG. 21. FIG. [Figure 23] 10 is an enlarged cross-sectional view showing the state in which a third ribbon is bonded to a third ribbon joint portion of a second ribbon using a wedge bonder. FIG. [Figure 24] 24 is an enlarged cross-sectional view showing the state in which the wedge bonder is moved from above the third ribbon joint portion, following FIG. 23. FIG. [Figure 25] 25 is an enlarged cross-sectional view showing the state in which the third ribbon is joined to the fourth ribbon joint portion of the second ribbon, following FIG. 24. FIG. [Figure 26] FIG. 26 is an enlarged cross-sectional view showing the state in which the third ribbon is cut, following FIG. 25. [Figure 27] 14 is an enlarged plan view showing a state in which the semiconductor chip shown in FIG. 13 and leads are electrically connected via wires. FIG. [Figure 28] 12 is an enlarged cross-sectional view showing a state in which a wire is bonded to a fifth ribbon joint portion of a third ribbon using a wedge bonder in the ribbon bonding step shown in FIG. 11. FIG. [Figure 29] FIG. 29 is an enlarged cross-sectional view showing the state of joining the wire to the sixth ribbon joint portion of the third ribbon, following FIG. 28. [Figure 30] 30 is an enlarged cross-sectional view showing a state in which a wire is joined to a lead joining portion of a source lead, following FIG. 29. FIG. [Figure 31] FIG. 31 is an enlarged cross-sectional view showing the state in which the wire is cut, following FIG. 30. [Figure 32]28 is an enlarged plan view showing a state in which a sealing body that seals the semiconductor chip and wires shown in FIG. 27 has been formed. FIG. [Figure 33] 12 is an enlarged plan view showing a state in which a plurality of device forming portions have been separated from one another in the singulation step shown in FIG. 11. FIG. [Figure 34] 28, and is an enlarged cross-sectional view showing a state in which a wire is bonded to a lead bonding portion of a source lead using a wedge bonder in the ribbon bonding step shown in FIG. [Figure 35] FIG. 35 is an enlarged cross-sectional view showing the state of joining the wire to the sixth ribbon joint portion of the third ribbon, following FIG. 34. [Figure 36] FIG. 36 is an enlarged cross-sectional view showing the state of joining the wire to the fifth ribbon joint portion of the third ribbon, following FIG. 35. [Figure 37] FIG. 37 is an enlarged cross-sectional view showing the state in which the wire is cut, following FIG. 36. [Figure 38] FIG. 6 is an enlarged plan view showing a modification of FIG. 5. [Figure 39] FIG. 39 is an enlarged cross-sectional view taken along line CC in FIG. 38. [Figure 40] FIG. 6 is an enlarged plan view showing a modification of FIG. 5. [Figure 41] FIG. 41 is an enlarged cross-sectional view taken along line DD in FIG. 40. DETAILED DESCRIPTION OF THE INVENTION

[0010] (Explanation of the description format, basic terms and usage in this application) In this application, the description of the embodiments will be divided into multiple sections, etc., for convenience, as necessary. However, unless otherwise expressly stated, these are not mutually independent and separate, and regardless of the order of description, they are each part of a single example, one being a partial detail of the other, or a partial or complete modification, etc. Furthermore, as a general rule, repeated explanations of similar parts will be omitted. Furthermore, each component in the embodiments is not essential unless otherwise expressly stated, there is a theoretical limit to the number, or it is clearly not essential from the context.

[0011] Similarly, in the description of embodiments, when a material, composition, etc. is described as "X consisting of A," this does not exclude elements other than A, unless otherwise expressly stated or clearly indicated by the context. For example, when referring to a component, it means "X containing A as its primary component." For example, a "silicon component" does not necessarily refer to pure silicon, but also includes SiGe (silicon-germanium) alloys and other multi-component alloys containing silicon as the primary component, as well as components containing other additives. Furthermore, unless otherwise expressly stated, gold plating, Cu layer, nickel plating, etc., include not only pure components but also components containing gold, Cu, nickel, etc. as their primary components.

[0012] Furthermore, even when a specific number or quantity is mentioned, unless otherwise specified, unless it is theoretically limited to that number, or unless it is clearly not the case from the context, the number may be greater than that specific number or less than that specific number.

[0013] Furthermore, in each drawing of the embodiment, the same or similar parts are indicated by the same or similar symbols or reference numbers, and descriptions thereof will not be repeated in principle.

[0014] In the accompanying drawings, hatching may be omitted even in cross sections if it would be too complicated or if the distinction from voids is clear. In relation to this, background contour lines may be omitted even in the case of holes that are closed in plan view if it is clear from the description, etc. Furthermore, hatching or dot patterns may be added even in cases where the drawing is not a cross section to clearly indicate that the hole is not a void or to clearly indicate the boundary of the area.

[0015] In the following description, the terms "contact," "adhesion," "bonding," "peeling," and "connection" are used with the following meanings. "Contact" refers to a state in which at least a portion of two separable components (adherends) is in contact with each other. "Adhesion" refers to a state in which at least a portion of two separable components (adherends) is bonded and fixed to each other via an adhesive. "Bonding" refers to a state in which at least a portion of two separable components (adherends) is bonded and fixed to each other. The above-mentioned "bonding" includes mechanical bonding such as the anchor effect, bonding due to physical interactions such as intermolecular forces, and bonding due to chemical interactions such as covalent bonds. "Bonding" also includes cases in which another component (e.g., an adhesive) is interposed between the adherends, as well as cases in which no other component is interposed. In other words, a "bonded state" includes an "adhered state." "Peeling" refers to the release of the above-mentioned "bonded" state and the transition to a separable state. The simple term "peeling" includes cases in which the bond between two components is released across the entire bonded portion, as well as cases in which the bond is released across only a portion of the bonded portion. Furthermore, "connection" refers to a state in which two components are in communication (i.e., the connection path is not interrupted and is continuously connected). It does not matter whether another component is interposed between the two components. For example, "a state in which component A and component B are electrically connected" means that component A and component B are electrically conductive, and includes the case where component C is interposed between component A and component B. Similarly, "a state in which component A and component B are connected" simply means that component A and component B are fixed together, and includes the case where component C is interposed between component A and component B. Furthermore, "a state in which component A and component B are connected" also includes the case in which component A and component B are formed as an inseparable, integrated entity and are distinct in shape or function. In this way, the state in which component A and component B are formed as an integrated entity is sometimes referred to as "connection."

[0016] In the following description, the terms solder, solder material, solder ingredients, or solder components refer to, for example, Sn-Pb solder containing lead (Pb), or so-called lead-free solder, which is essentially free of Pb. Examples of lead-free solder include tin (Sn) only, tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), and tin-copper (Sn-Cu). Here, lead-free solder refers to solder containing 0.1 wt% or less of lead (Pb), a limit stipulated by the RoHS (Restriction of Hazardous Substances) Directive.

[0017] In this embodiment, as an example of a semiconductor device, a semiconductor device called a power device or a power semiconductor device that is incorporated into a power control circuit such as a power supply circuit will be described. The semiconductor device described below is incorporated into a power conversion circuit and functions as a switching element.

[0018] <Circuit configuration example> Fig. 1 is an explanatory diagram schematically illustrating an example of a circuit included in a semiconductor device according to the present embodiment, and Fig. 2 is a cross-sectional view of a main part illustrating an example of the element structure of the field-effect transistor shown in Fig. 1.

[0019] Semiconductor devices for power control, known as power semiconductor devices, include semiconductor elements such as diodes, thyristors, and transistors. Transistors are used in a variety of fields, but a transistor incorporated in a power control circuit through which a large current of, for example, 1 A (ampere) or more flows and operating as a switching element, as in the present embodiment, is called a power transistor. As shown in FIG. 1, the semiconductor device PKG1 of this embodiment has a semiconductor chip 10 on which a power transistor Q1 is formed. In the example shown in FIGS. 1 and 2, the transistor Q1 formed on the semiconductor chip 10 is a field-effect transistor, more specifically, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In power semiconductor devices, transistors are used, for example, as switching elements. A MOSFET used in a power semiconductor device is called a power MOSFET.

[0020] The term "MOSFET" is used above as a general term to refer to a field-effect transistor having a structure in which a gate electrode made of a conductive material is disposed on a gate insulating film. Therefore, the term "MOSFET" does not exclude gate insulating films other than oxide films. Furthermore, the term "MOSFET" does not exclude gate electrode materials other than metals, such as polysilicon.

[0021] 1 is formed of, for example, an n-channel field effect transistor as shown in Fig. 2. Fig. 2 is a cross-sectional view of a main part showing an example of the element structure of the field effect transistor shown in Fig. 1.

[0022] In the example shown in FIG. 2, for example, n-type single crystal silicon is formed on a main surface WHt of a semiconductor substrate WH. -An epitaxial layer EP is formed on the semiconductor substrate WH. The semiconductor substrate WH and the epitaxial layer EP form the drain region of the MOSFET (a region corresponding to the drain D shown in FIG. 1). This drain region is electrically connected to a drain electrode DE formed on the back side of the semiconductor chip 10.

[0023] On the epitaxial layer EP, p + A channel forming region CH, which is a semiconductor region of n type, is formed on the channel forming region CH. + A source region SR (a region corresponding to the source S shown in FIG. 1) is formed as a semiconductor region of a semiconductor type. The source region SR is electrically connected to a source pad (electrode, source electrode pad) SE formed on the main surface side of the semiconductor chip 10 via a lead-out wiring. In addition, a trench (opening, groove) TR1 is formed in the semiconductor region stacked on the semiconductor substrate WH, penetrating the channel formation region CH from the upper surface of the source region SR and reaching the inside of the epitaxial layer EP.

[0024] A gate insulating film GI is formed on the inner wall of the trench TR1. A gate G is formed on the gate insulating film GI so as to fill the trench TR1. The gate G is electrically connected to a gate pad (electrode, gate electrode pad) GE of the semiconductor chip 10 via a lead-out wiring.

[0025] Furthermore, in the transistor Q1, the drain region and the source region SR are arranged in the thickness direction, sandwiching the channel formation region CH, so that the channel is formed in the thickness direction (hereinafter referred to as a vertical channel structure). In this case, the area occupied by the element in a plan view can be reduced compared to a field effect transistor with a horizontal channel structure in which the channel is formed along the main surface WHt. This allows the planar size of the semiconductor chip 10 to be reduced.

[0026] Furthermore, in the case of the vertical channel structure described above, the channel width per unit area can be increased in a plan view, thereby reducing the on-resistance. Fig. 2 shows the element structure of a field-effect transistor, and in the semiconductor chip 10 shown in Fig. 1, multiple (many) transistors Q1 each having the element structure shown in Fig. 2 are connected in parallel. This allows the construction of a power MOSFET through which a large current, for example, exceeding 1 ampere, can flow.

[0027] As described above, when a MOSFET is configured by connecting multiple transistors Q1 with a vertical channel structure in parallel, the electrical characteristics of the MOSFET (mainly the breakdown voltage characteristics, on-resistance characteristics, and capacitance characteristics) change depending on the planar size of the semiconductor chip 10. For example, if the planar area of ​​the semiconductor chip 10 is increased, the number of cells (i.e., the number of elements) of the parallel-connected transistors Q1 increases, so the on-resistance decreases and the capacitance increases.

[0028] 1 and 2, a MOSFET is shown as an example of a power transistor included in the power semiconductor device, but various modifications are possible. For example, an insulated gate bipolar transistor (IGBT) may be provided instead of a MOSFET.

[0029] <Semiconductor device> Next, the package structure of the semiconductor device PKG1 shown in Fig. 1 will be described. Fig. 3 is a top view of the semiconductor device shown in Fig. 1. Fig. 4 is a bottom view of the semiconductor device shown in Fig. 3. Fig. 5 is a perspective plan view showing the internal structure of the semiconductor device with the sealing body shown in Fig. 3 removed. Fig. 6 is a cross-sectional view taken along line AA in Fig. 5.

[0030] The semiconductor device PKG1 of this embodiment has a semiconductor chip 10 (see FIGS. 5 and 6), a die pad (metal plate, chip mounting portion, heat sink) 20 (see FIGS. 3 to 6) on which the semiconductor chip 10 is mounted, and multiple leads (terminals) 30 which are external terminals. The semiconductor chip 10 and the multiple leads 30 are electrically connected via wires 12S and multiple wires (conductive members) 12 (see FIGS. 5 and 6). The semiconductor chip 10, an upper surface 20t of the die pad 20, and inner portions (inner lead portions, sealed portions) 30M of the multiple leads 30 (see FIGS. 5 and 6) are sealed with a sealing body (resin sealing body, resin body, mold resin) 40. Details of the wires 12S will be described later.

[0031] As shown in FIG. 5, in a plan view, each of the multiple leads 30 extends in the Y direction and is arranged alongside the die pad 20 along the Y direction. The multiple leads 30 are also arranged adjacent to one another along the X direction, which intersects with the Y direction (orthogonal in the example of FIG. 5). In the example shown in FIG. 5, multiple source leads (source leads, source terminals) 30S, drain leads (drain leads, drain terminals) 30D, and gate leads (gate leads, gate terminals) 30G are arranged in this order along the X direction in a plan view. Each of the multiple leads 30 includes an inner portion 30M sealed in the sealing body 40 and an outer portion (outer lead portion, exposed portion) 30X exposed from the sealing body 40. As shown in FIG. 6, each of the multiple leads 30 has an upper surface 30t and a lower surface 30b opposite the upper surface 30t.

[0032] Of the multiple leads 30, the drain lead 30D is formed integrally with the die pad 20. As will be described in detail later, in the manufacturing process of the semiconductor device PKG1, the drain lead 30D functions as a suspension lead that supports the die pad 20. The lead 30D as a suspension lead is bent so that the die pad 20 is positioned lower than the lead 30S in a cross-sectional view.

[0033] 6, the semiconductor chip 10 has a front surface (surface, upper surface) 10t and a back surface (surface, lower surface) 10b located opposite the front surface 10t. As shown in FIG. 5, the front surface 10t of the semiconductor chip 10 (and the back surface 10b shown in FIG. 6) is quadrangular in plan view and has four side surfaces 10s on its periphery. In the example shown in FIG. 5, the semiconductor chip 10 is rectangular in plan view, with its long sides extending along the X direction.

[0034] 5, a gate pad GE electrically connected to the gate G (see FIG. 1) and a source pad SE electrically connected to the source S (see FIG. 1) are formed on the front surface 10t of the semiconductor chip 10. As shown in FIG. 6, a drain electrode (electrode) DE electrically connected to the drain D (see FIG. 1) is formed on the back surface 10b of the semiconductor chip 10. In the example shown in FIG. 6, the entire back surface 10b of the semiconductor chip 10 serves as the drain electrode DE.

[0035] As shown in FIG. 2, when the semiconductor chip 10 has a vertical channel structure, the on-resistance can be reduced by reducing the thickness of the semiconductor chip 10 (reducing the distance between the front surface 10t and the back surface 10b shown in FIG. 6). On the other hand, from the viewpoint of increasing the heat capacity of the die pad 20 or increasing the cross-sectional area of ​​the conductive path through which current flows, a thicker thickness of the die pad 20 is preferable. For this reason, in the example shown in FIG. 6, the thickness of the die pad 20 is thicker than the thickness of the lead 30 (more specifically, the source lead 30S shown in FIG. 5). For example, the thickness of the lead 30 (the distance from the top surface 30t to the bottom surface 30b) is about 0.4 mm to 0.6 mm, and the thickness of the die pad 20 (the distance from the top surface 20t to the bottom surface 20b) is about 0.5 mm to 1.3 mm.

[0036] The semiconductor device PKG1 also has a die pad (metal plate, chip mounting portion, heat sink) 20 on which the semiconductor chip 10 is mounted. As shown in FIG. 6, the die pad 20 has an upper surface (face, main surface, front surface, chip mounting surface) 20t on which the semiconductor chip 10 is mounted via a die bond material 11, and a lower surface (face, main surface, back surface, exposed surface, mounting surface) 20b opposite the upper surface 20t. In the example shown in FIG. 5, the planar size of the semiconductor chip 10 (area of ​​the front surface 10t) is smaller than the planar size of the die pad 20 (area of ​​the upper surface 20t). As shown in FIG. 4, the die pad 20 has a plurality of side surfaces 20s on its periphery that are continuous with the lower surface 20b.

[0037] As shown in FIG. 5, the die pad 20 is integrally formed with a lead 30D, which is a drain terminal. The lead 30D is an external terminal electrically connected to the drain D shown in FIG. 1. As shown in FIG. 6, a drain electrode DE, which is connected to the drain D of a MOSFET transistor Q1 (see FIG. 1), is formed on the back surface 10b of the semiconductor chip 10. The drain electrode DE is electrically connected to the die pad 20 via a die bond material 11 made of a conductive material. The die bond material 11 is, for example, solder or a conductive resin that is a hardened mixture of conductive particles such as silver (Ag) particles and a resin. The lead 30D is connected to the die pad 20 and electrically connected to the drain electrode DE of the semiconductor chip 10 via the die pad 20 and the die bond material 11. The lead 30D is also connected (coupled) to the die pad 20 and functions as a suspension lead that supports the die pad 20 in the manufacturing process of the semiconductor device, which will be described later.

[0038] In this embodiment, since the lower surface 20b of the die pad 20 is exposed from the sealing body 40, the die pad 20 itself can be treated as a drain terminal. Also, in this embodiment, an embodiment using a MOSFET is taken up and explained as an example of a power transistor, so the lead 30 and die pad 20 operate as the drain terminal of the semiconductor device PKG1 on the circuit. However, as a modified example, if an IGBT is used as the power transistor, a collector electrode is formed on the back surface of the semiconductor chip. Therefore, if the power transistor is an IGBT, the lead 30 and die pad 20 operate as the collector terminal of the semiconductor device PKG1 on the circuit.

[0039] 5, the side surfaces 20s of the die pad 20 are provided facing the respective leads 30 in a plan view, and include side surfaces 20s1 sealed by the sealing body 40. The side surfaces 20s are also provided on the opposite side of the side surface 20s1, and include side surfaces 20s2 that are exposed from the sealing body 40 and are covered with the metal film 22 (see FIG. 6).

[0040] 4 and 6, the lower surface 20b of the die pad 20 is exposed from the sealing body 40 on the lower surface 40b side of the sealing body 40. In the example shown in FIG. 4, the area of ​​the lower surface 20b of the die pad 20 is equal to or larger than the area of ​​the lower surface 40b of the sealing body 40. As shown in FIG. 3, a portion of the die pad 20 protrudes outward from one of the side surfaces 40s of the sealing body 40 in a plan view seen from the upper surface 20t side of the die pad 20. As shown in FIGS. 3 and 6, a portion of the upper surface 20t of the die pad 20 and some of the side surfaces 20s (at least the side surface 20s2) are exposed from the sealing body 40. By increasing the planar size of the die pad 20 and exposing a portion of the die pad 20 from the sealing body 40 as in the present embodiment, the heat dissipation efficiency of the heat generated in the semiconductor chip 10 can be improved. Although not shown in the drawings, as a modification of the present embodiment, there is a case where the lower surface 20b of the die pad 20 is not exposed from the sealing body 40. In another modification, there is a case where only a part of the die pad 20 is exposed from the sealing body 40, and the other part is sealed in the sealing body 40.

[0041] The die pad 20 has a substrate 21 made of the same metal material as the plurality of leads 30, for example, copper (Cu) or an alloy material containing copper (Cu) as a main component. Each of the plurality of leads 30 has a substrate 31 made of the same metal material as the die pad 20, for example, copper (Cu) or an alloy material containing copper (Cu) as a main component.

[0042] Furthermore, the portion of the die pad 20 exposed from the sealing body 40 (outer portion, exposed portion) is covered with a metal film 22. Similarly, the portion of the lead 30 exposed from the sealing body 40 (outer portion 30X) is covered with a metal film 32. These metal films 22 and 32 are metal films for improving the wettability of a solder material used as a connecting material when mounting the semiconductor device PKG1 on a mounting board. The metal films 22 and 32 are, for example, plated metal films formed by electrolytic plating. As will be described in detail later, the metal films 22 and 32 are made of, for example, a solder material containing tin (Sn).

[0043] The die bond material (adhesive) 11 shown in FIGS. 5 and 6 is a conductive member (die bond material) that fixes the semiconductor chip 10 on the die pad 20 and electrically connects the semiconductor chip 10 and the die pad 20. The die bond material 11 may be, for example, a solder material. Alternatively, the die bond material 11 may be a conductive resin adhesive material called silver (Ag) paste, which contains a plurality of silver (Ag) particles (Ag filler). Although not shown, a metal film (not shown) that has stronger adhesion to the die bond material 11 than the copper (Cu) or copper alloy that is the base material of the die pad 20 may be formed on a portion of the upper surface 20t of the die pad 20. In this case, the adhesive strength between the die bond material 11 and the die pad 20 can be improved.

[0044] 5, the gate pad (gate electrode pad) GE of the semiconductor chip 10 and the lead 30G are electrically connected via a wire 12 (specifically, a wire (gate wire) 12G). Meanwhile, the source pad SE of the semiconductor chip 10 and the lead 30S are electrically connected via a wire 12 (specifically, a wire (source wire) 12S) and a wire 12S. The wire 12 is a conductive member (metal wire) that connects the electrode pad on the front surface 10t of the semiconductor chip 10 to the lead 30, and is mainly composed of, for example, aluminum (Al). There are various variations in the material of the wire 12, and for example, a metal material such as copper (Cu), silver (Ag), or gold (Au) may be used as the main component.

[0045] 5, one end of the wire 12G is bonded to the gate pad GE of the semiconductor chip 10. Meanwhile, the other end of the wire 12G opposite to the one end is bonded to the upper surface 30t of a lead bonding portion (lead post, bonding pad) 30W formed on a part of the lead 30G.

[0046] 5 and 6, a wire 12S is bonded onto the source pad SE. One end of the wire 12S is bonded to a wire 12S bonded onto the source pad SE of the semiconductor chip 10. The other end of the wire 12S opposite to the one end is bonded to an upper surface 30t of a lead bonding portion 30W formed on a part of the lead 30S.

[0047] In a power semiconductor device, a larger current flows through the wiring path (power supply path) connected to the source pad SE than through the wiring path (power supply path) connected to the gate pad GE. For this reason, in this embodiment, from the viewpoint of reducing the on-resistance in the power supply path including the source pad SE, a wire 12S is interposed between the wire 12 and the source pad SE. The reason why the on-resistance of the power supply path including the source pad SE can be reduced by providing the wire 12S will be described in detail later. Because the value of the current flowing through the power path connected to the gate pad GE is smaller than that of the power supply path including the source pad SE, the gate pad GE and the lead 30G are electrically connected without the wire 12S.

[0048] In the example shown in FIG. 5, the wire 12S is thicker than the wire 12G. The shape and number of the wires 12 are not limited to the embodiment shown in FIG. 5, and various modifications are possible. For example, the wires 12G and 12S may have the same thickness. In another example, the source pad SE and the lead 30S may be electrically connected via multiple wires 12S. In this embodiment, multiple wires 12S are connected to the source pad SE of the semiconductor chip 10.

[0049] The semiconductor chip 10, the leads 30, and the wires 12 are encapsulated by an encapsulant 40. The encapsulant 40 is a resin body that encapsulates the semiconductor chip 10, the wires 12S, and the wires 12. The encapsulant 40 has an upper surface 40t (see FIGS. 3 and 6) and a lower surface (mounting surface) 40b (see FIGS. 4 and 6) located opposite the upper surface 40t. As shown in FIGS. 3 and 4, each of the upper surface 40t (see FIG. 3) and the lower surface 40b (see FIG. 4) of the encapsulant 40 has a plurality of side surfaces 40s along its periphery. The encapsulant 40 is primarily made of a thermosetting resin, such as an epoxy resin. In this embodiment, filler particles, such as silica (silicon dioxide; SiO2) particles, are mixed into the resin material to improve the properties of the encapsulant 40 (e.g., thermal expansion properties). <Details of the connection between the wire and electrode pad> Next, the details of the portion where the electrode pad of the semiconductor chip and the wire are connected will be described. FIG. 7 is an enlarged cross-sectional view of the periphery of the connection portion between the source pad and the wire shown in FIG. 6. FIG. 8 is an enlarged cross-sectional view showing an example of consideration of FIG. 7. FIGS. 9 and 10 are explanatory diagrams schematically showing the planar positional relationship between the source pad and multiple connection portions. Note that while FIG. 9 does not show the wire 12S shown in FIG. 7, FIG. 9 corresponds to the positional relationship between the connection portion 12B1 and connection portion 12B2 of the wire 12S shown in FIG. 7 and the source pad SE. FIG. 10 corresponds to the positional relationship between the connection portion 12B1 and connection portion 12B2 of the wire 12S shown in FIG. 8 and the source pad SE.

[0050] First, the details of the part electrically connecting the electrode pad and the wire will be described using the model of wire connection shown in Fig. 8, which is an example of the study. The example shown in Fig. 8 differs from the example of this embodiment shown in Fig. 7 in that the wire 12 is directly connected to the source pad SE.

[0051] 8, an insulating film 13 is formed on the surface 10t of the semiconductor chip 10. The insulating film 13 is a protective film that protects the surface 10t side of the semiconductor chip 10. The insulating film 13 may be an organic film made of an organic material such as polyimide resin, or an inorganic insulating film made of silicon dioxide (SiO2), silicon nitride (SiN), or the like.

[0052] A plurality of openings are formed in the insulating film 13. Of the plurality of openings, Fig. 8 illustrates an opening 13H1 that exposes a portion of the source pad SE from the insulating film 13. The plurality of openings in the insulating film 13 includes an opening that exposes the gate pad GE shown in Fig. 5 in addition to the opening 13H1 shown in Fig. 8. In addition, as shown in Figs. 9 and 10, in this embodiment, the plurality of openings in the insulating film 13 (see Fig. 8) includes an opening 13H2 that exposes another portion of the source pad SE.

[0053] As shown in FIG. 8, in the opening 13H1, a bonding surface (exposed surface, bonding portion) SEt1, which is a portion of the source pad SE, is exposed from the insulating film 13. A wire (source wire) 12S is bonded to the bonding surface SEt1. The wire 12S has a connection portion (stitch portion, portion) 12B1 bonded to the bonding surface SEt1, a connection portion (stitch portion, portion) 12B2 bonded to the bonding surface SEt1, and a loop portion (portion) 12L1 located between the connection portions 12B1 and 12B2 in the Y direction in a plan view. Each of the connection portions 12B1 and 12B2 is ultrasonically bonded to an electrode pad of the semiconductor chip 10, and the lower surfaces of the connection portions 12B1 and 12B2 are bonded to the same bonding surface SEt1. The loop portion 12L1 is a portion that connects the connection portions 12B1 and 12B2 and is spaced apart from the bonding surface SEt1. The wire 12S also has a connection portion (joint portion, stitch portion) 12B3 that is joined to the lead joint portion 30W of the lead 30S shown in Fig. 5. The wire 12S also has a loop portion 12L2 that is located between the connection portion 12B2 and the connection portion 12B3 (see Fig. 5) shown in Fig. 7 and connects the connection portion 12B2 and the connection portion 12B3.

[0054] In the example shown in FIG. 8 , the wire 12 is bonded by a so-called forward bonding method, in which the connection portion with the source pad SE is the first bond and the connection portion with the lead 30 is the second bond. In this case, the distance of the loop portion 12L2 in the Y direction must be increased to prevent interference between the lead 30 and the guide for supplying the wire in the bonder used for wire bonding. As a result, as shown in FIG. 8 , the connection portions 12B1 and 12B2 are positioned far from the tip of the lead 30. Although not shown, a so-called reverse bonding method, in which the connection portion with the lead 30 is the first bond and the connection portion with the source pad SE is the second bond, can prevent interference between the guide and the lead 30, as described below. However, if the difference in elevation between the lead 30 and the source pad SE is large, it is necessary to prevent breakage of the wire 12 due to a steep inclination angle of the loop portion 12L2. Therefore, in the case of the reverse bonding method, the connection portions 12B1 and 12B2 are disposed at positions far from the tip of the lead 30, similar to the example shown in FIG.

[0055] If the reverse bonding method were used in the example shown in FIG. 8 and the second bond were located near the lead 30 on the source pad SE shown in FIG. 8, the inclination angle of the loop portion 12L2 would be steep. In this case, even if the wire does not break immediately after bonding, there is a risk of it breaking during the encapsulation process described below. Alternatively, even if the wire does not break during the encapsulation process, it may break due to continuous current application during continued use as a product. Therefore, if the wire 12 is directly bonded to the source pad SE as shown in FIG. 8, the connection portions 12B1 and 12B2 of the wire 12 are located far from the tip of the lead 30.

[0056] Here, the inventors of the present application have studied the preferable positional relationship between the wire connection portion and the source pad SE from the viewpoint of reducing the resistance (hereinafter referred to as the on-resistance) at the electrical connection portion between the wire 12 and the source pad SE. As a result of this study, the following has been found.

[0057] First, the on-resistance can be reduced by increasing the bonding area between the wire 12 and the source pad SE. In other words, the on-resistance can be reduced by increasing the number of connection portions 12B (see FIG. 9) of the wire 12 connected to the source pad SE. For example, if the bonding areas of the connection portions 12B with the source pad SE of each of the plurality of connection portions 12B shown in FIGS. 9 and 10 are the same, increasing the number of wires connected to one source pad SE increases the number of connection portions 12B, thereby reducing the on-resistance. Furthermore, as will be described later as a modified example, replacing the wire 12 with a ribbon, which is a band-shaped conductive member, is also an effective method from the viewpoint of reducing the on-resistance.

[0058] Second, assuming that the number of connection portions (size of junction area) is the same, the on-resistance can be reduced in proportion to the area of ​​the region connecting all of the connection portions. For example, in the example shown in FIG. 9, six connection portions 12B are provided along the periphery of the source pad SE. On the other hand, in the example shown in FIG. 10, the six connection portions 12B are collectively arranged in a portion (top side) of the source pad SE. The area of ​​the region RB1 connecting the outer edges of the six connection portions 12B shown in FIG. 9 is larger than the area of ​​the region RB2 connecting the outer edges of the six connection portions 12B shown in FIG. 10. According to the study by the present inventors, when the example shown in FIG. 9 is compared with the example shown in FIG. 10, it was found that the on-resistance of the example shown in FIG. 9 is lower. This is thought to be because the wide distribution of the connection portions 12B allows the entire source pad SE to be effectively used as a current path.

[0059] The source pad SE is, for example, rectangular and has a side SEs1 extending in a direction (X direction in FIG. 9) intersecting the arrangement direction of the connection portions 12B1 and 12B2 (Y direction in FIG. 9), and a side SEs2 located opposite to the side SEs1 and extending in the X direction. In this case, the following aspect is preferable from the viewpoint of reducing the on-resistance. That is, the distance D1 from the connection portion 12B1 to the side SEs1 is shorter than the distance (separation distance) D2 between the connection portion 12B1 and the connection portion 12B2, and the distance D3 from the connection portion 12B2 to the side SEs2 is shorter than the distance D2 between the connection portion 12B1 and the connection portion 12B2. In this case, the area of ​​the region RB1 connecting the multiple connection portions 12B can be increased, thereby reducing the on-resistance.

[0060] Based on the above-mentioned study results, the connection structure between the wire 12S and the source pad SE shown in FIG. 7 will be described below. The source pad SE included in the semiconductor device PKG1 is located below the lead 30S. In addition, in the case of the semiconductor device PKG1, the connection portion 12B1 and the connection portion 12B2 of the wire 12 are each bonded to a ribbon (strip-shaped conductive member) 53 constituting the conductive member 50 bonded on the source pad SE. The total thickness of the conductive member 50 (or the thickness of each of the ribbons 51 to 53 constituting the conductive member 50) can reduce the height difference between the lead bonding portion 30W of the lead 30 and the connection portion 12B2 of the wire 12S. Therefore, even if the wire 12S is connected using a forward bonding method in the lead bonding process described below, interference between the lead 30 and a bonder can be prevented. Furthermore, in the process of bonding the wire 12S to the source pad SE, interference between the lead 30 and a bonder for the wire 12S can be prevented by using a reverse bonding method, so the wire 12S can be arranged near the lead 30. As a result, as shown in FIG. 9, the area of ​​the region RB1 connecting the plurality of connecting portions 12B can be increased in plan view, and therefore the on-resistance can be reduced.

[0061] In FIG. 7, the conductive member 50 is made up of ribbons (strip-shaped conductive member) 51, ribbons (strip-shaped conductive member) 52, and ribbons (strip-shaped conductive member) 53, which are conductive and stacked on the source pad SE. However, there are various variations in the number and thickness of the ribbons that make up the conductive member 50. For example, if one ribbon 51 can avoid interference between a bonder and a lead in the lead bonding process, the wire 12S may be made up of one ribbon 51. Furthermore, depending on the height difference between the lead bonding portion 30W of the lead 30 and the source pad SE, the conductive member 50 may be made up of two ribbons or four or more ribbons.

[0062] <Method of manufacturing a semiconductor device> Next, a manufacturing process of the semiconductor device PKG1 explained using Figures 1 to 10 will be described. The semiconductor device PKG1 is manufactured according to the flow shown in Figure 11. Figure 11 is an explanatory diagram showing an outline of the manufacturing process of the semiconductor device explained using Figures 1 to 10. In the following explanation, when explaining the components of the semiconductor device PKG1, reference may be made to Figures 1 to 10 which have already been explained, as necessary.

[0063] <Semiconductor chip preparation process> 11, the semiconductor chip 10 described with reference to Fig. 5 and Fig. 6 is prepared. As already described with reference to Fig. 2 etc., the semiconductor chip 10 has a MOSFET (transistor Q1 shown in Figs. 1 and 2) and a source pad SE electrically connected to the source of the MOSFET (source region SR shown in Fig. 2).

[0064] The semiconductor chip 10 prepared in this step has a surface 10t on which an insulating film 13 (see FIGS. 7 and 9) and a source pad (electrode) SE partially exposed from the insulating film 13 are formed. The source pad SE has a bonding surface SEt1 (see FIG. 9) exposed from the insulating film 13 at an opening 13H1 (see FIG. 9) formed in the insulating film 13, and a bonding surface SEt2 (see FIG. 9) exposed from the insulating film 13 at an opening 13H2 (see FIG. 9) formed in the insulating film 13.

[0065] 5, a gate pad (electrode) GE is formed on the front surface 10t of the semiconductor chip 10. The gate pad GE has a bonding surface (bonding surface GEt in FIG. 13, which will be described later) exposed from the insulating film 13 (see FIG. 7) at an opening (opening 13H3 in FIG. 13, which will be described later) formed in the insulating film. As shown in FIG. 6, the semiconductor chip 10 has a back surface 10b on the opposite side of the front surface 10t. A drain electrode (electrode) DE, which is electrically connected to the drain D (see FIG. 1), is formed on the back surface 10b of the semiconductor chip 10. In the example shown in FIG. 6, the entire back surface 10b of the semiconductor chip 10 serves as the drain electrode DE.

[0066] The semiconductor chip 10 is manufactured, for example, as follows: For example, an n-type monocrystalline silicon is formed on a main surface WHt (see FIG. 2) of a semiconductor substrate WH (see FIG. 2). -A semiconductor wafer (not shown) having a mold epitaxial layer EP formed thereon is prepared, and multiple transistors Q1 are formed on the epitaxial layer EP. The semiconductor wafer includes multiple chip regions, and multiple transistors Q1 are formed in each of the multiple chip regions. A source pad SE and a gate pad GE are also formed on the transistor Q1. The source pad SE is connected to multiple source regions SR, and the gate pad GE is connected to multiple gates (gate electrodes) G. Next, an insulating film 13 (see FIG. 7) is formed to entirely cover the source pad SE and the gate pad GE. After that, openings 13H1 (see FIG. 9) and 13H2 (see FIG. 9), and a gate pad opening (opening 13H3 in FIG. 13, which will be described later) are formed in the insulating film 13, exposing a portion of the source pad SE (bonding surfaces SEt1 and SEt2) and a portion of the gate pad GE (bonding surface GEt in FIG. 13, which will be described later) from the insulating film 13. After that, necessary tests (wafer tests), such as electrical tests on the circuits, are performed, and the wafer is then divided into multiple semiconductor chips 10. 6, when a metal film is formed on the back surface 10b as the drain electrode DE, the metal film used as the drain electrode DE is formed at any timing between the step of preparing the semiconductor wafer and the step of dividing the semiconductor wafer. When a metal film is not used as the drain electrode DE, this step can be omitted.

[0067] <Lead frame preparation process> 11, a lead frame LF shown in Fig. 12 is prepared. Fig. 12 is an enlarged plan view showing a part of the lead frame prepared in the lead frame preparation step shown in Fig. 11.

[0068] As shown in FIG. 12, the lead frame LF prepared in this step has a device forming portion LFd connected to a frame portion (frame portion) LFf. One device forming portion LFd corresponds to one semiconductor device PKG1 shown in FIG. 5. Although FIG. 12 shows one device forming portion LFd, the lead frame LF has a plurality of device forming portions LFd connected via the frame portion LFf. In this way, by using a lead frame LF having a plurality of device forming portions LFd, a plurality of semiconductor devices PKG1 (see FIG. 3) can be manufactured collectively, thereby improving manufacturing efficiency.

[0069] The lead frame LF is made of a metal material whose main component is, for example, copper (Cu). Each of the device formation portions LFd is connected to a frame portion LFf. The frame portion LFf is a support portion that supports each member formed in the device formation portion LFd until the lead separation step shown in FIG. 11. In this embodiment, for example, the thickness of the lead 30 (the distance from the upper surface 30t to the lower surface 30b) is about 0.4 mm to 0.6 mm, and the thickness of the die pad 20 (the distance from the upper surface 20t to the lower surface 20b) is about 0.5 mm to 1.3 mm.

[0070] 12, a die pad 20 and a plurality of leads 30 are formed in the device formation portion LFd. The die pad 20 is connected to the frame portion LFf via a lead 30D, which functions as a suspension lead, among the plurality of leads 30, and is supported by the frame portion LFf. The die pad 20 also has an upper surface 20t, which is a chip mounting surface.

[0071] The leads 30 are each connected to a frame portion LFf and supported by the frame portion LFf. The leads 30 extend along the Y direction and are arranged side by side so as to be adjacent to one another in the X direction. The leads 30 are each connected to one another via tie bars LFt.

[0072] The multiple leads 30 include multiple leads 30S that are source leads. The multiple leads 30S are arranged adjacent to each other in the X direction and are connected to lead joints 30W. The multiple leads 30 also include lead 30G that is a gate lead. A lead joint 30W is provided at the tip of lead 30G that faces the die pad 20. The multiple leads 30 also include lead 30D that is a drain lead. Lead 30D is located between leads 30G and 30S in the X direction, and its tip on the die pad 20 side in the Y direction is connected to the die pad 20.

[0073] In this embodiment, the upper surface 20t of the die pad 20 is located at a different height from the upper surfaces 30t of the lead bonding portions 30W of the leads 30. The leads 30D, which serve as suspension leads supporting the die pad 20, and the portions connecting the die pad 20 to the frame portion LFf are bent, offsetting the die pad 20. In this embodiment, the die pad 20 is set down relative to the other components of the lead frame LF. Therefore, as shown in FIG. 6, the upper surface 20t of the die pad 20 is located below the upper surfaces 30t of the leads 30S. In other words, the leads 30D, which serve as suspension leads, have bent portions 30BD that are bent so that the die pad 20 is located below the leads 30S in a cross-sectional view. By setting the die pad 20 down in this manner, the lower surface 20b of the die pad 20 is exposed from the sealing body 40, as shown in FIG. 6.

[0074] <Semiconductor chip mounting process> Next, in the semiconductor chip mounting step shown in Fig. 11, the semiconductor chip 10 is mounted on the die pad 20 of the lead frame LF as shown in Fig. 13. Fig. 13 is an enlarged plan view showing the state in which the semiconductor chip is mounted on the die pad shown in Fig. 12.

[0075] In this process, the semiconductor chip 10 is mounted (adhesively fixed) on the upper surface 20t of the die pad 20 via the die bond material 11. The semiconductor chip 10 is also adhesively fixed via the die bond material 11 so that the back surface 10b (see FIG. 6) on which the drain electrode DE (see FIG. 6) is formed faces the upper surface 20t, which is the chip mounting surface of the die pad 20. As a result, the drain electrode DE of the semiconductor chip 10 is electrically connected to the die pad 20 via the die bond material 11, which is a conductive connecting material.

[0076] In this step, after the die bond material 11 is applied onto the upper surface 20t of the die pad 20, the semiconductor chip 10 is placed on the die bond material 11. Then, the semiconductor chip 10 and the die pad 20 are fixed together by hardening the die bond material.

[0077] The die bond material 11 may be, for example, a solder material. Alternatively, the die bond material 11 may be a conductive resin adhesive material called silver (Ag) paste, which contains a plurality of silver (Ag) particles (Ag filler). When the die bond material 11 is a solder material, a reflow process is performed as a method for hardening the die bond material. When the die bond material 11 is a conductive resin adhesive material, a thermosetting resin component contained in the die bond material 11 is heated to harden it.

[0078] <Process for bonding conductive material on pad> Next, in the pad conductive member bonding step shown in FIG. 11, FIG. 14 is an enlarged plan view showing a state in which a conductive member has been bonded onto the source pad of the semiconductor chip shown in FIG. 13. As described above, the source pad SE is located below the leads 30 (more specifically, the source leads 30S) in a cross-sectional view. In this embodiment, a step of bonding wires 12S onto the source pad SE is included to reduce the height difference between the leads 30 and the source pad SE of the semiconductor chip 10. Details of the step of bonding wires 12S will be described below. As described above, this embodiment will be described with reference to an embodiment in which ribbons 51, 52, and 53, which are strip-shaped conductive members, are bonded as wires 12S, but there are various variations in the number of strip-shaped conductive members stacked.

[0079] 15 to 26 are enlarged cross-sectional views showing, for each step, the state of bonding a conductive member using a wedge bonder in the pad conductive member bonding step shown in FIG. 11. In this step, the bonding step is performed using a bonder (wedge bonder) 70 shown in FIGS. 15 to 26. When the source pad SE has two bonding surfaces, bonding surface SEt1 and bonding surface SEt2, as in the example shown in FIG. 14, the process described below is performed on each of bonding surface SEt1 and bonding surface SEt2. In the following description, the step of bonding a wire 12S onto bonding surface SEt1 will be described as a representative example.

[0080] The bonder 70 includes a cutter 71 capable of cutting the wire 12S, a guide 72 capable of supplying the wire 12S, and a wedge tool 73 located next to the guide 72 and capable of pressing the wire 12S. In the examples shown in FIGS. 15 to 26, the cutter 71 is disposed between the guide 72 and the wedge tool 73. However, as a modified example, the wedge tool 73 may be disposed between the guide 72 and the cutter 71.

[0081] Guide 72 is a tool capable of continuously supplying a strip-shaped metal member that is the raw material of wire 12S. Ribbons 51, 52, and 53 shown in Fig. 26 are sequentially unwound from the tip of guide 72 and placed on source pad SE in accordance with the operation of guide 72.

[0082] The wedge tool 73 is a tool that presses its tip against the bonded material (wire 12S in this embodiment) and further applies ultrasonic waves to the bonded material, thereby bonding the bonded material and the bonded material together.

[0083] In the conductive member on pad bonding step of this embodiment, if bonding is started from a position far from the lead 30S, interference may occur between the lead 30 and the guide 72. If bonding is started from a position far from the lead 30S, the bonder 70 needs to be moved toward the lead 30S, and if the distance between the joint and the lead 30S is too close, the guide 72 will collide with the lead 30S.

[0084] Therefore, in this embodiment, the wire 12S is bonded by a reverse bonding method. The on-pad conductive member bonding step of this embodiment includes a step of bonding ribbon 51 to the source pad SE as shown in Fig. 18, a step of bonding ribbon 52 onto ribbon 51 as shown in Fig. 22, and a step of bonding ribbon 53 onto ribbon 52 as shown in Fig. 26. Below, the steps will be described in order, starting with the step of bonding ribbon 51 arranged in the bottom layer.

[0085] The step of joining the ribbon 51 includes joining a portion 51A of the ribbon 51 of the wire 12S to a pad bonding portion SEA of the source pad SE, as shown in FIG. 15. The step of joining the ribbon 51 also includes joining the portion 51A of the ribbon 51 to a pad bonding portion SEB of the source pad SE that is located farther from the lead 30S than the pad bonding portion SEA of the source pad SE, as shown in FIG. 17. The step of joining the ribbon 51 also includes moving a bonder 70 from above the pad bonding portion SEA to above the pad bonding portion SEB, as shown in FIG. 16, after joining the portion 51A and before joining the portion 51B. The step of joining the ribbon 51 also includes joining the portion 51B of the ribbon 51 to the source pad SE, as shown in FIG. 18, after cutting the portion 51C of the ribbon 51 with a cutter 71, and separating the ribbon 51 including the portions 51A and 51B from the guide 72.

[0086] 15 , in the step of bonding portion 51A, the wedge tool 73 is pressed against the pad bonding portion SEA while the portion 51A of the ribbon 51 is sandwiched between the pad bonding portion SEA and the tip surface of the wedge tool 73. At this time, the wedge tool applies a load and ultrasonic waves to the ribbon 51, thereby bonding the portion 51A to the pad bonding portion SEA. Also, applying ultrasonic waves from the wedge tool 73 at this time makes it easier to bond the portion 51A of the ribbon 51 to the source pad SE.

[0087] 16, in the process of moving the bonder 70 from above the pad bonding portion SEA to above the pad bonding portion SEB, the wedge tool 73 is moved above the pad bonding portion SEB after being lifted above the portion 51A, or while being lifted above the portion 51A. At this time, from the viewpoint of stably bonding the ribbon 52 (see FIG. 22) onto the ribbon 51, it is preferable that the height of the loop formed between the portion 51A and the portion 51B shown in FIG. 18 be as low as possible.

[0088] In the step of bonding the portion 51B shown in FIG. 17, the portion 51A is bonded to the pad bonding portion SEA by thermocompression bonding in the same manner as the method for bonding the portion 51A described with reference to FIG.

[0089] 18, ribbon 51 is cut while wedge tool 73 is moved in a direction farther from portion 51A than portion 51B of ribbon 51. This is preferable because it makes it easier to position portion 52B shown in FIG. 22, which will be described later, farther from lead 30S than portion 51B shown in FIG. 18. This allows distance D52 shown in FIG. 22 to be longer than distance D51 shown in FIG. 18. As will be described in more detail later, if a loop is formed between portion 51A and portion 51B, bonding can be stabilized by making distance D52 shown in FIG. 22 longer than distance D51 shown in FIG. 18.

[0090] However, as a modified example, as shown in FIG. 17, after joining portion 51B, ribbon 51 may be cut without moving wedge tool 73. In this case, distance D51 can be made longer compared to the example shown in FIG. 18. For example, as a modified example of the present embodiment, if only ribbon 51 is used as wire 12S, ribbon 51 is cut and then the process proceeds to the lead joining process shown in FIG. 11. In this case, applying a method of joining portion 51B and then cutting without moving wedge tool 73 is more effective from the viewpoint of reducing on-resistance.

[0091] In the present embodiment, when bonding is first performed on the pad bonding portion SEA that is relatively closer to the lead 30S, the bonder 70 is positioned so that the guide 72 of the bonder 70 is positioned farther from the lead 30S than the wedge tool 73 of the bonder 70. In this case, even if the distance from the portion 51A of the ribbon 51 to be bonded first to the lead 30S is short, no interference occurs between the guide 72 and the lead 30S. Therefore, according to this embodiment, the distance between the portion 51A of the ribbon 51 and the lead 30S can be reduced. In other words, according to this embodiment, the distance D3 shown in FIG. 9 can be reduced.

[0092] In the present embodiment, after cutting the ribbon 51, ribbon 52 is joined onto the ribbon 51 as shown in FIGS. 19 to 22. The step of joining the ribbon 52 includes the following steps. First, ribbon 51 is cut as shown in FIG. 18, and then, as shown in FIG. 19, a step of joining portion 52A of ribbon 52 of wire 12S to ribbon joint 51D of ribbon 51 is included. The step of joining ribbon 52 also includes a step of joining portion 52A and then joining portion 52B of ribbon 52 to ribbon joint 51E of ribbon 51 that is located farther from lead 30S than ribbon joint 51D of ribbon 51. The step of joining ribbon 52 also includes a step of moving bonder 70 from above ribbon joint 51D to above ribbon joint 51E after the step of joining portion 52A and before the step of joining portion 52B. The step of joining ribbon 52 also includes the step of, after joining portion 52B, cutting portion 52C of ribbon 52 with a cutter, as shown in FIG. 22, and separating ribbon 52 including portions 52A and 52B from guide 72.

[0093] In the step of joining portion 52A shown in FIG. 19 , portion 52A of ribbon 52 is thermocompression-bonded to ribbon joint portion 51D of ribbon 51 in the same manner as in the step of joining portion 51A to pad joint portion SEA of source pad SE described with reference to FIG. 15 . When applying ultrasonic waves from wedge tool 73 at this time, as shown in FIG. 19 , portion 52A of ribbon 52 is preferably positioned closer to lead 30S than portion 51A of ribbon 51. In other words, in the step of joining portion 52A, ribbon joint portion 51D is preferably positioned closer to lead 30S than portion 51A of ribbon 51. When joining is performed by applying ultrasonic waves, it is preferable to avoid joining ribbon 52 to the loop portion between portions 51A and 51B shown in FIG. 18 . By joining ribbon 52 to a portion of ribbon 51 other than the loop portion between portions 51A and 51B, ultrasonic joining can be stabilized.

[0094] The process of moving the bonder 70 shown in Fig. 20 from above the ribbon joint portion 51D to above the ribbon joint portion 51E is the same as the process explained using Fig. 16, so a duplicated explanation will be omitted. The fact that it is preferable to reduce the loop height of the loop portion formed between the portion 52A and the portion 52B shown in Fig. 22 and the measures to achieve this have already been explained.

[0095] 21, the portion 51A is thermocompression-bonded to the pad bonding portion SEA by the same method as the method for bonding the portion 51A described with reference to FIG. 15. At this time, when applying ultrasonic waves from the wedge tool 73, it is preferable that the portion 52B of the ribbon 52 is located farther from the lead 30S than the portion 51B of the ribbon 51, as shown in FIG. 21. In other words, in the step of bonding the portion 52B, it is preferable that the ribbon bonding portion 51E is located farther from the lead 30S than the portion 51B of the ribbon 51. As described above, this is to stabilize the bonding by ultrasonic waves by preventing the ribbon 52 from being bonded to the loop portion between the portions 51A and 51B shown in FIG.

[0096] 22, ribbon 52 is cut with wedge tool 73 moved in a direction farther from portion 52A than portion 52B of ribbon 52. This is preferable because portion 53B shown in FIG. 26, which will be described later, can be more easily positioned farther from leads 30S than portion 52B shown in FIG. 22. This allows distance D53 shown in FIG. 26 to be longer than distance D52 shown in FIG. 22.

[0097] However, as a modified example, as shown in FIG. 21 , after joining portion 51B, ribbon 52 may be cut without moving wedge tool 73. In this case, distance D52 can be made longer compared to the example shown in FIG. 22 . For example, as a modified example of the present embodiment, if only ribbon 51 and ribbon 52 are used as wire 12S, ribbon 52 is cut and then the process proceeds to the lead joining step shown in FIG. 11 . In this case, applying a method of joining portion 52B and then cutting without moving wedge tool 73 is more effective from the viewpoint of reducing on-resistance.

[0098] In the present embodiment, after cutting the ribbon 52, ribbon 53 is joined onto the ribbon 52 as shown in FIGS. 23 to 26. The step of joining the ribbon 53 includes the following steps. First, as shown in FIG. 22, ribbon 52 is cut, and then, as shown in FIG. 23, a step of joining a portion 53A of the ribbon 53 of the wire 12S to a ribbon joint 52D of the ribbon 52 is included. The step of joining the ribbon 53 also includes a step of joining the portion 53A and then joining a portion 53B of the ribbon 53 to a ribbon joint 52E of the ribbon 52 that is located farther from the lead 30S than the ribbon joint 52D of the ribbon 52. The step of joining the ribbon 53 also includes a step of moving the bonder 70 from above the ribbon joint 52D to above the ribbon joint 52E after the step of joining the portion 53A and before the step of joining the portion 53B. The process of joining ribbon 53 also includes the step of, after joining portion 53B, cutting portion 53C of ribbon 53 with a cutter, as shown in FIG. 26, and separating ribbon 53 including portions 53A and 53B from guide 72.

[0099] In the step of joining portion 53A shown in FIG. 23 , portion 53A of ribbon 53 is thermocompression-bonded to ribbon joint portion 52D of ribbon 52 in the same manner as in the step of joining portion 52A to pad joint portion SEA of source pad SE described with reference to FIG. 15 . When applying ultrasonic waves from wedge tool 73 at this time, as shown in FIG. 23 , portion 53A of ribbon 53 is preferably positioned closer to lead 30S than portion 52A of ribbon 52. In other words, in the step of joining portion 53A, ribbon joint portion 52D is preferably positioned closer to lead 30S than portion 52A of ribbon 52. When joining is performed by applying ultrasonic waves, it is preferable to avoid joining ribbon 53 to the loop portion between portions 52A and 52B shown in FIG. 18 . By joining ribbon 53 to a portion of ribbon 52 other than the loop portion between portions 52A and 52B, ultrasonic joining can be stabilized.

[0100] The process of moving the bonder 70 shown in Fig. 24 from above the ribbon joint portion 52D to above the ribbon joint portion 52E is the same as the process explained using Fig. 16, so a duplicated explanation will be omitted. The fact that it is preferable to reduce the loop height of the loop portion formed between the portion 53A and the portion 53B shown in Fig. 26 and the measures to achieve this have already been explained.

[0101] 25, in the step of bonding portion 53B, portion 52A is thermocompression bonded to pad bonding portion SEA by the same method as the method of bonding portion 52A described with reference to FIG. 15. At this time, when ultrasonic waves are applied from wedge tool 73, as shown in FIG. 25, portion 53B of ribbon 53 is preferably positioned farther from lead 30S than portion 52B of ribbon 52. In other words, in the step of bonding portion 53B, ribbon bonding portion 52E is preferably positioned farther from lead 30S than portion 52B of ribbon 52. As with the above, this is to stabilize bonding by ultrasonic waves by preventing ribbon 53 from being bonded to the loop portion between portions 52A and 52B shown in FIG.

[0102] 26, after joining portion 52B as shown in FIG. 25, ribbon 53 is cut without moving wedge tool 73. In this case, distance D53 shown in FIG. 26 can be made longer. In the example of the present embodiment, distance (separation distance) D53 between portion 53A and portion 53B shown in FIG. 26 is longer than distance (separation distance) D52 between portion 52A and portion 52B shown in FIG. 22. Furthermore, distance (separation distance) D52 between portion 52A and portion 52B shown in FIG. 22 is longer than distance (separation distance) D51 between portion 51A and portion 51B shown in FIG. 18. This makes it easier to prevent the joined portion of the ribbon arranged in the upper layer from overlapping the loop portion of the ribbon in the lower layer.

[0103] However, as a modified example, after joining portion 52B as shown in Fig. 25, ribbon 53 may be cut in a state in which the position of wedge tool 73 is moved in a direction farther from portion 53A than portion 53B of ribbon 53, as in the examples described using Fig. 18 and Fig. 22. For example, when a ribbon (not shown) is further stacked on ribbon 53 as wire 12S, this modified example is effective from the viewpoint of avoiding bonding to the loop portion.

[0104] <Lead bonding process> Next, in the lead bonding step shown in Fig. 11, the source pad SE of the semiconductor chip 10 and a plurality of leads 30S are electrically connected via wires 12S and wires (conductive members) 12S, as shown in Fig. 27. Also, in this step, the gate pad GE of the semiconductor chip 10 and leads 30G are electrically connected via wires (conductive members) 12G. Fig. 27 is an enlarged plan view showing the state in which the semiconductor chip and leads shown in Fig. 14 are electrically connected via wires.

[0105] 27, in this process, the gate pad GE of the semiconductor chip 10 and the lead 30G are electrically connected via the wire 12G, not via the wire 12S. Also, in this process, the source pad SE of the semiconductor chip 10 and the lead 30S are electrically connected via the wire 12S and the wire 12S. The resistance value of the transmission path including the gate pad GE has a smaller effect on the performance of the semiconductor device (particularly the performance in terms of reducing the on-resistance) than the transmission path including the source pad SE. For this reason, the wire 12S is not bonded onto the gate pad GE, and the wire 12G is directly bonded to the gate pad GE.

[0106] On the other hand, in the transmission path including the source pad SE, as described above, the wire 12S is bonded to the wire 12S from the viewpoint of reducing the on-resistance. More specifically, the connection portion (portion) 12B1 and the connection portion (portion) 12B2 of the wire 12S are bonded to the wire 12S bonded to the source pad SE, and the connection portion 12B3 of the wire 12S is bonded to the upper surface (bonding surface) 30t of the lead bonding portion 30W of the lead 30S. Furthermore, the connection portion 12B1 and the connection portion 12B2 of the wire 12S (see FIG. 7) are bonded to the bonding surface SEt2 (see FIG. 7), which is another part of the source pad SE, and the connection portion 12B3 of the wire 12S is bonded to the upper surface (bonding surface) 30t of the lead bonding portion 30W of the lead 30S. Hereinafter, a step of electrically connecting the source pad SE and the source lead 30S among the lead bonding steps will be described with reference to FIGS. 27 to 31.

[0107] 28 to 31 are enlarged cross-sectional views showing, for each step, how a conductive member (wire in this embodiment) is bonded to a conductive member on a pad using a wedge bonder in the lead bonding step shown in FIG. 11. In this step, the lead bonding step is performed using a bonder (wedge bonder) 80 shown in FIGS. 28 to 31. In the case of this embodiment, six wires 12S are bonded to the wire 12S as shown in FIG. 27. In the following, one of the six wires 12S will be representatively described.

[0108] The bonder 80 includes a cutter 81 capable of cutting the wire 12S, which is a conductive member, a guide 82 capable of feeding the wire 12S, and a wedge tool 83 located adjacent to the guide 82 and capable of pressing the wire 12S. In the example shown in FIGS. 28 to 31, the bonder 80 and the bonder 70 differ in structure from the bonder 70 described with reference to FIGS. 15 to 26 in the following respects. The wedge tool 83 is disposed between the cutter 81 and the guide 82. The area of ​​the tip face (the face that presses the wire) of the wedge tool 83 of the bonder 80 is smaller than the area of ​​the tip face (the face that presses the ribbon 51) of the wedge tool 73 of the bonder 70 shown in FIG. 15. Therefore, the bonder 80 is smaller overall than the bonder 70. However, as a modified example, the lead bonding process can also be performed using the bonder 70 described with reference to FIGS. 15 to 26.

[0109] Guide 82 is a tool capable of continuously supplying metal wire, which is the raw material of wire 12S. Wire 12S shown in Fig. 28 is sequentially unwound from the tip of guide 82 and placed on the upper surface of conductive member 50 (the upper surface of ribbon 53 in this embodiment) in accordance with the operation of guide 82.

[0110] The wedge tool 83 presses its tip against the joining material (wire 12S in this embodiment) to apply heat and ultrasonic waves to the joining material and the joining target material (conductive material 50) to thermocompress the joining and joining workpieces together.

[0111] In the lead bonding process of this embodiment, the conductive member 50 is already bonded onto the source pad SE, so the difference in height between the upper surface of the conductive member 50 and the upper surface of the lead 30S is small. Therefore, even when using the bonder 80 or the bonder 70, interference between the lead 30S and the bonder guide is unlikely to occur. Therefore, in the lead bonding process of this embodiment, either the forward bonding method or the reverse bonding method can be applied. Below, a case where the forward bonding method is applied will be described as a representative example, and then a case where the reverse bonding method is applied will be described as a modified example.

[0112] As shown in FIG. 28, the lead bonding process includes a step of bonding a connection portion 12B1 of the wire 12S to a ribbon bond portion 53E of the ribbon 53. As shown in FIG. 29, the lead bonding process also includes a step of bonding a connection portion 12B2 of the wire 12S to a ribbon bond portion 53D of the ribbon 53 that is located closer to the lead 30S than the ribbon bond portion 53E of the ribbon 53. Although not shown, the lead bonding process also includes a step of moving the bonder 80 from above the ribbon bond portion 53E to above the ribbon bond portion 53D after the step of bonding the connection portion 12B1 and before the step of bonding the connection portion 12B2. As shown in FIG. 30, the lead bonding process also includes a step of bonding a connection portion 12B2 of the wire 12S to a lead bond portion 30W of the lead 30S. Although not shown, the lead bonding step includes a step of moving bonder 80 from above ribbon bonding portion 53D to above lead bonding portion 30W after the step of bonding connecting portion 12B2 and before the step of bonding connecting portion 12B3. Furthermore, the lead bonding step includes a step of cutting portion 12C of wire 12S with cutter 81 and separating wire 12S including connecting portions 12B1, 12B2, and 12B3 from guide 82, as shown in FIG.

[0113] 28, in the step of joining connection portion 12B1, wedge tool 83 is pressed with connection portion 12B1 of wire 12S sandwiched between ribbon joint portion 53E of ribbon 53 and the tip surface of wedge tool 83. At this time, pressure and heat are applied from the wedge tool to wire 12S, thereby thermocompression-bonding connection portion 12B1 to ribbon joint portion 53E. Also, ultrasonic waves are applied from wedge tool 83 at this time, which makes it easier to join connection portion 12B1 of wire 12S to source pad SE.

[0114] When applying ultrasonic waves from wedge tool 83, as shown in FIG. 28, it is preferable that connection portion 12B1 of wire 12S is located farther from lead 30S than portion 53B of ribbon 53. In other words, in the step of joining connection portion 12B1 of wire 12S, ribbon joining portion 53E is located farther from lead 30S than portion 52B of ribbon 52. When joining is performed by applying ultrasonic waves, it is preferable to avoid joining wire 12S to the loop portion between portions 53A and 53B shown in FIG. 26. By joining ribbon 53 to a portion of ribbon 53 other than the loop portion between portions 53A and 53B, it is possible to stabilize joining by ultrasonic waves.

[0115] However, as in this embodiment, when the area of ​​the tip surface of wedge tool 83 is smaller than the area of ​​the tip surface of wedge tool 73 shown in Figure 26, bonding to the loop portion can be avoided even if the center of portion 53B of ribbon 53 overlaps with the center of connection portion 12B1 of wire 12S.

[0116] Next, in the process of moving the bonder 80 from ribbon joint 53E to ribbon joint 53D, the wedge tool 83 is moved above ribbon joint 53D after being lifted above connecting portion 12B1, or while being lifted above connecting portion 12B1. In the case of wire 12S, no additional conductive member is layered on wire 12S. Therefore, in the lead bonding process, the height of the loop formed between connecting portions 12B1 and 12B2 shown in FIG. 31 is not particularly important. In the example of this embodiment, the height of the loop formed between connecting portions 12B1 and 12B2 shown in FIG. 31 is higher than the height of the loop between portions 51A and 51B shown in FIG. 18.

[0117] Next, in the step of joining the connection portion 12B2 shown in FIG. 29, the connection portion 12B1 is thermocompression bonded to the ribbon connection portion 53D in the same manner as the method for joining the connection portion 12B1 described with reference to FIG.

[0118] When applying ultrasonic waves from the wedge tool 83, the position of the connection portion 12B2 of the wire 12S is preferably located closer to the lead 30S than the portion 53A of the ribbon 53. In other words, in the process of joining the connection portion 12B2 of the wire 12S, the ribbon joining portion 53D is preferably located closer to the lead 30S than the portion 52A of the ribbon 52. This allows the ribbon 53 to be joined to a portion of the ribbon 53 other than the loop portion between the portions 53A and 53B, thereby stabilizing the joining by the ultrasonic waves. However, as shown in FIG. 29 , when the loop portion between the portions 53A and 53B of the ribbon 53 does not overlap with the connection portion 12B2 of the wire 12, the joining by the ultrasonic waves can be stabilized even if the connection portion 12B2 is not located closer to the lead 30S than the portion 52A of the ribbon 52.

[0119] In the process of joining connection portion 12B2 of wire 12S in this embodiment, the difference in height between the upper surface of ribbon 53 and the upper surface of lead 30S is small, so even if the distance between lead 30S and connection portion 12B2 of wire 12S is short, interference between guide 82 and lead 30S can be avoided as shown in FIG. 29. In other words, according to this embodiment, connection portion 12B2 of wire 12S can be joined near lead 30S. As a result, the above-mentioned on-resistance can be reduced.

[0120] Next, in the process of moving the bonder 80 from above the ribbon joint portion 53D to above the lead joint portion 30W, the wedge tool 83 is lifted above the connection portion 12B2, or is moved above the ribbon joint portion 53D while being lifted above the connection portion 12B2.

[0121] 30 to the lead bonding portion 30W, and the step of cutting the wire 12S shown in FIG. 31 are performed with at least the lower surface of the wire 30S fixed by the stage 85 shown in FIG. 30 and the upper surface of the wire 12S fixed by the clamper 86. The clamper 86 is preferably positioned as close as possible to the tip surface of the lead 30S (the surface facing the conductive member 50) within a range that can avoid interference with the guide 82. In this embodiment, the entire lead bonding step (i.e., from the step of bonding the connection portion 12B1 shown in FIG. 28) is performed with the lead frame LF (see FIG. 27) placed on the stage 85 and with a portion of the lead 30S held down by the clamper 86.

[0122] In the step of joining the connection portion 12B3 of the wire 12S to the lead joining portion 30W, the connection portion 12B1 is thermocompression-bonded to the lead joining portion 30W in the same manner as the method for joining the connection portion 12B1 described with reference to Fig. 28. In this step as well, ultrasonic waves may be applied to the connection portion 12B3 of the wire 12S from a wedge tool 83. In this step, the lead 30S is clamped between a stage 85 and a clamper 86, thereby stabilizing the joining strength.

[0123] In the step of cutting wire 12S shown in Fig. 31, wire 12S is cut in a state in which the position of wedge tool 83 is moved in a direction away from connection portion 12B1 of wire 12S with respect to connection portion 12B3 of wire 12S. When bonder 80 is used, it is necessary to move bonder 80 as shown in Fig. 31. On the other hand, when a bonder having a structure similar to that of bonder 70 shown in Fig. 18 is used, connection portion 12B3 shown in Fig. 30 can be cut without moving the bonder after being bonded to lead bonding portion 30W.

[0124] 28 to 31 have been described with reference to the process of joining the wire 12S to the conductive member 50, but in this embodiment, the wire 12G shown in FIG. 28 is connected using the bonder 80 shown in FIG. 28. In the case of a wedge bonding method using the wire 12G, the process shown in FIG. 28 can be omitted, but since it is similar to the wedge bonding method described with reference to FIGS. 28 to 31, a duplicated description will be omitted. However, since it is sufficient for the wire 12G to be joined to the gate pad GE at one point, a ball bonding method may be used instead of the wedge bonding method. In the ball bonding method, the tip of the wire is thermally melted to form a ball portion, and the ball portion is joined to the gate pad GE by thermocompression bonding.

[0125] When the lead bonding process is performed using the forward bonding method as in this embodiment, the wire 12S is cut on the lead 30S as shown in FIG. 31 . On the other hand, when the wire 12S is bonded using the reverse bonding method as described later as a modified example, the wire 12S is cut on the conductive member 50. Depending on the strength of the wire 12S, the load applied when cutting the wire 12S may leave scratches on the bonded portion. In particular, when the wire 12S is made of copper or a copper alloy, which has a higher hardness than aluminum, the material of the ribbons 51, 52, and 53, a strong load is required when cutting the wire 12S. In this embodiment, the wire 12S is cut on the lead 30S made of copper or a copper alloy, so that damage to the bonded portion (the lead 30S in this embodiment) can be suppressed even if the wire 12S is made of copper or a copper alloy. Furthermore, since the wire 12S is not cut on the conductive member 50, damage to the conductive member 50 can also be prevented.

[0126] <Sealing process> Next, in the sealing step shown in Fig. 11, the semiconductor chip 10, part of the die pad 20, the conductive member 30, parts of each of the plurality of leads 30, and the plurality of wires 12 shown in Fig. 27 are sealed with insulating resin to form the sealing body 40 shown in Fig. 32. Fig. 32 is an enlarged plan view showing the state in which the sealing body that seals the semiconductor chip and wires shown in Fig. 27 has been formed.

[0127] In this process, for example, the sealing body 40 is formed by a so-called transfer molding method with the lead frame LF placed in a molding die (not shown). In this process, as shown in Figures 4 and 6, the semiconductor chip 10 (see Figure 6), the conductive member 50 (see Figure 6), and the wires 12 (see Figure 6) are sealed with resin so that the lower surface 20b of the die pad 20 is exposed.

[0128] Although not shown in the drawings, as a modification of the present embodiment, there is a case where the lower surface 20b of the die pad 20 is not exposed from the sealing body 40. In another modification, there is a case where only a part of the die pad 20 is exposed from the sealing body 40, and the other part is sealed in the sealing body 40.

[0129] As shown in FIG. 32, in the lead frame LF, the tie bars LFt that connect the plurality of leads 30 are cut in the singulation step described below, and therefore the sealing body 40 is formed so that the tie bars LFt are exposed.

[0130] After the sealing body 40 is molded, it is heated until a portion of the thermosetting resin contained in the sealing body 40 is hardened (this is called pre-hardening). When this pre-hardening makes it possible to remove the lead frame LF from the molding die, the lead frame LF is removed from the molding die. The lead frame LF is then transported to a heating furnace and further heated (cure baked). This hardens the remaining portion of the thermosetting resin, and the sealing body 40 shown in FIG. 32 is obtained.

[0131] Furthermore, although the sealing body 40 is mainly composed of insulating resin, the functionality of the sealing body 40 (e.g., resistance to warpage) can be improved by mixing filler particles such as silica (silicon dioxide; SiO2) particles into the thermosetting resin.

[0132] <Plating process> Next, in the plating process shown in FIG. 11, the lead frame LF is immersed in a plating solution not shown, and a metal film (metal film 22 and metal film 32 shown in FIG. 6) is formed on the surface of the metal portion (outer portion) exposed from the sealing body 40.

[0133] In this process, metal films 22, 32 (FIG. 6) made of, for example, solder are formed on the surfaces of the metal members exposed from the resin by electroplating. Although not shown, in electroplating, the lead frame LF (see FIG. 32), which is the workpiece to be plated, is placed in a plating tank containing a plating solution. At this time, the workpiece is connected to a cathode in the plating tank. For example, the frame portion LFf (see FIG. 32) of the lead frame LF is electrically connected to the cathode. Then, for example, a DC voltage is applied between this cathode and an anode also placed in the plating tank, thereby forming the metal films 22, 32 on the exposed surfaces of the metal members connected to the frame portion LFf of the lead frame LF. In this embodiment, the metal films 22, 32 are formed by so-called electroplating.

[0134] As described above, the metal films 22 and 32 of this embodiment are made of so-called lead-free solder that does not substantially contain lead (Pb), such as tin (Sn) only, tin-bismuth (Sn-Bi), or tin-copper-silver (Sn-Cu-Ag). 2+ , or Bi 3+ It is an electrolytic plating solution containing metal salts such as: In the following explanation, Sn-Bi alloy metal plating will be explained as an example of lead-free solder plating, but bismuth (Bi) can be replaced with metals such as copper (Cu) or silver (Ag), or the electrolytic plating solution can be replaced with not only bismuth (Bi) but also copper (Cu) or silver (Ag) added.

[0135] In this embodiment, the plating process is carried out in a state where the die pad 20 (see FIG. 28) shown in FIG. 32 is electrically connected to the frame portion LFf via the leads 30. When a voltage is applied between the anode and the cathode with the lead frame LF immersed in the plating solution, electricity flows between the anode and the leads 30 and die pad 20 connected to the cathode via the plating solution. At this time, Sn in the plating solution 2+ , and Bi 3+ is deposited at a predetermined rate on the exposed surfaces of the leads 30 and the die pad 20 that are not covered by the sealing body 40, forming the metal films 22 and 32 shown in FIG.

[0136] <Singulation process> Next, in the singulation step shown in Fig. 11, the assembly PKG0 corresponding to the semiconductor device PKG1 (see Fig. 3) is separated from the frame portion LFf and the tie bar LFt of the lead frame LF and singulated as shown in Fig. 33. Fig. 33 is an enlarged plan view showing a state in which each of the multiple device forming portions has been separated in the singulation step shown in Fig. 11.

[0137] In this process, the frame portion LFf connected to the die pad 20 is cut, and the die pads 20 connected via the frame portion LFf are divided into each of them. Also, in this process, the tie bar LFt is cut, and the boundaries between the leads 30 and the frame portion LFf are cut, thereby separating each of the leads 30.

[0138] A processing method (press processing) in which a cutting jig is pressed against the cutting portion to shear the tie bars LFt, the frame portions LFf, and the leads 30 can be used to cut the tie bars LFt, the frame portions LFf, and the leads 30. This process is performed after the plating process, so the side surfaces newly formed by cutting in this process are exposed from the plating film (metal films 22 and 32 shown in FIG. 6).

[0139] After this process, necessary inspections and tests such as visual inspection and electrical test are carried out, and only those that pass the test become the finished semiconductor device PKG1 shown in Fig. 3. Then, the semiconductor device PKG1 is shipped or mounted on a mounting board (not shown).

[0140] The invention made by the present inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the above embodiments and the modifications described within the above embodiments, and various modifications are possible without departing from the gist of the invention. Representative modifications will be described below.

[0141] <Variation 1> First, as Modification 1, a method will be described in which the lead bonding step explained using Figures 28 to 31 is performed by a reverse bonding method. Figures 34 to 37 are enlarged cross-sectional views showing modifications to Figures 28 to 31.

[0142] In this step, the lead bonding step is performed using a bonder (wedge bonder) 90 shown in Figures 34 to 37. In the case of this embodiment, six wires 12S are bonded to the wire 12S as shown in Figure 27. In the following, one of the six wires 12S will be representatively described.

[0143] The bonder 90 has a similar structure to the bonder 70 described with reference to Figures 15 to 26, except for the following points: A cutter 91 is disposed between a wedge tool 93 and a guide 92. The area of ​​the tip face (the face that presses the wire) of the wedge tool 93 of the bonder 90 is smaller than the area of ​​the tip face (the face that presses the ribbon 51) of the wedge tool 73 of the bonder 70 shown in Figure 15. Therefore, the bonder 90 is smaller overall than the bonder 70. However, as a modification, the lead bonding process can also be performed using the bonder 70 described with reference to Figures 15 to 26, or the bonder 80 described with reference to Figures 28 to 31.

[0144] As described below, this modification differs from the embodiment described with reference to FIGS. 28 to 31 in that the wire 12S is bonded to the lead 30S and the conductive member 50 by a reverse bonding method. In this modification, the wire 12S is first bonded to the lead bonding portion 30W of the lead 30S. This eliminates the concern of interference between the clamper 86 and the guide 82 of the bonder 80, as in the embodiment described with reference to FIG. 31. Therefore, as can be seen by comparing FIGS. 30 and 36, when bonding the portion 12B3 of the wire 12S to the lead 12S, the clamper 86 can be positioned near the portion 12B3. In this way, the vicinity of the bonding point can be held down by the clamper 86, and therefore, in this modification, the bonding state between the wire 12S and the lead 12S can be stabilized. Details of this modification are described below.

[0145] As shown in FIG. 34, the lead bonding process includes a step of bonding the connection portion 12B3 of the wire 12S to the lead bonding portion 30W of the lead 30S. As shown in FIG. 35, the lead bonding process also includes a step of bonding the connection portion 12B2 of the wire 12S to the ribbon bonding portion 53D of the ribbon 53 after bonding the connection portion 12B3 of the wire 12S. Although not shown, the lead bonding process also includes a step of moving the bonder 90 from above the lead bonding portion 30W to above the ribbon bonding portion 53D after bonding the connection portion 12B3 and before bonding the connection portion 12B2. As shown in FIG. 36, the lead bonding process also includes a step of bonding the connection portion 12B2 of the wire 12S to the ribbon bonding portion 53E of the ribbon 53. Although not shown, the lead bonding process includes a step of moving bonder 90 from above ribbon bonding portion 53D to above ribbon bonding portion 53E after the step of bonding connecting portion 12B2 and before the step of bonding connecting portion 12B1. Furthermore, the lead bonding process includes a step of cutting portion 12C of wire 12S with cutter 91 and separating wire 12S including connecting portions 12B1, 12B2, and 12B3 from guide 92, as shown in FIG.

[0146] In this modified example, the wire bonding method is the same as the wire bonding method described using Figures 28 to 30, except that the bonding order and the position of the clamper 86 are different, so duplicated explanations will be omitted.

[0147] <Variation 2> Fig. 38 is an enlarged plan view showing a modification of Fig. 5. Fig. 39 is an enlarged cross-sectional view taken along line CC in Fig. 38. The semiconductor device PKG2 shown in Figs. 38 and 39 differs from the semiconductor device PKG1 shown in Fig. 5 in that the conductive member for electrically connecting the conductive member 50 and the lead 30S is a ribbon (strip-shaped conductive member) 14.

[0148] The ribbon 14 is a strip-shaped conductive member made of, for example, aluminum. More specifically, in the case of the wire 12, the cross-sectional shape of the portion other than the bonded portion with the pad or lead of the semiconductor chip is circular, but the cross-sectional shape of the portion with the pad or lead of the semiconductor chip is elliptical (or strip-shaped). On the other hand, in the case of the ribbon 14, not only the portion with the pad or lead of the semiconductor chip but also the portion other than the bonded portion with the pad or lead of the semiconductor chip are strip-shaped in cross-section. Furthermore, the width (or cross-sectional area) of the ribbon 14 is thicker (larger) than the width (or cross-sectional area) of the wire 12. Even if the wire 12 shown in FIG. 5 is replaced with the ribbon 14, it can be manufactured in the same manner as the lead bonding process described above. In the lead bonding, a wedge bonder for ribbon bonding is used. However, since the cutter, guide, and wedge tool are each wider in the X direction shown in FIG. 38 to bond the wide ribbon 14, a redundant description will be omitted. Therefore, the bonder 80 shown in FIGS. 28 to 31 or the bonder 90 shown in FIGS. 34 to 37 will not be repeated.

[0149] When the wire 12S shown in FIGS. 5 and 6 is replaced with the ribbon 14 shown in FIGS. 38 and 9, the following points are different.

[0150] First, since ribbon 14 is wider than wire 12S, it is difficult to bend ribbon 14 in the extending direction. For this reason, wire 12 is preferable when it is necessary to bend ribbon 14 in accordance with the position of lead bonding portion 30W.

[0151] On the other hand, the ribbon 14 is wider than the wire 12, and therefore has a larger bonding area with the conductive member 50. A larger bonding area is preferable from the viewpoint of reducing the on-resistance.

[0152] <Variation 3> FIG. 40 is an enlarged plan view showing another modified example of FIG. 5. FIG. 41 is an enlarged cross-sectional view taken along line DD in FIG. 40. The semiconductor device PKG3 shown in FIGS. 40 and 41 differs from the semiconductor device PKG1 shown in FIG. 5 in that the conductive members 50A and 50B, which are spaced apart from each other in the Y direction, are each bonded to the source pad SE. As shown in FIG. 41, an insulating film 13 is formed between the conductive members 50A and 50B, and the source pad SE is covered with the insulating film 13. The conductive members 50A and 50B each consist of a ribbon 51, a ribbon 52, and a ribbon 53. This is similar to the conductive member 50 shown in FIG. 6.

[0153] 6, it is preferable to reduce the exposed area of ​​the source pad SE. When the conductive member 50A and the conductive member 50B are selectively disposed in the portion where the wire 12S is bonded and a portion of the source pad SE is covered with the insulating film 13 between the conductive member 50A and the conductive member 50B as in this modification, it is preferable in that the exposed area of ​​the source pad SE can be reduced compared to the semiconductor device PKG1 shown in FIG.

[0154] In the case of this modified example, in the above-described on-pad conductive member bonding step, after bonding ribbon 51 that is a part of conductive member 50B and before bonding ribbon 51 that is a part of conductive member 50A, a step of cutting ribbon 51 is required. Therefore, from the viewpoint of improving the efficiency of the manufacturing process, the manufacturing methods of semiconductor device PKG1 shown in Fig. 5 and semiconductor device PKG2 shown in Fig. 38 are preferable in that the number of manufacturing steps can be reduced.

[0155] As a further modification, in the configuration of the semiconductor device PKG1 shown in FIG. 4, the wires 12S may be replaced with ribbons 14, similar to the semiconductor device PKG2 shown in FIG.

[0156] 5 in that the conductive member for electrically connecting the conductive member 50 and the lead 30S is a ribbon 14.

[0157] <Variation 4> 5, each of the plurality of wires 12S may be joined at three or more locations to one conductive member 50. In this case, the joining area between the wires 12S and the conductive member 50 increases, thereby reducing the impedance of the conductive path through the wires 12S and the conductive member 50.

[0158] <Variation 5> Furthermore, for example, although various modified examples have been described above, the modified examples described above may be combined and applied. Also, portions of the modified examples may be extracted and combined. [Explanation of symbols]

[0159] 10 Semiconductor chips 10b Back side (front, main side, bottom side) 10s side (surface) 10t surface (surface, main surface, top surface) 11 Die bond material (adhesive) 12, 12G, 12S Wire (metal wire, conductive material, metal wire) 12B1, 12B2, 12B3 Connections (parts, joints, stitched parts) 12L1,12L2 Loop part (extension part) 13 Insulating film (protective film) 13H1,13H2,13H3,13H4 opening 13R1,13R2 area 14, 51, 52, 53 Ribbon (strip-shaped conductive material) 20 Die pad (metal plate, chip mounting area, heat sink) 20b Bottom surface (front surface, main surface, back surface, exposed surface, mounting surface) 20s,20s1,20s2 side 20t Top surface (surface, main surface, surface, chip mounting surface) 21 Base material 22,32 Metal film (plated film) 30, 30D, 30G, 30S Lead (Terminal) 30b Bottom surface (side) 30M Inner part (inner lead part, sealed part) 30s side 30t Top surface (surface, wire bonding surface) 30W Lead joint (lead post, pad, bonding pad, joint) 30X Outer part (outer lead part, exposed part) 31 Base material 40 Sealing body (resin sealing body, resin body, molded resin) 40b Bottom surface (mounting surface) 40s side 40t top surface 50, 50A, 50B Conductive material (ribbon laminate) 51A, 51B, 52A, 52B, 53A, 53B parts (connection parts) 51D, 51E, 52D, 52E, 53D, 53E Ribbon joint 70, 80, 90 Bonder (Wedge Bonder) 71,81,91 cutter 72,82,92 Guide 73,83,93 Wedge Tool 85 Stages 86 Clamper CH channel formation region D Drain D1,D2,D3,D51,D52,D53 Distance (separation distance) DE drain electrode (electrode) EP epitaxial layer Gate (gate electrode) GE Gate pad (electrode, gate electrode) GEt,SEt1,SEt2 Joint surface (exposed surface, joint part) GI gate insulating film GW wiring (gate wiring) LF lead frame LFd Device Formation Department LFf Frame LFt tie bar PKG0 assembly PKG1, PKG2, PKG3 Semiconductor device Q1 transistor S Source (source electrode) SE, SE1 source pad (electrode, source electrode pad) SEA,SEB pad joint SEs1, SEs2 side SR Source Region SW wiring (source wiring) TR1 Trench (opening, groove) WH Semiconductor substrate

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of: (a) providing a lead frame having a die pad and a first lead spaced from the die pad; where: the die pad has a first surface and a second surface opposite to the first surface, (b) after the step (a), mounting a semiconductor chip having a MOSFET and a source pad electrically connected to a source of the MOSFET on the first surface of the die pad; (c) after the step (b), using a first bonder, bonding a first conductive member to the source pad located below the first lead in a cross-sectional view; (d) after the step (c), using a second bonder, bonding a second conductive member to the first conductive member and the first lead; (e) after the step (d), a step of sealing the semiconductor chip, the first conductive member, and the second conductive member with resin; where: The first bonder is a cutter capable of cutting the first conductive member; a guide capable of supplying the first conductive member; a wedge tool positioned adjacent to the cutter and capable of pressing the first conductive member; Equipped with In the step (c), the first bonder is disposed so that the guide of the first bonder is located farther from the first lead than the wedge tool of the first bonder; The step (c) (c1) bonding a first portion of the first conductive member to a first pad bond of the source pad; (c2) after the step (c1), bonding a second portion of the first conductive member to a second pad bond of the source pad located farther from the first lead than the first pad bond of the source pad; It has.

2. In claim 1, the first conductive member comprises a plurality of ribbons stacked on the source pad; The step (c) (c1) bonding the first portion of a first ribbon of the first conductive member to the first pad bond portion of the source pad; (c2) after the step (c1), bonding the second portion of the first ribbon to the second pad bond of the source pad located farther from the first lead than the first pad bond of the source pad; (c3) after the step (c2), cutting a third portion of the first ribbon with the cutter and separating the first ribbon including the first portion and the second portion from the guide; (c4) after the step (c3), joining a fourth portion of the second ribbon of the first conductive member to a first ribbon joint portion of the first ribbon; (c5) after the step (c4), joining a fifth portion of the second ribbon to a second ribbon joint portion of the first ribbon that is located farther from the first lead than the first ribbon joint portion of the first ribbon; (c6) after the step (c5), cutting a sixth portion of the second ribbon with the cutter and separating the second ribbon including the fourth portion and the fifth portion from the guide; The method for manufacturing a semiconductor device comprising the steps of:

3. In claim 2, The step (c) (c7) after the step (c6), joining a seventh portion of a third ribbon of the first conductive member to a third ribbon joint portion of the second ribbon; (c8) after the step (c7), joining an eighth portion of the third ribbon to a fourth ribbon joint portion of the second ribbon that is located farther from the first lead than the third ribbon joint portion of the second ribbon; (c9) after the step (c8), cutting the ninth portion of the third ribbon with the cutter and separating the third ribbon including the seventh portion and the eighth portion from the guide; The method for manufacturing a semiconductor device further comprises:

4. In claim 2, A method for manufacturing a semiconductor device, wherein in the step (c6), the distance between the fourth portion and the fifth portion of the second ribbon is longer than the distance between the first portion and the second portion of the first ribbon.

5. In claim 3, In the step (c6), a separation distance between the fourth portion and the fifth portion of the second ribbon is longer than a separation distance between the first portion and the second portion of the first ribbon, A method for manufacturing a semiconductor device, wherein in the (c9) step, the distance between the seventh portion and the eighth portion of the third ribbon is longer than the distance between the fourth portion and the fifth portion of the second ribbon.

6. In claim 2, A method for manufacturing a semiconductor device, wherein in the (c4) step, the first ribbon joint portion of the first ribbon is positioned closer to the first lead than the first portion of the first ribbon.

7. In claim 6, A method for manufacturing a semiconductor device, wherein in the (c6) step, the second ribbon joint portion of the first ribbon is positioned farther from the first lead than the second portion of the first ribbon.

8. In claim 1, In the step (d), a second conductive member is bonded to the first conductive member using the second bonder, and then the second conductive member is bonded to the first lead.

9. In claim 8, A method for manufacturing a semiconductor device, wherein the second conductive member is a wire made of copper or a copper alloy.

10. In claim 1, In the step (d), a second conductive member is bonded to the first lead using the second bonder, and then the second conductive member is bonded to the first conductive member.

11. In claim 1, The step (d) (d1) joining a first connection portion of the second conductive member to a portion of the first conductive member; (d2) after the step (d1), joining the second connection portion of the second conductive member to another portion different from the portion of the first conductive member; Including, the source pad has a first side extending in a first direction intersecting an arrangement direction of the first connection portions and the second connection portions, and a second side located opposite to the first side and extending in the first direction; A method for manufacturing a semiconductor device, wherein a first distance from the first connection portion to the first side is shorter than a second distance between the first connection portion and the second connection portion, and a third distance from the second connection portion to the second side is shorter than the second distance.

12. In claim 1, A method for manufacturing a semiconductor device, wherein the lead frame further supports the die pad and has a second lead that is bent so that the die pad is positioned lower than the first lead in a cross-sectional view.

13. In claim 1, the sealing body formed by performing the step (e) has an upper surface, a lower surface opposite to the upper surface, and a side surface located between the upper surface and the lower surface; In the step (e), the semiconductor chip, the first conductive member, and the second conductive member are sealed with the resin so that the first lead is exposed from the side surface of the sealing body and the second surface of the die pad is exposed from the bottom surface of the sealing body.

14. a die pad having a first surface and a second surface opposite the first surface; a first lead spaced from the die pad; a semiconductor chip having a front surface, a back surface opposite to the front surface, a MOSFET, and a source pad formed on the front surface and electrically connected to a source of the MOSFET, the semiconductor chip being mounted on the first surface of the die pad so that the back surface faces the die pad; a first conductive member bonded to the source pad of the semiconductor chip; a second conductive member joined to each of the first conductive member and the first lead; a sealing body that seals the semiconductor chip, the first conductive member, and the second conductive member; Including, In a cross-sectional view, the source pad of the semiconductor chip is located below the first lead, the source pad of the semiconductor chip is electrically connected to the first lead via the first conductive member and the second conductive member; the first conductive member comprises a plurality of ribbons stacked on the source pad; a first ribbon of the plurality of ribbons is bonded to the source pad of the semiconductor chip; A semiconductor device, wherein the second conductive member is bonded to a second ribbon among the plurality of ribbons that is positioned above the first ribbon.

15. In claim 14, A semiconductor device, wherein the second conductive member has a first connection portion joined to a portion of the first conductive member and a second connection portion joined to another portion of the first conductive member different from the portion.

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