Display device, method for manufacturing display device, and electronic device

Abstract

Provided is a display device that is capable of displaying a high-quality image. This display device has a first light-emitting element, a second light-emitting element, and voids. The first light-emitting element has a first lower electrode, a first light-emitting layer on the first lower electrode, and a first upper electrode on the first light-emitting layer, and the second light-emitting element has a second lower electrode, a second light-emitting layer on the second lower electrode, and a second upper electrode on the second light-emitting layer. The first light-emitting element and the second light-emitting element are adjacent to each other. The voids are provided between the first upper electrode and the first light-emitting layer, and between the second upper electrode and the second light-emitting layer. The first upper electrode has an area protruding beyond a side surface of the first light-emitting layer, and the second upper electrode has an area protruding beyond a side surface of the second light-emitting layer.

Description

[Technical Field]

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a display device and a manufacturing method thereof.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] In recent years, display devices are expected to be used in a variety of applications. For example, applications of large display devices include home television devices (also called televisions or television receivers), digital signage, and public information displays (PIDs). In addition, development of smartphones and tablet devices equipped with touch panels as mobile information terminals is progressing.

[0004] There is also a demand for higher resolution display devices. Devices requiring high resolution display devices, such as devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR), are being actively developed.

[0005] As a display device, for example, a light-emitting device having a light-emitting element (also referred to as a light-emitting device) has been developed. In particular, a light-emitting element (also referred to as an EL element or an EL device) utilizing the electroluminescence (hereinafter referred to as EL) phenomenon has features such as being easily thin and lightweight, being capable of high-speed response to input signals, and being capable of being driven by a DC constant voltage power supply, and is therefore applied to a display device.

[0006] Patent Document 1 discloses a display device for VR that uses an organic EL element (also called an organic EL device). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] International Publication No. 2018 / 087625 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a display device that displays a high-quality image.An object of one embodiment of the present invention is to provide a display device with high light extraction efficiency.An object of one embodiment of the present invention is to provide a display device with a high aperture ratio.An object of one embodiment of the present invention is to provide a high-resolution display device.An object of one embodiment of the present invention is to provide a low-cost display device.An object of one embodiment of the present invention is to provide a highly reliable display device.An object of one embodiment of the present invention is to provide a novel display device.

[0009] Another object of one embodiment of the present invention is to provide a manufacturing method of a display device that displays a high-quality image.Another object of one embodiment of the present invention is to provide a manufacturing method of a display device with high light extraction efficiency.Another object of one embodiment of the present invention is to provide a manufacturing method of a display device with a high aperture ratio.Another object of one embodiment of the present invention is to provide a manufacturing method of a high-resolution display device.Another object of one embodiment of the present invention is to provide a manufacturing method of a display device with simple steps.Another object of one embodiment of the present invention is to provide a manufacturing method of a highly reliable display device.Another object of one embodiment of the present invention is to provide a manufacturing method of a novel display device.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a display device including a first light-emitting element, a second light-emitting element, and a gap. The first light-emitting element has a first bottom electrode, a first light-emitting layer over the first bottom electrode, and a first upper electrode over the first light-emitting layer. The second light-emitting element has a second bottom electrode, a second light-emitting layer over the second bottom electrode, and a second upper electrode over the second light-emitting layer. The first light-emitting element and the second light-emitting element are adjacent to each other. A gap is provided between the first upper electrode and the first light-emitting layer, and between the second upper electrode and the second light-emitting layer. The first upper electrode has a region protruding beyond a side surface of the first light-emitting layer. The second upper electrode has a region protruding beyond a side surface of the second light-emitting layer.

[0012] Alternatively, in the above aspect, the distance between the side surface of the first upper electrode and the side surface of the second upper electrode may be 1 μm or less in an area.

[0013] Alternatively, in the above embodiment, the distance between the side surface of the first electron injection layer and the side surface of the second electron injection layer may be 100 nm or less in a region.

[0014] Alternatively, in the above embodiment, the voids may contain one or more elements selected from nitrogen, oxygen, carbon dioxide, and Group 18 elements.

[0015] Alternatively, in the above embodiment, the Group 18 element may be any one or more selected from helium, neon, argon, xenon, and krypton.

[0016] Alternatively, in the above embodiment, the refractive index of the first light-emitting layer and the refractive index of the second light-emitting layer may be higher than the refractive index of the void.

[0017] Alternatively, in the above aspect, the first light-emitting element and the second light-emitting element may be provided on an insulating layer, the upper surface of the insulating layer having a region in contact with the lower surface of the void, and the thickness of the insulating layer in the region where the upper surface of the insulating layer contacts the lower surface of the void may be thinner than the thickness of the insulating layer in the region overlapping with the first light-emitting layer and the thickness of the insulating layer in the region overlapping with the second light-emitting layer.

[0018] Alternatively, in the above aspect, a protective layer may be provided on the first upper electrode and the second upper electrode, and the protective layer may have a region in contact with the upper surface of the gap.

[0019] Alternatively, in the above aspect, a microlens array may be provided on the protective layer.

[0020] Alternatively, in the above aspect, the display device may include a first transistor and a second transistor, one of a source or a drain of the first transistor being electrically connected to a first lower electrode, one of a source or a drain of the second transistor being electrically connected to a second lower electrode, and the first transistor and the second transistor each having silicon or metal oxide in a channel formation region.

[0021] An electronic device including the display device of one embodiment of the present invention and a lens is also one embodiment of the present invention.

[0022] Another embodiment of the present invention is a method for manufacturing a display device, in which a layer to be a first bottom electrode and a second bottom electrode, a layer to be a first light-emitting layer and a second light-emitting layer, and a layer to be a first top electrode and a second top electrode are formed in this order and processed by a first etching to form first and second bottom electrodes, first and second light-emitting layers, and first and second top electrodes; and the first and second light-emitting layers are processed by a second etching so that the first top electrode has a region protruding beyond a side surface of the first light-emitting layer and the second top electrode has a region protruding beyond a side surface of the second light-emitting layer.

[0023] Alternatively, in the above aspect, the second etch may be more isotropic than the first etch.

[0024] Alternatively, in the above embodiment, after the second etching, a protective layer may be formed so that a gap is provided between the first upper electrode and the first light-emitting layer and between the second upper electrode and the second light-emitting layer.

[0025] Alternatively, in the above embodiment, a microlens array may be formed on the protective layer. [Effects of the Invention]

[0026] According to one embodiment of the present invention, a display device that displays a high-quality image can be provided. According to one embodiment of the present invention, a display device with high light extraction efficiency can be provided. According to one embodiment of the present invention, a display device with a high aperture ratio can be provided. According to one embodiment of the present invention, a high-definition display device can be provided. According to one embodiment of the present invention, a low-cost display device can be provided. According to one embodiment of the present invention, a highly reliable display device can be provided. According to one embodiment of the present invention, a novel display device can be provided.

[0027] According to one embodiment of the present invention, a method for manufacturing a display device that displays a high-quality image can be provided. According to one embodiment of the present invention, a method for manufacturing a display device with high light extraction efficiency can be provided. According to one embodiment of the present invention, a method for manufacturing a display device with a high aperture ratio can be provided. According to one embodiment of the present invention, a method for manufacturing a high-resolution display device can be provided. According to one embodiment of the present invention, a method for manufacturing a display device with simple steps can be provided. According to one embodiment of the present invention, a method for manufacturing a highly reliable display device can be provided. According to one embodiment of the present invention, a novel method for manufacturing a display device can be provided.

[0028] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0029] 1A and 1B are cross-sectional views showing examples of the configuration of a display device. 2A to 2D are cross-sectional views showing an example of a method for manufacturing a display device. 3A to 3C are cross-sectional views showing an example of a method for manufacturing a display device. FIG. 4 is a cross-sectional view showing an example of the configuration of a display device. 5A to 5D are cross-sectional views showing an example of a method for manufacturing a display device. 6A to 6D are cross-sectional views showing an example of a method for manufacturing a display device. 7A to 7D are cross-sectional views showing an example of a method for manufacturing a display device. FIG. 8 is a cross-sectional view showing an example of the configuration of a display device. FIG. 9 is a cross-sectional view showing an example of the configuration of a display device. FIG. 10 is a cross-sectional view showing an example of the configuration of a display device. 11A to 11C are cross-sectional views showing examples of the structure of a transistor. FIG. 12 is a cross-sectional view showing an example of the configuration of a display device. FIG. 13 is a cross-sectional view showing an example of the configuration of a display device. FIG. 14 is a cross-sectional view showing an example of the configuration of a display device. Fig. 15A is a block diagram showing an example of the configuration of a display device, and Fig. 15B is a circuit diagram showing an example of the configuration of a pixel. 16A is a top view illustrating an example of the structure of a transistor, and FIGS. 16B and 16C are cross-sectional views illustrating an example of the structure of a transistor. 17A to 17C are cross-sectional views showing examples of the configuration of a light-emitting element. Fig. 18A is a diagram explaining the classification of IGZO crystal structures, Fig. 18B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Fig. 18C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. 19A to 19D are diagrams showing an example of an electronic device. 20A and 20B are diagrams showing an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0030] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may include semiconductor devices.

[0031] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0032] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display element, a light-emitting element, or a load) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling its on and off states. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0033] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, etc., operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0034] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0035] Note that even when independent components are shown electrically connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, the term "electrically connected" as used in this specification also includes such cases where one conductive film has the functions of multiple components.

[0036] Furthermore, in this specification and the like, the term "node" can be rephrased as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration, device structure, etc. Furthermore, the term "node" can be rephrased as a terminal, wiring, etc.

[0037] Furthermore, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0038] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment, in the claims, etc. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment, in the claims, etc.

[0039] Furthermore, in this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in this specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0040] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0041] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," and the like are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0042] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0043] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply "OSs"). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, the term "OS transistor" can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0044] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0045] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0046] In this specification and the like, a void refers to a region containing gas.

[0047] The embodiments described in this specification will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in perspective views, top views, etc.

[0048] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size, aspect ratio, etc. are not necessarily limited to the size or aspect ratio. Note that the drawings are schematic illustrations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations, etc. may be included.

[0049] (Embodiment 1) In this embodiment, a display device according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings.

[0050] One aspect of the present invention relates to a display device in which pixels each having a light-emitting element such as an organic EL element are arranged in a matrix. In the display device of one aspect of the present invention, the light-emitting elements provided in adjacent pixels are separated by a gap containing a gas such as air. Light emitted from the light-emitting element in an oblique direction can be totally reflected by the gap. This prevents the light emitted from the light-emitting element from entering adjacent pixels.

[0051] In this specification and the like, light emitting elements provided in adjacent pixels are referred to as adjacent light emitting elements. The same applies to other elements provided in pixels.

[0052] In a display device according to one embodiment of the present invention, a light-emitting element includes a lower electrode, a light-emitting layer on the lower electrode, and an upper electrode on the light-emitting layer. The lower electrode, the light-emitting layer, and the upper electrode are provided separately for each light-emitting element. The upper electrode has a region that protrudes from a side surface of the light-emitting layer. This makes the width of the gap between adjacent light-emitting layers wider than the width of the gap between adjacent upper electrodes. The wider gap between adjacent light-emitting layers makes it easier for light emitted from the light-emitting layer to enter the gap.

[0053] <Display device configuration example 1> 1A is a cross-sectional view showing an example of the configuration of a display device 10. The display device 10 includes a transistor 11, an insulating layer 13 on the transistor 11, a light-emitting element 20 on the insulating layer 13, a protective layer 43 on the light-emitting element 20, a microlens array 45 on the protective layer 43, an adhesive layer 47 on the microlens array 45, colored layers 55R, 55G, and 55B, and a light-shielding layer 49 on the adhesive layer 47, an insulating layer 51 on the colored layers 55R, 55G, and 55B, and the light-shielding layer 49, and a substrate 53 on the insulating layer 51. The microlens array 45, the colored layers 55R, 55G, and 55B, and the light-shielding layer 49 are bonded together by the adhesive layer 47.

[0054] In this specification and the like, for example, when it is said that "B is on A" or "B is below A," A and B do not necessarily have to have an area where they contact each other.

[0055] In addition, in this specification and the like, the term "element" can sometimes be replaced with "device." For example, a light-emitting element can be called a light-emitting device.

[0056] Furthermore, in this specification and the like, when describing matters common to the colored layer 55R, the colored layer 55G, and the colored layer 55B, or when there is no need to distinguish between the three, they may be simply referred to as "colored layer 55." The same applies to other elements.

[0057] The light-emitting element 20 has a lower electrode 21, a hole injection layer 31, a light-emitting layer 33, an electron injection layer 35, and an upper electrode 25. Here, the hole injection layer 31, the light-emitting layer 33, and the electron injection layer 35 are collectively referred to as an EL layer 30.

[0058] The light-emitting element 20 can be a top-emission type light-emitting element. When the light-emitting element 20 is a top-emission type light-emitting element, the lower electrode 21 has a function of reflecting visible light, and the upper electrode 25 has a function of transmitting visible light. The lower electrode 21 also functions as a pixel electrode of the display device 10.

[0059] The hole injection layer 31 contains a material having a hole injection property. Here, a layer containing a material having a hole transport property (hole transport layer) can be provided between the hole injection layer 31 and the light emitting layer 33.

[0060] The electron injection layer 35 contains a material having electron injection properties. Here, a layer containing a material having electron transport properties (electron transport layer) can be provided between the light emitting layer 33 and the electron injection layer 35.

[0061] Here, the hole injection layer 31 and the electron injection layer 35 may be interchanged. That is, the electron injection layer 35, the light-emitting layer 33, and the hole injection layer 31 may be stacked in this order on the lower electrode 21. In this case, for example, the electron injection layer 35, the electron transport layer, the light-emitting layer 33, the hole transport layer, and the hole injection layer 31 may be stacked in this order on the lower electrode 21. In the following description, the hole injection layer 31, the light-emitting layer 33, and the electron injection layer 35 are assumed to be stacked in this order on the lower electrode 21. However, the following description can be referred to even in the case of a configuration in which the electron injection layer 35, the light-emitting layer 33, and the hole injection layer 31 are stacked in this order on the lower electrode 21 by, for example, replacing "holes" with "electrons" and "electrons" with "holes."

[0062] As shown in FIG. 1A, the lower electrode 21, the hole injection layer 31, the light emitting layer 33, the electron injection layer 35, and the upper electrode 25 can be separated for each light emitting element 20.

[0063] The display device 10 includes a pixel 60R, a pixel 60G, and a pixel 60B. The pixel 60R is provided with a colored layer 55R, the pixel 60G is provided with a colored layer 55G, and the pixel 60B is provided with a colored layer 55B.

[0064] The light-emitting layer 33 of the pixel 60R, the light-emitting layer 33 of the pixel 60G, and the light-emitting layer 33 of the pixel 60B can emit light of the same color. For example, these light-emitting layers 33 can all emit white light. In this case, the light-emitting element 20 can have, for example, a single structure or a tandem structure. The single structure and the tandem structure will be described in detail later.

[0065] The coloring layer 55 can change the hue of light that passes through it. For example, the hue of light that passes through the coloring layer 55R can be red, the hue of light that passes through the coloring layer 55G can be green, and the hue of light that passes through the coloring layer 55B can be blue. Note that the coloring layer 55 may change the hue of the light that passes through it to cyan, magenta, yellow, or other hues.

[0066] A full color display can be achieved by providing the colored layers 55R, 55G, and 55B, for example, in the display device 10. The display device 10 may have pixels 60 in which no colored layer 55 is provided.

[0067] Materials that can be used for the colored layer 55 include metal materials, resin materials, and resin materials containing pigments or dyes.

[0068] The transistor 11 is provided in each of the pixels 60R, 60G, and 60B. Here, conductive layers 15 and 17 are embedded in the insulating layer 13, and the transistor 11 is electrically connected to the lower electrode 21 via the conductive layers 15 and 17.

[0069] Here, the conductive layer 15 functions as, for example, a wiring, and the conductive layer 17 functions as, for example, a plug for electrically connecting the conductive layer 15 and the lower electrode 21.

[0070] In this specification and the like, the wiring and the plug electrically connected to the wiring may be integral with each other, that is, a part of the conductive layer may function as the wiring and another part may function as the plug.

[0071] A light-shielding layer 49 is provided at the boundary between adjacent pixels 60. This makes it possible to prevent light of different colors from mixing, thereby enabling the display device 10 to display a high-quality image. Note that, although the present embodiment has been described with reference to a configuration in which the light-shielding layer 49 is provided, the present invention is not limited to this, and a configuration in which the light-shielding layer 49 is not provided may also be used.

[0072] The protective layer 43 is formed on the upper electrode 25. The protective layer 43 can be an insulating layer, and for example, an oxide film, a nitride film, or an oxynitride film can be used. The oxide film can be a layer containing silicon oxide, aluminum oxide, or hafnium oxide. The nitride film can be a layer containing silicon nitride or aluminum nitride. The oxynitride film can be a layer containing silicon oxynitride, silicon nitride oxide, aluminum oxynitride, or aluminum nitride oxide.

[0073] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0074] The protective layer 43 may be a semiconductor layer, for example, a layer containing a metal oxide (also referred to as IGZO) containing In, Ga, and Zn. The protective layer 43 may be a conductive layer, for example, a layer containing a light-transmitting conductive material. As will be described in detail later, examples of the light-transmitting conductive material include conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide doped with gallium, or graphene. As the light-transmitting conductive material, an oxide conductor may be used.

[0075] Furthermore, the protective layer 43 may have a laminated structure of two or more layers. For example, it may have a laminated structure of an insulating layer and a semiconductor layer or a conductive layer, or it may have a laminated structure of a layer containing silicon nitride and a layer containing metal oxide. Specifically, the protective layer 43 may have a two-layer laminated structure, for example, where the lower layer is a layer containing silicon nitride and the upper layer is a layer containing metal oxide.

[0076] The protective layer 43 is preferably a layer that is difficult for impurities such as water and oxygen to diffuse into, or a layer that can capture (also called gettering) impurities such as water and oxygen. This can prevent impurities from entering the light-emitting element 20, specifically, for example, the EL layer 30. This can improve the reliability of the display device 10.

[0077] Here, the protective layer 43 is preferably formed by a method with low coverage, such as a method with lower coverage than atomic layer deposition (ALD). For example, the protective layer 43 is formed by sputtering or chemical vapor deposition (CVD). As a result, the openings separating adjacent light-emitting elements 20 are not covered by the protective layer 43, and gaps 40 are formed.

[0078] 1B is an enlarged view of a region 150 shown in FIG. 1A. As shown in FIG. 1B, the protective layer 43 may extend below the upper electrode 25. Also, a gap 42 may be formed between the protective layer 43 and the upper electrode 25.

[0079] The shorter the distance between the upper electrodes 25, the easier it is to form the voids 40. For example, when the distance is 1 μm or less, preferably 500 nm or less, and more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm, the voids 40 can be suitably formed.

[0080] The void 40 contains, for example, one or more selected from air, nitrogen, oxygen, carbon dioxide, and a Group 18 element. The void 40 may also contain, for example, a gas used when forming the upper electrode 25. For example, when the protective layer 43 is formed by sputtering, the void 40 may contain a Group 18 element (typically, helium, neon, argon, xenon, krypton, etc.). When the void 40 contains a gas, the gas can be identified by gas chromatography or the like. When the upper electrode 25 is formed by sputtering, the gas used during sputtering may also be contained in the film of the upper electrode 25. In this case, when the upper electrode 25 is analyzed by energy dispersive X-ray analysis (EDX analysis), elements such as argon may be detected. The void 42 may also contain the same gas as the gas contained in the void 40.

[0081] When the refractive index of the void 40 is lower than the refractive index of the light-emitting layer 33, the refractive index of the electron injection layer 35, or the refractive index of the upper electrode 25, light 61 emitted from the light-emitting layer 33 and incident on the interface between the light-emitting layer 33 and the void 40, the interface between the electron injection layer 35 and the void 40, or the interface between the upper electrode 25 and the void 40 is totally reflected. This prevents the light 61 from entering an adjacent pixel 60. Specifically, for example, the light 61 emitted from the light-emitting layer 33 provided in pixel 60G can be prevented from entering pixel 60R or pixel 60B. This prevents light of different colors from mixing, allowing the display device 10 to display high-quality images.

[0082] 1A, the upper electrode 25 has a region 63 that protrudes from the side surface of the light-emitting layer 33. That is, when viewed from above, the light-emitting layer 33 is formed at a position more inward than the upper electrode 25. With this configuration, the width of the gap 40 between adjacent light-emitting layers 33 can be made wider than the width of the gap 40 between adjacent upper electrodes 25. Therefore, for example, it is possible to prevent the gap 40 from being embedded in the protective layer 43, while making it easier for light emitted from the light-emitting layer 33 to enter the gap 40. Therefore, the display device 10 can be a highly reliable display device that can display high-quality images.

[0083] The upper electrode 25 may have a region protruding from the side surface of the electron injection layer 35 in addition to a region protruding from the side surface of the light-emitting layer 33. This allows light emitted from the light-emitting layer 33 to easily enter the gap 40. The upper electrode 25 may also have a region protruding from the side surface of the hole injection layer 31 and the side surface of the lower electrode 21. For example, when the upper electrode 25 has a region protruding from the side surface of the lower electrode 21, the width of the gap 40 between adjacent lower electrodes 21 becomes wider than the width of the gap 40 between adjacent upper electrodes 25. This makes it possible to prevent, for example, adjacent lower electrodes 21 from coming into contact inside the gap 40 and causing an electrical short circuit. This can therefore improve the reliability of the display device 10.

[0084] Here, the void 40 can be configured to penetrate into the insulating layer 13. In this configuration, the thickness of the insulating layer 13 in the region where the upper surface of the insulating layer 13 contacts the lower surface of the void 40 is thinner than the thickness of the insulating layer 13 in the region overlapping with the light-emitting layer 33. Furthermore, the thickness of the insulating layer 13 in the region where the upper surface of the insulating layer 13 contacts the lower surface of the void 40 can be thinner than the thickness of the insulating layer 13 in the region overlapping with the lower electrode 21, the hole injection layer 31, or the electron injection layer 35.

[0085] When the refractive index of the adhesive layer 47 is lower than the refractive index of the microlenses included in the microlens array 45, the microlenses can condense the light emitted by the light-emitting layer 33. This prevents the light from entering the light-shielding layer 49. This increases the light extraction efficiency of the display device 10. Therefore, a bright image can be viewed, particularly when a user of the display device 10 views the display surface of the display device 10 from directly in front of the display surface.

[0086] The following describes materials that can be used for elements such as those shown in FIG. 1A.

[0087] [Insulating layer] Each insulating layer is made of a single layer or a stack of layers of a material selected from aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. Alternatively, a mixture of two or more materials selected from oxide materials, nitride materials, oxynitride materials, and nitride oxide materials may be used.

[0088] In this specification, "nitride oxide" refers to a compound containing more nitrogen than oxygen. "Oxynitride" refers to a compound containing more oxygen than nitrogen. The content of each element can be measured, for example, by Rutherford Backscattering Spectrometry (RBS).

[0089] Furthermore, CMP may be performed on the surface of the insulating layer, etc. By performing CMP, unevenness on the sample surface can be reduced, and the coverage of the insulating layer and conductive layer to be formed subsequently can be improved.

[0090] [Conductive layer] Conductive materials that can be used for conductive layers such as the gate, source, and drain of a transistor, as well as various wirings, plugs, and electrodes that constitute a display device, include metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium (Hf), vanadium (V), niobium (Nb), manganese, magnesium, zirconium, and beryllium, alloys containing the above metal elements, and alloys combining the above metal elements. Semiconductors, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides, such as nickel silicide, may also be used. The method for forming the conductive material is not particularly limited, and various formation methods, such as vapor deposition, CVD, sputtering, and spin coating, may be used.

[0091] Examples of conductive materials that can be used for the conductive layer include conductive materials containing oxygen, such as indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon oxide has been added. Also, conductive materials containing nitrogen, such as titanium nitride, tantalum nitride, and tungsten nitride, can be used. A layered structure can also be formed by appropriately combining conductive materials containing oxygen, conductive materials containing nitrogen, and materials containing the aforementioned metal elements.

[0092] The conductive material that can be used for the conductive layer may have a single-layer structure or a stacked structure of two or more layers. For example, there are a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is stacked on an aluminum layer, a two-layer structure in which a titanium layer is stacked on a titanium nitride layer, a two-layer structure in which a tungsten layer is stacked on a titanium nitride layer, a two-layer structure in which a tungsten layer is stacked on a tantalum nitride layer, and a three-layer structure in which a titanium layer is stacked on an aluminum layer and a titanium layer is further stacked on the titanium layer. Furthermore, an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used as the conductive material.

[0093] When the light-emitting element 20 is a top-emission type light-emitting element, the lower electrode 21 is preferably formed using a conductive material that efficiently reflects light emitted from the light-emitting layer 33. The configuration of the lower electrode 21 is not limited to a single layer, and it may also have a stacked structure of multiple layers. For example, when the lower electrode 21 is used as an anode, a layer in contact with the hole injection layer 31 may be a light-transmitting layer such as indium tin oxide, and a highly reflective layer (such as aluminum, an alloy containing aluminum, or silver) may be provided in contact with that layer. Furthermore, by forming the upper electrode 25 using a light-transmitting conductive material, light emitted from the light-emitting layer 33 can be efficiently extracted to the outside of the display device 10.

[0094] Examples of conductive materials that reflect visible light include metal materials such as aluminum, gold, platinum, silver, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, and palladium, as well as alloys containing these metal materials. Lanthanum, neodymium, germanium, and the like may be added to the above metal materials and / or alloys. Furthermore, the conductive material may be formed using alloys containing aluminum (aluminum alloys), such as an alloy of aluminum and titanium, an alloy of aluminum and nickel, and an alloy of aluminum and neodymium, or an alloy containing silver, such as an alloy of silver and copper, an alloy of silver, palladium, and copper, or an alloy of silver and magnesium. Silver-copper alloys are preferred because of their high heat resistance. Furthermore, a metal film or alloy film and a metal oxide film may be stacked. For example, stacking a metal film or a metal oxide film in contact with an aluminum alloy film can suppress oxidation of the aluminum alloy film. Other examples of metal films and metal oxide films include titanium and titanium oxide. As described above, a light-transmitting conductive film and a film made of a metal material may be stacked. For example, a laminated film of silver and indium tin oxide, a laminated film of an alloy of silver and magnesium and indium tin oxide, or the like can be used.

[0095] Examples of light-transmitting conductive materials include conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide doped with gallium, or graphene. Alternatively, oxide conductors can be used as light-transmitting conductive materials. Metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, and titanium, and alloy materials containing these metal materials can be used. Alternatively, nitrides of these metal materials (e.g., titanium nitride) can be used. When using metal materials or alloy materials (or their nitrides), they should be thin enough to have light-transmitting properties. A stacked film of the above materials can be used as a conductive layer. For example, a stacked film of an alloy of silver and magnesium and indium tin oxide is preferable because it can enhance conductivity. These can also be used for conductive layers such as various wirings and electrodes constituting a display device, and conductive layers (conductive layers functioning as a lower electrode or an upper electrode) of light-emitting elements.

[0096] Here, an oxide conductor, which is a type of metal oxide, will be described. In this specification and the like, an oxide conductor may be referred to as an OC (Oxide Conductor). For example, an oxide conductor can be formed by forming oxygen vacancies in a metal oxide (typically IGZO), which is an oxide containing at least indium or zinc, and adding hydrogen to the oxygen vacancies to form donor levels near the conduction band. As a result, the metal oxide becomes highly conductive and becomes a conductor. A metal oxide that has become a conductor can be called an oxide conductor. In general, metal oxides that function as semiconductors (oxide semiconductors) have a large energy gap and are therefore transparent to visible light. On the other hand, an oxide conductor is a metal oxide that has a donor level near the conduction band. Therefore, an oxide conductor is less affected by absorption due to the donor level and has the same level of transparency to visible light as an oxide semiconductor.

[0097] [EL layer] The layers of the EL layer 30 may be made of either low molecular weight compounds or high molecular weight compounds, and may also contain inorganic compounds. The layers constituting the EL layer 30 may be formed by a deposition method (including vacuum deposition), a transfer method, a printing method, a coating method, or the like.

[0098] Specifically, the hole injection layer 31 of the EL layer 30 includes a material having a hole transport property. For example, an aromatic amine compound or an organic compound having a π-electron-rich heteroaromatic ring can be used as the material having a hole transport property.

[0099] Compounds with an aromatic amine skeleton, carbazole derivatives, aromatic hydrocarbons, aromatic hydrocarbons with a vinyl group, and polymeric compounds (oligomers, dendrimers, polymers, etc.) can be used as materials with hole transport properties for the composite material. In addition, the hole mobility can be 1×10 -6 cm 2 A material having a Vs value of 1 / Vs or more can be suitably used as a material having hole transport properties.

[0100] For example, a substance having any one of a carbazole skeleton, a dibenzofuran skeleton, a dibenzothiophene skeleton, and an anthracene skeleton can be suitably used as a material having hole transport properties for the composite material. Furthermore, a substance having an aromatic amine with a substituent containing a dibenzofuran ring or a dibenzothiophene ring, an aromatic monoamine with a naphthalene ring, or an aromatic monoamine in which a 9-fluorenyl group is bonded to the nitrogen of the amine via an arylene group can be used as a material having hole transport properties for the composite material. The use of a substance having an N,N-bis(4-biphenyl)amino group can improve the reliability of the light-emitting element.

[0101] The electron injection layer 35 of the EL layer 30 includes a material having electron transport properties. For example, a compound having an unshared electron pair and an electron-deficient heteroaromatic ring can be used as the material having electron transport properties. Specifically, a compound having at least one of a pyridine ring, a diazine ring (pyrimidine ring, pyrazine ring, pyridazine ring), and a triazine ring can be used.

[0102] The organic compound having an unshared electron pair preferably has a lowest unoccupied molecular orbital (LUMO) of -3.6 eV to -2.3 eV. Generally, the highest occupied molecular orbital (HOMO) level and the LUMO level of an organic compound can be estimated by cyclic voltammetry (CV), photoelectron spectroscopy, optical absorption spectroscopy, inverse photoelectron spectroscopy, or the like.

[0103] Examples of organic compounds with lone electron pairs include 4,7-diphenyl-1,10-phenanthroline (abbreviated as BPhen), 2,9-bis(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviated as NBPhen), diquinoxalino[2,3-a:2',3'-c]phenazine (abbreviated as HATNA), and 2,4,6-tris[3'-(pyridin-3-yl)biphenyl-3-yl]-1,3,5-triazine (abbreviated as TmPPPyTz). NBPhen has a higher glass transition temperature (Tg) and superior heat resistance compared to BPhen. The chemical formulas of BPhen, NBPhen, HANTA, and TmPPPyTz are shown below.

[0104] [ka]

[0105] Furthermore, for example, copper phthalocyanine, which has an odd number of electrons, can be used as the organic compound having an unshared electron pair.

[0106] The electron injection layer 35 may also contain a metal. For example, the electron injection layer 35 may contain an organic compound having the lone electron pair and a metal. Here, it is preferable that the sum of the number of electrons in the organic compound and the number of electrons in the metal is an odd number. For example, the electron injection layer 35 preferably contains NBPhen and silver. The molar ratio of the metal to 1 mole of the organic compound is preferably 0.1 to 10, more preferably 0.2 to 2, and even more preferably 0.2 to 0.8.

[0107] This allows the organic compound having an unshared electron pair to interact with the metal to form a Singly Occupied Molecular Orbital (SOMO). Furthermore, when electrons are injected from the upper electrode 25 into the electron injection layer, the barrier between them can be reduced. Furthermore, since metals have low reactivity with water and oxygen, the moisture resistance of the light-emitting element 20 can be improved.

[0108] [Adhesive layer] The adhesive layer 47 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as epoxy resin, is preferable. Alternatively, a two-component resin may be used. Alternatively, an adhesive sheet or the like may be used.

[0109] [Light blocking layer] Materials that can be used for the light-shielding layer include carbon black, titanium black, metals, metal oxides, and composite oxides containing solid solutions of multiple metal oxides. The light-shielding layer may be a film containing a resin material or a thin film of an inorganic material such as a metal. The light-shielding layer may also be a laminated film of films containing the material of the colored layer. For example, a laminated structure may be used in which a film containing the material used for a colored layer that transmits light of one color and a film containing the material used for a colored layer that transmits light of another color. Using a common material for the colored layer and the light-shielding layer is preferred because it allows for the use of common equipment and simplifies the process.

[0110] <Example of a display device manufacturing method_1> An example of a method for manufacturing the display device 10 shown in FIG. 1A will be described below with reference to the drawings.

[0111] The insulating layers, semiconductor layers, and conductive layers for forming electrodes and wiring that constitute the display device can be formed using a sputtering method, a CVD method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, a plasma enhanced ALD (PEALD) method, or the like. The CVD method may be a plasma enhanced chemical vapor deposition (PECVD) method or a thermal CVD method. An example of a thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0112] Furthermore, insulating layers, semiconductor layers, and conductive layers for forming electrodes and wiring that constitute the display device may be formed by methods such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, slit coating, roll coating, curtain coating, and knife coating.

[0113] The PECVD method can produce high-quality films at relatively low temperatures. When using a film formation method that does not use plasma during film formation, such as the MOCVD method, the ALD method, or the thermal CVD method, damage to the surface on which the film is formed is less likely to occur. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, film formation methods that do not use plasma do not cause such plasma damage, thereby increasing the yield of semiconductor devices. Furthermore, since plasma damage does not occur during film formation, films with fewer defects can be obtained.

[0114] When forming an oxide semiconductor by sputtering, the chamber of the sputtering device is maintained at a high vacuum (5×10) using an adsorption-type vacuum exhaust pump such as a cryopump to remove as much water as possible, which is an impurity for the oxide semiconductor. -7 Pa to 1 x 10 -4 In particular, when the sputtering device is in standby mode, it is preferable to evacuate the chamber to a partial pressure of 1×10 Pa or less of the gas molecules corresponding to HO (gas molecules corresponding to m / z=18). -4 Pa or less, and 5×10 -5 The film formation temperature is preferably from room temperature to 500°C, more preferably from room temperature to 300°C, and even more preferably from room temperature to 200°C.

[0115] In addition, the sputtering gas must be highly purified. For example, oxygen gas and argon gas used as sputtering gases are highly purified to have a dew point of −40° C. or lower, preferably −80° C. or lower, more preferably −100° C. or lower, and even more preferably −120° C. or lower, so that moisture and the like can be prevented from being introduced into the oxide semiconductor film as much as possible.

[0116] When an insulating layer, a conductive layer, a semiconductor layer, or the like is formed by sputtering, oxygen can be supplied to the layer to be formed by using a sputtering gas containing oxygen. The more oxygen contained in the sputtering gas, the more oxygen is likely to be supplied to the layer to be formed.

[0117] When processing a layer (thin film) constituting a display device, it can be processed using a photolithography method or the like. Alternatively, an island-shaped layer may be formed by a film formation method using a masking mask. Alternatively, the layer may be processed by a nanoimprint method, a sandblasting method, a lift-off method or the like. Photolithography methods include a method in which a resist mask is formed on the layer (thin film) to be processed, and a method in which a portion of the layer (thin film) is selectively removed using the resist mask as a mask, and then the resist mask is removed, and a method in which a photosensitive layer is formed, and then the layer is processed into a desired shape by exposure and development.

[0118] When light is used in photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet light (EUV) or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0119] The layer (thin film) can be removed (etched) by dry etching, wet etching, etc. These etching methods may also be used in combination.

[0120] 1A, a conductive layer 15 is first formed so as to be electrically connected to a transistor 11. Next, an insulating layer 13 is formed on the transistor 11 and the conductive layer 15. After that, an opening reaching the conductive layer 15 is formed in the insulating layer 13, and a conductive layer 17 is formed in the opening (FIG. 2A).

[0121] Next, layer 21A to become lower electrode 21, layer 31A to become hole injection layer 31, layer 33A to become light-emitting layer 33, layer 35A to become electron injection layer 35, and layer 25A to become upper electrode 25 are sequentially deposited on insulating layer 13 and conductive layer 17 ( FIG. 2B ). Layers 21A, 31A, 33A, 35A, and 25A can be deposited by, for example, vapor deposition or sputtering. However, other deposition methods may be used as appropriate. Furthermore, if a hole transport layer is to be provided on hole injection layer 31, the layer to become the hole transport layer is deposited on layer 31A, and then layer 33A is deposited. Furthermore, if an electron transport layer is to be provided on light-emitting layer 33, layer 33A is deposited first, and then the layer to become the electron transport layer is deposited.

[0122] Next, the layers 25A, 35A, 33A, 31A, and 21A are processed using an etching method or the like. Specifically, for example, after a resist mask is formed on the layer 25A, the layers 25A, 35A, 33A, 31A, and 21A are processed using an etching method or the like. As a result, for example, the island-shaped upper electrode 25, electron injection layer 35, light-emitting layer 33, hole injection layer 31, and lower electrode 21 can be formed ( FIG. 2C ).

[0123] 2C, the insulating layer 13 may also be etched during the etching process. As a result, the thickness of the insulating layer 13 in the region overlapping the processed region of the layer 21A may become thinner than the thickness of the insulating layer 13 in the region overlapping the lower electrode 21.

[0124] As described above, in one embodiment of the present invention, a metal mask, specifically a fine metal mask, is not used when separately forming EL layers. Therefore, one embodiment of the present invention can be a method for manufacturing a display device with high productivity.

[0125] When the light-emitting elements 20 are formed using a fine metal mask, it is difficult to make the distance between the light-emitting elements 20 20 μm or less due to restrictions on dimensional accuracy. On the other hand, in the method for manufacturing a display device according to one embodiment of the present invention, the light-emitting elements 20 are formed without using a fine metal mask, and therefore the distance between adjacent light-emitting elements 20 can be made 20 μm or less. For example, the distance between adjacent electron-injection layers 35 can be made 20 μm or less. Specifically, the distance between adjacent light-emitting elements 20 can be made 0.5 μm to 15 μm, preferably 0.5 μm to 10 μm, and more preferably 0.5 μm to 5 μm. Therefore, improvement in pixel aperture ratio, high definition, miniaturization, and the like can be achieved.

[0126] In this specification, etc., a device fabricated using a metal mask or FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or FMM may be referred to as a device with an MML (metal maskless) structure.

[0127] When the distance between the light-emitting elements 20 is set to 100 nm or less, typically 90 nm or less, an optimal exposure device must be used. Examples of the exposure device that can be used include a stepper and a scanner. Examples of wavelengths of the light source that can be used in the exposure device include 13 nm (EUV), 157 nm (F2), 193 nm (ArF), 248 nm (KrF), 308 nm (XeCl), 365 nm (i-line), and 436 nm (g-line). By using a light source with a short wavelength, a display device with high definition or finer details can be obtained.

[0128] The electron injection layer 35, the light-emitting layer 33, the hole injection layer 31, and the lower electrode 21 are then etched in the horizontal direction. As a result, the upper electrode 25 has a region 63 that protrudes from the side surfaces of the light-emitting layer 33 and the like (FIG. 2D). The horizontal etching can be performed, for example, by highly isotropic etching. For example, the etching of the layers 25A, 35A, 33A, 31A, and 21A shown in FIGS. 2B and 2C is referred to as the first etching, and the etching shown in FIGS. 2C and 2D is referred to as the second etching. In this case, the second etching is preferably performed using a method that is less anisotropic than the first etching, i.e., more isotropic.

[0129] In this specification, for example, when etching layers 25A, 35A, 33A, 31A, and 21A by the first etching, layers 25A, 35A, 33A, 31A, and 21A do not have to be etched all at once. For example, different etching conditions may be used for each layer to be etched. Even in such a case, layers 25A, 35A, 33A, 31A, and 21A are all referred to as being etched by the first etching. The same applies to the second and subsequent etchings.

[0130] 2D, the insulating layer 13 may also be etched horizontally due to the horizontal etching of the electron injection layer 35, the light-emitting layer 33, the hole injection layer 31, and the lower electrode 21. The hole injection layer 31 and the lower electrode 21 may not be etched horizontally. In this case, the insulating layer 13 may not be etched horizontally. Furthermore, the electron injection layer 35 may not be etched horizontally.

[0131] Next, the protective layer 43 is formed. The protective layer 43 is preferably formed by a method with low coverage, for example, a method with lower coverage than the ALD method. For example, the protective layer 43 is formed by a sputtering method or a CVD method. As a result, the openings separating adjacent light-emitting elements 20 are not covered by the protective layer 43, and a gap 40 is formed (FIG. 3A).

[0132] Thereafter, a microlens array 45 is formed on the protective layer 43 (FIG. 3B). The microlens array 45 can be formed, for example, by forming a resist pattern by photolithography, and then performing a heat treatment to reflow the resist.

[0133] Next, a substrate 53 is prepared, an insulating layer 51 is formed on the substrate 53, a light-shielding layer 49 is formed on the insulating layer 51, and then colored layers 55R, 55G, and 55B are formed on the insulating layer 51 and the light-shielding layer 49 (FIG. 3C). Then, an adhesive layer 47 is formed on the colored layers 55R, 55G, 55B, and the light-shielding layer 49, and the microlens array 45 is bonded to the colored layers 55 and the light-shielding layer 49 by the adhesive layer 47. The adhesive layer 47 can be formed by a screen printing method, a dispensing method, or the like. In this manner, the display device 10 shown in FIG. 1A can be fabricated.

[0134] <Display device configuration example 2> FIG. 4 is a cross-sectional view showing an example of the configuration of a display device 10, which is a modification of the display device 10 shown in FIG. 1A. The display device 10 shown in FIG. 4 differs from the display device 10 shown in FIG. 1A in that a colored layer 55 is not provided in the pixel 60. In the display device 10 shown in FIG. 4, as the light-emitting layer 33, a light-emitting layer 33R is provided in the pixel 60R, a light-emitting layer 33G is provided in the pixel 60G, and a light-emitting layer 33B is provided in the pixel 60B. Note that a light-emitting element 20 having a light-emitting layer 33R is referred to as a light-emitting element 20R, a light-emitting element 20 having a light-emitting layer 33G is referred to as a light-emitting element 20G, and a light-emitting element 20 having a light-emitting layer 33B is referred to as a light-emitting element 20B.

[0135] The light-emitting layers 33R, 33G, and 33B may each have the function of emitting light of a different color. For example, the light-emitting layer 33R has the function of emitting red light, the light-emitting layer 33G has the function of emitting green light, and the light-emitting layer 33B has the function of emitting blue light. The light-emitting layers 33R, 33G, and 33B may each have the function of emitting light of a color such as cyan, magenta, or yellow. Although FIG. 1A shows three types of light-emitting layers 33, the display device 10 may have four or more types of light-emitting layers 33. For example, the display device 10 may have a light-emitting layer that emits white light in addition to the light-emitting layer 33R that emits red light, the light-emitting layer 33G that emits green light, and the light-emitting layer 33B that emits blue light.

[0136] A structure in which the light-emitting layer 33R, the light-emitting layer 33G, and the light-emitting layer 33B each emit light of a different color is said to be an SBS (Side By Side) structure for the light-emitting element 20. By using an SBS structure for the light-emitting element 20, the power consumption of the display device 10 can be reduced compared to when all the light-emitting layers 33 emit light of the same color.

[0137] <Example of a display device manufacturing method_2> An example of a method for manufacturing the display device 10 shown in Fig. 4 will be described below with reference to the drawings. Note that the description of steps common to the example of a method for manufacturing the display device 10 shown in Fig. 1A will be omitted as appropriate.

[0138] First, layers up to layer 31A are formed using the same method as shown in FIGS. 2A and 2B. Next, layer 33RA, which will become light-emitting layer 33R, is formed (FIG. 5A). Layer 33RA can be formed using the same film-forming method as layer 33A. Furthermore, when a hole transport layer is provided on hole injection layer 31, the layer that will become the hole transport layer is formed on layer 31A, and then layer 33RA is formed. Furthermore, when an electron transport layer is provided on light-emitting layer 33R, after layer 33RA is formed, the layer that will become the electron transport layer is formed.

[0139] Thereafter, the layer 140A is formed on the layer 33RA (FIG. 5B). The layer 140A can be formed using a wet film-forming method such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife printing, slit coating, roll coating, curtain coating, or knife coating. Note that other film-forming methods may also be used, and the above-mentioned film-forming methods, including vapor deposition, may be used as appropriate.

[0140] It is preferable to use a material that can be dissolved in a chemically stable solvent for the layer 140A. In particular, a material that can be dissolved in water or alcohol is suitable for use in the layer 140A. When forming the layer 140A, it is preferable to apply the material dissolved in a solvent such as water or alcohol by the wet film formation method described above, and then perform a heat treatment to evaporate the solvent. In this case, performing the heat treatment under a reduced pressure atmosphere is preferable because it allows the solvent to be removed at a low temperature in a short time, thereby reducing thermal damage to the layer 33RA.

[0141] Layer 140A can be made of an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin.

[0142] Next, the layer 140A, the layer 33RA, and the layer 31A are processed using an etching method or the like. Specifically, for example, after forming a resist mask on the layer 140A, the layer 140A, the layer 33RA, and the layer 31A are processed using an etching method or the like. As a result, for example, an island-shaped sacrificial layer 140, an emitting layer 33R, and a hole injection layer 31 can be formed ( FIG. 5C ). In other words, the layer 140A is a layer that becomes the sacrificial layer 140 on the emitting layer 33R.

[0143] Thereafter, layer 31B, which will become hole injection layer 31, layer 33GA, which will become light-emitting layer 33G, and layer 140B are deposited on layer 21A and sacrificial layer 140 (FIG. 5D). Layer 31B can be deposited by the same deposition method as layer 31A, layer 33GA can be deposited by the same deposition method as layer 33RA, and layer 140B can be deposited by the same deposition method as layer 140A. Layer 140B can be made of the same material as layer 140A. If a hole transport layer is to be provided on hole injection layer 31, the layer that will become the hole transport layer is deposited on layer 31B, and then layer 33GA is deposited. If an electron transport layer is to be provided on light-emitting layer 33G, layer 33GA is deposited first, and then the layer that will become the electron transport layer is deposited.

[0144] Next, the layer 140B, the layer 33GA, and the layer 31B are processed using an etching method or the like. Specifically, for example, after forming a resist mask on the layer 140B, the layer 140B, the layer 33GA, and the layer 31B are processed using an etching method or the like. As a result, for example, an island-shaped sacrificial layer 140, an emitting layer 33G, and a hole injection layer 31 can be formed ( FIG. 6A ). In other words, the layer 140B is a layer that becomes the sacrificial layer 140 on the emitting layer 33G.

[0145] Thereafter, layer 31C, which will become hole injection layer 31, layer 33BA, which will become light-emitting layer 33B, and layer 140C are deposited on layer 21A and sacrificial layer 140 (FIG. 6B). Layer 31C can be deposited using the same deposition method as layer 31A, layer 33BA can be deposited using the same deposition method as layer 33RA, and layer 140C can be deposited using the same deposition method as layer 140A. Layer 140C can be made of the same material as layer 140A. When a hole transport layer is provided on hole injection layer 31, the layer that will become the hole transport layer is deposited on layer 31C, and then layer 33BA is deposited. When an electron transport layer is provided on light-emitting layer 33B, layer 33BA is deposited first, and then the layer that will become the electron transport layer is deposited.

[0146] Next, the layer 140C, the layer 33BA, and the layer 31C are processed using an etching method or the like. Specifically, for example, after forming a resist mask on the layer 140C, the layer 140C, the layer 33BA, and the layer 31C are processed using an etching method or the like. As a result, for example, an island-shaped sacrificial layer 140, an emitting layer 33B, and a hole injection layer 31 can be formed (FIG. 6C). In other words, the layer 140C is a layer that becomes the sacrificial layer 140 on the emitting layer 33B.

[0147] Thereafter, the sacrificial layer 140 is removed to expose the upper surfaces of the light-emitting layers 33R, 33G, and 33B (FIG. 6D).

[0148] The sacrificial layer 140 can be removed by etching. At this time, it is preferable to use a method that causes as little damage as possible to the light-emitting layers 33R, 33G, and 33B. In particular, it is preferable to remove the sacrificial layer 140 by dissolving it in a solvent such as water or alcohol. As alcohol that can dissolve the sacrificial layer 140, various alcohols such as ethyl alcohol, methyl alcohol, isopropyl alcohol (IPA), or glycerin can be used.

[0149] After removing the sacrificial layer 140, it is preferable to perform a drying treatment to remove water contained inside the light-emitting layers 33R, 33G, and 33B and water adsorbed on their surfaces. For example, it is preferable to perform a heat treatment in an inert gas atmosphere or a reduced-pressure atmosphere. The heat treatment can be performed at a substrate temperature of 50°C or higher and 200°C or lower, preferably 60°C or higher and 120°C or lower, and more preferably 70°C or higher and 100°C or lower. A reduced-pressure atmosphere is preferable because it allows drying at a lower temperature.

[0150] Through the above steps, for example, the light-emitting layer 33R, the light-emitting layer 33G, and the light-emitting layer 33B can be separately formed. In this manner, in one embodiment of the present invention, for example, a metal mask, specifically a fine metal mask, is not used when separately forming the light-emitting layer 33R, the light-emitting layer 33G, and the light-emitting layer 33B. Therefore, one embodiment of the present invention can be a method for manufacturing a display device with high productivity. Note that the light-emitting layers 33 do not necessarily need to be formed in the order of the light-emitting layer 33R, the light-emitting layer 33G, and the light-emitting layer 33B, and can be formed in any order. For example, the light-emitting layer 33G may be formed after the light-emitting layer 33B, and then the light-emitting layer 33R may be formed.

[0151] When the light-emitting elements 20 are formed using a fine metal mask, it is difficult to make the distance between the light-emitting elements 20 20 μm or less due to restrictions on dimensional accuracy. On the other hand, in the method for manufacturing a display device according to one embodiment of the present invention, the light-emitting elements 20 are formed without using a fine metal mask, and therefore the distance between adjacent light-emitting elements 20 can be made 20 μm or less. For example, the distance between adjacent electron-injection layers 35 can be made 20 μm or less. Specifically, the distance between adjacent light-emitting elements 20 can be made 0.5 μm to 15 μm, preferably 0.5 μm to 10 μm, and more preferably 0.5 μm to 5 μm. Therefore, improvement in pixel aperture ratio, high definition, miniaturization, and the like can be achieved.

[0152] When the distance between the light-emitting elements 20 is set to 100 nm or less, typically 90 nm or less, an optimal exposure device must be used. Examples of the exposure device that can be used include a stepper and a scanner. Examples of wavelengths of the light source that can be used in the exposure device include 13 nm (EUV), 157 nm (F2), 193 nm (ArF), 248 nm (KrF), 308 nm (XeCl), 365 nm (i-line), and 436 nm (g-line). By using a light source with a short wavelength, a display device with high definition or finer details can be obtained.

[0153] Next, a layer 35A to become the electron injection layer 35 and a layer 25A to become the upper electrode 25 are formed on the light-emitting layers 33R, 33G, 33B, and 21A (FIG. 7A). The layers 35A and 25A can be formed by, for example, a vapor deposition method or a sputtering method. However, the method is not limited to these, and the above-mentioned film formation methods can be used as appropriate.

[0154] Thereafter, the layer 25A, the layer 35A, and the layer 21A are processed using an etching method or the like. Specifically, for example, a resist mask is formed on the layer 25A, and then the layer 25A, the layer 35A, and the layer 21A are processed using an etching method or the like. As a result, for example, an island-shaped upper electrode 25, an electron injection layer 35, and a lower electrode 21 can be formed (FIG. 7B).

[0155] 7B, when etching layer 21A, insulating layer 13 may also be etched. As a result, the thickness of insulating layer 13 in the region overlapping with the processed region of layer 21A may become thinner than the thickness of insulating layer 13 in the region overlapping with lower electrode 21.

[0156] Next, the electron injection layer 35, the light-emitting layer 33, the hole injection layer 31, and the lower electrode 21 are etched horizontally in the same manner as shown in Figure 2D. Thereafter, a protective layer 43 and a microlens array 45 are formed in the same manner as shown in Figures 3A and 3B (Figure 7C). As described above, forming the protective layer 43 forms the air gap 40.

[0157] Thereafter, a substrate 53 is prepared, an insulating layer 51 is formed on the substrate 53, and a light-shielding layer 49 is formed on the insulating layer 51 (FIG. 7D). Thereafter, an adhesive layer 47 is formed on the insulating layer 51 and the light-shielding layer 49, and the microlens array 45 is bonded to the insulating layer 51 and the light-shielding layer 49 by the adhesive layer 47. The adhesive layer 47 can be formed by a screen printing method, a dispensing method, or the like. In this manner, the display device 10 shown in FIG. 4 can be fabricated.

[0158] <Display device configuration example 3> FIG. 8 is a cross-sectional view showing an example of the configuration of a display device 10, which is a modification of the display device 10 shown in FIG. 1A. The display device 10 shown in FIG. 8 differs from the display device 10 shown in FIG. 1A in that it does not have a microlens array 45. Since the display device 10 does not have a microlens array 45, the manufacturing process of the display device 10 can be simplified. This reduces the manufacturing cost of the display device 10 and increases the yield. As a result, the price of the display device 10 can be reduced. Note that display devices 10 shown in other than FIG. 1A, such as FIG. 4, can also be configured not to have a microlens array 45.

[0159] Fig. 9 is a cross-sectional view showing an example of the configuration of a display device 10, which is a modification of the display device 10 shown in Fig. 1A. The display device 10 shown in Fig. 9 differs from the display device 10 shown in Fig. 1A in that a partition wall 19 is provided on the insulating layer 13. The partition wall 19 can be, for example, an insulating layer.

[0160] The partition wall 19 is provided between adjacent pixels 60 so as to cover the edge of the lower electrode 21. In the display device 10 shown in FIG. 9, the hole injection layer 31 is provided on the lower electrode 21 and on the partition wall 19. Note that the hole injection layer 31, the light-emitting layer 33, and the electron injection layer 35 may not have an area overlapping with the partition wall 19. Furthermore, the upper electrode 25 may not have an area overlapping with the partition wall 19.

[0161] By providing the partition 19, it is possible to prevent electrical short circuits that may occur between adjacent lower electrodes 21, etc. On the other hand, if a configuration is adopted in which the partition 19 is not provided, the aperture ratio can be increased. For example, in the case of a configuration in which the partition 19 is not provided, the aperture ratio of the pixel can be set to 70% or more, preferably 80% or more, and more preferably 90% or more.

[0162] 9, when the layer that will become the hole injection layer 31 is etched into, for example, an island shape, the partition wall 19 may be partially etched. Furthermore, when the electron injection layer 35, the light-emitting layer 33, and the hole injection layer 31 are etched horizontally, the partition wall 19 may also be etched horizontally. As a result, the voids 40 can be configured to penetrate the partition wall 19.

[0163] 9, the lower electrode 21 is not etched in the horizontal direction. Since the display device 10 shown in Fig. 9 is provided with the partition wall 19, even if a part of the upper electrode 25 enters the void 40, the upper electrode 25 and the lower electrode 21 will not come into contact with each other inside the void 40 and will not be electrically short-circuited.

[0164] Fig. 10 is a cross-sectional view showing an example of the configuration of the display device 10. Fig. 10 is a cross-sectional view showing an example of the configuration of layers below the insulating layer 13 of the display device 10 shown in Fig. 1A.

[0165] 10, the display device 10 includes a transistor 80 and an element isolation layer 86 on a substrate 81. In addition, on the substrate 81, an insulating layer 131, an insulating layer 133, an insulating layer 135, and an insulating layer 137 are provided.

[0166] The display device 10 also has an insulating layer 71 on the insulating layer 137 and an insulating layer 13 on the insulating layer 71. Note that, although the configuration in which the insulating layer 71 is provided is illustrated in Fig. 10, the present invention is not limited to this. For example, a configuration in which the insulating layer 13 is provided on the insulating layer 137 without providing the insulating layer 71 may also be used.

[0167] Furthermore, the display device 10 has a conductive layer 67 and a conductive layer 69. The conductive layer 67 is embedded in the insulating layer 131, the insulating layer 133, the insulating layer 135, and the insulating layer 137, and the conductive layer 69 is embedded in the insulating layer 71. Furthermore, the height of the conductive layer 67 and the height of the insulating layer 137 can be made approximately the same, and the height of the conductive layer 69 and the height of the insulating layer 71 can be made approximately the same.

[0168] 10, the light-emitting element 20 and the transistor 80 are stacked. Here, the layer where the light-emitting element 20 is provided is referred to as a layer 121, and the layer where the transistor 80 is provided is referred to as a layer 125.

[0169] The transistor 80 is provided in each of the pixels 60R, 60G, and 60B. One of the source and the drain of the transistor 80 is electrically connected to the lower electrode 21 of the light-emitting element 20R, the lower electrode 21 of the light-emitting element 20G, or the lower electrode 21 of the light-emitting element 20B via the conductive layer 67, the conductive layer 69, the conductive layer 15, and the conductive layer 17. That is, in the display device 10 shown in FIG. 10, the transistor 80 corresponds to the transistor 11 shown in FIG. 1A and the like.

[0170] Here, the conductive layer 69 functions as a plug for electrically connecting the conductive layer 67 and the conductive layer 15, for example.

[0171] The layer 125 can be provided with transistors included in the pixel 60 as well as transistors included in a driver circuit such as a scan line driver circuit.

[0172] The transistor 80 can be a transistor having silicon in a channel formation region (Si transistor). The silicon in the Si transistor can be single crystal silicon, polycrystalline silicon (polysilicon), amorphous silicon, or the like. In particular, the channel formation region of the transistor 80 is preferably formed from single crystal silicon.

[0173] The transistor 80 includes a conductive layer 82 that functions as a gate electrode, an insulating layer 83 that functions as a gate insulating layer, and a part of a substrate 81. The transistor 80 also includes a semiconductor region including a channel formation region, a low-resistance region 85a that functions as one of a source region and a drain region, and a low-resistance region 85b that functions as the other of the source region and the drain region. The transistor 80 may be either a p-channel type or an n-channel type. Alternatively, the transistor 80 may be a so-called CMOS (Complementary Metal Oxide Semiconductor) transistor that combines an n-channel type transistor and a p-channel type transistor.

[0174] The transistor 80 is electrically isolated from other transistors by an isolation layer 86. Fig. 10 shows a case where the transistors 80 are electrically isolated from each other by the isolation layer 86. The isolation layer 86 can be formed by using a LOCOS (LOCal Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like.

[0175] FIG. 11A is a cross-sectional view showing a configuration example of the transistor 80 shown in FIG. 10 in the channel width direction (A1-A2 direction).

[0176] 10 and 11A, the semiconductor region of the transistor 80 has a convex shape. The side and top surfaces of the semiconductor region are covered with a conductive layer 82 via an insulating layer 83. The conductive layer 82 can be made of a material that adjusts the work function.

[0177] A transistor having a convex semiconductor region, such as transistor 80 shown in Figures 10 and 11A, is called a fin transistor because it utilizes a convex portion of a semiconductor substrate. An insulator that functions as a mask for forming the convex portion may be provided in contact with the top of the convex portion. While Figure 10 shows a configuration in which the convex portion is formed by processing a portion of substrate 81, a semiconductor having a convex portion may also be formed by processing an SOI (Silicon On Insulator) substrate.

[0178] 11B and 11C are cross-sectional views illustrating an example of a structure of a transistor 80 in the channel length direction, which is a variation of the transistor 80 illustrated in FIG. 10. The transistor 80 illustrated in FIG. 11B is a planar transistor, which differs from the transistor 80 illustrated in FIG. 10. The structure illustrated in FIG. 11C also differs from the structure illustrated in FIG. 10 in that an insulating layer 88 is provided over a substrate 81, and the transistor 80 is provided over the insulating layer 88.

[0179] The transistor 80 shown in FIG. 11C includes a semiconductor layer 87. The semiconductor layer 87 may be a thin film, for example, a thin film including silicon. Specifically, the semiconductor layer 87 may be a thin film including amorphous silicon or low-temperature polysilicon. Alternatively, the semiconductor layer 87 may be a single-crystal silicon (SOI) layer formed on an insulating layer 88.

[0180] 10 function as interlayer films. The insulating layer 131, the insulating layer 133, the insulating layer 135, the insulating layer 137, and the insulating layer 71 may also function as planarizing layers that cover uneven shapes below the insulating layer 131, the insulating layer 133, the insulating layer 135, the insulating layer 137, and the insulating layer 71.

[0181] Materials that can be used for the substrate 81 and the substrate 53 will be described below.

[0182] There are no significant limitations on the materials used for the substrate 81 and the substrate 53. The materials may be determined depending on the purpose, taking into consideration the presence or absence of light transmission and the heat resistance sufficient to withstand heat treatment. For example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. may be used. Furthermore, semiconductor substrates, flexible substrates, laminated films, base films, etc. may also be used.

[0183] Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. The semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0184] In order to increase the flexibility of the display device 10, the substrate 81 and the substrate 53 may be made of a flexible substrate, a laminate film, a base film, or the like.

[0185] Examples of materials that can be used for flexible substrates, laminated films, base films, etc. include polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, and cellulose nanofiber.

[0186] By using the above materials for the substrate, a lightweight display device can be provided.Furthermore, by using the above materials for the substrate, a display device that is resistant to impact can be provided.Furthermore, by using the above materials for the substrate, a display device that is less likely to break can be provided.

[0187] The lower the linear expansion coefficient of the flexible substrate used for the substrate 81 and the substrate 53, the more preferable it is, since deformation due to the environment is suppressed. For example, the linear expansion coefficient of the flexible substrate used for the substrate 81 and the substrate 53 is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less. Aramid is particularly preferable as a flexible substrate because it has a low linear expansion coefficient.

[0188] Fig. 12 is a cross-sectional view showing an example of the configuration of display device 10, which is a modified example of display device 10 shown in Fig. 10. Display device 10 shown in Fig. 12 differs from display device 10 shown in Fig. 10 in that layer 123 is provided between layer 121 and layer 125.

[0189] The layer 123 includes a transistor 70. The transistor 70 is provided in each of the pixels 60R, 60G, and 60B. In the display device 10 shown in FIG. 12, one of the source and the drain of the transistor 70 is electrically connected to the lower electrode 21 of the light-emitting element 20R, the lower electrode 21 of the light-emitting element 20G, or the lower electrode 21 of the light-emitting element 20B via the conductive layer 15 and the conductive layer 17. That is, in the display device 10 shown in FIG. 10, the transistor 70 corresponds to the transistor 11 shown in FIG. 1A and the like.

[0190] The transistor 70 can be a transistor having a metal oxide in a channel formation region (OS transistor). The metal oxide of the OS transistor preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. Furthermore, it preferably contains aluminum, gallium, yttrium, tin, or the like in addition to these. Furthermore, the metal oxide may contain one or more elements selected from the group consisting of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0191] <Display device configuration example 4> FIG. 13 is a cross-sectional view showing an example of the configuration of the display device 10, and in addition to the configuration shown in FIG. 10, shows a sealing material 91, a connection electrode 93, an anisotropic conductive layer 95, an FPC (Flexible Printed Circuit) 97, and the like.

[0192] 13, the substrate 53 and the insulating layer 13 are bonded together with a sealing material 91. Furthermore, a connection electrode 93 is provided on the insulating layer 13 and on the conductive layer 17 so as to be electrically connected to, for example, one of the source or drain of the transistor 80. Furthermore, an anisotropic conductive layer 95 is provided so as to be electrically connected to the connection electrode 93, and an FPC 97 is provided so as to be electrically connected to the anisotropic conductive layer 95. Various signals and the like are supplied to the display device 10 from outside the display device 10 via the FPC 97. Note that the sealing material 91 may be omitted, and the FPC 97 may be wire-bonded.

[0193] Fig. 14 is a cross-sectional view illustrating a configuration example of a display device 10, which is a variation of the display device 10 illustrated in Fig. 13. The display device 10 illustrated in Fig. 14 differs from the display device 10 illustrated in Fig. 13 in that it includes a transistor 70 that can be an OS transistor or the like.

[0194] 15A is a block diagram showing an example of the configuration of the display device 10. The display device 10 has a display unit 100, a scanning line driving circuit 101, and a data line driving circuit 103. The display unit 100 has pixels 60 arranged in a matrix. The scanning line driving circuit 101 and the data line driving circuit 103 can be configured to include transistors 80.

[0195] The scanning line driving circuit 101 is electrically connected to the pixels 60 via wiring 105. The data line driving circuit 103 is electrically connected to the pixels 60 via wiring 107. The wiring 105 and the wiring 107 can be configured to extend in directions perpendicular to each other.

[0196] The scanning line driving circuit 101 has a function of generating a selection signal for selecting a pixel 60 to which image data is written. The data line driving circuit 103 has a function of generating a signal (data signal) representing image data. The selection signal is supplied to the pixel 60 via a wiring 105, and the data signal is supplied to the pixel 60 via a wiring 107.

[0197] 15B is a circuit diagram showing an example of the configuration of the pixel 60. The pixel 60 includes a light-emitting element 20 and a pixel circuit 110.

[0198] The pixel circuit 110 includes a transistor 111, a transistor 11, a transistor 113, and a capacitor 115. The pixel circuit 110 is electrically connected to one electrode of the light-emitting element 20. As described above, the transistor 11 can be the transistor 80 shown in FIG. 10 or the like or the transistor 70 shown in FIG. 12 or the like.

[0199] One of the source or drain of the transistor 111 is electrically connected to the gate of the transistor 11. The gate of the transistor 11 is electrically connected to one electrode of the capacitor 115. One of the source or drain of the transistor 11 is electrically connected to one of the source or drain of the transistor 113. One of the source or drain of the transistor 113 is electrically connected to the other electrode of the capacitor 115. The other electrode of the capacitor 115 is electrically connected to one electrode of the light-emitting element 20. Here, a node where one of the source or drain of the transistor 111, the gate of the transistor 11, and one electrode of the capacitor 115 are electrically connected is referred to as node 117. Furthermore, a node where one of the source or drain of the transistor 111, one of the source or drain of the transistor 113, the other electrode of the capacitor 115, and one electrode of the light-emitting element 20 are electrically connected is referred to as node 119.

[0200] The other of the source and the drain of the transistor 111 is electrically connected to the wiring 107. The gate of the transistor 111 and the gate of the transistor 113 are electrically connected to the wiring 105. The other of the source and the drain of the transistor 111 is electrically connected to the potential supply line VL_a. The other of the source and the drain of the transistor 113 is electrically connected to the potential supply line VL0. The other electrode of the light-emitting element 20 is electrically connected to the potential supply line VL_b.

[0201] The transistor 111 has a function of controlling writing of image data to the node 117. The capacitor 115 functions as a storage capacitor for holding data written to the node 117.

[0202] In a display device having the pixel circuits 110 , the pixel circuits 110 in each row are sequentially selected by the scanning line driver circuit 101 , and the transistors 111 and 113 are turned on to write image data to the nodes 117 .

[0203] The pixel circuit 110, in which image data has been written to the node 117, is put into a holding state by turning off the transistors 111 and 113. The amount of current flowing between the drain and source of the transistor 11 is controlled in accordance with the potential of the node 119, and the light-emitting element 20 emits light at a luminance corresponding to the amount of current. By performing this process sequentially for each row, an image can be displayed on the display unit 100.

[0204] <Transistor configuration example> 16A, 16B, and 16C are a top view and a cross-sectional view of the transistor 70 and the periphery of the transistor 70. FIG.

[0205] FIG. 16A is a top view of the transistor 70. Also, FIGS. 16B and 16C are cross-sectional views of the transistor 70. Here, FIG. 16B is a cross-sectional view of the portion indicated by the dashed-dotted line X1-X2 in FIG. 16A, and is also a cross-sectional view of the transistor 70 in the channel length direction. Also, FIG. 16C is a cross-sectional view of the portion indicated by the dashed-dotted line Y1-Y2 in FIG. 16A, and is also a cross-sectional view of the transistor 70 in the channel width direction. Note that in the top view of FIG. 16A, some elements are omitted for clarity.

[0206] 16A, 16B, and 16C, the transistor 70 includes a metal oxide 230a disposed on a substrate (not shown), a metal oxide 230b disposed on the metal oxide 230a, a conductor 242a and a conductor 242b disposed spaced apart from each other on the metal oxide 230b, an insulator 280 disposed on the conductors 242a and 242b and having an opening formed between the conductors 242a and 242b, a conductor 260 disposed in the opening, an insulator 250 disposed among the metal oxide 230b, the conductors 242a, 242b, and the insulator 280, and the conductor 260, and a metal oxide 230c disposed among the metal oxide 230b, the conductors 242a, 242b, the insulator 280, and the insulator 250. 16B and 16C, it is preferable that the top surface of the conductor 260 substantially coincides with the top surfaces of the insulators 250, 254, metal oxide 230c, and 280. Note that, hereinafter, the metal oxides 230a, 230b, and 230c may be collectively referred to as metal oxides 230. Furthermore, the conductors 242a and 242b may be collectively referred to as conductors 242.

[0207] 16B, the side surfaces of the conductors 242a and 242b facing the conductor 260 have a substantially vertical shape. Note that the transistor 70 shown in FIG. 16B is not limited to this, and the angle formed between the side surface and the bottom surface of the conductors 242a and 242b may be 10° to 80°, preferably 30° to 60°. Furthermore, the opposing side surfaces of the conductors 242a and 242b may have multiple surfaces.

[0208] 16B and 16C, it is preferable that an insulator 254 be disposed between the insulator 224, the metal oxide 230a, the metal oxide 230b, the conductor 242a, the conductor 242b, and the metal oxide 230c and the insulator 280. Here, it is preferable that the insulator 254 be in contact with the side surface of the metal oxide 230c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the metal oxide 230a and the metal oxide 230b, and the top surface of the insulator 224, as shown in FIG.

[0209] Although the transistor 70 has a three-layer structure of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c in and around a region where a channel is formed (hereinafter also referred to as a channel formation region), the present invention is not limited to this. For example, a two-layer structure of the metal oxide 230b and the metal oxide 230c or a stacked structure of four or more layers may be provided. Furthermore, the conductor 260 of the transistor 70 has a two-layer structure, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c may have a stacked structure of two or more layers.

[0210] For example, when metal oxide 230c has a layered structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has a composition similar to that of metal oxide 230b, and the second metal oxide has a composition similar to that of metal oxide 230a.

[0211] Here, the conductor 260 functions as the gate electrode of the transistor, and the conductors 242a and 242b function as the source electrode and drain electrode, respectively. As described above, the conductor 260 is formed so as to be embedded in the opening of the insulator 280 and in the region sandwiched between the conductors 242a and 242b. Here, the arrangement of the conductors 260, 242a, and 242b is selected in a self-aligned manner with respect to the opening of the insulator 280. That is, in the transistor 70, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductor 260 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 70. This allows for a high-resolution display device. Furthermore, the display device can have a narrow frame.

[0212] As shown in Figures 16B and 16C, it is preferable that the conductor 260 has a conductor 260a arranged inside the insulator 250 and a conductor 260b arranged so as to be embedded inside the conductor 260a.

[0213] The transistor 70 preferably includes an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on the insulator 214, a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and the conductor 205, and an insulator 224 disposed on the insulator 222. A metal oxide 230a is preferably disposed on the insulator 224.

[0214] An insulator 274 and an insulator 281, which function as interlayer films, are preferably disposed over the transistor 70. Here, the insulator 274 is preferably disposed in contact with top surfaces of the conductor 260, the insulator 250, the insulator 254, the metal oxide 230c, and the insulator 280.

[0215] It is preferable that the insulators 222, 254, and 274 have a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). For example, it is preferable that the insulators 222, 254, and 274 have lower hydrogen permeability than the insulators 224, 250, and 280. It is also preferable that the insulators 222 and 254 have a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, it is preferable that the insulators 222 and 254 have lower oxygen permeability than the insulators 224, 250, and 280.

[0216] Here, the insulator 224, the metal oxide 230, and the insulator 250 are separated by the insulators 280 and 281, and the insulators 254 and 274. Therefore, impurities such as hydrogen contained in the insulators 280 and 281, or excess oxygen, can be prevented from being mixed into the insulators 224, the metal oxide 230a, the metal oxide 230b, and the insulator 250.

[0217] It is preferable that a conductor 240 (conductor 240a and conductor 240b) electrically connected to the transistor 70 and functioning as a plug is provided. Note that an insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 functioning as a plug. That is, the insulator 241 is provided in contact with the inner wall of the opening of the insulators 254, 280, 274, and 281. Alternatively, a first conductor of the conductor 240 may be provided in contact with the side surface of the insulator 241, and a second conductor of the conductor 240 may be provided further inside. Here, the height of the top surface of the conductor 240 and the height of the insulator 281 can be made approximately the same. Note that, in the transistor 70, a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked is described, but the present invention is not limited to this. For example, the conductor 240 may be configured to have a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, it may be distinguished by assigning an ordinal number to the order of formation.

[0218] The transistor 70 preferably uses a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) for the metal oxide 230 (metal oxide 230a, metal oxide 230b, and metal oxide 230c) including the channel formation region. For example, the metal oxide that forms the channel formation region of the metal oxide 230 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more.

[0219] The metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that it contains indium (In) and zinc (Zn). In addition to these, it is preferable that it contains element M. As element M, one or more of aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), and cobalt (Co) can be used. In particular, element M is preferably one or more of aluminum (Al), gallium (Ga), yttrium (Y), and tin (Sn). Furthermore, it is more preferable that element M contains either or both of Ga and Sn.

[0220] 16B, the film thickness of the metal oxide 230b in the region that does not overlap with the conductor 242 may be thinner than the film thickness of the region that overlaps with the conductor 242. This is formed by removing a portion of the upper surface of the metal oxide 230b when forming the conductors 242a and 242b. When a conductive film that will become the conductor 242 is formed on the upper surface of the metal oxide 230b, a low-resistance region may be formed near the interface with the conductive film. In this way, by removing the low-resistance region located between the conductors 242a and 242b on the upper surface of the metal oxide 230b, it is possible to prevent a channel from being formed in that region.

[0221] According to one embodiment of the present invention, a display device having high definition and a small transistor can be provided. Alternatively, a display device having high luminance and a transistor with high on-state current can be provided. Alternatively, a display device having high-speed operation and a transistor with stable electrical characteristics can be provided. Alternatively, a display device having low power consumption and a transistor with low off-state current can be provided.

[0222] A detailed structure of the transistor 70 that can be used in the display device of one embodiment of the present invention will be described.

[0223] The conductor 205 is disposed so as to have an overlapping region with the metal oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 216.

[0224] The conductor 205 includes conductor 205a, conductor 205b, and conductor 205c. The conductor 205a is provided in contact with the bottom surface and sidewall of an opening provided in the insulator 216. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the upper surface of the conductor 205b is lower than the upper surface of the conductor 205a and the upper surface of the insulator 216. The conductor 205c is provided in contact with the upper surface of the conductor 205b and the side surface of the conductor 205a. Here, the height of the upper surface of the conductor 205c is approximately the same as the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216. In other words, the conductor 205b is configured to be enclosed by the conductors 205a and 205c.

[0225] The conductors 205a and 205c are preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0226] By using a conductive material that can reduce hydrogen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the metal oxide 230 via the insulator 224 or the like. Furthermore, by using a conductive material that can reduce oxygen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can reduce oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be made of titanium nitride.

[0227] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0228] Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. The conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the potential applied to the conductor 205 may be changed independently of the potential applied to the conductor 260, thereby controlling the V th In particular, applying a negative potential to conductor 205 can control the V th It is possible to make the off-state current smaller by making the potential greater than 0 V. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0 V than when no potential is applied.

[0229] The conductor 205 is preferably provided to be larger than the channel formation region of the metal oxide 230. In particular, as shown in Fig. 16C, the conductor 205 preferably extends also in a region outside the end portion intersecting with the channel width direction of the metal oxide 230. In other words, the conductor 205 and the conductor 260 preferably overlap with each other with an insulator interposed therebetween on the outside of the side surface of the metal oxide 230 in the channel width direction.

[0230] With the above structure, the channel formation region of the metal oxide 230 can be electrically surrounded by the electric field of the conductor 260 that functions as a first gate electrode and the electric field of the conductor 205 that functions as a second gate electrode.

[0231] 16C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor that functions as wiring may be provided below the conductor 205.

[0232] The insulator 214 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 70 from the substrate side. Therefore, the insulator 214 is preferably made of an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (i.e., the impurities are less likely to permeate through the material). Alternatively, the insulator 214 is preferably made of an insulating material that has a function of preventing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate through the material).

[0233] For example, aluminum oxide, silicon nitride, or the like is preferably used as the insulator 214. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulator 214 to the transistor 70 side. Alternatively, it can prevent oxygen contained in the insulator 224 or the like from diffusing to the substrate side of the insulator 214.

[0234] The insulators 216, 280, and 281, which function as interlayer films, preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like can be used as appropriate for the insulators 216, 280, and 281.

[0235] The insulators 222 and 224 function as gate insulators.

[0236] Here, the insulator 224 in contact with the metal oxide 230 preferably releases oxygen upon heating. In this specification, oxygen released upon heating is sometimes referred to as excess oxygen. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the metal oxide 230, oxygen vacancies in the metal oxide 230 can be reduced, and the reliability of the transistor 70 can be improved.

[0237] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as the insulator 224. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted into oxygen atoms is 1.0×10 in TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0238] 16C, the thickness of the region of insulator 224 that does not overlap with insulator 254 and metal oxide 230b may be thinner than the thickness of the other region. It is preferable that the thickness of the region of insulator 224 that does not overlap with insulator 254 and metal oxide 230b is a thickness that allows sufficient diffusion of the oxygen.

[0239] Like the insulator 214 and the like, the insulator 222 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 70 from the substrate side. For example, the insulator 222 preferably has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the metal oxide 230, the insulator 250, and the like with the insulators 222, 254, and 274, impurities such as water or hydrogen can be prevented from entering the transistor 70 from the outside.

[0240] Furthermore, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (i.e., the oxygen is less likely to permeate). For example, the insulator 222 preferably has lower oxygen permeability than the insulator 224. The insulator 222 preferably has a function of suppressing the diffusion of oxygen or impurities, which can reduce the diffusion of oxygen contained in the metal oxide 230 toward the substrate side. Furthermore, the conductor 205 can be prevented from reacting with oxygen contained in the insulator 224 or oxygen contained in the metal oxide 230.

[0241] The insulator 222 may be an insulator containing an oxide of one or both of insulating materials, aluminum and hafnium. Aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator containing an oxide of one or both of aluminum and hafnium. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the metal oxide 230 and the intrusion of impurities such as hydrogen from the periphery of the transistor 70 into the metal oxide 230.

[0242] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0243] The insulator 222 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0244] The insulator 222 and the insulator 224 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to the stacked structure made of the same material, and may be a stacked structure made of different materials. For example, an insulator similar to the insulator 224 may be provided below the insulator 222.

[0245] The metal oxide 230 includes a metal oxide 230a, a metal oxide 230b on the metal oxide 230a, and a metal oxide 230c on the metal oxide 230b. By providing the metal oxide 230a below the metal oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the metal oxide 230a to the metal oxide 230b. Furthermore, by providing the metal oxide 230c on the metal oxide 230b, it is possible to suppress the diffusion of impurities from structures formed above the metal oxide 230c to the metal oxide 230b.

[0246] The metal oxide 230 preferably has a stacked structure of multiple oxide layers with different atomic ratios of each metal atom. For example, when the metal oxide 230 contains at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the metal oxide 230a to the number of atoms of all elements constituting the metal oxide 230a is preferably higher than the ratio of the number of atoms of the element M contained in the metal oxide 230b to the number of atoms of all elements constituting the metal oxide 230b. Furthermore, the atomic ratio of the element M contained in the metal oxide 230a to In is preferably higher than the atomic ratio of the element M contained in the metal oxide 230b to In. Here, the metal oxide 230c can be any metal oxide that can be used for the metal oxide 230a or the metal oxide 230b.

[0247] The energy of the conduction band minimum of the metal oxide 230a and the metal oxide 230c is preferably higher than the energy of the conduction band minimum of the metal oxide 230b. In other words, the electron affinity of the metal oxide 230a and the metal oxide 230c is preferably lower than the electron affinity of the metal oxide 230b. In this case, the metal oxide 230c is preferably a metal oxide that can be used for the metal oxide 230a. Specifically, the ratio of the number of atoms of the element M contained in the metal oxide 230c to the number of atoms of all elements constituting the metal oxide 230c is preferably higher than the ratio of the number of atoms of the element M contained in the metal oxide 230b to the number of atoms of all elements constituting the metal oxide 230b. Furthermore, the atomic ratio of the element M contained in the metal oxide 230c to In is preferably higher than the atomic ratio of the element M contained in the metal oxide 230b to In.

[0248] Here, the energy level of the conduction band minimum changes smoothly at the junction between the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c. In other words, the energy level of the conduction band minimum at the junction between the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c changes continuously or can be said to be a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the metal oxide 230a and the metal oxide 230b and the interface between the metal oxide 230b and the metal oxide 230c.

[0249] Specifically, the metal oxide 230a and the metal oxide 230b, and the metal oxide 230b and the metal oxide 230c, may have a common element other than oxygen (as a main component), thereby forming a mixed layer with a low density of defect states. For example, when the metal oxide 230b is an In-Ga-Zn oxide, the metal oxide 230a and the metal oxide 230c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, or the like. The metal oxide 230c may also have a stacked structure. For example, a stacked structure of an In-Ga-Zn oxide and a Ga-Zn oxide on the In-Ga-Zn oxide, or a stacked structure of an In-Ga-Zn oxide and a gallium oxide on the In-Ga-Zn oxide, may be used. In other words, the metal oxide 230c may have a stacked structure of an In-Ga-Zn oxide and an oxide that does not contain In.

[0250] Specifically, the metal oxide 230a may have an atomic ratio of In:Ga:Zn=1:3:4 or 1:1:0.5. The metal oxide 230b may have an atomic ratio of In:Ga:Zn=4:2:3 or 3:1:2. The metal oxide 230c may have an atomic ratio of In:Ga:Zn=1:3:4, In:Ga:Zn=4:2:3, Ga:Zn=2:1, or Ga:Zn=2:5. Specific examples of the metal oxide 230c having a layered structure include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

[0251] In this case, the main carrier path is the metal oxide 230b. By configuring the metal oxide 230a and the metal oxide 230c as described above, the defect level density at the interface between the metal oxide 230a and the metal oxide 230b and at the interface between the metal oxide 230b and the metal oxide 230c can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 70 to achieve a high on-state current and high frequency characteristics. Note that, when the metal oxide 230c has a stacked structure, in addition to the effect of reducing the defect level density at the interface between the metal oxide 230b and the metal oxide 230c, it is expected that the diffusion of constituent elements of the metal oxide 230c toward the insulator 250 can be suppressed. More specifically, by configuring the metal oxide 230c as a stacked structure and positioning an oxide that does not contain In above the stacked structure, it is possible to suppress In diffusion toward the insulator 250. Because the insulator 250 functions as a gate insulator, diffusion of In can cause poor transistor characteristics. Therefore, by forming the metal oxide 230c into a laminated structure, it is possible to provide a highly reliable display device.

[0252] Conductors 242 (conductors 242a and 242b) functioning as a source electrode and a drain electrode are provided on the metal oxide 230b. Conductor 242 is preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, or an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when they absorb oxygen.

[0253] By providing the conductor 242 so as to be in contact with the metal oxide 230, the oxygen concentration may decrease in the vicinity of the conductor 242 of the metal oxide 230. Furthermore, a metal compound layer containing the metal contained in the conductor 242 and components of the metal oxide 230 may be formed in the vicinity of the conductor 242 of the metal oxide 230. In such a case, the carrier density increases in the region of the metal oxide 230 in the vicinity of the conductor 242, and this region becomes a low-resistance region.

[0254] Here, the region between the conductor 242a and the conductor 242b is formed to overlap the opening of the insulator 280. This allows the conductor 260 to be arranged in a self-aligned manner between the conductor 242a and the conductor 242b.

[0255] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the metal oxide 230c. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0256] The insulator 250 preferably has a reduced concentration of impurities such as water or hydrogen, similar to the insulator 224. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0257] A metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. This makes it possible to suppress oxidation of the conductor 260 due to oxygen in the insulator 250.

[0258] The metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By forming the gate insulator into a stacked structure of the insulator 250 and the metal oxide, it is possible to achieve a stacked structure that is thermally stable and has a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0259] Specifically, it is possible to use a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0260] Although the conductor 260 is shown as having a two-layer structure in FIGS. 16B and 16C, it may have a single-layer structure or a laminated structure of three or more layers.

[0261] The conductor 260a is preferably made of a conductor having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0262] The conductor 260a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0263] The conductor 260b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Furthermore, the conductor 260b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0264] 16A and 16C, in a region of the metal oxide 230b that does not overlap with the conductor 242, in other words, in the channel formation region of the metal oxide 230, the conductor 260 is arranged to cover the side surface of the metal oxide 230. This makes it easier for the electric field of the conductor 260, which functions as the first gate electrode, to act on the side surface of the metal oxide 230. This increases the on-state current of the transistor 70 and improves its frequency characteristics.

[0265] Like the insulator 214, the insulator 254 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 70 from the insulator 280 side. For example, the insulator 254 preferably has lower hydrogen permeability than the insulator 224. Furthermore, as shown in FIGS. 16B and 16C , the insulator 254 preferably contacts the side surface of the metal oxide 230c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the metal oxide 230a and the metal oxide 230b, and the top surface of the insulator 224. This configuration prevents hydrogen contained in the insulator 280 from entering the metal oxide 230 from the top or side surfaces of the conductor 242a, the conductor 242b, the metal oxide 230a, the metal oxide 230b, and the insulator 224.

[0266] Furthermore, the insulator 254 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (i.e., the oxygen is less likely to permeate). For example, the insulator 254 preferably has lower oxygen permeability than the insulator 280 or the insulator 224.

[0267] The insulator 254 is preferably formed by sputtering. By forming the insulator 254 by sputtering in an oxygen-containing atmosphere, oxygen can be added to the insulator 224 near the region where the insulator 254 is in contact with the insulator 254. This allows oxygen to be supplied from this region to the metal oxide 230 through the insulator 224. The insulator 254 has a function of suppressing upward oxygen diffusion, thereby preventing oxygen from diffusing from the metal oxide 230 to the insulator 280. The insulator 222 has a function of suppressing downward oxygen diffusion, thereby preventing oxygen from diffusing from the metal oxide 230 toward the substrate. In this way, oxygen is supplied to the channel formation region of the metal oxide 230. This reduces oxygen vacancies in the metal oxide 230 and suppresses the transistor from becoming normally on.

[0268] For example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed as the insulator 254. Note that as the insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.

[0269] By covering the insulator 224, the insulator 250, and the metal oxide 230 with the insulator 254, which has a barrier property against hydrogen, the insulator 280 is separated from the insulator 224, the metal oxide 230, and the insulator 250 by the insulator 254. This can prevent impurities such as hydrogen from penetrating from the outside of the transistor 70, thereby providing the transistor 70 with good electrical characteristics and reliability.

[0270] The insulator 280 is provided over the insulator 224, the metal oxide 230, and the conductor 242 with the insulator 254 interposed therebetween. For example, the insulator 280 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly preferred because they can easily form a region containing oxygen that is released by heating.

[0271] It is preferable that the concentration of impurities such as water or hydrogen is reduced in the insulator 280. The top surface of the insulator 280 may be flattened.

[0272] Similar to the insulator 214, the insulator 274 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulator 280 from above. As the insulator 274, for example, an insulator that can be used for the insulator 214, the insulator 254, etc. may be used.

[0273] An insulator 281 functioning as an interlayer film is preferably provided over the insulator 274. Like the insulator 224 and the like, the insulator 281 preferably has a reduced concentration of impurities such as water or hydrogen.

[0274] The conductor 240a and the conductor 240b are arranged in openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 254. The conductor 240a and the conductor 240b are arranged opposite each other with the conductor 260 interposed therebetween. The upper surfaces of the conductor 240a and the conductor 240b may be flush with the upper surface of the insulator 281.

[0275] Note that insulator 241a is provided in contact with the inner walls of the openings of insulators 281, 274, 280, and 254, and a first conductor of conductor 240a is formed in contact with the side surface of insulator 241a. Conductor 242a is located on at least a portion of the bottom of the openings, and conductor 240a is in contact with conductor 242a. Similarly, insulator 241b is provided in contact with the inner walls of the openings of insulators 281, 274, 280, and 254, and a first conductor of conductor 240b is formed in contact with the side surface of insulator 241b. Conductor 242b is located on at least a portion of the bottom of the openings, and conductor 240b is in contact with conductor 242b.

[0276] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 240a and 240b may have a layered structure.

[0277] When the conductor 240 has a layered structure, it is preferable to use the above-mentioned conductors that have the function of suppressing the diffusion of impurities such as water or hydrogen for the conductors in contact with the metal oxide 230a, the metal oxide 230b, the conductor 242, the insulator 254, the insulator 280, the insulator 274, and the insulator 281. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, the conductive material that has the function of suppressing the diffusion of impurities such as water or hydrogen may be used in a single layer or a layered structure. The use of such a conductive material can suppress the absorption of oxygen added to the insulator 280 by the conductors 240a and 240b. Furthermore, it can suppress the intrusion of impurities such as water or hydrogen from layers above the insulator 281 into the metal oxide 230 through the conductors 240a and 240b.

[0278] The insulators 241a and 241b may be, for example, insulators that can be used for the insulator 254. The insulators 241a and 241b are provided in contact with the insulator 254, and therefore can prevent impurities such as water or hydrogen from the insulator 280 from being mixed into the metal oxide 230 through the conductors 240a and 240b. Furthermore, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.

[0279] Although not shown, a conductor functioning as wiring may be disposed in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b. The conductor functioning as wiring is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0280] <Configuration example of light-emitting element> As described above, the EL layer 30 of the light-emitting element 20 can be composed of multiple layers such as a hole injection layer 31, a light-emitting layer 33, and an electron injection layer 35, as shown in FIG. 17A.

[0281] A configuration in which a hole injection layer 31, a light-emitting layer 33, and an electron injection layer 35 are provided between a lower electrode 21 and an upper electrode 25 can function as a single light-emitting unit, and in this specification, the configuration of Figure 17A is referred to as a single structure.

[0282] As shown in FIG. 17B, a configuration in which a plurality of light-emitting layers (for example, light-emitting layer 33a, light-emitting layer 33b, and light-emitting layer 33c) are provided between electron injection layer 35 and hole injection layer 31 is also a variation of the single structure.

[0283] Furthermore, as shown in FIG. 17C, a configuration in which a plurality of light-emitting units (e.g., EL layer 30a and EL layer 30b) are connected in series via an intermediate layer (charge generating layer) 37 is referred to as a tandem structure in this specification. FIG. 17C shows a configuration in which EL layer 30a has light-emitting layer 33d, and EL layer 30b has light-emitting layer 33e. Note that, although the configuration shown in FIG. 17C is referred to as a tandem structure in this specification and the like, it is not limited thereto, and for example, the tandem structure may also be referred to as a stack structure. Note that a tandem structure can be used to obtain a light-emitting element capable of emitting light with high brightness.

[0284] Furthermore, when the above-described single structure and tandem structure are compared with the previously described SBS structure, power consumption decreases in the order of the SBS structure, the tandem structure, and the single structure. To reduce the power consumption of a display device according to one embodiment of the present invention, the SBS structure is preferably used. On the other hand, the manufacturing process of the single structure and the tandem structure is simpler than that of the SBS structure. Therefore, the manufacturing cost of the display device according to one embodiment of the present invention can be reduced and the yield can be increased. As described above, the display device according to one embodiment of the present invention can be manufactured at a low price.

[0285] The light-emitting element 20 can emit light in red, green, blue, cyan, magenta, yellow, white, or the like, depending on the material of the EL layer 30. Furthermore, the color purity can be further improved by providing the light-emitting element 20 with a microcavity structure.

[0286] A light-emitting element that emits white light preferably has a structure in which two or more light-emitting substances are contained in the light-emitting layer. To obtain white light emission, light-emitting substances are selected such that the respective emissions of the two or more light-emitting substances are in a complementary color relationship.

[0287] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), or the like.

[0288] For example, when the light-emitting layer 33a has a function of emitting red light, the light-emitting layer 33b has a function of emitting green light, and the light-emitting layer 33c has a function of emitting blue light, the light-emitting element 20 shown in Fig. 17B can emit white light. When the light-emitting layer 33d has a function of emitting yellow light, and the light-emitting layer 33e has a function of emitting blue light, the light-emitting element 20 shown in Fig. 17C can emit white light.

[0289] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0290] (Embodiment 2) In this embodiment, a metal oxide that can be used for the OS transistor described in the above embodiment will be described.

[0291] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 18A. Fig. 18A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0292] As shown in FIG. 18A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). The "Crystalline" classification excludes single crystal, polycrystal, and completely amorphous (excluding single crystal and polycrystal). "Crystal" includes single crystal and polycrystal.

[0293] The structure within the bold frame shown in Figure 18A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "Amorphous" and "Crystal."

[0294] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 18B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." In Figure 18B, the horizontal axis represents 2θ [deg.], and the vertical axis represents intensity [au]. The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 18B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 18B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 18B is 500 nm.

[0295] In Figure 18B, the horizontal axis is 2θ [deg.] and the vertical axis is intensity [au]. As shown in Figure 18B, a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 18B, the peak near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0296] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 18C. Figure 18C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 18C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In nanobeam electron diffraction, electron diffraction is performed using a probe diameter of 1 nm.

[0297] As shown in FIG. 18C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0298] [Structure of oxide semiconductor] Note that oxide semiconductors may be classified differently from those shown in FIG. 18A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0299] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0300] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. Considering an atomic arrangement as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a location where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0301] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0302] In an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. Furthermore, the In layer may contain element M. Furthermore, the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0303] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0304] For example, in the electron diffraction pattern of a CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0305] When the crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries can be observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0306] A crystal structure in which clear grain boundaries are observed is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for forming a CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0307] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0308] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0309] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0310] [Oxide semiconductor composition] Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0311] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that, hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0312] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0313] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0314] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0315] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0316] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0317] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0318] Oxide semiconductors have a variety of structures and each has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0319] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0320] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0321] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm-3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0322] A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore, the density of trap states may also be low.

[0323] Charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0324] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0325] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0326] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17atoms / cm 3 The following applies.

[0327] When an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0328] When nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0329] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0330] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0331] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0332] (Embodiment 3) In this embodiment, an electronic device including a display device according to one embodiment of the present invention will be described.

[0333] FIG. 19A is a diagram showing the appearance of the head mounted display 8200.

[0334] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 has a built-in battery 8206.

[0335] A cable 8205 supplies power from a battery 8206 to the main body 8203. The main body 8203 is equipped with a wireless receiver or the like, and can display an image corresponding to received image data or the like on a display portion 8204. In addition, a camera provided in the main body 8203 captures the movement of the user's eyeball or eyelid, and calculates the coordinates of the user's line of sight based on the information, thereby allowing the user's line of sight to be used as an input means.

[0336] The wearing unit 8201 may be provided with a plurality of electrodes at positions that come into contact with the user. The main body 8203 may have a function of recognizing the user's line of sight by detecting a current flowing through the electrodes in accordance with the movement of the user's eyeballs. The main body 8203 may also have a function of monitoring the user's pulse by detecting the current flowing through the electrodes. The wearing unit 8201 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display unit 8204. The wearing unit 8201 may also detect the movement of the user's head, etc., and change the image displayed on the display unit 8204 in accordance with the movement.

[0337] The display device of one embodiment of the present invention can be applied to the display portion 8204. Accordingly, high-quality images can be displayed on the display portion 8204.

[0338] 19B, 19C, and 19D are diagrams showing the appearance of a head-mounted display 8300. The head-mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305. A battery 8306 is built into the housing 8301, and power can be supplied from the battery 8306 to the display portion 8302 and the like.

[0339] A user can view the display on the display portion 8302 through the lens 8305. Note that it is preferable to arrange the display portion 8302 in a curved manner. By arranging the display portion 8302 in a curved manner, a user can feel a high sense of presence. Note that although the configuration in which one display portion 8302 is provided has been illustrated in this embodiment, the present invention is not limited thereto, and for example, a configuration in which two display portions 8302 are provided may be used. In this case, if one display portion is provided for one eye of the user and the other display portion is provided for the other eye, three-dimensional display using parallax or the like can be performed.

[0340] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. Accordingly, high-quality images can be displayed in the display portion 8302.

[0341] Next, an example of an electronic device different from the electronic device shown in FIGS. 19A to 19D is shown in FIGS. 20A and 20B.

[0342] The electronic device shown in Figures 20A and 20B has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), and a battery 9009.

[0343] The electronic device shown in FIGS. 20A and 20B has various functions. For example, it may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to connect to various computer networks using the wireless communication function, a function to send or receive various data using the wireless communication function, a function to read programs or data recorded on a recording medium and display them on a display unit, etc. Note that the functions that the electronic device shown in FIGS. 20A and 20B can have are not limited to these, and it may have various other functions. Also, although not shown in FIGS. 20A and 20B, the electronic device may be configured to have multiple display units. Furthermore, the electronic device may be equipped with a camera or the like to capture still images, capture videos, save the captured images on a recording medium (external or built-in to the camera), display the captured images on a display unit, etc.

[0344] The electronic device shown in FIGS. 20A and 20B will be described in detail below.

[0345] FIG. 20A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 has one or more functions selected from, for example, a telephone, a notebook, an information viewing device, and the like. Specifically, it can be used as a smartphone. The mobile information terminal 9101 can display text or images on multiple surfaces thereof. For example, operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one surface of the display unit 9001. Information 9051, indicated by a dashed rectangle, can be displayed on the other surface of the display unit 9001. Examples of the information 9051 include a display notifying an incoming email, SNS (social networking service), or phone call, the title of the email or SNS, the name of the sender of the email or SNS, the date and time, the remaining battery level, and signal strength. Alternatively, the operation buttons 9050, etc., may be displayed in place of the information 9051 at the position where the information 9051 is displayed.

[0346] The display device of one embodiment of the present invention can be applied to the portable information terminal 9101. Accordingly, high-quality images can be displayed on the display portion 9001.

[0347] FIG. 20B is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can execute various applications such as mobile phone calls, e-mail, document browsing and creation, music playback, internet communication, and computer games. The display unit 9001 has a curved display surface, and can display information along the curved display surface. FIG. 20B shows an example in which time 9251, operation buttons 9252 (also referred to as operation icons or simply icons), and content 9253 are displayed on the display unit 9001. The content 9253 can be, for example, a video.

[0348] The mobile information terminal 9200 can also perform short-distance wireless communication according to a communication standard. For example, hands-free conversation is also possible by mutual communication with a wireless headset. The mobile information terminal 9200 also has a connection terminal 9006, and can directly exchange data with other information terminals via a connector. Charging can also be performed via the connection terminal 9006. Note that charging may also be performed by wireless power supply without using the connection terminal 9006.

[0349] The display device of one embodiment of the present invention can be applied to the portable information terminal 9200. This allows high-quality images to be displayed on the display portion 9001.

[0350] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification. [Explanation of symbols]

[0351] 10: display device, 11: transistor, 13: insulating layer, 15: conductive layer, 17: conductive layer, 19: partition wall, 20: light-emitting element, 20B: light-emitting element, 20G: light-emitting element, 20R: light-emitting element, 21: lower electrode, 21A: layer, 25: upper electrode, 25A: layer, 30: EL layer, 30a: EL layer, 30b: EL layer, 31: hole injection layer, 31A: layer, 31B: layer, 31C: layer, 33: light-emitting layer, 33a: light-emitting layer, 33A: layer, 33b: light-emitting layer, 33B: light-emitting layer, 33BA: layer, 33c: light-emitting layer, 33d: light-emitting layer, 33e: light-emitting layer, 33G: light-emitting layer, 33GA: layer, 33R: light-emitting layer, 33RA: layer, 35: electron injection layer, 35A: layer, 40: gap, 42: gap, 43: protective layer, 45: microlens array, 47: adhesive layer, 49: light-shielding layer, 51: insulating layer, 53: substrate, 55: colored layer, 55B: colored layer, 55G: colored layer, 55R: colored layer, 60: pixel, 60B: pixel, 60G: pixel, 60R: pixel, 61: light, 63: region, 67: conductive layer, 69: conductive layer, 70: transistor, 71: insulating layer, 80: transistor, 81: substrate, 82: conductive layer, 83: insulating layer, 85a: low-resistance region, 85b: low-resistance region, 86: element isolation layer, 87: semiconductor layer, 8 8: insulating layer, 91: sealing material, 93: connecting electrode, 95: anisotropic conductive layer, 97: FPC, 100: display section, 101: scanning line driving circuit, 103: data line driving circuit, 105: wiring, 107: wiring, 110: pixel circuit, 111: transistor, 113: transistor, 115: capacitor, 117: node, 119: node, 121: layer, 123: layer, 125: layer, 131: insulating layer, 133: insulating layer, 135: insulating layer, 137: insulating layer, 140: sacrificial layer, 140A: layer, 140B: layer, 140C: layer, 150: region, 205: conductor, 205a: conductor, 205b: conductor conductor, 205c: conductor, 214: insulator, 216: insulator, 222: insulator, 224: insulator, 230: metal oxide, 230a: metal oxide, 230b: metal oxide, 230c: metal oxide, 240: conductor, 240a: conductor, 240b: conductor, 241: insulator, 241a: insulator, 241b: insulator, 242: conductor, 242a: conductor, 242b: conductor, 250: insulator, 254: insulator, 260: conductor, 260a: conductor, 260b: conductor, 274: insulator, 280: insulator, 281: insulator, 8200: head-mounted display,8201: Mounting part, 8202: Lens, 8203: Main body, 8204: Display part, 8205: Cable, 8206: Battery, 8300: Head mounted display, 8301: Housing, 8302: Display part, 8304: Fixing device, 8305: Lens, 8306: Battery, 9000: Housing, 9001: Display part, 9003: Speaker, 9005: Operation keys, 9006: Connection terminal, 9007: Sensor, 9009: Battery, 9050: Operation button, 9051: Information, 9101: Portable information terminal, 9200: Portable information terminal, 9251: Time, 9252: Operation button, 9253: Content,

Claims

1. a layer to be a first lower electrode and a second lower electrode, a layer to be a first light-emitting layer and a second light-emitting layer, and a layer to be a first upper electrode and a second upper electrode are sequentially formed, and then processed by a first etching process to form the first and second upper electrodes, the first and second light-emitting layers, and the first and second lower electrodes; a second upper electrode that has a region protruding beyond a side surface of the first light-emitting layer and a second upper electrode that has a region protruding beyond a side surface of the second light-emitting layer;

2. In claim 1, The second etching is more isotropic than the first etching.

3. In claim 1 or claim 2, a protective layer formed after the second etching so that a gap is provided between the first upper electrode and the first light-emitting layer, and between the second upper electrode and the second light-emitting layer;

4. In claim 3, The method for manufacturing a display device further comprises forming a microlens array on the protective layer.

5. In claim 3, The method for manufacturing a display device includes forming the protective layer by a sputtering method or a CVD method.

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