Semiconductor Devices

Abstract

To provide a semiconductor device in which wiring length and a current path can be shortened and of which the inductance therefore can be reduced.SOLUTION: An semiconductor device comprises: an insulated circuit board 1 having a first conductive layer 12a and a second conductive layer 12b on the upper surface side; first semiconductor chips 3a and 3b mounted on the first conductive layer 12a; second semiconductor chips 3c and 3d mounted on the second conductive layer 12b; a printed board 6 having a first lower wiring layer 63a arranged to face the first semiconductor chips 3a and 3b, and a second lower wiring layer 63b arranged to face the second semiconductor chips 3c and 3d, and including a curved portion 60 curved toward the board 1; first connection members 21a and 21b connecting the first semiconductor chips 3a and 3b and the first lower wiring layer 63a; second connection members 21c and 21d connecting the second semiconductor chips 3c and 3d and the second lower wiring layer 63b; and a third connection member 21 connecting the first conductive layer 12a and the second lower wiring layer 63b in the curved portion 60.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device (semiconductor module) incorporating a power semiconductor element. [Background technology]

[0002] Power semiconductor elements are used, for example, as switching elements for power conversion. A known conventional semiconductor device incorporating a power semiconductor element has a structure in which a power semiconductor chip (hereinafter simply referred to as a "semiconductor chip") constituting the power semiconductor element is disposed on an insulating circuit board, and the semiconductor chip is bonded to the insulating circuit board and terminals with bonding wires.

[0003] Patent Document 1 discloses a wiring structure for a semiconductor device in which a semiconductor LSI package is mounted on a motherboard substrate via solder balls, in which an IC is flip-chip connected to a flexible substrate in a package substrate that is wired and connected to the motherboard substrate, and the IC is connected to the package substrate via the flexible substrate.

[0004] Patent Document 2 discloses a semiconductor device in which upper and lower arms for three phases are formed using an insulating circuit board, multiple semiconductor chips mounted on the insulating circuit board, and a printed circuit board arranged above the multiple semiconductor chips. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-167610 [Patent Document 2] Patent Publication No. 2021-19063 Summary of the Invention [Problem to be solved by the invention]

[0006] In a conventional semiconductor device incorporating a power semiconductor element, when the semiconductor chip is joined to the insulating circuit board and terminals with bonding wires, the wiring length and current path become longer, resulting in a problem of increased inductance.

[0007] In view of the above problems, an object of the present invention is to provide a semiconductor device that can shorten the wiring length and current path and reduce inductance. [Means for solving the problem]

[0008] One aspect of the present invention is a semiconductor device comprising: (a) an insulated circuit board having first and second conductive layers on its upper surface; (b) a first semiconductor chip mounted on the first conductive layer; (c) a second semiconductor chip mounted on the second conductive layer; (d) a printed circuit board having a first lower wiring layer arranged opposite the first semiconductor chip and a second lower wiring layer arranged opposite the second semiconductor chip, the printed circuit board having a curved portion curved toward the insulated circuit board; (e) a first connecting member connecting the first semiconductor chip and the first lower wiring layer; (f) a second connecting member connecting the second semiconductor chip and the second lower wiring layer; (g) a third connecting member connecting the first conductive layer and the second lower wiring layer at the curved portion; and (h) a sealing member sealing the first and second semiconductor chips, the printed circuit board, and the first to third connecting members. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a semiconductor device that can shorten the wiring length and current path and reduce inductance. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a side view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a plan view of the insulating circuit board and semiconductor chip according to the first embodiment. [Figure 3] 1 is a plan view of a printed circuit board according to a first embodiment, viewed from the upper surface side. [Figure 4] FIG. 2 is a plan view of the printed circuit board according to the first embodiment, viewed from the bottom side. [Figure 5] 1 is an equivalent circuit diagram of a semiconductor device according to a first embodiment. [Figure 6] FIG. 10 is a cross-sectional view of a semiconductor device according to a comparative example. [Figure 7] 2A and 2B are side views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 8 is a side view continuing from FIG. 7 for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 9] 9 is a side view continuing from FIG. 8 for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 10] FIG. 10 is a plan view of a printed circuit board according to a second embodiment, as viewed from the upper surface side. [Figure 11] FIG. 10 is a plan view of the printed circuit board according to the second embodiment, viewed from the bottom side. [Figure 12] FIG. 10 is a plan view of a printed circuit board according to a third embodiment, as viewed from the upper surface side. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, first to third embodiments will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the first to third embodiments shown below are examples of devices and methods for embodying the technical concept of the present invention, and the technical concept of the present invention does not limit the materials, shapes, structures, arrangements, etc. of component parts to those described below.

[0012] In the following description, the "first main electrode" of a semiconductor chip means either the source electrode or the drain electrode in the case of a field effect transistor (FET) or a static induction transistor (SIT). In the case of an insulated gate bipolar transistor (IGBT), it means either the emitter electrode or the collector electrode. In the case of a static induction thyristor (SI thyristor), a gate turn-off thyristor (GTO), or a diode, it means either the anode electrode or the cathode electrode. Also, semiconductor chip The "second main electrode" in the above means either the source electrode or the drain electrode, which is not the first main electrode, in the case of an FET or SIT. In the case of an IGBT, it means either the emitter electrode or the collector electrode, which is not the first main electrode. In the case of an SI thyristor, GTO, or diode, it means either the anode electrode or the cathode electrode, which is not the first main electrode. In other words, if the "first main electrode" is the source electrode, the "second main electrode" means the drain electrode. If the "first main electrode" is the emitter electrode, the "second main electrode" means the collector electrode. If the "first main electrode" is the anode electrode, the "second main electrode" means the cathode electrode. Also, the "main electrode" of a semiconductor chip means either the "first main electrode" or the "second main electrode."

[0013] In addition, the definitions of directions such as "up," "down," "up and down," "left," "right," and "left and right" in the following explanation are merely definitions for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, "up and down" is converted and read as "left and right," and of course, if it is rotated 180 degrees and observed, "up and down" is read in reverse.

[0014] In the following description, of the three directions that are orthogonal to each other in space, the first and second directions that are orthogonal to each other in the same plane are referred to as the X direction and the Y direction, respectively, and the third direction that is orthogonal to each of the first and second directions is referred to as the Z direction.

[0015] (First embodiment) <Configuration of semiconductor device> The semiconductor device according to the first embodiment is a semiconductor module called "2-in-1" that has the functions of two power semiconductor elements. As shown in Fig. 1, the semiconductor device according to the first embodiment includes an insulating circuit board 1 and semiconductor chips 3a-3d mounted on the insulating circuit board 1 via bonding materials 2a-2d such as solder or sintered material.

[0016] A printed circuit board 6 is arranged above the semiconductor chips 3a to 3d at a distance from the semiconductor chips 3a to 3d. The printed circuit board 6 includes lower wiring layers 63a and 63c arranged opposite the semiconductor chips 3a and 3b, and a lower wiring layer 63b arranged opposite the semiconductor chips 3c and 3d. Ta The printed circuit board 6 has lower wiring layers 63b and 63d. The printed circuit board 6 has a curved portion 60 curved toward the insulating circuit board 1 at the center in the longitudinal direction (X-axis direction) of the printed circuit board 6.

[0017] The semiconductor chips 3a to 3d are electrically connected to the printed circuit board 6 via connection members 21a to 21d and 23a to 23d. Connection members 21a and 21b connect the semiconductor chips 3a and 3b to the lower wiring layer 63a. Connection members 23a and 23b connect the semiconductor chips 3a and 3b to the lower wiring layer 63c. Connection members 21c and 21d connect the semiconductor chips 3c and 3d to the lower wiring layer 63b. Connection members 23c and 23d connect the semiconductor chips 3c and 3d to the lower wiring layer 63d. Connection members 21a and 21b connect the semiconductor chips 3a and 3b to the lower wiring layer 63b. upper side The conductive layer 12a and the curved portion 60 of the printed circuit board 6 R It is connected to the lower wiring layer 63b.

[0018] The semiconductor chips 3a to 3d and the printed circuit board 6 are sealed with a sealing member 8, and the semiconductor chips 3a to 3d and the printed circuit board 6 are electrically insulated from the surroundings.

[0019] The insulating circuit board 1 includes an insulating substrate 11 and an upper surface (circuit surface side) of the insulating substrate 11. Conductive layer (Conductive plates) 12a, 12b and a lower side disposed on the lower surface (cooling surface side) which is the other main surface of the insulating substrate 11. Conductive layer(heat sink) 13.

[0020] The insulating substrate 11 is made of a resin substrate made of a resin such as epoxy. By using a resin substrate instead of a ceramic substrate as the insulating substrate 11, the upper side provided on the insulating substrate 11 can be easily formed. Conductive layer The shapes of 12a and 12b can be freely set. Conductive layer 12a, 12b and the lower side Conductive layer The reference numeral 13 is made of a conductive foil made of, for example, copper (Cu) or aluminum (Al).

[0021] 2 is a plan view of the insulating circuit board 1 and the semiconductor chips 3a to 3h as viewed from the top side. Conductive layer 12a has a rectangular planar pattern. Conductive layer 12b has an L-shaped planar pattern. Conductive layer 12b is the high-potential external connection terminal (drain side connection terminal) 71 are integrally formed. The drain side connection terminal 71 protrudes from the insulating substrate 11 and extends along the short side direction (Y direction) of the insulating circuit board 1. The drain side connection terminal 71 protrudes from the side surface of the sealing member 8 shown in FIG. 1 and is connected to an external circuit. Conductive layer The position of the drain-side connection terminal 71 formed integrally with 12b is not particularly limited and can be changed as appropriate. Furthermore, the drain-side connection terminal 71 may be bent into an L shape and extended upward (in the Z-axis direction).

[0022] The insulating circuit board 1 may be, for example, a direct copper bonded (DCB) board or an activated metal brazing (AMB) board. The insulating substrate 11 may be a ceramic substrate made of, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), or boron nitride (BN). When the insulating substrate 11 is made of a ceramic substrate, the upper Conductive layer 12b is provided in a rectangular planar pattern, and the upper Conductive layerA drain-side connection terminal 71 may be connected onto 12b via a bonding material such as solder. In this case, too, the drain-side connection terminal 71 may be bent into an L shape and extended upward (in the Z-axis direction).

[0023] As shown in Figure 2, the upper Conductive layer Four semiconductor chips 3a, 3b, 3e, and 3f that form the lower arm are mounted on 12a. Conductive layer Four semiconductor chips 3c, 3d, 3g, and 3h that constitute the upper arm are mounted on 12b. The number of semiconductor chips 3a to 3h is not particularly limited and can be selected appropriately depending on the rated current, etc. For example, the lower arm and the upper arm may be composed of one semiconductor chip each.

[0024] The semiconductor chips 3a-3h may be made of, for example, silicon (Si) material, or wide bandgap semiconductor material such as silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga2O3). The types of the semiconductor chips 3a-3h vary depending on the application, but possible examples include power semiconductor elements such as field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), static induction (SI) thyristors, and gate turn-off (GTO) thyristors, and rectifying elements such as free wheel diodes (FWDs). Here, we will explain the case where the semiconductor chips 3a-3h are SiC MOSFETs.

[0025] The semiconductor chips 3a to 3h each have a first main electrode (drain electrode) on the bottom surface side, and a control electrode (gate electrode) and a second main electrode (source electrode) on the top surface side. The drain electrodes on the bottom surfaces of the semiconductor chips 3a, 3b, 3e, and 3f are connected to the top surface of the insulating circuit board 1 via bonding materials 2a and 2b such as solder or sintered material. Conductive layer The drain electrodes on the lower surfaces of the semiconductor chips 3c, 3d, 3g, and 3h are bonded to the upper surface of the insulating circuit board 1 via bonding materials 2c and 2d, such as solder or sintered material. Conductive layer It is joined to 12b.

[0026] The source electrodes of the semiconductor chips 3a to 3h are provided with connecting members 21a to 21h, 23a to 23h. 23h are bonded to the gate electrodes of the semiconductor chips 3a to 3h via a bonding material such as solder or a sintered material. Connection members 22a to 22h are bonded to the gate electrodes of the semiconductor chips 3a to 3h via a bonding material such as solder or a sintered material.

[0027] Eight connection members 21a and one connection member 23a are bonded to the source electrode of the semiconductor chip 3a. One connection member 22a is bonded to the gate electrode of the semiconductor chip 3a. Eight connection members 21b and one connection member 23b are bonded to the source electrode of the semiconductor chip 3b. One connection member 22b is bonded to the gate electrode of the semiconductor chip 3b. Eight connection members 21c and one connection member 23c are bonded to the source electrode of the semiconductor chip 3c. One connection member 22c is bonded to the gate electrode of the semiconductor chip 3c. Eight connection members 21d and one connection member 23d are bonded to the source electrode of the semiconductor chip 3d. One connection member 22d is bonded to the gate electrode of the semiconductor chip 3d.

[0028] Eight connecting members 21e and one connecting member 23e are bonded to the source electrode of the semiconductor chip 3e. One connecting member 22e is bonded to the gate electrode of the semiconductor chip 3e. Eight connecting members 21f and one connecting member 23f are bonded to the source electrode of the semiconductor chip 3f. One connecting member 22f is bonded to the gate electrode of the semiconductor chip 3f. Eight connecting members 21g and one connecting member 23g are bonded to the source electrode of the semiconductor chip 3g. One connecting member 22g is bonded to the gate electrode of the semiconductor chip 3g. Eight connecting members 21h and one connecting member 23h are bonded to the source electrode of the semiconductor chip 3h. One connecting member 22h is bonded to the gate electrode of the semiconductor chip 3h.

[0029] The numbers of connecting members 21a to 21h, 22a to 22h, and 23a to 22h connected to the semiconductor chips 3a to 3h are not particularly limited and can be set as appropriate.

[0030] Top side of insulating circuit board 1 Conductive layer Upper side of 12a Conductive layer A plurality of (2 columns x 8 rows) connecting members 21 are joined to the end portion adjacent to 12b via a joining material such as solder or a sintered material. The connecting members 21 are provided in the center of the insulating circuit board 1 in the longitudinal direction (X-axis direction). The connecting members 21 are arranged in two rows in the lateral direction (Y-axis direction) of the insulating circuit board 1, but may also be arranged in a single row. The number of connecting members 21 is not particularly limited and can be set as appropriate.

[0031] The connection members 21, 21a to 21h, 22a to 22h, and 23a to 23h have the same configuration and the same length. The connection members 21, 21a to 21h, 22a to 22h, and 23a to 23h are configured as pins made of a metal material such as copper (Cu). The connection members 21, 21a to 21h, 22a to 22h, and 23a to 23h are rod-shaped or column-shaped, and specifically may be polygonal prisms such as circular cylinders, elliptical cylinders, triangular prisms, and quadrangular prisms. The connection members 21, 21a to 21h, 22a to 22h, and 23a to 23h may be bumps or balls made of a metal material such as copper (Cu), or may be solder balls.

[0032] Here, a case will be illustrated in which the connection members 21, 21a to 21h, 22a to 22h, and 23a to 23h are inserted into through holes in the printed circuit board 6 and penetrate up to the upper wiring layers 62a to 62d of the printed circuit board 6. In Fig. 1, the portions where the connection members 21, 21a to 21d, and 23a to 23d penetrate the printed circuit board 6 are schematically shown by dashed lines. The connection members 21, 21a to 21h, 22a to 22h, and 23a to 23h may protrude upward from the upper wiring layers 62a to 62d of the printed circuit board 6.

[0033] When the connection members 21, 21a to 21h, 22a to 22h, and 23a to 23h are configured with bumps or the like, the connection members 21, 21a to 21h, 22a to 22h, and 23a to 23h may be joined to the lower wiring layers 63a to 63d of the printed circuit board 6 via a joining material such as solder or a sintered material, without penetrating the printed circuit board 6. In this case, by providing through holes in the insulating layer 61 of the printed circuit board 6 and filling them with filled vias or the like, the upper wiring layers 62a to 62d and the lower wiring layers 63a to 63 d may be electrically connected to each other.

[0034] The printed circuit board 6 shown in FIG. 1 is made of a flexible board (laminate flexible board). FIG. 3 is a plan view of the printed circuit board 6 seen from the top side, and FIG. 4 is a plan view of the printed circuit board 6 seen from the bottom side. As shown in FIGS. 1, 3, and 4, the printed circuit board 6 includes an insulating layer 61, upper wiring layers 62a to 62d arranged on the top surface of the insulating layer 61, and lower wiring layers 63a to 63d arranged on the bottom surface of the insulating layer 61. The insulating layer 61 is made of a resin film made of a resin such as polyimide. The upper wiring layers 62a to 62d and the lower wiring layers 63a to 63d are made of conductive foil made of, for example, copper (Cu) or aluminum (Al).

[0035] A curved portion 60 is provided in the center of the printed circuit board 6 in the longitudinal direction (X direction), where part of the printed circuit board 6 is curved so as to be convex toward the insulating circuit board 1. The curved portion 60 includes part of the insulating layer 61, part of the upper wiring layer 62b, and part of the lower wiring layer 63b.

[0036] The step of the curved portion 60 shown in FIG. D1 may be the same as the total thickness t1 of the bonding materials 2a to 2d and the semiconductor chips 3a to 3d. Conductive layerThe height h1 of the connection member 21 connecting the semiconductor chips 12a to the lower wiring layer 63b of the curved portion 60 of the printed circuit board 6 can be set to be the same as the height h2 of the connection members 21a to 21h, 22a to 22h, and 23a to 23h connecting the semiconductor chips 3a to 3h to the lower wiring layers 63a to 63d of the printed circuit board 6. Since the connection members 21 and the connection members 21a to 21h, 22a to 22h, and 23a to 23h penetrate the printed circuit board 6 having a thickness t2, the length (h1+t2) of the connection member 21 and the height h2 of the connection members 21a to 21h, 22a to 22h, and 23a to 23h are set to be the same as the height h2 of the connection members 21a to 21h, 22a to 22h, and 23a to 23h. The lengths (h2+t2) of 1a to 21h, 22a to 22h, and 23a to 23h are the same.

[0037] 3, the upper wiring layer 62a has a C-shaped planar pattern. The connection members 21a, 21b, 21e, and 21f penetrate and are joined to the through holes of the upper wiring layer 62a. The upper wiring layer 62a is electrically connected to the source electrodes of the semiconductor chips 3a, 3b, 3e, and 3f via the connection members 21a, 21b, 21e, and 21f.

[0038] One end of a low-potential side external connection terminal (source-side connection terminal) 73 is joined to the upper wiring layer 62a via a joining material such as solder. The source-side connection terminal 73 is made of a metal material such as copper (Cu). The source-side connection terminal 73 protrudes from the printed circuit board 6 and extends along the short-side direction (Y-axis direction) of the printed circuit board 6. The other end of the source-side connection terminal 73 protrudes from the side surface of the sealing member 8 shown in FIG. 1 and is connected to an external circuit. The source-side connection terminal 73 may be bent into an L shape and extended upward (Z-axis direction). The source-side connection terminal 73 is not shown in FIG. 1.

[0039] 3, the upper wiring layer 62b is spaced apart from the upper wiring layer 62a and has a C-shaped planar pattern. The connection members 21c, 21d, 21g, and 21h penetrate and are bonded to the through holes of the upper wiring layer 62b. The upper wiring layer 62b is electrically connected to the source electrodes of the semiconductor chips 3c, 3d, 3g, and 3h via the connection members 21c, 21d, 21g, and 21h.

[0040] At the curved portion 60 of the printed circuit board 6, the connection member 21 is passed through and joined to the through-hole of the upper wiring layer 62b. The upper wiring layer 62b is connected to the upper side of the insulating circuit board 1 via the connection member 21. Conductive layer 12a.

[0041] One end of an output-side external connection terminal (output terminal) 72 is connected to the upper wiring layer 62b via a bonding material such as solder. The output terminal 72 is made of a metal material such as copper (Cu). The output terminal 72 protrudes from the printed circuit board 6 and extends in the opposite direction to the source-side connection terminal 73 along the short side direction (Y-axis direction) of the printed circuit board 6. The other end of the output terminal 72 protrudes from the side surface of the sealing member 8 shown in FIG. 1 and is connected to an external circuit. The output terminal 72 may be bent into an L shape and extended upward (Z-axis direction). The output terminal 72 is not shown in FIG. 1.

[0042] 3, the upper wiring layer 62c is disposed so as to be surrounded by the upper wiring layer 62a and has a rectangular planar pattern. Connection members 22a, 22b, 22e, and 22f penetrate and are bonded to the through holes of the upper wiring layer 62c. The upper wiring layer 62c is electrically connected to the gate electrodes of the semiconductor chips 3a, 3b, 3e, and 3f via the connection members 22a, 22b, 22e, and 22f. Connection members 23a, 23b, 23e, and 23f penetrate the other through holes of the upper wiring layer 62c, but are separated from the upper wiring layer 62c.

[0043] One end of a gate control terminal 76 is connected to the upper wiring layer 62c via a bonding material such as solder. The gate control terminal 76 protrudes from the printed circuit board 6 and extends in the same direction as the output terminal 72 along the short side direction (Y-axis direction) of the printed circuit board 6. The other end of the gate control terminal 76 protrudes from the side surface of the sealing member 8 shown in FIG. 1 and is connected to an external circuit. The gate control terminal 76 may be bent into an L shape and extended upward (Z-axis direction). The gate control terminal 76 is not shown in FIG. 1.

[0044] The upper wiring layer 62d is disposed so as to be surrounded by the upper wiring layer 62b and has a rectangular planar pattern. Connection members 22c, 22d, 22g, and 22h penetrate and are bonded to the through holes of the upper wiring layer 62d. The upper wiring layer 62d is electrically connected to the gate electrodes of the semiconductor chips 3c, 3d, 3g, and 3h via the connection members 22c, 22d, 22g, and 22h. Connection members 23c, 23d, 23g, and 23h penetrate the other through holes of the upper wiring layer 62d, but are separated from the upper wiring layer 62d.

[0045] One end of a gate control terminal 74 is connected to the upper wiring layer 62d via a bonding material such as solder. The gate control terminal 74 protrudes from the printed circuit board 6 and extends in the same direction as the gate control terminal 76 and the output terminal 72 along the short side direction (Y-axis direction) of the printed circuit board 6. The other end of the gate control terminal 74 protrudes from the side surface of the sealing member 8 shown in FIG. 1 and is connected to an external circuit. The gate control terminal 74 may be bent into an L shape and extended upward (Z-axis direction). The gate control terminal 74 is not shown in FIG. 1.

[0046] As shown in FIGS. 3 and 4, for example, the upper wiring layers 62a-62d and the lower wiring layers 63a-63d have similar circuit patterns that overlap each other with the insulating layer 61 sandwiched therebetween. As shown in FIG. 4, the lower wiring layer 63a is provided at a position overlapping the upper wiring layer 62a with the insulating layer 61 sandwiched therebetween and has a C-shaped planar pattern. Connection members 21a, 21b, 21e, and 21f penetrate and are bonded to the through holes of the lower wiring layer 63a. The lower wiring layer 63a is electrically connected to the source electrodes of the semiconductor chips 3a, 3b, 3e, and 3f and the upper wiring layer 62a via the connection members 21a, 21b, 21e, and 21f. Note that instead of bonding the source side connection terminal 73 to the upper wiring layer 62a, the source side connection terminal 73 may be bonded to the lower wiring layer 63a.

[0047] The lower wiring layer 63b is provided at a position overlapping the upper wiring layer 62b with the insulating layer 61 sandwiched therebetween. The lower wiring layer 63b is provided at a distance from the lower wiring layer 63a and has a C-shaped planar pattern. The connection members 21c, 21d, 21g, and 21h penetrate and are joined to the through holes of the lower wiring layer 63b. The lower wiring layer 63b is electrically connected to the source electrodes of the semiconductor chips 3c, 3d, 3g, and 3h and the upper wiring layer 62b via the connection members 21c, 21d, 21g, and 21h.

[0048] At the curved portion 60 of the printed circuit board 6, the connection member 21 is passed through and joined to the through-hole of the lower wiring layer 63b. The lower wiring layer 63b is connected to the upper side of the insulating circuit board 1 via the connection member 21. Conductive layer The output terminal 72 is electrically connected to the lower wiring layer 63b instead of the upper wiring layer 62b.

[0049] The lower wiring layer 63c is provided at a position overlapping the upper wiring layer 62c with the insulating layer 61 sandwiched therebetween. The lower wiring layer 63c is disposed so as to be surrounded by the lower wiring layer 63a and has a rectangular planar pattern. The connection members 23a, 23b, 23e, and 23f penetrate and are bonded to the through holes of the lower wiring layer 63c. The lower wiring layer 63c is electrically connected to the source electrodes of the semiconductor chips 3a, 3b, 3e, and 3f via the connection members 23a, 23b, 23e, and 23f. The connection members 22a, 22b, 22e, and 22f penetrate the other through holes of the lower wiring layer 63c, but are separated from the lower wiring layer 63c.

[0050] The lower wiring layer 63c is connected to an auxiliary terminal, which is an external connection terminal for control, via a bonding material such as solder. sauce One end of the terminal (sense terminal) 77 is connected. sauce The terminal 77 protrudes from the printed circuit board 6 and extends in the same direction as the gate control terminals 74, 76 and the output terminal 72 along the short side direction (Y-axis direction) of the printed circuit board 6. sauce The other end of the terminal 77 protrudes from the side surface of the sealing member 8 shown in FIG. 1 and is connected to an external circuit. sauceThe terminal 77 may be bent into an L-shape and extended upward (in the Z-axis direction). sauce The terminal 77 is not shown in FIG.

[0051] The lower wiring layer 63d is disposed at a position overlapping the upper wiring layer 62d with the insulating layer 61 sandwiched therebetween. The lower wiring layer 63d is disposed so as to be surrounded by the lower wiring layer 63b and has a rectangular planar pattern. The connection members 23c, 23d, 23g, and 23h penetrate and are bonded to the through holes of the lower wiring layer 63d. The lower wiring layer 63d is electrically connected to the source electrodes of the semiconductor chips 3c, 3d, 3g, and 3h via the connection members 23c, 23d, 23g, and 23h. The connection members 22c, 22d, 22g, and 22h penetrate the other through holes of the lower wiring layer 63d, but are separated from the lower wiring layer 63d.

[0052] The lower wiring layer 63d is connected to an auxiliary external connection terminal for control via a bonding material such as solder. sauce One end of the terminal (sense terminal) 75 is connected. sauce The terminal 75 protrudes from the printed circuit board 6 and is connected to the gate control terminals 74 and 76, the output terminal 72, and the auxiliary terminals 74 and 76 along the Y-axis. sauce It extends in the same direction as terminal 77. sauce The other end of the terminal 75 protrudes from the side surface of the sealing member 8 shown in FIG. 1 and is connected to an external circuit. sauce The terminal 75 may be bent into an L-shape and extended upward (in the Z-axis direction). sauce The terminal 75 is not shown in FIG.

[0053] 1 constitutes the housing of the semiconductor device according to the first embodiment and has a substantially rectangular parallelepiped shape. The insulating circuit board 1 is exposed from the bottom surface of the sealing member 8. For the sealing member 8, for example, a resin material such as a highly heat-resistant and hard thermosetting resin can be used, and specifically, epoxy resin, maleimide resin, cyanate resin, etc. can be used.

[0054] An example of an equivalent circuit of the semiconductor device according to the first embodiment is shown in FIG. 5. As shown in FIG. 5, the semiconductor device according to the first embodiment constitutes a part of a three-phase bridge circuit. A second main electrode (drain electrode) of the transistor T1 on the upper arm side is connected to the drain side connection terminal P, and a first main electrode (source electrode) of the transistor T2 on the lower arm side is connected to the source side connection terminal N. The source electrode of the transistor T1 and the drain electrode of the transistor T2 are connected to the output terminal U and the auxiliary source terminal S1, respectively. The auxiliary source terminal S2 is connected to the source electrode of the transistor T2. Gate control terminals G1 and G2 are connected to the gate electrodes of the transistors T1 and T2. Body diodes D1 and D2, which serve as freewheeling diodes (FWD), are built into the transistors T1 and T2 and are connected in anti-parallel.

[0055] The drain side connection terminal P shown in Fig. 5 corresponds to the drain side connection terminal 71 shown in Fig. 2, and the source side connection terminal N and output terminal U shown in Fig. 5 correspond to the source side connection terminal 73 and output terminal 72 shown in Fig. 3. The transistor T1 shown in Fig. 5 corresponds to the semiconductor chips 3c, 3d, 3g, and 3h shown in Fig. 1, and the transistor T2 shown in Fig. 5 corresponds to the semiconductor chips 3a, 3b, 3e, and 3f shown in Fig. 1. The gate control terminals G1 and G2 shown in Fig. 5 correspond to the gate control terminals 74 and 76 shown in Fig. 3, and the auxiliary source terminals S1 and S2 shown in Fig. 5 correspond to the auxiliary source terminals 75 and 77 shown in Fig. 3.

[0056] <Operation of the semiconductor device> Next, the operation of the semiconductor device according to the first embodiment will be described with reference to Figures 1 to 4. A control signal from the gate control terminal 76 shown in Figure 3 is applied to the gate electrodes of the semiconductor chips 3a, 3b, 3e, and 3f constituting the lower arm via the upper wiring layer 62c and the connecting members 22a, 22b, 22e, and 22f. A control signal from the gate control terminal 74 is applied to the gate electrodes of the semiconductor chips 3c, 3d, 3g, and 3h constituting the upper arm via the upper wiring layer 62d and the connecting members 22c, 22d, 22g, and 22h. The semiconductor chips 3a, 3b, 3e, and 3f and the semiconductor chips 3c, 3d, 3g, and 3h alternately perform switching operations in response to the control signal.

[0057] The current that enters from the drain side connection terminal 71 shown in FIG. Conductive layer Current flows from the source electrodes of the semiconductor chips 3c, 3d, 3g, and 3h on the upper arm side through the connecting members 21c, 21d, 21g, and 21h, the upper wiring layer 62b, and the lower wiring layer 63b of the printed circuit board 6 shown in FIG.

[0058] In addition, the current that has entered the output terminal 72 from the external circuit flows through the upper wiring layer 62b and the lower wiring layer 63b of the printed circuit board 6, the connecting member 21, the upper wiring layer 62b of the insulating circuit board 1, and the lower wiring layer 63b of the insulating circuit board 1. Conductive layer Current is supplied to the drain electrodes of the semiconductor chips 3a, 3b, 3e, and 3f on the lower arm side via the connection members 21a, 21b, 21e, and 21f, the upper wiring layer 62a, and the lower wiring layer 63a of the printed circuit board 6, and flows from the source-side connection terminal 73 to an external circuit.

[0059] The current on the source electrode side of the semiconductor chips 3a, 3b, 3e, and 3f is detected by an external circuit via the connecting members 23a, 23b, 23e, and 23f, the lower wiring layer 63c of the printed circuit board 6, and the auxiliary source terminal 77. The current on the source electrode side of the semiconductor chips 3c, 3d, 3g, and 3h is detected by an external circuit via the connecting members 23c, 23d, 23g, and 23h, the lower wiring layer 63d of the printed circuit board 6, and the auxiliary source terminal 75.

[0060] <Comparative Example> Here, a semiconductor device (power semiconductor module) according to a comparative example will be described. As shown in Fig. 6, power semiconductor module 113 according to the comparative example includes metal base plate 101 for heat dissipation, insulating circuit board 102 mounted on metal base plate 101 via solder 103, and semiconductor chip 104 mounted on insulating circuit board 102 via solder 105. Insulating circuit board 102 is composed of ceramic substrate 102a and copper plates 102b and 102c attached to the upper and lower surfaces of ceramic substrate 102a.

[0061] The insulating circuit board 102 and the metal base plate 101 are housed in a resin case 106. Terminals 107 and 108 are arranged inside the resin case 106. The semiconductor chip 104, the terminals 107 and 108, and the insulating circuit board 102 are joined by bonding wires 110 and 111. The side surfaces of the resin case 106, together with the upper surfaces of the metal base plate 101 and the insulating circuit board 102, form a space surrounding the semiconductor chip 104, and the interior is filled with a sealing member 112. This ensures insulation between the semiconductor chip 104, the insulating circuit board 102, the metal base plate 101, and the terminals 107 and 108.

[0062] The power semiconductor module 113 according to the comparative example is attached to a cooling member 116 via a ring 115 by screws 114 at two or four points on both ends of a metal base plate 101, and heat is dissipated via a heat dissipation grease 117.

[0063] In power semiconductor module 113 according to the comparative example, semiconductor chip 104 is joined to insulating circuit board 102 and terminals 107, 108 with bonding wires 110, 111, resulting in long wiring and long current paths, and increased inductance in the main circuit. In contrast, in the semiconductor device according to the first embodiment, printed circuit board 6 is curved and insulating circuit board 1 is connected to printed circuit board 6 using connecting member 21, thereby shortening the wiring length and reducing the inductance of the main circuit. Furthermore, since there is no need to provide a relay area such as a bonding wire, the semiconductor module can be made more compact.

[0064] <Method of manufacturing a semiconductor device> Next, an example of a method for manufacturing (assembling) the semiconductor device according to the first embodiment will be described with reference to Fig. 7 to Fig. 9. As shown in Fig. 7, an insulating circuit board 1 is prepared. Conductive layer The semiconductor chips 3a to 3d are mounted on the insulating circuit board 1 via the bonding materials 2a to 2d. Conductive layer The insulating substrate 11 of the insulating circuit board 1 is made of a resin substrate, and the upper side of the insulating circuit board 1 is Conductive layer The drain side connection terminal 71 shown in FIG. 2 is integrally formed on 12b.

[0065] Next, as shown in Fig. 8, a printed circuit board 6 made of a flat flexible substrate is prepared, and the connecting members 21, 21a, 23a, 21b, 23b, 21c, 23c, 21d, and 23d are inserted into the printed circuit board 6 to form an implant substrate. At this time, the connecting members 21e to 21h, 22a to 22h, and 23e to 23h shown in Figs. 3 and 4 are also inserted into the printed circuit board 6. Furthermore, the output terminal 72 and the source-side connecting terminal 73 shown in Figs. 3 and 4 are joined to the printed circuit board 6.

[0066] Next, the implant substrate shown in FIG. 8 is attached to the upper side of the insulating circuit board 1 shown in FIG. Conductive layerThe printed circuit board 6 is mounted on 12a and 12b via bonding materials 2a to 2d, etc. Subsequently, as shown in FIG.

[0067] Next, by heat treatment, the insulating circuit board 1 and the semiconductor chips 3a to 3h, and the semiconductor chips 3a to 3h and the connecting members 21, 21a to 21h, 22a to 22h, and 23a to 23h are bonded together. 21, 21a-21h, 22a-22h, 23a-23h The printed circuit board 6 is then sealed with a sealing member 8, completing the semiconductor device according to the first embodiment shown in FIG.

[0068] <Effects> As described above, in the semiconductor device according to the first embodiment, in the connection of the intermediate portion of the half bridge formed by the semiconductor chips 3a to 3h, the printed circuit board 6 is curved by taking advantage of the flexibility of the flexible board, and the insulating circuit board 1 and the printed circuit board 6 are electrically connected using the connecting member 21. This allows the wiring length to be shorter than when wire or pin connections are made using a conventional flat printed circuit board, thereby reducing the inductance of the main circuit. Furthermore, since there is no need to provide a relay area such as a bonding wire, the semiconductor module can be made more compact.

[0069] Furthermore, the height h1 of connecting member 21 that connects insulating circuit board 1 and printed circuit board 6 at curved portion 60 of printed circuit board 6 can be made the same as the height h2 of connecting members 21a-21h, 22a-22h, and 23a-23h that connect semiconductor chips 3a-3h to positions on printed circuit board 6 other than curved portion 60. Therefore, the length (h1+t2) of connecting member 21 can be the same as the length (h2+t2) of connecting members 21a-21h, 22a-22h, and 23a-23h, allowing the use of the same parts. This eliminates the need for metal blocks for height adjustment or pin terminals of different lengths, as in the prior art, reducing the number of parts and the number of processes.

[0070] Furthermore, the insulating substrate 11 of the insulating circuit board 1 is made of a resin substrate, and the upper side of the insulating substrate 11 Conductive layer By integrally forming the drain side connection terminal 71 on the insulating circuit board 12b, it is possible to reduce the number of parts and the number of steps required to connect the drain side connection terminal 71 to the insulating circuit board 1.

[0071] Furthermore, upper wiring layers 62c and 62d connected to gate control terminals 74 and 76 of the printed circuit board 6 and auxiliary wiring layers 62c and 62d connected to the gate control terminals 74 and 76 of the printed circuit board 6 are sauce The lower wiring layers 63c and 63d connected to the terminals 75 and 77 have the same plane pattern across the insulating layer 61, and the current paths are configured to be opposite to each other, so that inductance can be reduced.

[0072] (Second embodiment) As shown in FIGS. 10 and 11 , the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment shown in FIGS. 3 and 4 in that slits 64 and 65 are provided in the printed circuit board 6. FIG. 10 is a plan view of the printed circuit board 6 as viewed from the top, and FIG. 11 is a plan view of the printed circuit board 6 as viewed from the bottom. As shown in FIG. 10 , a slit 64 is provided in the upper wiring layer 62b of the printed circuit board 6. As shown in FIG. 11 , a slit 65 is provided in the lower wiring layer 63b of the printed circuit board 6 at a position corresponding to the slit 64. Although FIGS. 10 and 11 illustrate the case where the slits 64 and 65 are provided in two rows, they may also be provided in a single row. Furthermore, a slit may also be provided in the insulating layer 61 sandwiched between the upper wiring layer 62b and the lower wiring layer 63b at a position corresponding to the slits 64 and 65.

[0073] Other configurations of the semiconductor device according to the second embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted. The semiconductor device according to the second embodiment can be realized by the same procedures as the manufacturing method of the semiconductor device according to the first embodiment, except for providing slits 64, 65 in the printed circuit board 6.

[0074] According to the semiconductor device of the second embodiment, the wiring length and current path can be shortened and inductance can be reduced, similar to the configuration of the semiconductor device of the first embodiment. Furthermore, by providing slits 64 and 65 in the printed circuit board 6, the printed circuit board 6 can be easily bent at the positions of the slits 64 and 65 during assembly of the semiconductor device of the second embodiment, making it easier to form the bent portion 60. (Third embodiment) 12, the semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 1 in that notches 66a and 66b indicating the positions where the curved portions 60 are to be formed are provided in the insulating layer 61 of the printed circuit board 6. Note that instead of providing the notches 66a and 66b in the insulating layer 61, notches indicating the positions where the curved portions 60 are to be formed may be provided in the upper wiring layer 62b.

[0075] Other configurations of the semiconductor device according to the third embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted. The semiconductor device according to the third embodiment can be realized by the same procedures as the manufacturing method of the semiconductor device according to the first embodiment, except that notches 66a and 66b are provided in the insulating layer 61 of the printed circuit board 6.

[0076] According to the semiconductor device of the third embodiment, it is possible to shorten the wiring length and current path and reduce inductance, similar to the configuration of the semiconductor device of the first embodiment. Furthermore, by providing notches 66a and 66b indicating the position where the curved portion 60 is to be formed in the insulating layer 61 of the printed circuit board 6, it becomes easier to position the jig 9 and the like when forming the curved portion 60 during assembly of the semiconductor device of the third embodiment.

[0077] (Other embodiments) As described above, the present invention has been described with reference to the first to third embodiments, but the descriptions and drawings that form part of this disclosure should not be construed as limiting the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0078] For example, the configurations disclosed in the first to third embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description. [Explanation of symbols]

[0079] 1...Insulated circuit board 2a~2d…Joining material 3a~3h...Semiconductor chips 6...Printed circuit board 8...Sealing member 9...Jig 11...Insulating substrate 12a,12b...upper side Conductive layer (Conductive plate) 13…lower side Conductive layer (heat sink) 21, 21a to 21h, 22a to 22h, 23a to 23h...Connecting parts 60...Bend 61...insulating layer 62a to 62d...Upper wiring layer 63a~63d...lower wiring layer 64,65...Slit 66a, 66b...Notch 71...External connection terminal (drain side connection terminal) 72...External connection terminal (output terminal) 73...External connection terminal (source side connection terminal) 74, 76...External connection terminals (gate control terminals) 75, 77...External connection terminals (auxiliary source terminals) 101...Metal base plate 102...Insulated circuit board 102a...Ceramic substrate 102b,102c…Copper plate 104...Semiconductor chip 106...Resin case 107, 108...Terminals 110,111...Bonding wire 112...Sealing member 113...Power semiconductor module 114...Screw 115...Ring 116...Cooling member 117...Thermal grease D1, D2...Body diode G1, G2...Gate control terminals N: Source side connection terminal P: Drain side connection terminal S1, S2...Auxiliary source terminals T1, T2...Transistors U: Output terminal

Claims

1. an insulating circuit board having first and second conductive layers on an upper surface thereof; a first semiconductor chip mounted on the first conductive layer; a second semiconductor chip mounted on the second conductive layer; a printed circuit board having an insulating layer, a first lower wiring layer disposed on a lower surface of the insulating layer so as to face the first semiconductor chip, and a second lower wiring layer disposed on a lower surface of the insulating layer so as to face the second semiconductor chip, the printed circuit board having a curved portion curved toward the insulating circuit board; a first connection member that connects the first semiconductor chip and the first lower wiring layer; a second connection member that connects the second semiconductor chip and the second lower wiring layer; a third connection member connecting the first conductive layer and the second lower wiring layer in the curved portion; a sealing member that seals the first and second semiconductor chips, the printed circuit board, and the first to third connection members; Equipped with The semiconductor device is characterized in that a slit or a notch is provided in the printed circuit board at a position corresponding to the curved portion.

2. 2. The semiconductor device according to claim 1, wherein the first to third connection members have the same height.

3. 3. The semiconductor device according to claim 1, wherein the curved portion has a step height equal to the total thickness of the bonding material bonding the first semiconductor chip and the first conductive layer and the thickness of the first semiconductor chip.

4. 4. The semiconductor device according to claim 1, wherein the curved portion is located at the center of the printed circuit board in the longitudinal direction.

5. 5. The semiconductor device according to claim 1, wherein the insulating layer is made of a resin.

6. 6. The semiconductor device according to claim 1, wherein the insulating circuit board comprises a resin substrate having the first and second conductive layers provided on an upper surface thereof.

7. 7. The semiconductor device according to claim 6, further comprising a first external connection terminal formed integrally with the second conductive layer and extending to the outside of the sealing member.

8. the first lower wiring layer is electrically connected to a main electrode of the first semiconductor chip; the second lower wiring layer is electrically connected to a main electrode of the first semiconductor chip; 8. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

9. The printed circuit board is a first upper wiring layer disposed on the upper surface of the insulating layer at a position overlapping the first lower wiring layer with the insulating layer interposed therebetween, the first upper wiring layer being electrically connected to the first lower wiring layer; a second upper wiring layer disposed on the upper surface of the insulating layer at a position overlapping the second lower wiring layer with the insulating layer interposed therebetween, the second upper wiring layer being electrically connected to the second lower wiring layer; 9. The semiconductor device according to claim 1, further comprising:

10. 10. The semiconductor device according to claim 9, further comprising a second external connection terminal connected to the first upper wiring layer.

11. 11. The semiconductor device according to claim 10, further comprising a third external connection terminal connected to the second upper wiring layer.

12. The printed circuit board is a third lower wiring layer disposed on a lower surface of the insulating layer and electrically connected to a first main electrode of the first semiconductor chip; a third upper wiring layer disposed on the upper surface of the insulating layer at a position overlapping the third lower wiring layer with the insulating layer sandwiched therebetween, the third upper wiring layer being electrically connected to a control electrode of the first semiconductor chip; Equipped with 12. The semiconductor device according to claim 9, wherein the current paths of the third lower wiring layer and the third upper wiring layer are opposite to each other.

13. an insulating circuit board having first and second conductive layers on an upper surface thereof; a first semiconductor chip mounted on the first conductive layer; a second semiconductor chip mounted on the second conductive layer; a printed circuit board having an insulating layer, a first lower wiring layer disposed on one main surface of the insulating layer so as to face the first semiconductor chip, and a second lower wiring layer disposed on one main surface of the insulating layer so as to face the second semiconductor chip, the printed circuit board having a curved portion curved toward the insulating circuit board; a first connection member that connects the first semiconductor chip and the first lower wiring layer; a second connection member that connects the second semiconductor chip and the second lower wiring layer; a third connection member connecting the first conductive layer and the second lower wiring layer in the curved portion; a sealing member that seals the first and second semiconductor chips, the printed circuit board, and the first to third connection members; Equipped with The semiconductor device is characterized in that a slit is provided in the printed circuit board at a position corresponding to the curved portion.

14. an insulating circuit board having first and second conductive layers on an upper surface thereof; a first semiconductor chip mounted on the first conductive layer; a second semiconductor chip mounted on the second conductive layer; a printed circuit board having an insulating layer, a first lower wiring layer disposed on one main surface of the insulating layer so as to face the first semiconductor chip, and a second lower wiring layer disposed on one main surface of the insulating layer so as to face the second semiconductor chip, the printed circuit board having a curved portion curved toward the insulating circuit board; a first connection member that connects the first semiconductor chip and the first lower wiring layer; a second connection member that connects the second semiconductor chip and the second lower wiring layer; a third connection member connecting the first conductive layer and the second lower wiring layer in the curved portion; a sealing member that seals the first and second semiconductor chips, the printed circuit board, and the first to third connection members; Equipped with The semiconductor device is characterized in that a notch is provided in the printed circuit board at a position corresponding to the curved portion.

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