semiconductor circuit device

Abstract

Provided is a semiconductor circuit device in which gating can be achieved easily and autonomously. A semiconductor circuit device 10 is provided with arithmetic modules 11A, 11B and a memory module 13, and is provided with gating units 14A, 14B, 15 corresponding to these modules. The gating units 14A, 14B turn on and off, according to an enable signal inputted into the arithmetic modules 11A, 11B corresponding thereto, a power gate switch and a clock gate switch provided corresponding thereto. The gating unit 15 turns on and off, according to a select signal and an enable signal inputted into the memory module 13, a power gate switch provided corresponding to each memory block in the memory module 13, and turns on and off, according to an enable signal, a power gate switch and a clock gate switch provided corresponding to a resistor in the memory module 13.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor circuit device. [Background technology]

[0002] Known technologies for reducing power consumption by reducing leakage current include power gating, which cuts off the power supply, and clock gating, which stops the clock supply. For example, in a semiconductor device described in Patent Document 1, a power supply generation circuit and a clock generation circuit are connected to multiple processor cores having registers, cache memories, and nonvolatile memories via switches, and the on / off of these switches is controlled by a single controller. In addition, in a semiconductor device described in Patent Document 2, power supply voltage is supplied to a memory cell array, peripheral circuits, and backup / recovery drive circuits via switches provided in each of them, and the on / off of each switch is controlled by a single controller.

[0003] Furthermore, in the semiconductor circuit device of Patent Document 3, when power gating is performed on a processor and a cache memory, the temperatures of the nonvolatile storage circuit that holds data obtained by the arithmetic circuit and the nonvolatile storage circuit held in the cache memory are detected, and the controller uses the overhead calculated from the detected temperatures to set the optimal power-off time or to determine whether to perform a power-off, and the controller turns the power-gating switch on and off. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-2726 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-195075 [Patent Document 3] Japanese Patent Application Laid-Open No. 2013-214296 [Patent Document 4] International Publication No. 2015 / 041305 [Patent Document 5] Japanese Patent Application Laid-Open No. 2012-69100 Summary of the Invention [Problem to be solved by the invention]

[0005] In a semiconductor circuit device that performs power gating or clock gating as described above, power consumption can be reduced more effectively by increasing the number of circuits that are the target of the gating. However, if individual gating is controlled by a controller as described above, each time the number of target circuits increases, the controller circuit or program must be modified to achieve gating for the increased number of circuits. This makes it difficult to achieve gating control in large-scale, highly parallel processor systems or SoC systems that are based on circuit technologies such as multi-core (e.g., GPUs (Graphics Processing Units) and TPUs (Tensor Processing Units)).

[0006] The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor circuit device that can easily and autonomously realize gating. [Means for solving the problem]

[0007] In order to achieve the above object, the present invention provides a semiconductor circuit device in which a plurality of target circuits are provided and a control signal is input to each of the target circuits to control whether the circuits are enabled or disabled, the device comprising: a gating control circuit provided for each target circuit, which receives the control signal for the corresponding target circuit and outputs an ON signal in response to the control signal that enables the target circuit; and a power gate switch for each target circuit, which is provided on a power supply line for each target circuit to supply a drive voltage to the target circuit and is turned ON by the ON signal. [Effects of the Invention]

[0008] According to the present invention, the on / off of the power gate switch is controlled using a control signal input to the target circuit, so there is no need to change the circuit or program of the controller to achieve power gating or clock gating, and gating can be easily achieved. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram showing an outline of a semiconductor circuit device; [Figure 2] FIG. 2 is a block diagram showing the configuration of an arithmetic module and a gating unit. [Figure 3] FIG. 2 is a block diagram showing the configuration of a memory module and a gating unit. [Figure 4] FIG. 10 is a block diagram showing an example of power gating of an arithmetic module on the reference potential side. [Figure 5] FIG. 10 is a block diagram showing an example of power gating a memory module on the reference potential side. [Figure 6] FIG. 1 is a block diagram illustrating an example of a semiconductor circuit device that performs arithmetic processing corresponding to a convolutional neural network. [Figure 7] FIG. 10 is an explanatory diagram showing an example of an on / off pattern of a circuit unit. [Figure 8] FIG. 10 is an explanatory diagram showing an example of an on / off pattern of a circuit module according to a processing sequence corresponding to a convolutional neural network. [Figure 9] FIG. 1 is a block diagram illustrating an example of a semiconductor circuit device that performs arithmetic processing corresponding to a full-layer convolutional neural network. [Figure 10] FIG. 10 is an explanatory diagram showing an example of an on / off pattern of a circuit module according to a processing sequence corresponding to a full-layer convolutional neural network. [Figure 11] 10 is a graph showing the results of a simulation of the effect of improving power performance in a semiconductor circuit device. [Figure 12]10 is a graph showing the results of simulating changes in power consumption performance ratio for different overall operating rates. [Figure 13] FIG. 1 is a block diagram showing a configuration of a semiconductor circuit device that performs clustering. [Figure 14] FIG. 1 is a block diagram showing the configuration of a clustering device that performs pipeline clustering. [Figure 15] FIG. 10 is an explanatory diagram showing an example of an on / off pattern of each unit during batch processing of a pipelined clustering device. [Figure 16] FIG. 10 is an explanatory diagram showing an example of an on / off pattern of each unit during high-speed classification processing of a pipelined clustering device. [Figure 17] FIG. 10 is a block diagram showing an example of a semiconductor circuit device in which a detection unit is provided in a circuit module. [Figure 18] FIG. 2 is a circuit diagram showing a gating control circuit corresponding to a memory module. [Figure 19] FIG. 10 is a circuit diagram showing a gating control circuit corresponding to the operation module. DETAILED DESCRIPTION OF THE INVENTION

[0010] [First embodiment] 1, a semiconductor circuit device 10 is provided with a plurality of circuit modules. In this example, the semiconductor circuit device 10 is provided with operation modules 11A and 11B that perform logic operations and a memory module 13 as circuit modules. The semiconductor circuit device 10 is also provided with gating units 14A, 14B, and 15 and a controller 16. For example, the memory module 13 holds data to be used in the operations of the operation modules 11A and 11B, and also stores the operation results of the operation modules 11A and 11B. Note that, while this example shows one memory module 13 and two operation modules 11A and 11B in the semiconductor circuit device 10, the present invention is not limited to this. For example, the number of these modules can be any number. Furthermore, the semiconductor circuit device 10 may be configured with a plurality of either memory modules or operation modules, or may further include other circuit modules.

[0011] The operation modules 11A, 11B and memory module 13 operate by receiving a drive voltage from a power supply 17 and a clock from a clock generation unit 18, and the enable / disable of the circuit modules themselves or their internal circuits is controlled by a control signal from a controller 16. Therefore, the operation modules 11A, 11B and memory module 13 are target circuits that are themselves or their internal circuits are power gating or clock gating. In other words, the target circuits are circuits that are subject to power gating or clock gating, but the target circuits are also circuits that are input with control signals from a circuit (controller 16 in this example) that controls the enable / disable of the target circuits via control signals, and the enable / disable of the circuits is controlled by the control signals.

[0012] "Enabling" a circuit module or circuit means that the circuit module or circuit is active, i.e., in operation or permitted to operate, while "disabling" means that the circuit module or circuit is inactive, i.e., not in operation or prohibited to operate, and a control signal is a signal that puts the circuit module or circuit into such a state. For example, a control signal could be an enable signal for a circuit module composed of a latch circuit or register, or a select signal for specifying a memory element or group of memory elements that has decoded an address. A control signal could also be a trigger signal that causes a circuit module or circuit to start a specific operation, or a command that instructs the circuit module or circuit to execute a specific function.

[0013] In this example, as will be described later, the operation modules 11A and 11B include registers, and the memory module 13 includes a register and a memory array. The controller 16 inputs an enable signal as a control signal to the operation modules 11A and 11B, and also inputs the enable signal and a select signal obtained by decoding a memory address to the memory module 13. The controller 16 may be provided outside the semiconductor circuit device 10.

[0014] The gating units 14A and 14B corresponding to the operation modules 11A and 11B autonomously perform power gating and clock gating for the operation modules 11A and 11B using enable signals input to the operation modules 11A and 11B, respectively. The operation unit 19 of the semiconductor circuit device 10 in this example is capable of independently performing power gating and clock gating for the multiple operation modules (in this example, operation modules 11A and 11B) that make it up. The gating unit 15 corresponding to the memory module 13 autonomously performs power gating and clock gating for the memory module 13 using enable signals and select signals input to the memory module 13.

[0015] 2, the arithmetic module 11A in this example has a plurality of arithmetic circuits 21 and registers 22. Each arithmetic circuit 21 operates by receiving a drive voltage from the power supply 17 via a power supply line LP1A common to the arithmetic module 11A, performs a logical operation on data input from the register 22 in the previous stage, and outputs the result to the register 22 in the next stage.

[0016] Each register 22 operates by receiving a drive voltage from the power supply 17 and a clock from the clock generating unit 18 via a power supply line LP1A and a clock line LC1A. An enable signal from the controller 16 is input to each register 22 via a signal line LS1A common to all registers. When a drive voltage is supplied and the enable signal is active, each register 22 latches and outputs the input multi-bit data in synchronization with the clock. The configuration of the arithmetic module 11A shown in FIG. 2 is merely an example and is not limiting.

[0017] The gating section 14A corresponding to the operation module 11A is composed of a gating control circuit 24, a power gate switch 25, and a clock gate switch 26. In this example, the gating control circuit 24 is composed of two NOT circuits 24a connected in series. A signal line LS1A is connected to this gating control circuit 24, and an enable signal input from the controller 16 to the operation module 11A is input. The gating control circuit 24 outputs an ON signal (activates the output) when the enable signal is active, and outputs an OFF signal (deactivates the output) when the enable signal is inactive. That is, the gating control circuit 24 outputs an ON signal in response to an active enable signal that enables the operation module 11A, and outputs an OFF signal in response to an inactive enable signal that disables the operation module 11A.

[0018] The power gate switch 25 is a switch configured of a MOS transistor or the like, and is controlled to be turned on or off by the gating control circuit 24. This power gate switch 25 is provided on a power line LP1A that supplies a drive voltage to the operation module 11A, and is turned on when an on signal is input from the gating control circuit 24, and is turned off when an off signal is input. In this example, the power gate switch 25 is provided on the power supply potential (VDD) side of the power line LP1A. When the power gate switch 25 is turned on, the drive voltage is supplied to the operation module 11A, and when the power gate switch 25 is turned off, the supply of the drive voltage is cut off. Note that the configuration of the power gate switch 25 is not limited as long as it can switch between supplying and cutting off the drive voltage.

[0019] The clock gate switch 26 is provided on the clock line LC1A that supplies a clock to the operation module 11A. In this example, the clock gate switch 26 is configured as a three-state buffer, and the output of the gating control circuit 24 is connected to its control input terminal, and its operation is controlled by the gating control circuit 24. The clock gate switch 26 is turned on (conductive) by an on signal from the gating control circuit 24, and supplies the clock from the clock generating unit 18 to the operation module 11A. In addition, the output of the clock gate switch 26 becomes high impedance, i.e., is turned off (non-conductive), by an off signal from the gating control circuit 24, and blocks the clock to the operation module 11A.

[0020] The configuration of the operation module 11B is the same as that of the operation module 11A. A drive voltage and a clock are supplied to the operation module 11B via a power supply line LP1B and a clock line LC1B. An enable signal from the controller 16 is input to the operation module 11B via a signal line LS1B.

[0021] Furthermore, the gating unit 14B provided corresponding to the operation module 11B has the same configuration as the gating unit 14A provided corresponding to the operation module 11A, and is composed of a gating control circuit 24, a power gate switch 25, and a clock gate switch 26. In the gating unit 14B, the power gate switch 25 is provided on the power supply line LP1B, and the clock gate switch 26 is provided on the clock line LC1B, and the gating control circuit 24 is connected to a signal line LS1B, and receives an enable signal input from the controller 16 to the operation module 11B.

[0022] The above-mentioned operation modules 11A and 11B are circuits to be power-gated and clock-gated by a power gate switch 25 and a clock gate switch 26 which are turned on and off by the corresponding gating control circuit 24, respectively.

[0023] In FIG. 3, the memory module 13 includes a memory array 31 and a register 32. The memory array 31 includes a plurality of nonvolatile memory cells 31a arranged in a matrix. The memory array 31 is divided into a plurality of memory blocks MBa, MBb, etc. Hereinafter, the memory blocks MBa, MBb, etc. will be referred to as a memory block MB unless otherwise specified. In this example, one memory block MB is composed of a plurality of memory cells 31a arranged in a vertical row in FIG. 3. Power supply lines LP2a, LP2b, etc. and signal lines LS2a, LS2b, etc. are provided corresponding to each of the memory blocks MBa, MBb, etc. Hereinafter, the power supply lines LP2a, LP2b, etc. will be referred to as a power supply line LP2 unless otherwise specified, and the signal lines LS2a, LS2b, etc. will be referred to as a signal line LS2 unless otherwise specified. The memory cells 31a are preferably configured using, for example, an STT-MRAM using magnetic tunnel junction (MTJ) elements.

[0024] Each memory cell 31a in each memory block MB is connected to a power supply line LP2 and a signal line LS2 corresponding to that memory block MB. The power supply line LP2 is connected to a power supply 17, and a drive voltage is supplied to the memory cell 31a via this power supply line LP2.

[0025] Signal line LS2 is also connected to the controller 16, and a select signal as a control signal is input to the memory cell 31a via this signal line LS2. The memory cell 31a performs a data read or write operation when the select signal is active, and does not operate when the select signal is inactive. Therefore, in the memory array 31, data read or write is selected on a memory block basis. The controller 16 controls whether the select signal is active or inactive based on, for example, the address from which data is read or written.

[0026] The register 32 is a data input / output circuit that temporarily holds data read from the memory block MB or data to be written. Data is input / output between the memory array 31 and the operation modules 11A and 11B via the register 32. The register 32 operates by receiving a drive voltage from the power supply 17 and a clock from the clock generating unit 18 via a power supply line LP3 and a clock line LC3. An enable signal from the controller 16 is also input to the register 32 via a signal line LS3. When a drive voltage is supplied and the enable signal is active, the register 32 latches and outputs the input multi-bit data in synchronization with the clock.

[0027] The gating unit 15 corresponding to the memory module 13 is made up of gating control circuits 34a, 34b... and power gate switches 35a, 35b... provided corresponding to each of the memory blocks MBa, MBb..., and a gating control circuit 36, power gate switch 37, and clock gate switch 38 for the register 32. In the following description, when the gating control circuits 34a, 34b... are not distinguished, they will be referred to as the gating control circuit 34, and when the power gate switches 35a, 35b... are not distinguished, they will be referred to as the power gate switch 35.

[0028] The gating control circuit 34 turns on and off the power gate switch 35 of the corresponding memory block MB. The gating control circuit 34 has a configuration in which a NOT circuit 41a and a NAND circuit 41b are connected in series, and the output of the NOT circuit 41a is the output of the gating control circuit 34. The signal line LS2 of the corresponding memory block MB and the signal line LS3 to the register 32 are connected to the inputs of the NAND circuit 41b, and a select signal to the corresponding memory block MB and an enable signal to the register 32 are input. As a result, the gating control circuit 34 outputs an ON signal (the output of the NOT circuit 41a is active) when the select signal to the corresponding memory block MB and the enable signal to the register 32 are active, and outputs an OFF signal (the output of the NOT circuit 41a is inactive) when they are inactive.

[0029] The power gate switch 35 is provided on the power supply line LP2 of the corresponding memory block MB, and its on / off state is controlled by the gating control circuit 34 of the corresponding memory block MB. The power gate switch 35 is provided on the power supply potential (VDD) side of the power supply line LP2. The configuration of the power gate switch 35 is similar to that of the power gate switch 25. The power gate switch 35 is turned on when an on signal is input from the gating control circuit 34, and is turned off when an off signal is input from the gating control circuit 34. When the power gate switch 35 is turned on, a drive voltage is supplied to each memory cell 31a of the corresponding memory block MB, and when the power gate switch 35 is turned off, the supply of the drive voltage is cut off. Therefore, when a select signal for the memory block MB is active and an enable signal to the register 32 is active, the power gate switch 35 is turned on, a drive voltage is supplied, and reading or writing becomes possible for any memory block MB in the memory array 31.

[0030] In this example, as described above, power gating for the memory block MB is controlled by both the select signal for the memory block MB and the enable signal to register 32, but power gating for the memory block MB may also be controlled by only the select signal for the memory block MB.

[0031] The power gate switch 37 is provided on the power supply line LP3, and the clock gate switch 38 is provided on the clock line LC3, and both are turned on and off by a gating control circuit 36 ​​consisting of two NOT circuits 36a connected in series. The power gate switch 37 is provided on the power supply potential (VDD) side of the power supply line LP3. A signal line LS3 is connected to the gating control circuit 36.

[0032] The gating control circuit 36, power gate switch 37, and clock gate switch 38 for the register 32 are similar to the gating control circuit 24, power gate switch 25, and clock gate switch 26 corresponding to the register 22 of the arithmetic module 11A. Therefore, when the enable signal input to the register 32 is active, the power gate switch 37 and the clock gate switch 38 are turned on by the on signal from the gating control circuit 36, and a drive voltage and a clock are supplied to the register 32.

[0033] The memory module 13 configured as described above is itself a circuit subject to power gating and clock gating, and each of the memory blocks MB constituting the memory array 31 is also a circuit subject to power gating.

[0034] In the semiconductor circuit device 10, for example, when the operation module 11A is to perform an operation and the operation module 11B is not to perform an operation, the controller 16 activates the enable signal for the operation module 11A and deactivates the enable signal for the operation module 11B. Therefore, an ON signal is output from the gating control circuit 24 of the gating unit 14A, and the power gate switch 25 and the clock gate switch 26 are turned ON by the ON signal. As a result, the operation module 11A performs an operation because the enable signal is active and the drive voltage and clock are supplied. Meanwhile, an OFF signal is output from the gating control circuit 24 of the gating unit 14B, and the power gate switch 25 and the clock gate switch 26 are turned OFF by the OFF signal, thereby cutting off the supply of the drive voltage and clock to the operation module 11B.

[0035] Conversely, when the computing module 11A is not to perform a computation and the computing module 11B is to perform a computation, the controller 16 deactivates the enable signal for the computing module 11A and activates the enable signal for the computing module 11B. As a result, in the gating unit 14A, an off signal is output from the gating control circuit 24, and the power gate switch 25 and the clock gate switch 26 are turned off, so the supply of drive voltage and clock to the computing module 11A is cut off. In contrast, in the gating unit 14B, an on signal is output from the gating control circuit 24, and the power gate switch 25 and the clock gate switch 26 are turned on, so the enable signal for the computing module 11B is active and the driving voltage and clock are supplied, so the computing module 11B performs a computation.

[0036] When causing the operation modules 11A and 11B to perform operations, the controller 16 activates the enable signals for the operation modules 11A and 11B. As a result, the power gate switch 25 and the clock gate switch 26 in each of the gating units 14A and 14B are turned on, and the operation modules 11A and 11B perform operations because their enable signals are active and they are supplied with drive voltages and clocks. When not causing the operation modules 11A and 11B to perform operations, the controller 16 deactivates the enable signals for the operation modules 11A and 11B, and as a result, the power gate switch 25 and the clock gate switch 26 in each of the gating units 14A and 14B are turned off, and the supply of drive voltages and clocks to the operation modules 11A and 11B is cut off.

[0037] In the memory module 13, when writing or reading data to one memory block MB, the controller 16 activates the select signal for the target memory block MB and deactivates the select signals for the other non-target memory blocks MB. To write or read data, the controller 16 also activates the enable signal for the register 32. This activates the select signal and enable signal input to the gating control circuit 34 corresponding to the target memory block MB, causing the gating control circuit 34 to output an ON signal. This turns on the power gate switch 35 corresponding to the target memory block MB, supplying a drive voltage to each memory cell 31a in the target memory block MB. As a result, the drive voltage is supplied to the target memory block MB and the select signal is active, enabling data to be written or read. The read data is then input to the register 32. In contrast, the select signal for the other memory blocks MB is inactive, preventing data from being written or read, and the supply of drive voltage is cut off.

[0038] When no data is being read or written, the select signal and enable signal become inactive in the memory module 13, so that the power gate switches 35a, 35b, ..., the power gate switch 37, and the clock gate switch 38 are all turned off. As a result, the supply of drive voltage to each memory block MB is cut off, and the supply of drive voltage and clock to the register 32 is also cut off.

[0039] As described above, in the semiconductor circuit device 10, the inside is subdivided into the operation modules 11A, 11B and the memory module 13, and power gating and clock gating are performed thereon, and the memory array 31 is subdivided into memory blocks and power gating is performed thereon, thereby effectively reducing power consumption.

[0040] Furthermore, as described above, the semiconductor circuit device 10 performs power gating and clock gating by dividing the memory array 31. The power gating and clock gating are easily achieved by inputting control signals (enable signals and select signals) used to enable or disable the divided target circuits (the arithmetic modules 11A, 11B, and the memory module 13) to gating control circuits provided for each target circuit to turn on and off the power gate switches and clock gate switches. For example, when the number of target circuits is increased, corresponding control signals are added, which results in power gating and clock gating of the added target circuits. Furthermore, when the operation timing of the target circuits is changed, such as by changing the operation order, the timing of the control signals is changed accordingly, which results in a change in the timing of the power gating and clock gating of the target circuits. In this way, the semiconductor circuit device 10 autonomously power-gates and clock-gates the target circuits based on the control signals input thereto, eliminating the need to modify the circuitry or program of the controller 16 for power gating and clock gating.

[0041] In the above example, the power gate switch is provided on the power supply potential (VDD) side of the power supply line, but it may also be provided on the reference potential (GND) side of the power supply line. In the example shown in Fig. 4, the power gate switch 25 corresponding to the arithmetic module 11A is provided on the reference potential (GND) side of the power supply line LP1A, and in the example shown in Fig. 5, each power gate switch 35 corresponding to each memory block MB and the power gate switch 37 corresponding to the register 32 are provided on the reference potential (GND) sides of the power supply lines LP2 and LP3, respectively.

[0042] [Second embodiment] The second embodiment autonomously performs power gating and clock gating in a semiconductor circuit device that performs arithmetic processing corresponding to a neural network.

[0043] In FIG. 6, a semiconductor circuit device 40 performs arithmetic processing corresponding to a convolutional neural network (CNN). The semiconductor circuit device 40 is provided with multiple circuit units U40a, U40b, etc., each having the same circuit configuration, and the circuit units U40a, U40b, etc. can perform arithmetic processing in parallel. As shown in an example in FIG. 7, the circuit units U40a, U40b, etc. are controlled so that drive voltage is supplied only to those performing processing according to a processing sequence, thereby reducing the power consumption of the semiconductor circuit device 40. Hereinafter, when there is no need to distinguish between the circuit units U40a, U40b, etc., they will be referred to as circuit unit U40.

[0044] Since the circuit units U40a, U40b, etc. have the same circuit configuration, only the circuit unit U40a will be described below. The circuit unit U40a has, as circuit modules, a buffer memory module (hereinafter referred to as the buffer module) M41, a main memory module M42, a multiplication module A43, an accumulation operation module A44, a batch normalization module A45, an activation function module A46, a pooling module A47, a sampling module A48, and a fully connected classification module A49.

[0045] The buffer module M41 and main memory module M42, which are memory modules, have the same configuration as the memory module 13 (see FIG. 3) of the first embodiment, and include a memory array consisting of a plurality of non-volatile memory cells and a register. Input data is held in each memory block of the memory array in the buffer module M41, and filter data (filter coefficients) of a filter used for convolution calculations is written in each memory block of the memory array in the main memory module M42.

[0046] A gating unit 51 is provided for the buffer module M41, and a gating unit 52 is provided for the main memory module M42, and their configurations and functions are similar to the gating unit 15 (see FIG. 3) provided for the memory module 13 of the first embodiment. Therefore, for example, in the buffer module M41, the gating unit 51 performs power gating for each memory block and power gating and clock gating for the register based on an enable signal input to the register and a select signal input to each memory block. The same is true for the main memory module M42.

[0047] The buffer module M41 is actually part of a buffer memory unit serving as a memory circuit shared by the circuit units U40a, U40b, etc. Similarly, the main memory module M42 is actually part of a main memory unit serving as a memory circuit shared by the circuit units U40a, U40b, etc.

[0048] The multiplication module A43, cumulative calculation module A44, batch normalization module A45, activation function module A46, pooling module A47, sampling module A48, and fully connected classification module A49, which are calculation modules that perform logic calculations, are connected in series in this order, forming a pipeline in which each performs calculations using data input (acquired) from the previous module and outputs the calculation results to the subsequent module. The multiplication module A43 receives outputs from the buffer module M41 and the main memory module 42. Hereinafter, when there is no need to distinguish between the multiplication module A43, cumulative calculation module A44, batch normalization module A45, activation function module A46, pooling module A47, sampling module A48, and fully connected classification module A49, they will be referred to as calculation modules A.

[0049] The multiplication module A43 and the accumulation calculation module A44 constitute a convolution calculation unit corresponding to the convolution layer of the convolutional neural network, and are convolution calculation modules that perform convolution calculations using a filter on input data read from the buffer module M41. The multiplication module A43 has, as an arithmetic circuit, a plurality of multipliers arranged in parallel that multiply input data from the buffer module M41 by filter data from the main memory module 42, and a selector that selects and outputs the multiplication results of each multiplier. The accumulation calculation module A44 has, as an arithmetic circuit, an adder that sequentially adds (accumulates) the multiplication results output from the selector of the multiplication module A43.

[0050] The batch normalization module A45 corresponds to the batch normalization layer and has an arithmetic circuit that performs batch normalization processing on the output result of the accumulation calculation module A44, i.e., the result of the convolution calculation. The activation function module A46 corresponds to the activation layer and has an arithmetic circuit that performs calculation processing (activation function calculation) using activation functions such as a step function, a sigmoid function, a rectified linear unit (ReLU), a leaky rectified linear unit (Leaky ReLU), and a hyperbolic tangent function. The pooling module A47 corresponds to the pooling layer and has an arithmetic circuit that performs pooling calculations (pooling processing) such as max pooling and average pooling. The sampling module A48 corresponds to the sampling layer and has an arithmetic circuit that performs sampling processing such as upsampling and downsampling. The fully connected classification module A49 has an arithmetic circuit that performs processing (fully connected classification processing) corresponding to a fully connected layer that performs a product-sum calculation on the entire previous layer.

[0051] The operation module A has a configuration similar to that of the operation module 11A (see FIG. 2) of the first embodiment. That is, the operation module A is composed of one or more operation circuits that perform the above-mentioned processing, and multiple registers arranged in the preceding and succeeding stages of each operation circuit, and the operation circuit performs an operation on the data output by the register in the preceding stage, and the register in the succeeding stage latches and outputs the operation result in synchronization with a clock.

[0052] The multiplication module A43, the accumulation calculation module A44, the batch normalization module A45, the activation function module A46, the pooling module A47, the sampling module A48, and the fully connected classification module A49 are provided with gating units 53 to 59, respectively. The configurations and functions of the gating units 53 to 59 are similar to those of the gating unit 14A (see FIG. 2) provided for the calculation module 11A of the first embodiment. Therefore, for example, in the multiplication module A43, the gating unit 53 performs power gating and clock gating for each register of the multiplication module A43 based on an enable signal input to the register. As a result, a drive voltage and a clock are supplied to each register of the multiplication module A43 only when the multiplication module A43 performs calculation.

[0053] The select signals and enable signals for the buffer module M41, the main memory module M42, and each arithmetic module A are switched between active and inactive states by a controller (not shown) at predetermined timings according to the processing sequence of the convolutional neural network. Power gating and clock gating are performed for the buffer module M41, the main memory module M42, and each arithmetic module A. For the buffer module M41 and the main memory module M42, a drive voltage is supplied only to the memory blocks from which input data and filter data are to be read, and a drive voltage and clock are supplied to the registers only while the data is being read. Furthermore, for the arithmetic module A, a drive voltage and clock are supplied only while the data from the previous module is latched in the input-side register, the latched data is used to perform an operation in the arithmetic circuit, and the operation result is latched in the output-side register and output to the subsequent module.

[0054] 8 shows the power gating and clock gating states of the buffer module M41, main memory module M42, and arithmetic module A when four input data (#1 to #4) are read and processed from the buffer module M41. In FIG. 8, the horizontal direction of the table indicates the passage of time, and "ON" in the table indicates that the module is operating with a drive voltage or a drive voltage and a clock supplied, and "OFF" indicates that a drive voltage or a drive voltage and a clock is not supplied. For example, if the timing of the power gating and clock gating of a preceding module and a succeeding module is synchronized with the clock, and a succeeding module that is transitioning "ON" receives data from a preceding module that is transitioning "OFF," its register latches the data from the preceding module at the edge of the clock input to it.

[0055] In the example of Fig. 8, the processing in each module uses one cycle per input data, but the processing may be performed using any number of cycles per input data, which may be 1 or more. Also, although four input data are processed simultaneously, the number of data processed simultaneously may be any number, which may be 1 or more.

[0056] As described above, in a pipeline, the circuit modules of each stage operate independently, so power consumption can be effectively reduced by subdividing each module into units such as the circuit unit U40. Furthermore, because the control signals (enable signals, select signals) used to enable or disable the target circuits (buffer module M41, main memory module M42, and each arithmetic module A) are input to gating control circuits provided for each target circuit to turn on and off the power gate switches and clock gate switches, power gating and clock gating can be easily achieved even if the number of circuit modules in the circuit unit U40 increases or even if the number of circuit units U40 in the semiconductor circuit device 40 increases.

[0057] The semiconductor circuit device 60 shown in FIG. 9 performs arithmetic processing corresponding to a Fully Convolutional Neural Network (FCN). The semiconductor circuit device 60 is provided with multiple circuit units U60a, U60b, etc., each having the same circuit configuration, and the circuit units U60a, U60b, etc. can perform arithmetic processing in parallel. The circuit units U60a, U60b, etc. are controlled so that drive voltage and clocks are supplied only to those performing processing according to a processing sequence, thereby reducing the power consumption of the semiconductor circuit device 60. Hereinafter, when there is no need to distinguish between the circuit units U60a, U60b, etc., they will be referred to as circuit unit U60.

[0058] Since the circuit units U60a, U60b, etc. have the same circuit configuration, the configuration of the circuit unit U60a will be described below. The circuit unit U60a has the same configuration as the circuit unit U40a, except that it does not have the sampling module A48 and the fully connected classification module A49. Therefore, the circuit unit U60a has a configuration in which a buffer module M41, a main memory module M42, a multiplication module A43, an accumulation operation module A44, a batch normalization module A45, an activation function module A46, and a pooling module A47 are connected in series. In this semiconductor circuit device 60, the buffer module M41 and the main memory module M42 are respectively part of a buffer memory unit and a main memory unit, which are memory circuits provided in common to the circuit units U40a, U40b, etc. In this example, bit adjustment modules (not shown) that adjust the number of bits of the calculation result of the fixed-point arithmetic processing are provided immediately after the accumulation operation module A44 and immediately after the activation function module A46. The calculation results of the accumulation calculation module A44 and the calculation results of the activation function module A46 are each input to the subsequent module after the number of bits is reduced by a bit adjustment module.

[0059] Furthermore, gating units 51 to 57 are provided corresponding to each circuit module. The functions and operations of these gating units 51 to 57 are the same as those of the circuit unit U40a, and they autonomously perform power gating and clock gating for the buffer module M41, main memory module M42, multiplication module A43, accumulation operation module A44, batch normalization module A45, activation function module A46, and pooling module A47. Figure 10 shows, similar to Figure 8, the power gating and clock gating states of the buffer module M41, main memory module M42, and each operation module A when four input data are read from the buffer module M41 and processed.

[0060] The graph in Figure 11 shows the results of a simulation of the improvement in power performance of the semiconductor circuit device 60. Each circuit module basically has a CMOS circuit configuration, and the memory cells of the buffer module M41 and main memory module M42 have a non-volatile circuit configuration using magnetic tunnel junction (MTJ) elements. A configuration with 64 circuit units U60 was used, and the simulation was performed for a 100% overall operation rate with no standby time. The overall operation rate is the percentage of operation time of the semiconductor circuit device 60.

[0061] The left side of the graph ("without PM") shows the power consumption and its breakdown when power gating and clock gating (CG) are not performed, while the right side of the graph ("with PM") shows the case when power gating and clock gating are performed as described above. The breakdown is as follows: (i) is the power consumption of the convolution operation module consisting of the multiplication module A43 and the accumulation operation module A44; (ii) is the total power consumption of the batch normalization module A45 and the activation function module A46; and (iii) is the total power consumption of the bit adjustment modules provided immediately after the accumulation operation module A44 and the activation function module A46. Furthermore, (iv) is the power consumption of the pooling module A47; (v) is the power consumption of the main memory module M42; and (vi) is the power consumption of the buffer memory module M41. These results confirm that when power gating and clock gating are performed as described above in the semiconductor circuit device 60, a power consumption reduction effect of 82.2% is achieved.

[0062] 12 shows the results of a simulation of the change in the power consumption performance ratio (%) for different overall availability rates, assuming a change in the proportion of standby time in the semiconductor circuit device 60. In the simulation, the overall availability rates were examined as 100%, which means there is no standby time, assuming an application such as automatic vehicle operation; 20%, which assumes an application such as edge surveillance; and 2.5%, which assumes an application such as a sensor network. The results were compared for cases where power gating and clock gating were performed (with PM) and cases where they were not performed (without PM). The power consumption performance ratio is the ratio (%) of power consumption to the reference value (100%) of a case where a configuration similar to the semiconductor circuit device 60 is used, with each memory being CMOS SRAM, and where power gating and clock gating were not performed. The power consumption performance ratio was examined for cases where power gating and clock gating were performed (with PM) and cases where power gating and clock gating were not performed (without PM) in the semiconductor circuit device 60. The results of this simulation confirmed that when power gating and clock gating were performed, the power consumption performance ratio improved by 82.2% at both operating rates compared to when power gating and clock gating were not performed, demonstrating superiority.

[0063] The above describes an example in which calculation processing corresponding to a neural network is performed in a pipeline, but even in configurations in which other calculation processing is performed in a pipeline, power gating and clock gating can be performed by gating units provided corresponding to each of the circuit modules at each stage of the pipeline as target circuits.

[0064] [Third embodiment] The third embodiment autonomously performs power gating and clock gating on semiconductor circuit devices that perform clustering.

[0065] In FIG. 13, a clustering device 70 performs clustering on multiple pieces of element data. The clustering performed by this clustering device 70 can be classified into batch processing (offline processing) and high-speed classification processing (online processing). While details of these processing methods are omitted, batch processing involves performing clustering using all element data while varying the number of clusters to obtain an evaluation value for each cluster number, determining the optimal number of clusters from the evaluation value, and classifying the element data using the optimal number of clusters—a process known as "unsupervised learning." For example, the k-means method is used as the clustering method, and the optimal number of clusters is determined to be the number of clusters that maximizes the evaluation value (maximum). High-speed classification processing is a process for efficiently and quickly classifying new element data into existing clusters when new element data is added after batch processing or when new element data is recognized using the results of batch processing.

[0066] The clustering device 70 includes a semiconductor circuit device 71 that performs calculations for clustering, and a controller 72 that controls the operation of the semiconductor circuit device 71. The controller 72 outputs various control signals, such as enable signals, to each section of the semiconductor circuit device 71. The semiconductor circuit device 71 includes a main memory 74, a centroid memory 75, a clustering calculation section 76, a neighborhood search circuit section 77, and an evaluation value calculation circuit 78.

[0067] The main memory 74 stores a plurality of element data to be clustered. The main memory 74 has a plurality of unit blocks (memory blocks) arranged in a matrix, and the element data has vector components, which are components for each dimension, written into the unit blocks and held in the main memory 74. The main memory 74 reads and outputs the vector components for each stored element data in parallel, one dimension at a time, in synchronization with a clock.

[0068] For example, if the element data is n-dimensional data and the main memory 74 stores a maximum of m pieces of element data, the main memory 74 has m memory modules arranged in parallel, each consisting of n memory blocks configured similarly to that of the first embodiment, and the unit blocks arranged in a matrix of m columns and n rows. Each unit block stores a vector component of the element data, with one column of n unit blocks, i.e., one memory module, storing one piece of element data. When reading, for example, rows are selected sequentially by a row select signal from the controller 72, and the vector components of each memory block in the selected row are output.

[0069] The centroid memory 75 stores the cluster centroid of each cluster and has a configuration similar to the main memory 74, but is configured so that the cluster centroid to be read can be selected by selecting an arbitrary memory module using, for example, a column select signal. The centroid memory 75 reads out each vector component for each cluster centroid one-dimensionally for each cluster centroid in synchronization with a clock, and also writes the cluster centroid calculated by the clustering calculation unit 76. The main memory 74 and centroid memory 75 are configured as non-volatile memories.

[0070] The clustering calculation unit 76 performs various clustering calculations for batch processing and classifies each element data into clusters. This clustering calculation unit 76 consists of a calculation unit 81 and a main register unit 82. The calculation unit 81 performs the main clustering calculation and includes a distance calculation circuit 81a that calculates the distance between element data and the cluster centroid in parallel for each element data, and a centroid calculation circuit 81b that calculates the cluster centroid and the data centroid of all element data. The main register unit 82 consists of various registers that temporarily store the distance between element data and the cluster centroid calculated by the calculation unit 81, the cluster ID assigned to the element data, etc. The calculation unit 81 and main register unit 82 perform calculations in synchronization with a clock and latch the distance and cluster ID.

[0071] During high-speed classification processing, the neighborhood search circuit unit 77 identifies the cluster with the smallest data centroid distance from the new element data to be added, and classifies the new element data into the identified cluster. This neighborhood search circuit unit 77 includes a calculation unit that calculates the data centroid distance between the new element data and each cluster centroid sequentially read from the centroid memory 75, a short-distance CID register unit that sequentially updates the cluster ID with the smallest data centroid distance during calculation based on the calculation results of the calculation unit, and the data centroid distance, and a short-distance register unit. The cluster ID finally stored in the short-distance CID register unit becomes the cluster ID of the cluster into which the new element data will be classified. The calculation unit of the neighborhood search circuit unit 77 is also used to calculate an evaluation value for the number of clusters. The neighborhood search circuit unit 77 performs calculations, latches into registers, etc. in synchronization with a clock.

[0072] The evaluation value calculation circuit 78 calculates an evaluation value at the end of each clustering in batch processing and during high-speed classification processing. The evaluation value calculation circuit 78 is broadly divided into a logic unit 78a and an evaluation register unit 78b. The logic unit 78a calculates an evaluation value according to a predetermined calculation formula using the number of element data, the number of clusters, the distance between the element data and the cluster centroid, etc. Furthermore, during high-speed classification processing, the logic unit 78a calculates the cluster centroid into which new element data has been classified and writes this to the centroid memory 75. The logic unit 78a performs calculations of the evaluation value, etc.

[0073] The evaluation register unit 78b holds data necessary for calculating the evaluation value, such as the data centroid calculated by the centroid calculation circuit 81b, the number of element data in each cluster, and data obtained during the calculation by the centroid calculation circuit 81b and usable for calculating the evaluation value. The evaluation register unit 78b latches and outputs data in synchronization with a clock.

[0074] In the semiconductor circuit device 71, the main memory 74 and the centroid memory 75 are nonvolatile, but it is preferable to use nonvolatile registers for all or part of the various registers. In this example, the main memory 74 and the centroid memory 75 are each memory circuits. The arithmetic unit 81 of the clustering arithmetic unit 76, the neighborhood search circuit unit 77, and the logic unit 78a of the evaluation value calculation circuit 78 are each arithmetic modules that perform clustering operations to classify multiple element data into multiple clusters, and the main register unit 82 of the clustering arithmetic unit 76 is an intermediate result storage unit that stores intermediate results of the clustering operations.

[0075] In the clustering device 70, the main memory 74, centroid memory 75, clustering calculation unit 76, neighborhood search circuit unit 77, evaluation value calculation circuit 78, or their internal circuits are operated in a predetermined order and combination to perform optimal clustering for all element data by batch processing and classification of new element data into existing clusters by high-speed classification processing. Note that the configuration of this clustering device 70 and the details of the batch processing and high-speed classification processing are the same as the batch processing and update processing described in WO 2020 / 161845.

[0076] In the semiconductor circuit device 71, the main memory 74, the centroid memory 75, the arithmetic unit 81, the main register unit 82, the logic unit 78a, the evaluation register unit 78b, and the neighborhood search circuit unit 77 are circuits that are subject to power gating and clock gating, respectively, and gating units 83 to 89 are provided corresponding to these circuits. The configurations and functions of the gating units 83 to 89 are similar to those of the gating unit 14A (see FIG. 2) provided corresponding to the arithmetic module 11A of the first embodiment.

[0077] A row select signal that specifies the row to be read, an enable for a data input / output register provided within a memory module or commonly to each memory module, and the like are input as control signals to the main memory 74. A row select signal, for example, is input to the gating unit 83 corresponding to the main memory 74, and power gating and clock gating of the main memory 74 are performed depending on whether the row select signal is active or inactive.

[0078] A column select signal that specifies the column (cluster center of gravity) to be read, an enable signal for a data input / output register provided within a memory module or shared by each memory module, and the like are input as control signals to the center of gravity memory 75. A column select signal, for example, is input to a gating unit 84 corresponding to the center of gravity memory 75, and power gating and clock gating of the center of gravity memory 75 are performed depending on whether the column select signal is active or inactive.

[0079] Note that power gating and clock gating may be performed on the main memory 74 and the center of gravity memory 75 by the gating units 83 and 84 using enable signals input to registers for data input / output.

[0080] Enable signals and the like for arithmetic circuits such as adders and registers that constitute the distance calculation circuit 81a and the center of gravity calculation circuit 81b are input as control signals to the arithmetic unit 81, and for example, one of these enable signals is input to the gating unit 85. The gating unit 85 performs power gating and clock gating for the arithmetic unit 81 based on the input enable signal.

[0081] The proximity search circuit unit 77, logic unit 78a, and corresponding gating units 87 and 88 are similar to the gating unit 85. That is, the gating units 87 and 88 perform power gating and clock gating on the proximity search circuit unit 77 and logic unit 78a in response to control signals, such as enable signals, input to the proximity search circuit unit 77 and logic unit 78a, respectively.

[0082] An enable signal is input as a control signal to each of the registers constituting the main register unit 82, and the enable signal is input to the gating section 86. As a result, the gating section 86 performs power gating and clock gating on the main register unit 82 in response to the enable signal input to the main register unit 82.

[0083] The enable signal input to the gating unit 86 is also input to the gating unit 89 corresponding to the evaluation register unit 78b. As a result, the evaluation register unit 78b is power-gated and clock-gated by the gating unit 89 at the same timing as the main register unit 82. This is because the main register unit 82 and the evaluation register unit 78b only need to operate at the same timing. Note that a control signal, such as an enable signal, input to the evaluation register unit 78b may be input to the gating unit 89 corresponding to the evaluation register unit 78b to perform power gating and clock gating on the evaluation register unit 78b. Furthermore, when two circuits that perform power gating and clock gating at the same timing are provided, even if one of the circuits does not receive a control signal, power gating and clock gating can be performed using a control signal input to the other circuit. In other words, these two circuits can be considered as a single target circuit that is subject to power gating and clock gating.

[0084] For example, in the arithmetic unit 81, the gating unit 85 performs power gating and clock gating on the arithmetic unit 81 based on an enable signal input thereto. Also, as described above, the same enable signal is input to the main register unit 82 and the evaluation register unit 78b, so that the main register unit 82 and the evaluation register unit 78b are simultaneously power gated and clock gated.

[0085] As described above, the semiconductor circuit device 71 effectively reduces power consumption by applying power gating and clock gating to each of its subdivided sections. Also, the control signals (enable signal, column select signal, row select signal, etc.) used to enable or disable the target circuits, namely the main memory 74, the centroid memory 75, the arithmetic unit 81, the main register unit 82, the logic section 78a, the evaluation register section 78b, and the neighborhood search circuit section 77, are input to gating control circuits provided for each target circuit to turn on or off the power gate switch and the clock gate switch, so that power gating and clock gating can be easily realized.

[0086] An example of autonomous power gating and clock gating in a pipelined clustering device is shown in Fig. 14. The clustering device 90 has a semiconductor circuit device 91 that performs calculations for clustering, and a controller 92 that outputs various control signals, such as enable signals, to each part of the semiconductor circuit device 91 to control the operation of the semiconductor circuit device 91. This clustering device 90 performs batch processing and high-speed classification processing in the same way as the clustering device 70 shown in Fig. 13.

[0087] The semiconductor circuit device 91 has a main memory 94, a centroid memory 95, a clustering operation module 96, an intermediate result storage module 97, an evaluation value calculation module 98, and a nearby search module 99. The semiconductor circuit device 91 has a first pipeline for performing batch processing and a second pipeline for performing high-speed classification processing. The first pipeline is composed of the main memory 94, the centroid memory 95, the clustering operation module 96, the intermediate result storage module 97, and the evaluation value calculation module 98, while the second pipeline is composed of the centroid memory 95, the nearby search module 99, and the evaluation value calculation module 98. Therefore, the centroid memory 95, the intermediate result storage module 97, and the evaluation value calculation module 98 operate in both batch processing and high-speed classification processing.

[0088] Each stage of the first pipeline and the second pipeline, namely, the main memory 94, the centroid memory 95, the clustering calculation module 96, the intermediate result storage module 97, the evaluation value calculation module 98, and the neighborhood search module 99, is configured to operate independently and to perform calculations using data input from the previous stage.

[0089] In the first pipeline, a clustering operation module 96, an intermediate result storage module 97, and an evaluation value calculation module 98 are connected in this order, and a main memory 94 and a centroid memory 95 are connected to the clustering operation module 96 as its upstream stages. On the other hand, in the second pipeline, the intermediate result storage module 97 and a neighborhood search module 99 are connected to the evaluation value calculation module 98 as its upstream stages, and the neighborhood search module 99 is connected to the centroid memory 95 as its upstream stage.

[0090] The main memory 94 and the centroid memory 95 are similar to the main memory 74 and the centroid memory 75 of the semiconductor circuit device 71. That is, the main memory 94 stores element data in each of a plurality of memory modules provided in parallel, and reads out vector components of each stored element data in parallel, one dimension at a time, in synchronization with a clock. The centroid memory 95 stores cluster centroids in each of a plurality of memory modules provided in parallel, and reads out vector components of a selected cluster centroid in parallel, one dimension at a time, in synchronization with a clock. The main memory 94 and the centroid memory 95 are configured as non-volatile memories.

[0091] The clustering calculation module 96 performs calculation processing similar to that of the calculation unit 81 (see FIG. 13) in the above-described clustering calculation section 76. This clustering calculation module 96 has distance calculation circuits, addition circuits, division circuits, multiplexers, registers, etc., a plurality of which are provided in parallel corresponding to each memory module of the plurality of main memories 94, and calculates the distance between element data and the cluster centroid in parallel for each element data, and calculates the cluster centroid and the data centroid of all element data, etc.

[0092] The intermediate result storage module 97 has the same function as the above-mentioned main register unit 82 (see FIG. 13). The evaluation value calculation module 98 performs calculation processing similar to that of the above-mentioned evaluation value calculation circuit 78, and has the same function as the logic unit 78a and evaluation register unit 78b (both see FIG. 13) in the evaluation value calculation circuit 78. During high-speed classification processing, this evaluation value calculation module 98 calculates an evaluation value using the distance between data centroids calculated by the proximity search module 99, as well as the data output by the clustering calculation module 96 during batch processing and held in the intermediate result storage module 97 as the intermediate calculation result. The proximity search module 99 performs calculation processing similar to that of the above-mentioned proximity search circuit unit 77 (see FIG. 13).

[0093] In the semiconductor circuit device 91, a main memory 94, a centroid memory 95, a clustering calculation module 96, an intermediate result storage module 97, an evaluation value calculation module 98, and a neighborhood search module 99 are target circuits that are subject to power gating and clock gating, respectively, and gating units 101 to 106 are provided corresponding to these. The configurations and functions of the gating units 101 to 106 are similar to those of the gating unit 14A (see FIG. 2) provided corresponding to the calculation module 11A of the first embodiment.

[0094] In this example, the main memory 94 and the centroid memory 95 are memory circuits. The clustering calculation module 96, the evaluation value calculation module 98, and the neighborhood search module 99 are calculation modules that perform calculations for clustering to classify multiple element data into multiple clusters, and the intermediate result storage module 97 is an intermediate result storage unit that stores intermediate results during the calculations for clustering.

[0095] A control signal (for example, a row select signal) to be input to the main memory 94 is input to the gating unit 101, and a control signal (for example, a column select signal) to be input to the center of gravity memory 95 is input to the gating unit 102. As a result, the main memory 94 and the center of gravity memory 95 are power-gated and clock-gated by the gating units 101 and 102 based on the control signals input to them.

[0096] Furthermore, the gating units 103 to 106 receive control signals (e.g., enable signals) that are input to the corresponding clustering operation module 96, intermediate result storage module 97, evaluation value calculation module 98, and neighborhood search module 99. As a result, the clustering operation module 96, intermediate result storage module 97, evaluation value calculation module 98, and neighborhood search module 99 are power-gated and clock-gated by the gating units 103 to 106 based on the control signals input thereto.

[0097] 15 shows an example of the power gating and clock gating states of each part of the semiconductor circuit device 91 when performing batch processing, similar to FIG. 8. For convenience, FIG. 15 shows a case where four element data (#1 to #4) are clustered from the main memory 94. Similarly, FIG. 16 shows an example of the power gating and clock gating states of each part of the semiconductor circuit device 91 when performing high-speed classification processing. FIG. 16 shows a case where two new element data (#1, #2) are input to the neighborhood search module 99 and classified into existing clusters.

[0098] As described above, the semiconductor circuit device 91 effectively reduces power consumption by applying power gating and clock gating to each unit during batch processing and high-speed classification processing. Also, the control signals used to enable or disable the target circuits, that is, the main memory 94, the centroid memory 95, the clustering calculation module 96, the intermediate result storage module 97, the evaluation value calculation module 98, and the neighborhood search module 99, are input to gating control circuits provided for each target circuit to turn on or off the power gate switch and the clock gate switch, so that power gating and clock gating can be easily realized.

[0099] [Fourth embodiment] In the fourth embodiment, a detection unit provided for each target circuit detects information about the target circuit, and if the detected information does not satisfy a predetermined condition, a feedback signal is output to suppress the output of an on signal from the gating control circuit.

[0100] 17, a semiconductor circuit device 110 is provided with a plurality of circuit units U110a, U110b, etc., each having the same circuit configuration, and the circuit units U110a, U110b, etc. can perform arithmetic processing in parallel. Hereinafter, when there is no need to distinguish between the circuit units U110a, U110b, etc., they will be referred to as circuit unit U110.

[0101] Since the circuit units U110a, U110b, etc. have the same circuit configuration, the following describes the configuration of the circuit unit U110a. The circuit unit U110a has a memory module 112 and operation modules 113a, 113b, etc. The memory module 112 has the same configuration as the memory module 13 of the first embodiment (see FIG. 3), and has a memory array consisting of multiple non-volatile memory cells and a register, and receives an enable signal and multiple select signals from a controller (not shown). The operation modules 113a, 113b each have the same configuration as the operation module 11A of the first embodiment (see FIG. 2), and receive an enable signal as an input.

[0102] Each memory module 112 is provided with a corresponding gating unit 114, which performs power gating and clock gating. This memory module 112 is also provided with a detection unit 115. In this example, the detection unit 115 is configured with a temperature sensor that detects the temperature of the memory module 112, and a determination circuit that activates a feedback signal when the temperature detected by this temperature sensor is equal to or higher than a predetermined threshold. The feedback signal from the detection unit 115 is input to the gating unit 114.

[0103] The computing modules 113a, 113b... are provided with corresponding gating units 116a, 116b.... The computing modules 113a, 113b... are also provided with detecting units 117a, 117b.... The detecting units 117a, 117b... have a configuration similar to that of the detecting unit 115, detect the temperature of the corresponding computing module 113a, 113b..., and activate a feedback signal when the detected temperature is equal to or higher than a predetermined threshold. The feedback signal from the detecting units 117a, 117b... is input to the gating units 116a, 116b... provided in the corresponding computing modules 113a, 113b....

[0104] The configurations of the gating unit 114 and the gating units 116a, 116b... are the same as the gating unit 15 (see FIG. 3) and the gating unit 14A (see FIG. 2) of the first embodiment, except that a gating control circuit applies a feedback signal to control the on / off of the power gate switch and the clock gate switch, as will be described later. Therefore, the power gating and clock gating of the memory module 112 by the gating unit 114 and the power gating and clock gating of the operation modules 113a, 113b... by the gating units 116a, 116b... are the same as those of the memory module 13 and the operation module 11A of the first embodiment, except that they are controlled using a feedback signal.

[0105] 18 controls the on / off of a power gate switch corresponding to each memory block of the memory module 112. This gating control circuit 118 is composed of a NOT circuit 118a and a NAND circuit 118b connected in series, and a NOT circuit 118c connected to one input terminal of the NAND circuit 118b, and controls the power gate switch with the output of the NOT circuit 118a. An enable signal and a select signal input to the memory module 112 are input to the other two input terminals of the NAND circuit 118b. In addition, a feedback signal from the detection unit 115 is input to the NOT circuit 118c.

[0106] If the feedback signal from the detection unit 115 is active, the gating control circuit 118 continues to output an OFF signal even if the enable signal and select signal become active. As a result, if the temperature of the memory module 112 is above the threshold, the output of the ON signal is suppressed and no drive voltage is supplied to that memory block. Of course, if the temperature of the memory module 112 is lower than the threshold, the feedback signal is inactive, so when the enable signal and select signal become active, the gating control circuit 118 outputs an ON signal, and drive voltage is supplied to the memory block corresponding to the active select signal.

[0107] 19 controls the on / off of the power gate switch and clock gate switch corresponding to the register of the operation module 113a. This gating control circuit 119 is composed of a NOT circuit 119a and a NAND circuit 119b connected in series, and a NOT circuit 119c connected to one input terminal of the NAND circuit 119b, and controls the power gate switch and the clock gate switch with the output of the NOT circuit 119a. An enable signal input to the operation module 113a is input to the other input terminal of the NAND circuit 119b. In addition, a feedback signal from the detection unit 117a is input to the NOT circuit 119c.

[0108] Therefore, if the feedback signal from the detection unit 117a is active, the gating control circuit 119 continues to output an OFF signal even if the enable signal becomes active. As a result, when the temperature of the computing module 113a is equal to or higher than the threshold, the output of the ON signal is suppressed, and no drive voltage is supplied to the computing module 113a. Of course, when the temperature of the computing module 113a is lower than the threshold, the feedback signal is inactive, so when the enable signal becomes active, the gating control circuit 119 outputs an ON signal, and the drive voltage is supplied to the computing module 113a. The same applies to the register of the memory module 112 and the computing module 113b.

[0109] In this example, the feedback signal is switched between active and inactive when the temperature is lower than a threshold value, but the condition is not limited to this. For example, the condition may be that the number of calculations executed by the calculation module within a certain period of time, the frequency of calculation execution, the number of data reads or writes to the memory module, power consumption, processing delay, etc. are smaller than a threshold value. The detection unit may be configured according to the set conditions. Different conditions may also be set for each circuit module. Furthermore, a feedback signal may be sent to a controller, and when the feedback signal for a module in a circuit unit is active, control may be performed such that another module in the circuit unit performs the calculation instead, or another circuit unit is used to perform the calculation.

[0110] The above-described configuration for suppressing the output of an ON signal using a feedback signal can also be used in the semiconductor circuit devices of the other embodiments described above.

[0111] The target circuits shown in the above embodiments are examples. The target circuits are not limited to those described above, and various circuits to which control signals such as register enable signals and memory column select signals are input can be used as target circuits. Furthermore, the configurations of the gating units shown in the above embodiments are examples and are not limited to those described above. The gating unit may be any unit that can perform power gating and clock gating in response to control signals, and may have a circuit configuration that corresponds to the control signal, for example. [Explanation of symbols]

[0112] 10, 40, 60, 71, 91, 110 Semiconductor circuit devices 11A, 11B, 113a, 113b Computing Modules 13, 112 memory modules 14A, 14B, 15, 51-59, 83-89, 101-106, 114, 116a, 116b Gating section 24, 34, 36, 118, 119 Gating control circuit 25, 35, 37 Power gate switch 26, 38 Clock gate switch 42 Main Memory Module 70, 90 Clustering device 74, 94 main memory 75, 95 center of gravity memory 76 Clustering calculation unit 77 Neighborhood Search Circuit 78 Evaluation value calculation circuit 78a Logic section 78b Evaluation register section 81 arithmetic unit 82 Main Register Unit 96 Clustering Calculation Module 97 Intermediate result memory module 98 Evaluation Value Calculation Module 99 Neighbor Discovery Module 115, 117a, 117b detection unit A43 Multiplication Module A44 Accumulation calculation module A45 Batch Normalization Module A46 Activation Function Module A47 Pooling Module A48 Sampling Module A49 Fully Connected Classification Module M41 Buffer Module M42 main memory module

Claims

1. A semiconductor circuit device is provided with a plurality of target circuits, and a control signal for controlling enable / disable of each of the target circuits is input, a gating control circuit provided for each of the target circuits, receiving the control signal for the corresponding target circuit and outputting an ON signal in response to the control signal that enables the target circuit; a power gate switch for each of the target circuits, which is provided on a power supply line for each of the target circuits to supply a drive voltage to the target circuits and which is turned on by the on signal; any one of the target circuits includes a first register whose enable and disable are controlled by a first enable signal; The gating control circuit corresponding to the target circuit including the first register receives the first enable signal as the control signal. A semiconductor circuit device characterized by:

2. A semiconductor circuit device including a plurality of target circuits, each of which receives a control signal for controlling whether the target circuits are enabled or disabled, a gating control circuit provided for each of the target circuits, receiving the control signal for the corresponding target circuit and outputting an ON signal in response to the control signal that enables the target circuit; a power gate switch for each of the target circuits, which is provided on a power supply line for each of the target circuits to supply a drive voltage to the target circuits and which is turned on by the on signal; One of the target circuits is a non-volatile memory circuit having a plurality of memory blocks whose enable and disable are controlled by a select signal corresponding to a memory address, The gating control circuit corresponding to the memory circuit receives a select signal as the control signal. A semiconductor circuit device characterized by:

3. A semiconductor circuit device having a plurality of target circuits, each of which receives a control signal for controlling whether the target circuits are enabled or disabled, a gating control circuit provided for each of the target circuits, receiving the control signal for the corresponding target circuit and outputting an ON signal in response to the control signal that enables the target circuit; a power gate switch for each of the target circuits, which is provided on a power supply line for each of the target circuits to supply a drive voltage to the target circuits and which is turned on by the on signal; one of the target circuits is a memory circuit having a plurality of memory blocks whose enable / disable status is controlled by a select signal corresponding to a memory address, and having a second register whose enable / disable status is controlled by a second enable signal; The gating control circuit corresponding to the memory circuit receives the select signal as the control signal and the second enable signal, and outputs the on signal in response to the select signal that enables the memory circuit and the second enable signal that enables the second register. A semiconductor circuit device characterized by:

4. A semiconductor circuit device having a plurality of target circuits, each of which receives a control signal for controlling whether the target circuits are enabled or disabled, a gating control circuit provided for each of the target circuits, receiving the control signal for the corresponding target circuit and outputting an ON signal in response to the control signal that enables the target circuit; a power gate switch for each of the target circuits, which is provided on a power supply line for each of the target circuits to supply a drive voltage to the target circuits and which is turned on by the on signal; any one of the target circuits is an arithmetic module having an arithmetic circuit and a third register whose enable / disable is controlled by a third enable signal; The gating control circuit corresponding to the arithmetic module receives the third enable signal as the control signal. A semiconductor circuit device characterized by:

5. A semiconductor circuit device having a plurality of target circuits, each of which receives a control signal for controlling whether the target circuits are enabled or disabled, a gating control circuit provided for each of the target circuits, receiving the control signal for the corresponding target circuit and outputting an ON signal in response to the control signal that enables the target circuit; a power gate switch for each of the target circuits, which is provided on a power supply line for each of the target circuits to supply a drive voltage to the target circuits and which is turned on by the on signal; a detection unit provided for each of the target circuits, detecting information about the target circuit, and activating a feedback signal when the detected information does not satisfy a predetermined condition; The gating control circuit does not output the ON signal when the feedback signal from the detection unit provided in the corresponding target circuit is active. A semiconductor circuit device characterized by:

6. A semiconductor circuit device having a plurality of target circuits, each of which receives a control signal for controlling whether the target circuits are enabled or disabled, a gating control circuit provided for each of the target circuits, receiving the control signal for the corresponding target circuit and outputting an ON signal in response to the control signal that enables the target circuit; a power gate switch for each of the target circuits, which is provided on a power supply line for each of the target circuits to supply a drive voltage to the target circuits and which is turned on by the on signal; the plurality of target circuits include a plurality of operation modules each including an operation circuit; The plurality of arithmetic modules are connected in series, and the arithmetic module in the subsequent stage acquires the arithmetic result of the arithmetic module in the preceding stage and uses it in the arithmetic operation; each of the plurality of operation modules is an operation module having an operation circuit and a third register whose enable / disable is controlled by a third enable signal; The gating control circuit corresponding to the arithmetic module receives the third enable signal as the control signal. A semiconductor circuit device characterized by:

7. A clock gate switch for each target circuit is provided on a clock line for supplying a clock to the target circuit and is turned on by the on signal.

7. The semiconductor circuit device according to claim 1, 2, 4, 5, or 6.

8. the plurality of calculation modules include a convolution calculation module that performs a convolution calculation, an activation function module that performs an activation function calculation, a pooling module that performs a pooling process, and a fully connected classification module that performs a fully connected classification process calculation, 7. The semiconductor circuit device according to claim 6, wherein the semiconductor circuit device performs arithmetic processing corresponding to a convolutional neural network.

9. the plurality of calculation modules include a convolution calculation module that performs a convolution calculation, an activation function module that performs an activation function calculation, and a pooling module that performs a pooling process; 7. The semiconductor circuit device according to claim 6, wherein the semiconductor circuit device performs arithmetic processing corresponding to a full-layer convolutional neural network.

10. 10. The semiconductor circuit device according to claim 8, wherein the convolution operation module comprises a multiplication module that performs multiplication, and an accumulation operation module that performs an accumulation operation on the multiplication results of the multiplication module.

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