Floating point arithmetic device and method of operating the same

Abstract

A floating point arithmetic device with two floating point operands and its operation method are disclosed. The floating point arithmetic device includes an exponent subtraction circuit, an exponent calculation circuit, a mantissa calculation circuit, and a conversion circuit. The exponent subtraction circuit calculates the difference between the exponents of the two operands and generates a sign bit and an exponent difference. The exponent calculation circuit generates the post-operation exponent bits according to the larger one of the exponents of the two operands. The mantissa calculation circuit aligns the mantissa bits of the two operands and performs one of addition and subtraction on the aligned mantissa bits. To improve the calculation efficiency and reduce the power consumption, the floating point arithmetic device can complete the floating point addition or subtraction operation in one step (one clock cycle) without moving the intermediate floating point data between the registers and the functional circuit units as in the multi-step operation.

Description

TECHNICAL FIELD

[0001] The present invention relates to floating point addition and subtraction circuit arrangements, and in particular to a floating point arithmetic arrangement and method of operation thereof. BACKGROUND

[0002] In digital electronic computer systems, all numbers are represented in binary format. For example, an integer A is represented in m-bit binary format as follows:

[0003] A = a m-1 2 m-1 +a m-2 2 m-2 +...+a12 1 +a0= (a m-1 a m-2 ...a1a0)b,

[0004] where a i = [0,1], i = 0,..., (m-1), and the symbol b represents that the integer A is represented in binary format. For performing binary addition / subtraction operation, another m-bit integer B is represented as follows:

[0005] B = b m-1 2 m-1 +b m-2 2 m-2 +...+b12 1 +b0= (b m-1 b m-2 ...b1b0)b, where b i = [0,1], i = 0,..., (m-1).

[0006] The resulting final integer C is represented as follows:

[0007] C = A ± B = (a m-1 ±b m-1 )2 m-1 +(a m-2 ±b m-2 )2 m-2 +...+(a1±b1)2 1 +(a0±b0)2 0 =(c m s m-1 ...s1s0)b.

[0008] For each bit operation: (a k ±b k ), where k = 0,..., (m-1), the output can be written into the next higher significant bit using the sum bit s k and the carry-over bit c k . Note that the most significant carry-over bit cm This represents the carry bit in an m-bit addition, while s g The negation (or borrow) bit represents the subtraction of m bits, such as... Figure 1 As shown. The binary number s for bit-to-bit addition / subtraction. k and c k+1 It is constructed from combinational logic gates 110 (including a full adder 112 and an XOR gate 111). Therefore, the configuration of the addition / subtraction circuit 100 for two m-bit integers is as follows: Figure 1 As shown. The m-bit binary integer addition / subtraction circuit 100 includes an m-bit addition / subtraction circuit 11 located in the first row (composed of m sub-circuit units 110), a 2's complement conversion circuit 12 located in the second row, and a logic circuit 13. Simultaneously, the voltage signal Sub on node 101, if it has V... SS (Logical value 0) represents performing the addition operation C = A + B. If V is present... DD A logic value of 1 indicates a subtraction operation of C = AB. This is based on the voltage signal Sub at node 101 and the carry bit c from the m-bit adder / subtractor circuit 11 at node 102. ′ m During the subtraction operation, logic circuit 13 generates a signal s at node 103. g (V represents the negation bit 1) DD During addition, a signal c is generated at node 104. m (V represents the carry-in 1) DD By verifying the voltage signals of the logic values ​​of the bit-to-bit operation circuits 11 and 12, the correctness of the addition and subtraction operations of two m-bit binary integers A and B can be easily verified.

[0009] In addition to representing integers in "m-bit" binary format in numerical computation, floating-point representation was introduced to extend the dynamic range of computation within a fixed bit length in electronic computer systems. According to the IEEE 754 binary floating-point format, a binary floating-point number A is represented by a sign bit sa, a q-bit exponent ea, and a p-bit mantissa a, as follows:

[0010]

[0011] Where ea = (ea q-1 2 q-1 +ea q-2 2 q-2 +…+ea12 1 +ea02 0 )-2 q-1+1, and

[0012]

[0013] Among them, binary numbers sa and ea i and a j = [0,1]; i = 0,1,…,(q-1) and j = 0,1,…,(p-1); the symbol f represents a floating-point binary representation. Note that because it can be expressed by the exponent ea i (Where i = 0, 1, ..., (q-1)) Decoding yields a subnormal floating-point number (representing all equal values). i The binary value of a = 0) p-1 =0) and represents a normal floating-point number (with any non-zero ea) i The binary value of (a) p-1 =1), when storing or transmitting a floating-point number, the most significant bit (MSB) of the mantissa is usually not included. p-1 Therefore, the total number of bits used to store and transmit floating-point numbers in IEEE 754 format remains at (p+q) bits. For example, in electronic computer systems, floating-point 8 uses 8 bits (p+q=8) to store a floating-point number, half-precision floating-point uses 16 bits (p+q=16), single-precision floating-point uses 32 bits (p+q=32), double-precision floating-point uses 64 bits (p+q=64), quadruple-precision floating-point uses 128 bits (p+q=128), octuple-precision floating-point uses 256 bits (p+q=256), and so on. Before performing binary arithmetic operations, the floating-point decoder in the arithmetic hardware is always used to read the q-bit exponent (ea0,...,ea) in IEEE 754 format. q-1 )b Decodes the MSB of the p-th bit of the mantissa. p-1 The binary value.

[0014] Similar to the format of binary floating-point number A above, binary floating-point number B is represented as follows: a sign bit sb, a q-bit exponent eb, and a p-bit mantissa b.

[0015]

[0016] Where, eb = (eb q-1 2 q-1 +eb q-2 2 q-2 +…+eb12 1+eb02 0 )-2 q-1 +1, and

[0017]

[0018] Among them, the binary numbers sb and eb i and b j = [0,1]; i = 0,1,…,(q-1) and j = 0,1,…,(p-1); the symbol f represents the floating-point binary representation. Therefore, the floating-point number C is the value after the addition or subtraction of A and B, that is, C = A ± B, expressed as follows:

[0019]

[0020] As can be seen from the above equation, since ea≠eb and the mantissas of A are not aligned with the mantissas of B, the final floating-point number C cannot be obtained directly through bit-to-bit operations. Summary of the Invention

[0021] To address the problems in the prior art, this application provides a floating-point arithmetic device and its operation method.

[0022] To solve the above-mentioned technical problems, this application provides the following technical solution:

[0023] In a first aspect, this application provides a floating-point arithmetic apparatus for performing an arithmetic operation on a first operand and a second operand according to an external operand to generate a final number, wherein the external operand represents one of addition and subtraction, wherein the first operand, the second operand, and the final number are all binary floating-point numbers, and each includes a sign bit, a q-bit exponent, and a p-bit mantissa, the apparatus comprising:

[0024] An exponential subtraction circuit is used to calculate the difference between the q-bit exponents of the first operand and the second operand, so as to generate a first sign bit and an exponential difference.

[0025] An exponent calculation circuit, coupled to the exponent subtraction circuit, is used to select a larger exponent from the q-bit exponents of the first and second operands based on the first sign bit, and to generate an intermediate (q+1)-bit exponent based on the larger exponent.

[0026] A mantissa calculation circuit, coupled to the exponent subtraction circuit, is configured to (1) select a smaller exponent from the q-bit exponents of the first and second operands based on the first sign bit; (2) right-shift one of the p-bit mantissas of the first and second operands corresponding to the smaller exponent based on a first q-bit shifted-binary code to generate a right-shifted p-bit mantissa; and (3) perform one of addition and subtraction on the right-shifted p-bit mantissa and another p-bit mantissa of the first and second operands based on an internal operator to generate an intermediate (p+1)-bit mantissa, wherein the internal operator relates to the sign bit of the external operator and the first and second operands, and wherein the first q-bit shifted-binary code is equivalent to the exponent difference; and

[0027] A conversion circuit, coupled to the exponent calculation circuit and the mantissa calculation circuit, is used to convert the intermediate (q+1)-bit exponent and the intermediate (p+1)-bit mantissa into the q-bit exponent and p-bit mantissa of the final number, respectively.

[0028] Secondly, this application provides a method for operating a floating-point arithmetic device, wherein the floating-point arithmetic device performs an arithmetic operation on a first operand and a second operand according to an external operator to generate a final number, wherein the floating-point arithmetic device includes a first barrel shifter circuit and a conversion circuit, wherein the external operator represents one of addition and subtraction, wherein the first operand, the second operand, and the final number are all binary floating-point numbers, and each includes a sign bit, a q-bit exponent, and a p-bit mantissa, the method comprising the following steps:

[0029] Calculate the difference between the q-bit exponents of the first and second operands to produce a first sign bit and an exponent difference;

[0030] Using the first barrel shifter circuit, a p-bit mantissa of the first and second operands corresponding to a smaller exponent is right-shifted according to a first q-bit shifted binary code, so as to generate a right-shifted p-bit mantissa, wherein the first q-bit shifted binary code is equivalent to the exponent difference.

[0031] According to an internal operator, one of addition and subtraction is performed on the right-shifted p-bit mantissa and another p-bit mantissa of the first and second operands to produce an intermediate (p+1)-bit mantissa, wherein the internal operator is with respect to the sign bit of the external operator and the first and second operands.

[0032] A middle (q+1)-bit exponent is obtained based on a larger exponent, wherein the larger exponent is selected from the q-bit exponents of the first and second operands based on the first sign bit; and

[0033] The middle (q+1)-bit exponent and the middle (p+1)-bit mantissa are respectively converted into the q-bit exponent and p-bit mantissa of the final number.

[0034] Based on the floating-point arithmetic device and its operation method provided in this manual, floating-point addition or subtraction operations can be completed within one clock cycle, without having to move intermediate floating-point data between temporary registers and various functional circuit units as in multi-step operations. Attached Figure Description

[0035] Figure 1 Show an existing m-bit binary adder / subtractor circuit.

[0036] Figure 2 According to the present invention, a schematic diagram of a floating-point addition and subtraction circuit device 200 is shown.

[0037] Figure 3 According to an embodiment of the present invention, a circuit diagram of the most significant bit circuit 210 is shown, which obtains the most significant mantissa bits of two floating-point operands with IEEE 754 format.

[0038] Figure 4 According to an embodiment of the present invention, a schematic diagram of a q-bit exponent subtraction circuit 220 applied to the exponents of two floating-point operands is shown.

[0039] Figure 5A According to an embodiment of the present invention, a circuit diagram of a mantissa alignment circuit 221 is shown, which is used to right-shift the mantissa of a floating-point operand with a smaller exponent.

[0040] Figure 5B According to one embodiment of the present invention, a circuit diagram of a barrel shifter circuit 520 is shown.

[0041] Figure 6 According to one embodiment of the present invention, a schematic diagram of an addition / subtraction circuit 222 for calculating the aligned mantissas of two floating-point operands is shown.

[0042] Figure 7 According to one embodiment of the present invention, a circuit diagram of an exponent selection / addition circuit 223 is shown, which is used to select a larger exponent to add to an additional carry bit mc(p).

[0043] Figure 8According to an embodiment of the present invention, a circuit diagram of a leading zero detection circuit 231 is shown. The leading zero detection circuit 231 is used to detect the first non-zero leading mantissa bit of the mantissa mc(0:p).

[0044] Figure 9 According to an embodiment of the present invention, a circuit diagram of a leading zero shift code generation circuit 232 is shown. The leading zero shift code generation circuit 232 is used to generate a non-zero shift code LZCk(0:q-1).

[0045] Figure 10 According to an embodiment of the present invention, a circuit diagram of an LZ barrel shifter circuit 233 is shown. The LZ barrel shifter circuit 233 is used to shift the mantissa bits of the calculated result to the left to conform to the IEEE 754 mantissa format.

[0046] Figure 11 According to one embodiment of the present invention, a schematic diagram of a subnormal barrel shifter circuit 234 conforming to the IEEE 754 subnormal mantissa format is shown.

[0047] Figure 12 According to one embodiment of the present invention, a schematic diagram of an exponent adjustment circuit 235 conforming to the IEEE 754 exponent format is shown.

[0048] Figure 13 According to one embodiment of the present invention, a logic table 1310 is provided to display the "subtraction" bit and the sign bit (sc) of the final floating-point number output by the addition / subtraction selection and sign logic circuit 240.

[0049] Figure 14 According to one embodiment of the present invention, a schematic diagram of an addition / subtraction (A / S) selection and symbol logic circuit 240 conforming to the IEEE 754 symbol format is shown.

[0050] Icon labels:

[0051] 11 m-bit adder / subtractor circuit

[0052] 12. Two-complement converter circuit

[0053] 13 Logic Circuits

[0054] 110-times circuit

[0055] 200 Floating-Point Addition / Subtraction Circuit Device

[0056] Nodes 101–104, 201m, 201e, 201s, 201m, 201, 202, 202e

[0057] Nodes 202s, 202m, 203, 204, 205, 205s, 205e, 205m, 206

[0058] Nodes 314, 315, 411-416, 501, 503, 504, 506, 531, 532, 604-606

[0059] Nodes 705, 802, 902, 1003, 1005, 1202, 1221, 1222, and 1231

[0060] Nodes 1406-1407

[0061] 210 Most Significant Bit Circuit

[0062] 220-fold exponent subtraction circuit

[0063] 221 Mantissa Alignment Circuit

[0064] 100, 222 Addition / Subtraction Circuits

[0065] 223 Exponent Selection / Adder Circuit

[0066] 230 IEEE 754 format conversion circuit

[0067] 231 Leading Zero Detection Circuit

[0068] 232 Leading Zero Shift Code Generation Circuit

[0069] 233 Leading Zero Barrel Shifter Circuit

[0070] 234-order regular barrel shifter circuit

[0071] 235 Index Adjustment Circuit

[0072] 240 Addition / Subtraction Selection and Sign Logic Circuit

[0073] 301, 302 NMOSFET devices

[0074] 410 q-bit exponent subtraction circuit

[0075] 420 Complementary Number Converter Circuit

[0076] 430 and 720 adder circuits

[0077] 510 Selection Circuit

[0078] 520 Barrel Shifter Circuit

[0079] 530 Operation Sequence Circuit

[0080] 610 p-bit adder / subtractor circuit

[0081] 620 p-bit two's complement converter circuit

[0082] 630 Carry / Negative Logic Circuit

[0083] 710 line of transmission gate

[0084] 910 transistor

[0085] 911 Metal Contact

[0086] 1210, 1230 "Add One" Circuit

[0087] 1220 Subtraction Circuit

[0088] Logic circuits 1240, 1421-1423

[0089] 1310 Logic Table Detailed Implementation

[0090] The following detailed description is illustrative only and not limiting. It should be understood that other embodiments of floating-point formats besides the IEEE 754 format can be used, for example, manipulating the mantissa and exponent bits of two floating-point numbers without departing from the scope of the invention. Furthermore, it should be understood that the syntax and terminology used in this specification are for illustrative purposes only and should not be considered limiting. Those skilled in the art will understand that the embodiments of methods and diagrams in this specification are merely illustrative and not limiting. Those skilled in the art who understand the spirit of the invention through the disclosure of this specification may use other embodiments, all of which should fall within the scope of the claims of this invention.

[0091] To achieve better computational efficiency and save computational power, the floating-point addition and subtraction circuit device of the present invention performs single-step floating-point addition or subtraction operations without shifting intermediate data into and out of memory and arithmetic circuit units as in multi-step operations. To achieve single-step floating-point addition / subtraction operations, the floating-point addition and subtraction circuit device of the present invention includes: (1) a circuit for converting two input operand codes in IEEE 754 floating-point format into a complete floating-point binary representation containing two most significant mantissa bits; (2) a circuit for aligning the mantissa bits of the operands according to the exponent difference of the two input operand codes; (3) a circuit for performing addition or subtraction operations on the aligned mantissa bits, and a circuit for performing sign bit operations; (4) a circuit for converting the final binary code into an IEEE 754 floating-point digital format for subsequent arithmetic operations or memory storage.

[0092] To address the problem that existing technologies cannot directly obtain the final floating-point number C through bit-to-bit operations, this invention, in order to obtain the correct floating-point number and avoid errors such as A+B≠B+A and AB≠-(BA), requires first adjusting the operand exponents to the same exponent and aligning the mantissas of the number in order to correctly perform addition / subtraction operations.

[0093] According to a primary embodiment of the present invention, an addition and subtraction circuit device is designed to perform addition / subtraction operations on two floating-point numbers represented in floating-point format in a single arithmetic step, and output a final floating-point number represented in the same floating-point format. In contrast, conventional floating-point addition or subtraction circuit devices require multiple arithmetic steps, typically involving the transfer of intermediate data between temporary data storage circuits and other logic circuits (e.g., comparison circuits and shift circuits) via bus lines. Therefore, since no intermediate data transfer and temporary memory storage are required, the addition and subtraction circuit device of the present invention can significantly improve computational efficiency through a single-step operation.

[0094] According to another embodiment of the present invention, since there is no intermediate data transmission between the memory circuit and other arithmetic circuits, the power consumed by intermediate data transmission between circuit modules via connecting busbars can be completely saved. Power consumption for data transmission via fixed-bandwidth busbars is considered a major factor in the power consumption of digital computing systems.

[0095] According to another embodiment of the invention, when the final floating-point number obtained by the circuit operation cannot be represented in a finite-length floating-point format (e.g., IEEE 754), the arithmetic circuit should generate an overflow flag signal to indicate that the final floating-point number exceeds the numerical representation range. This out-of-range floating-point number cannot be used for further arithmetic operations and memory storage to prevent calculation errors using the same finite-length floating-point representation.

[0096] According to another embodiment of the present invention, since the input / output floating-point numbers of the addition and subtraction circuit devices of the present invention adopt the same floating-point format as the complete numerical elements of data transmission and memory storage in the computer system, it is easier to master the data management of complete numerical elements of arithmetic operations and memory access. Thus, the addition and subtraction circuit devices of the present invention can be effectively applied to matrix calculations, and are particularly suitable for neural network model calculations in machine learning (ML) to expand large-scale model systems.

[0097] The equations for floating-point addition / subtraction operations are expressed as follows:

[0098]

[0099] To elaborate further:

[0100] Where ed≥0, and

[0101] Where ed < 0,

[0102] Wherein, the exponential difference ed = ea - eb.

[0103] The exponential difference ed is represented by a sign bit sed (= logical value [0,1]) and an absolute value |ed| in binary format. "sed = logical value 1" represents a negative value, and "sed = logical value 0" represents ed as a positive value or the same value. The binary format of the absolute value |ed| is as follows: (ed q-1 ed q-2 ...ed1ed0)b represents |ed| = ed q-1 2 q-1 +ed q-2 2 q-2 +…+ed12 1 +ed02 0 , where ed i =Logical value [0,1], and i = (q-1),...,0. When the sign bit sed is "0", ed is a positive number or zero (ed≥0). The range of numbers A is greater than or equal to the range of numbers B. Then, the exponent of the value A is chosen as the exponent for the addition or subtraction of the two floating-point numbers A and B. At the same time, all mantissa bits of the floating-point number B are shifted down (or right) by a shift amount equal to the binary code (ed). q-1 ed q-2 ...ed1ed0)b represents the value of |ed|, so as to align with the mantissa of the value A for addition or subtraction operations. When the sign bit sed is "1", ed is negative (ed<0), the exponent of A is less than or equal to the exponent of B. Then, the exponent of the value B is chosen as the exponent for the addition or subtraction operation of the two floating-point numbers A and B. At the same time, all mantissa bits of floating-point number A are shifted down (or right) by a shift amount in binary code (ed1ed0)b. q-1 ed q-2 ...ed1ed0)b represents the value of |ed| so that it can be aligned with the mantissa of the value B for addition or subtraction operations.

[0104] Based on the above two operational rules for addition or subtraction of binary floating-point numbers conforming to the IEEE 754 format, Figure 2The addition and subtraction circuit device 200 of the present invention includes: (1) an addition / subtraction (A / S) selection and sign logic circuit 240 for selecting one of the addition and subtraction operations (i.e., generating a "subtraction" bit) and the sign bit operation of the final floating-point number; (2) a most significant bit circuit 210 for decoding the two most significant mantissa bits of two floating-point numbers A and B in IEEE 754 format; (3) an exponent subtraction (ea-eb) circuit 220 for obtaining the sign bit (sed) and the exponent difference bit (ed(0:q-1)) representing the absolute value of the difference between the exponents of the two floating-point numbers A and B; (4) a mantissa alignment circuit 221 for aligning the mantissa bits; (5) an addition / subtraction circuit 222 for performing addition or subtraction operations based on the "subtraction" bit; (6) an exponent selection / addition circuit 223 for obtaining the exponent bits es(0:q) after the operation; and (7) an IEEE 754 formatted array. IEEE 754 format conversion circuit 230. The IEEE 754 format conversion circuit 230 includes: (i) a leading zero (LZ) detection circuit 231 for detecting the first non-zero leading mantissa from mc(0:p) to output SL(0:p); and (ii) a leading zero shift code generation circuit 232 for encoding the output SL(0:p) of the LZ detection circuit 231 into a one-shift binary code LZC. k (0:q-1); (iii) LZ barrel shifter circuit 233, used to adjust the shift code LZC. k (iv) The subnormal barrel shifter circuit 234, based on the output Sb(0:q-1) of the exponent adjustment circuit 235, shifts the entire mantissa of the output ml(0:p-1) of the LZ barrel shifter circuit 233 to the right to conform to the subnormal floating-point format; (v) The exponent adjustment circuit 235, based on the exponent bits es(0:q) and the shift code LZC, shifts the entire mantissa of the output ml(0:p-1) of the LZ barrel shifter circuit 233 to the right to conform to the subnormal floating-point format. k (0:q-1), adjust the exponent bits to conform to the IEEE 754 exponent format.

[0105] When the addition / subtraction selection and sign logic circuit 240 is controlled by the voltage signal V on node Enb 204 DDUpon startup, the addition / subtraction selection signal (i.e., an external operator) on node A / S203, along with the voltage signal of the sign bit sa of floating-point number A on node 201s and the voltage signal of the sign bit sb of floating-point number B on node 202s, are input to circuit 240 to generate a voltage signal of a "subtraction" bit (i.e., an internal operator). The addition / subtraction circuit 222 then uses this "subtraction" bit to perform addition or subtraction operations. After receiving the voltage signal of the "negation" bit / flag generated by the addition / subtraction circuit 222, the voltage signal of the sign bit sc of the final floating-point number C is output on node 205s.

[0106] The input voltage signal for a floating-point number A in IEEE 754 format includes: the voltage signal of the sign bit sa at node 201s, and the voltage signal of the exponent bit "ea" at node 201e. q-1 The voltage signal of “,...,ea0)b≡ea(0:q-1)” and the mantissa “(a” on node 201m p-2 The voltage signal is defined as ",...,a0)b≡a(0:q-2)". Voltage input nodes 201s, 201e, and 201m constitute voltage input node 201 with floating-point number A in IEEE 754 format. The input voltage signal with floating-point number B in IEEE 754 format includes: the voltage signal with sign bit sb on node 202s, and the voltage signal with exponent bit "(eb)" on node 202e. q-1 The voltage signal of ",...,eb0)b≡eb(0:q-1)" and the mantissa "(b" at node 202m p-2 The voltage signal is defined as follows: ,...,b0)b≡b(0:p-2)”. Voltage input nodes 202s, 202e, and 202m constitute voltage input node 202 with floating-point number B in IEEE 754 format.

[0107] The most significant bit circuit 210 is based on the exponent (ea) at node 201e. q-1 ,...,ea0)b and the index on 202e (eb) q-1 The voltage signal of ,...,eb0)b is used to obtain the most significant mantissa bits of the two floating-point numbers A and B, "a". p-1 ≡a(p-1)” and “b p-1 ≡b(p-1)". Voltage signals a(p-1) and b(p-1), along with the mantissa "(a" at node 201m p-2 The voltage signal of “,...,a0)b≡a(0:p-2)” and the mantissa “(b” on node 202m p-2 The voltage signals ",...,b0)b≡b(0:p-2)" respectively form the voltage signals of the p mantissa bits of two floating-point numbers A and B. The exponential subtraction (ea-eb) circuit 220, based on the exponent bit "(ea-eb)" at node 201e...q-1 The voltage signal of “,...,ea0)b≡ea(0:q-1)” and the exponent bit “(eb)” on node 202e. q-1 The voltage signal “,...,eb0)b≡eb(0:q-1)” generates a signed binary exponent difference: a sign bit (sed) and an exponent difference bit (ed(0:q-1)). Then, the voltage signals sed and ed(0:q-1) are fed into the mantissa alignment circuit 221 to right-shift the mantissa of floating-point number A or B (whichever has the smaller exponent) in parallel, aligning their mantissas in the mantissa alignment circuit 221 for addition and subtraction operations. After the mantissa alignment circuit 221 shifts the mantissa bits of floating-point number A or B, the aligned mantissa bits of floating-point number A are... The voltage signal a(0:p-1) and the voltage signal of the aligned mantissa bits mb(0:p-1) of B are fed into the adder / subtractor circuit 220 for addition / subtraction operations. Note that in the mantissa alignment circuit 221, the mantissa of the floating-point operand with the larger exponent is shifted by 0 positions, while the barrel shifter circuit 520 shifts the mantissa of the floating-point operand with the smaller exponent to the right according to the shift code ed(0:q-1). For the floating-point operand with the smaller exponent, the shifted mantissa bits are truncated at the least significant bit (LSB) of "p" mantissa bits to ensure a truncated mantissa precision of 1 / 2. (p-1) .

[0108] Simultaneously, the voltage signal of the sign bit sed is fed into the exponent selection / adder circuit 223 to select the larger exponent between ea(0:q-1) and eb(0:q-1) so that it can be added to the carry bit mc(p) generated from the adder / subtractor circuit 222 to generate the arithmetic exponent es(0:q). Next, the voltage signal of the mantissa bit mc(0:p) from the adder / subtractor circuit 222 and the arithmetic exponent bit es(0:q) from the exponent selection / adder circuit 223 are fed into the format conversion circuit 230 to convert the arithmetic exponent es(0:q) and the arithmetic mantissa bit mc(0:p) into a final floating-point number in IEEE 754 format.

[0109] In a general embodiment, Figure 2 A schematic diagram of a (q+p) bit floating-point addition / subtraction circuit device 200 conforming to IEEE 754 format is shown. Figure 3 The most significant bit display circuit 210 generates voltage signals for the most significant mantissa bits a(p-1) and b(p-1) based on the input voltage signal of the exponent bits "ea(0:q-1)" of floating-point number A at node 201e and the input voltage signal of the exponent bits "eb(0:q-1)" of floating-point number B at node 202e. When the voltage signal Enb at node 204 is... DDUpon startup, NMOSFET devices 301 and 302 output voltage signals with the most significant mantissa bits a(p-1) and b(p-1) respectively at nodes 314 and 315. The gate of NMOSFET device 301 is connected to node 201e to receive voltage signal ea(0:q-1), while the gate of NMOSFET device 302 is connected to node 202e to receive voltage signal eb(0:q-1). If the voltage signals ea(0:q-1) are all input V... SS (That is, all values ​​are 0), then all NMOSFET devices 301 are turned off, and the output voltage signal V at node 314 is... SS (Digital value 0). If the voltage signal of any bit in ea(0:q-1) is input to V DD (i.e., digital value 1), then the gate voltage is V. DD The corresponding NMOSFET device 301 will be turned on, and the output voltage signal V at node 314 will be activated. DD (Digital value 1). Similarly, if all eb(0:q-1) voltage signals are input V SS (i.e., all values ​​are 0), then all NMOSFET devices 302 are turned off and the output voltage signal V at node 315 is turned off. SS (Digital value 0). If the voltage signal of any bit in eb(0:q-1) is input to V DD (i.e., digital value 1), then the gate voltage is V. DD The corresponding NMOSFET device 302 will be turned on, and the output voltage signal V will be generated at node 315. DD (Numerical value 1).

[0110] like Figure 4 As shown, the exponential subtraction circuit 220 is constructed using a q-bit binary subtraction circuit. Figure 4 In the diagram, the exponential subtraction circuit 220 includes a q-bit exponential subtraction circuit 410 in the first row, a two's complement conversion circuit 420 in the second row, an addition circuit 430 (used for one normal floating-point operation and one normal floating-point operation) in the third row, and an XOR gate 411. The voltage signals ea (0:q-1) at node 201e and eb (0:q-1) at node 202e are input to the subtraction circuit 410 to generate a sign bit sed at node 412, used to select the floating-point operand with the smaller exponent, and a shift code ed (0:q-1) at node 416, used to shift down the mantissa of the floating-point operand with the smaller exponent to align with the mantissa of the floating-point operand with the larger exponent. If the voltage signal of the sign bit sed output at node 412 is V... SS(A digital value of 0) indicates that the exponent of floating-point operand A is greater than or equal to the exponent of floating-point operand B, meaning the exponent difference is positive or zero. If the voltage signal of the sign bit sed output on node 412 is V... DD (i.e., the digital value 1) indicates that the exponent of floating-point operand A is less than the exponent of floating-point operand B, meaning the exponent difference is negative. For negative exponent differences, the two's complement conversion circuit 420 in the second row will convert the input voltage signal of the binary code at the output node 413 of the first row circuit 410 into the output voltage signal of the two's complement binary code at the output node 414; otherwise, for positive or zero exponent differences, the voltage signal output from the two's complement conversion circuit 420 in the second row at node 414 will be the same as the voltage signal output from the output node 413 of the first row circuit 410.

[0111] In finite floating-point binary representation, subnormal floating-point numbers are represented by a binary exponent consisting entirely of "0"s, with a leading mantissa of "0"; while normal floating-point numbers are represented by at least one non-zero binary exponent, with a leading mantissa of "1". To correctly align the mantissa positions of the normal and subnormal floating-point operands for addition and subtraction operations, the mantissa position of the subnormal floating-point operand needs to be shifted down one bit because the leading mantissas of "0" and "1" are different. Therefore, the adder circuit 430 in the third row adds the output binary value ("1" represents a(p-1)≠b(p-1), and "0" represents a(p-1)=b(p-1)) on the output node 415 of the XOR gate 411 to the output of the circuit 420 in the second row to obtain the correct shift code ed(0:q-1) of the mantissa of a normal floating-point operand, so as to align the mantissa of another normal floating-point operand in subsequent addition and subtraction operations.

[0112] Figure 5A According to an embodiment of the present invention, the display Figure 2 A schematic diagram of the mantissa alignment circuit 221 is shown. The mantissa alignment circuit 221 is used to right-shift the mantissa of a floating-point operand with a smaller exponent to align it with the mantissa of a floating-point operand with a larger exponent. Figure 5AIn this circuit, the mantissa alignment circuit 221 includes a selection circuit 510, a barrel shifter circuit 520, and an operation sequence circuit 530. The selection circuit 510 selects the mantissa bits with the smaller exponent as si(0:p-1) to be fed into the input of the barrel shifter circuit 520; the barrel shifter circuit 520 shifts the input mantissa bits si(0:p-1) in parallel and fills empty bits with "0"s to serve as the mantissa bits so(0:p-1) with the smaller exponent; the operation sequence circuit 530 restores the operands to their original operation order (always placing the mantissa bits of A in the first operation position and the mantissa bits of B in the second operation position, regardless of which floating-point number has a smaller exponent). (See reference) Figure 5B The barrel shifter circuit 520 includes 2p columns of transmission gates (Clm(0) to Clm(2p-1)), wherein the input nodes of the first p columns of transmission gates (Clm(0) to Clm(p-1)) are connected to the ground voltage V of node 501. SS (Number value 0), fill the shifted-down blank mantissas with "0", and output it at node 504 as the left part of so(0:p-1). From Figure 4 The voltage signal of the shift code ed(0:q-1) input to node 416 in circuit 220 is used to control the mantissa position of the right shift of si(0:p-1) on input node 503, so as to obtain the signal so(0:p-1) on output node 504. When the signal sed on node 412 is equal to the voltage signal V SS When (A>=B), the selection circuit 510 transmits the input voltage signal a(0:p-1) to node 506 as the voltage signal o(0:p-1), and transmits the input voltage signal b(0:p-1) to the input node 503 of the barrel shifter circuit 520 as the input signal si(0:p-1), so as to right shift the mantissa of the floating-point operand B with the smaller exponent; at the same time, if the signal sed on node 412 is equal to the voltage signal V SS (A>=B), the operation sequence circuit 530 transmits the voltage signal o(0:p-1) on node 506 to output node 531 as the voltage signal ma(0:p-1), and also transmits the voltage signal so(0:p-1) on output node 504 of the barrel shifter circuit 520 to output node 532 as the voltage signal mb(0:p-1). When the signal sed on node 412 equals the voltage signal V DDWhen (A < B), the selection circuit 510 transfers the input voltage signal b(0:p - 1) to the node 506 as the voltage signal o(0:p - 1), and transfers the input voltage signal a(0:p - 1) to the input node 503 of the barrel shifter circuit 520 as the input signal si(0:p - 1), so as to shift the mantissa position of the floating - point number A with a smaller exponent to the right; at the same time, if the signal sed on the node 412 is equal to the voltage signal V DD When (A < B), the operation sequence circuit 530 transfers the voltage signal o(0:p - 1) on the node 506 to the output node 532 as the voltage signal mb(0:p - 1), and transfers the voltage signal so(0:p - 1) on the output node 504 of the barrel shifter circuit 520 to the output node 531 as the voltage signal ma(0:p - 1).

[0113] Figure 6 Display Figure 2 Schematic diagram of the addition / subtraction circuit 222. The addition / subtraction circuit 222 includes a p - bit addition / subtraction circuit 610, a p - bit two's complement conversion circuit 620, and a carry / negation logic circuit 630. Figure 6 In Figure 5A The aligned mantissas ma(0:p - 1) and mb(0:p - 1) generated by the circuit 221 are respectively fed into the nodes 531 and 532. Figure 14 The voltage signal V of the "subtraction" bit (i.e., an internal operator) output from the addition / subtraction selection and sign logic circuit 240 to the node 1406 DD (numerical value ①) and V SS (numerical value ②) respectively select the subtraction operation (i.e., the subtraction operation of the aligned mantissas: (ma(0:p - 1)-mb(0:p - 1))) and the addition operation (i.e., the addition operation of the aligned mantissas: (ma(0:p - 1)+mb(0:p - 1))). After the addition / subtraction operation, the voltage signal mc(0:p - 1) is output at the node 604 and a carry bit mc(p) is output at the node 605. The carry bit on the node 605: "mc(p) is equal to V DD (numerical value ①)" represents an additional carry after the addition operation, otherwise, "mc(p) is equal to V SS (numerical value ②)" represents no additional carry after the addition operation. At the same time, the "negation" bit / flag on the node ⑥ is equal to V DD (numerical value ①) represents that the result of the subtraction operation is negative, i.e., ma(0:p - 1)<mb(0:p - 1), otherwise, the "negation" bit / flag is equal to V SS(A digital value of 0) represents that the result of the subtraction operation is a positive value or 0, i.e., ma(0:p-1)>=mb(0:p-1). Then, the voltage signal of the "negation" bit / flag on node 606 is fed into the addition / subtraction selection and sign logic circuit 240 to obtain... Figure 2 The voltage signal of the symbol sc of the final floating-point number C on node 205s.

[0114] Figure 7 According to an embodiment of the present invention, a circuit diagram of an exponent selection / addition circuit 223 is shown. The exponent selection / addition circuit 223 includes a row of transmission gates 710 and an adder circuit 720. The row of transmission gates 710 uses a selection control voltage signal sed to select the larger exponent between ea(0:q-1) at output node 201e and eb(0:q-1) at node 202e. The adder circuit 720 adds the selected larger exponent to the carry bit mc(p) at node 605 to generate the calculated exponent es(0:q) at nodes 705 and 206. Figure 7 The post-operation exponents es(0:q) on nodes 705 and 206 and Figure 6 The mantissas mc(0:p) on nodes 604 and 605 represent the exponent and mantissa bits of the resulting floating-point number, respectively, excluding the sign bit. Then, by Figure 2 The IEEE 754 format conversion circuit 230 converts the exponent es (0:q) and mantissa mc (0:p) after the operation.

[0115] For the IEEE 754 format conversion circuit 230, Figure 8 The circuit diagram of the leading zero detection circuit 231 is shown. The leading zero detection circuit 231 is used to detect the first non-zero leading mantissa bit in the mantissa mc(0:p) relative to the MSB mc(p). Figure 8 In the circuit 231, the voltage signal of mc(0:p) (including the carry bit mc(p)) is input at nodes 604 and 605; when the first non-zero bit mc(k) relative to MSB mc(p) is detected from mc(0:p), the circuit 231 outputs a voltage signal V at the corresponding column SL(pk) of node 802. DD (“1”), as for the other columns SL(n), the output voltage signal V SS (“0”), where n = 0 to p but n ≠ (pk). Then, the voltage signal of SL(0:p) is fed into... Figure 9 The leading zero-shift code generation circuit 232 generates the shift code LZC. k The voltage signal of (0:q-1) is in Figure 10In the LZ barrel shifter circuit 233, the mantissa bits mc(0:p-1) are shifted up (or left) to the first non-zero leading mantissa position (i.e., ml(p-1)). Please note that Figure 9 The intermediate shift code generation circuit 232 includes a read memory (ROM) array with multiple ROM cells, wherein each metal contact 911 is predefined and used to connect the drain active area of ​​the corresponding transistor 910 to two metal lines (each applied V). DD and V SS One method involves pre-storing multiple predefined binary codes in the aforementioned ROM units. In input node 802, only the selected character line SL(pk) is V... DD Turn on so that the corresponding ROM code LZC is output on node 902. k (0:q-1), that is: the value (pk) = LZC k (q-1)2 q-1 +LZC k (q-2)2 q-2 +...+LZC k (1)2 1 +LZC k (0)2 0 For example, if mc(p-2) = 1 and mc(p) = mc(p-1) = 0, then mc(p-2) is called the leading / first non-zero bit in mc(0:p), resulting in SL(2) = 1 and other SL(k) = 0, where k = 0, 1, 3, ..., p. Then, at... Figure 9 The bit line node 902 of circuit 232 outputs the shift code LZC. k The voltage signal of (0:q-1)=(00…10)b.

[0116] Figure 10 This diagram shows the circuit diagram of the LZ barrel shifter circuit 233, which is used to... Figure 9 The shift code LZC of node 902 in the leading zero shift code generation circuit 232 k (0:q-1), shifting mc(0:p-1) on input node 604 to the left in parallel to ml(0:p-1) on output node 1003, i.e., the position of the first non-zero leading mantissa. The barrel shifter circuit 233 contains 2p columns of transmission gates (Clm(0) to Clm(2p-1)), wherein the input nodes of the last p columns of transmission gates (Clm(p) to Clm(2p-1)) are connected to the ground voltage V of node 1005. SS (Digital value 0). Then, the voltage signal of ml(0:p-1) is fed into... Figure 11The input node 1003 of the subnormal barrel shifter circuit 234. Figure 11 In the middle, the subnormal barrel shifter circuit 234 is based on Figure 12 The exponent adjustment circuit 235 shifts the mantissa ml (0:p-1) down at node 1202 using the shift code Sb(0:q-1) and fills the leading subnormal blank mantissa with 0 to output c(0:p-2) at output node 205m. The subnormal barrel shifter circuit 234 contains 2p columns of transmission gates (Clm(0) to Clm(2p-1)), wherein the input nodes of the first p columns of transmission gates (Clm(0) to Clm(p-1)) are connected to the ground voltage V at node 1205. SS (Numerical value 0). Figure 11 The subnormal barrel shifter circuit 234 shifts the mantissa of the normal floating-point number by zero positions according to the shift code Sb(0:q-1)=(0…0)b, so as to output c(0:p-2) at the output node 205m. In other words, the voltage signal ml(0:p-1) at node 1003 is directly transmitted to node 205m to output the voltage signal c(0:p-2). Figure 12 The exponential adjustment circuit 235 generates a voltage signal of subnormal shift code Sb(0:q-1). It should be noted that the above... Figure 5B and Figure 10-11 The barrel shifter circuits 520, 233, and 234 described herein are provided as examples only and are not intended to limit the invention. In actual implementation, as long as the same result can be achieved, the barrel shifter circuits 520, 233, and 234 described above can be implemented with other types of barrel shifters, such as crossbar barrel shifters and barrel shifters implemented by cascading multiple parallel multiplexers, which also fall within the scope of the invention.

[0117] Figure 12 In the circuit, the exponent adjustment circuit 235 includes an increment circuit 1210, a subtraction circuit 1220, an increment circuit 1230, and a logic circuit 1240. The increment circuit 1210 is used to increment the shift code LZC. k (0:q-1) is added to the value 1, and the subtraction circuit 1220 is used to subtract the output (LZC) of circuit 1210 from the exponent es(0:q-1) after the operation. k (0:q-1)+(0...1)b). This "add one" circuit 1230 is used to add the value 1 back to compensate for the extra 1 subtracted from the normal floating-point number; that is, at node 1231, [es(0:q-1)-(LZC)] is output. k[(0:q-1)+(0...1)b)+(0...1)b]; Logic circuit 1240 generates a voltage signal for the final exponent ec(0:q-1) at node 205e and a voltage signal for the shift code Sb(0:q-1) at node 1202. In logic circuit 1240, the voltage signal for the exponent symbol esg at node 1221 is used to determine whether the floating-point number after the above operation is a subnormal or normal floating-point number. The voltage signal V for the exponent symbol esg at node 1221 is... DD This indicates that the floating-point number after the above operation is a subnormal floating-point number, with all its exponent bits equal to 0. Therefore, the exponent ec(0:q-1) at node 205e is set to V. SS (“0”), and simultaneously, the voltage signal of the non-zero normal shift code Sb(0:q-1) generated by the output node 1222 of the subtraction circuit 1220 and output at node 1202 is fed into the circuit. Figure 11 The subnormal barrel shifter circuit 234 shifts the subnormal mantissa down (or right) and fills its leading blank mantissa with 0. On the other hand, the voltage signal V of the exponent symbol esg at node 1221... SS This indicates that the floating-point number after the above operation is a normal floating-point number with a non-zero exponent. The output of node 1222 of the subtraction circuit 1220 is fed into the "add-one" circuit 1230 to add back the value 1 to compensate for the extra subtraction of the value 1, so as to obtain the correct non-zero exponent ec(0:q-1) of a normal floating-point number. At the same time, because the voltage signal of the exponent sign esg at node 1221 is V SS The logic circuit 1240 generates a zero-shift code Sb(0:q-1) = (0...0)b, therefore... Figure 11 The subnormal barrel shifter circuit 2341 does not shift down any mantissa position, but instead directly transmits ml(0:p-2) to node 205m to output c(0:p-2). Please note that Figure 7 The most significant exponent bit es(q) generated by the exponent selection / adder circuit 223 is directly transmitted to the overflow node 206, representing the flag symbol of the overflow status.

[0118] Figure 13 and 14The diagrams show logic table 1310 and the corresponding addition / subtraction selection and sign logic circuit 240. The first column of logic table 1310 defines the addition / subtraction formula for the absolute values ​​of two floating-point numbers A and B. The first row of logic table 1310 displays the inputs: the sign bits sa and sb of the two floating-point numbers A and B, the A / S bit (an external operator) for selecting addition or subtraction, the "subtraction" bit (an internal operator provided to the addition / subtraction circuit 222 for adding or subtracting the absolute values ​​of the two floating-point numbers A and B), and the sign bit sc of the final floating-point number C. The sign bits sa, sb, and sc of floating-point numbers A, B, and C are 1 if they represent a negative number, and 0 if they represent a positive number or equal to 0; an A / S bit of 0 represents addition, and 1 represents subtraction. The sc logic value in the last column includes the "negation" bit and the "..." bit. The "negation bit" bit represents the sign of the resulting floating-point number after the addition / subtraction circuit 222 performs a subtraction between the two aligned p-bit mantissas ma(0:p-1) and mb(0:p-1) of the absolute values ​​of the two floating-point operands A and B. The "negation bit" / sign of the resulting floating-point number from the addition / subtraction circuit 222 is defined as follows: 0 represents a positive value or a value equal to 0, and 1 represents a negative value.

[0119] Figure 14 This diagram shows the addition / subtraction selection and sign logic circuit 240 that implements logic table 1310. The addition / subtraction selection and sign logic circuit 240 receives... Figure 2 The voltage signals sa, sb, and A / S on nodes 201s, 202s, and 203. Based on the logic values ​​in columns 2, 3, and 4 of logic table 1310 and the input voltage signals sa, sb, and A / S, logic circuit 1421 obtains the voltage signal of the "subtraction bit" on node 1406 (corresponding to column 5 of logic table 1310). Then, the voltage signal of the "subtraction bit" on node 1406 is fed into adder / subtractor circuit 222 to subtract the two aligned mantissa bits ma(0:p-1) and mb(0:p-1) of the absolute value of floating-point operand A and the absolute value of floating-point operand B. Simultaneously, the voltage signal of the "negation bit" from adder / subtractor circuit 222 is fed into logic circuit 1422. Logic circuit 1422 responds to the "negation" bit or... The "(negative inverse)" bit (selected by the control voltage signal sa (corresponding to the logic value in the second column of logic table 1310)) is used to output a voltage signal at node 1407. Therefore, based on the voltage signal sa (corresponding to the logic value in the second column of logic table 1310) or The bit (corresponding to the logic value in the 5th column of logic table 1310 (selected by the "subtraction" bit on node 1406 (corresponding to the logic value in the 4th column of logic table 1310))) and the circuit 1423 generate the output signal of the sign sc of the final floating-point number C at node 205s.

[0120] In one embodiment, an addition and subtraction circuit for 16-bit floating-point numbers in IEEE 754 format has been designed and manufactured using a 40nm CMOS process technology at a wafer fab. This circuit has been verified to produce a final floating-point number derived from the addition / subtraction of two floating-point numbers, rounded to the nearest floating-point number in IEEE 754 16-bit format. Based on post-circuit simulation and RC load, the circuit's operating time is approximately 0.6 nanoseconds. DD Under a high voltage supply of 1.2V, the average peak current for various floating-point operations is approximately tens of microamperes (μA).

[0121] The preferred embodiments provided above are merely illustrative of the invention and are not intended to limit the invention to a specific type or exemplary embodiment. Therefore, this specification should be considered illustrative rather than restrictive. The preferred embodiments provided above are intended to effectively illustrate the spirit of the invention and its best mode of implementation, thereby enabling those skilled in the art to understand the various embodiments and modifications of the invention to suit specific uses or purposes. The scope of the invention is defined by the claims and their equivalents, wherein all terms are intended to have the broadest reasonable meaning unless otherwise specified. Therefore, terms such as "the invention" do not limit the scope of the claims to a particular embodiment, and any references to specific preferred embodiments of the invention are not intended to limit the invention, nor is the absence of such limitation presumed. The invention is defined only by the scope and spirit of the appended claims. The abstract of the invention is provided in accordance with regulatory requirements to enable a searcher to quickly identify the subject matter of this disclosure from any patents approved under this specification, and is not intended to interpret or limit the scope and meaning of the claims. Any advantages and benefits may not apply to all embodiments of the invention. It should be understood that various modifications or alterations can be made by those skilled in the art, all of which should fall within the scope of the invention as defined in the claims. Furthermore, all elements and components in this specification are not intended for public distribution, regardless of whether they are listed in the claims.

Claims

1. A floating-point arithmetic device, characterized in that, The device is used to perform an arithmetic operation on a first operand and a second operand according to an external operand to produce a final number, wherein the external operand represents one of addition and subtraction, wherein the first operand, the second operand, and the final number are all binary floating-point numbers, and each includes a sign bit, a q-bit exponent, and a p-bit mantissa. The device includes: An exponential subtraction circuit is used to calculate the difference between the q-bit exponents of the first operand and the second operand, so as to generate a first sign bit and an exponential difference. An exponent calculation circuit, coupled to the exponent subtraction circuit, is used to select a larger exponent from the q-bit exponents of the first operand and the second operand based on the first sign bit, and to generate an intermediate (q+1)-bit exponent based on the larger exponent. A mantissa calculation circuit, coupled to the exponent subtraction circuit, is configured to (1) select a smaller exponent from the q-bit exponents of the first operand and the second operand according to the first sign bit; (2) right-shift one of the p-bit mantissas of the first operand and the second operand corresponding to the smaller exponent according to a first q-bit shifted binary code to generate a right-shifted p-bit mantissa; and (3) add or subtract one of the right-shifted p-bit mantissas and another p-bit mantissa of the first operand and the second operand according to an internal operator to generate an intermediate (p+1)-bit mantissa, wherein the internal operator is with respect to the sign bit of the external operator and the first operand and the second operand, and wherein the first q-bit shifted binary code is equivalent to the exponent difference; as well as A conversion circuit, coupled to the exponent calculation circuit and the mantissa calculation circuit, is used to convert the intermediate (q+1)-bit exponent and the intermediate (p+1)-bit mantissa into the q-bit exponent and p-bit mantissa of the final number, respectively.

2. The apparatus as claimed in claim 1, characterized in that, It also includes: A sign and operator logic circuit is coupled to the mantissa calculation circuit. Based on the sign bits of the external operator, the first operand, and the second operand, and a negation flag, the sign bit of the final number and the internal operator are generated. The negation flag indicates whether the absolute value of the right-shifted p-bit mantissa is less than the absolute value of another p-bit mantissa among the p-bit mantissas of the first operand and the second operand.

3. The apparatus as described in claim 2, characterized in that, The symbol and operational sub-logic circuit includes: Two cascaded XOR gates have three inputs for receiving the external operator and the sign bits of the first and second operands to generate the internal operator.

4. The apparatus as claimed in claim 1, characterized in that, The exponent calculation circuit includes: A first adder circuit adds the larger exponent to the most significant bit (MSB) of the intermediate (p+1)-bit mantissa to generate the intermediate (q+1)-bit exponent.

5. The apparatus as claimed in claim 1, characterized in that, The exponential subtraction circuit includes: A first subtraction circuit subtracts the q-bit exponent of the second operand from the q-bit exponent of the first operand to produce a signed intermediate exponent difference. An XOR gate device having two inputs for receiving the MSB of the p-bit mantissa of the first operand and the second operand to generate an output bit; and A second adder circuit adds the output bit to the signed intermediate exponent difference to produce the first sign bit and the exponent difference.

6. The apparatus as claimed in claim 1, characterized in that, The mantissa calculation circuit includes: A first barrel shifter circuit, based on the first q-bit shifted binary code, shifts the p-bit mantissa corresponding to the first operand and the second operand with the smaller exponent in parallel to the right, so as to generate the right-shifted p-bit mantissa.

7. The apparatus as claimed in claim 1, characterized in that, The mantissa calculation circuit includes: An arithmetic circuit, based on the internal operator, performs one of addition and subtraction on another p-bit mantissa among the p-bit mantissas of the right-shifted p-bit mantissa and the p-bit mantissas of the first operand and the second operand, to generate the intermediate (p+1)-bit mantissa.

8. The apparatus as claimed in claim 1, characterized in that, The MSB of the middle (q+1) bit exponent indicates whether the final number exceeds the range of numerical representation.

9. The apparatus as claimed in claim 1, characterized in that, The conversion circuit is used to (a) identify a leading non-zero position from the intermediate (p+1) mantissa relative to the MSB position of the intermediate (p+1) mantissa; (b) convert the leading non-zero position into a second q-bit shifted binary code; (c) shift the p less significant bits of the intermediate (p+1) mantissa to the left in parallel according to the second q-bit shifted binary code to generate an intermediate p-bit mantissa; and (d) generate the q-bit exponent of the final value according to the difference between the intermediate (q+1)-bit exponent and the second q-bit shifted binary code.

10. The apparatus as claimed in claim 9, characterized in that, The conversion circuit includes: A third adder circuit adds a value of 1 to the second q-bit shifted binary code to generate a first q-bit sum binary code; A second subtraction circuit subtracts the first q-bit sum binary code from the intermediate (q+1)-bit exponent to generate a second sign bit esg and a q-bit difference binary code. A fourth adder circuit adds a value of 1 to the q-bit difference binary code to generate a second q-bit sum binary code; and A logic circuit is coupled to the second subtraction circuit and the fourth addition circuit to generate the q-bit exponent and a third q-bit shifted binary code of the final number. Wherein, if the second sign bit esg equals 1, the logic circuit sets the q-bit exponent of the final number to equal the binary code of a zero vector, and sets the third q-bit shift binary code to equal the q-bit difference binary code; and Wherein, if the second symbol bit esg is equal to 0, the logic circuit sets the q-bit exponent of the final number to be equal to the second q-bit sum binary code, and sets the third q-bit shift binary code to be equal to the binary code of a zero vector.

11. The apparatus as claimed in claim 10, characterized in that, The conversion circuit includes: A second barrel shifter circuit, based on the second q-bit shifted binary code, shifts p less significant bits of the middle (p+1)-bit mantissa in parallel to the left to generate the middle p-bit mantissa; as well as A third barrel shifter circuit, based on the third q-bit shift binary code, parallelly shifts the middle p-bit mantissa to the right to generate the p-bit mantissa of the final value.

12. The apparatus as claimed in claim 11, characterized in that, The conversion circuit includes: A detection circuit, coupled to the mantissa calculation circuit and having (p+1) outputs, is used to distinguish the leading non-zero bit position from the middle (p+1) mantissa bits relative to the MSB position of the middle (p+1) mantissa bits, so as to generate a consistent moving bit and p invalid bits on the (p+1) outputs; and A read memory array receives the actuation bit and the p invalid bits to output the second q-bit shifted binary code.

13. The apparatus as claimed in claim 12, characterized in that, The detection circuit includes: A series of (p-1) logic blocks and a logic element are used to check the (p-1)th to the 0th bits of the (p+1)th mantissa of the middle part, so as to provide data to the 1st to the pth outputs of the (p+1)th outputs. The MSB of the middle (p+1) bits is provided to the 0th output of the (p+1) outputs, and the data provided to the (p+1) outputs forms the actuator bit and the p invalid bits.

14. The apparatus as claimed in claim 12, characterized in that, The ROM array includes: Multiple ROM units are configured with a row and column circuit configuration to pre-store multiple predefined binary codes; (p+1) character lines are respectively connected to (p+1) output terminals of the detection circuit; as well as q bit lines are coupled to the second barrel shifter; When one of the (p+1) character lines is activated by the actuation bit, a corresponding row of ROM cells is turned on to output the second q-bit shifted binary code on the q-bit line.

15. A method for operating a floating-point arithmetic device, characterized in that, The floating-point arithmetic device performs an arithmetic operation on a first operand and a second operand using an external operator to generate a final number. The floating-point arithmetic device includes a first barrel shifter circuit and a conversion circuit. The external operator represents either addition or subtraction. The first operand, the second operand, and the final number are all binary floating-point numbers, each containing a sign bit, a q-bit exponent, and a p-bit mantissa. The method includes the following steps: Calculate the difference between the q-bit exponents of the first operand and the second operand to generate a first sign bit and an exponent difference; Using the first barrel shifter circuit, a p-bit mantissa corresponding to the first operand and the second operand with a smaller exponent is shifted right according to a first q-bit shifted binary code, so as to generate a p-bit mantissa that is shifted right, wherein the first q-bit shifted binary code is equivalent to the exponent difference. According to an internal operator, one of addition and subtraction is performed on the right-shifted p-bit mantissa and another p-bit mantissa among the first operand and the second operand to produce an intermediate (p+1)-bit mantissa, wherein the internal operator is with respect to the sign bit of the external operator and the first operand and the second operand. A middle (q+1) bit exponent is obtained based on a larger exponent, wherein the larger exponent is selected from the q-bit exponents of the first operand and the second operand based on the first sign bit; and The middle (q+1)-bit exponent and the middle (p+1)-bit mantissa are respectively converted into the q-bit exponent and p-bit mantissa of the final number.

16. The method as described in claim 15, characterized in that, It also includes: The sign bit of the final number and the internal operator are obtained based on the external operator, the sign bit of the first operand and the second operand, and a negation flag, wherein the negation flag indicates whether the absolute value of the right-shifted p-bit mantissa is less than the absolute value of another p-bit mantissa among the p-bit mantissas of the first operand and the second operand.

17. The method as described in claim 16, characterized in that, The steps of obtaining the sign bit of the final number and the internal operators include: An XOR operation is performed on the sign bits of the external operator, the first operand, and the second operand to obtain the internal operator; and The sign bit of the final number is obtained based on the sign bit of the first operand, the negation flag, and the internal operator.

18. The method as described in claim 15, characterized in that, The step of obtaining the intermediate (q+1) bit exponent includes: The larger exponent is added to the most significant bit (MSB) of the middle (p+1) mantissa to obtain the middle (q+1)-bit exponent.

19. The method as described in claim 15, characterized in that, The calculation steps include: Subtract the q-bit exponent of the second operand from the q-bit exponent of the first operand to obtain a signed intermediate exponent difference. Perform an XOR operation on the MSB of the p-bit mantissas of the first operand and the second operand to obtain an output bit; and The output bit is added to the signed intermediate exponent difference to obtain the first sign bit and the exponent difference.

20. The method as described in claim 15, characterized in that, The separate conversion steps include: A detection circuit is used to identify a leading non-zero bit position from the middle (p+1) bit mantissa relative to the MSB position of the middle (p+1) bit mantissa. Using a read-only ROM array, the leading non-zero bit position is converted into a second q-bit shifted binary code; and Using a second barrel shifter circuit, based on the second q-bit shifted binary code, the p lower significant bits of the intermediate (p+1)-bit mantissa are shifted to the left in parallel to generate an intermediate p-bit mantissa. The conversion circuit includes the detection circuit, the second barrel shifter circuit, and the ROM array.

21. The method as described in claim 20, characterized in that, The separate conversion steps include: After the discrimination step and the conversion step, the q-bit exponent of the final value is obtained based on the difference between the intermediate (q+1)-bit exponent and the second q-bit shifted binary code.

22. The method as described in claim 21, characterized in that, The step of obtaining the q-bit exponent of the final value includes: Add a value of 1 to the second q-bit shifted binary code to obtain a first q-bit sum binary code; Subtract the first q-bit sum binary code from the middle (q+1) bit exponent to obtain a second sign bit esg and a q-bit difference binary code. Add a value of 1 to the q-bit difference binary code to obtain a second q-bit sum binary code; If the second symbol bit esg is equal to 1, the q-bit exponent of the final number is set to a binary code of a zero vector, and a third q-bit shift binary code is set to the q-bit difference binary code. as well as If the second symbol bit esg is equal to 0, the q-bit exponent of the final number is set to be equal to the second q-bit sum binary code, and the third q-bit shift binary code is set to a zero vector binary code.

23. The method as described in claim 22, characterized in that, The separate conversion steps further include: After the step of parallel left shifting the middle (p+1) bit mantissa by p less significant bits, a third barrel shifter circuit is used to parallel right shift the middle p bit mantissa according to the third q bit shifted binary code to output the p bit mantissa of the final value. The conversion circuit further includes the third barrel shifter circuit.

24. The method as described in claim 20, characterized in that, The distinguishing step includes: Using the detection circuit, the position of the leading non-zero bit is determined from the (p+1) bits of the middle mantissa relative to the MSB position of the (p+1) bits of the middle mantissa, so as to obtain a consistent moving bit and p invalid bits. The detection circuit comprises (p-1) logic blocks connected in series and a logic element.

25. The method as described in claim 24, characterized in that, The step of converting the leading non-zero bit position into the second q-bit shifted binary code includes: Apply the actuation bit and the p invalid bits to the (p+1) character lines of the ROM array; and When the actuator bit activates one of the (p+1) character lines, a corresponding row of ROM cells is turned on to output the second q-bit shift binary through the q bit lines of the ROM array; The ROM array contains multiple ROM units configured with rows and columns to pre-store multiple predefined binary codes.

26. The method as described in claim 15, characterized in that, The MSB of the middle (q+1) bit exponent indicates whether the final number exceeds the range of numerical representation.

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