CMOS compatible graphene structures, interconnects and methods for fabricating same

Abstract

The MLG (multilayer graphene) device layer structure is connected using vias. The structure includes an M1 MLG interconnect device layer on a dielectric layer. An interlayer dielectric insulates the M1 MLG interconnect device layer. The M2 MLG interconnect device layer is on top of the interlayer dielectric. Metal vias penetrate the M2 MLG interconnect device layer, the interlayer dielectric, and the M1 MLG interconnect device layer, making edge contacts across the thickness of both the M1 MLG layer and the M2 MLG layer. The method forms an MLG layer by diffusing carbon from a solid-phase graphene precursor through a catalyst layer and depositing MLG on a dielectric or metal layer using mechanical pressure at a diffusion temperature.

Description

[Technical Field]

[0001] (U.S. Government Statement of Interest) This invention was made with government support under Contract No. W911NF-18-1-0366 awarded by the U.S. Army Research Office. The U.S. Government has certain rights in this invention.

[0002] (Cross-reference to priority and related applications) This application claims priority under 35 U.S.C. Section 119 and all applicable statutes and treaties to U.S. Provisional Application No. 63 / 123,587, filed December 10, 2020.

[0003] (Technical field) The field of the invention is semiconductor devices and manufacturing methods, and more particularly, the invention relates to interconnects and the formation of interconnects in integrated circuits (ICs). [Background technology]

[0004] Interconnects are critical components in all integrated circuits (ICs). They are the conductive pathways connecting the numerous transistors in digital, analog, or radio frequency (RF) ICs and are key factors determining their performance (speed), switching energy (power), and reliability (lifetime). Currently, the semiconductor industry employs copper (Cu) as the primary interconnect metal in most ICs, including various microprocessors. However, as Cu scales, its resistivity increases significantly due to size effects (increased grain boundary and surface scattering, and the effect of highly resistive barrier layers makes it difficult to thin), resulting in increased self-heating and reduced current-carrying capacity (or reliability). (Non-Patent Document 1) Therefore, the industry has been searching for solutions to replace Cu with other types of interconnects that scale with better performance attributes than Cu.

[0005] Cobalt (Co) has recently been introduced as a potential replacement for the narrowest Cu interconnects due to its higher melting point compared to Cu. As interconnect dimensions approach <20 nm, conventional (i.e., bulk or 3D) conductors such as Cu, Co, and noble metals such as ruthenium (Ru) suffer from significant size effects, leading to a nonlinear increase in resistivity, increased RC delay and self-heating (SH), and reduced electromigration (EM) reliability, thereby limiting performance, current carrying capability, and energy efficiency.

[0006] Graphene, particularly multilayer graphene (MLG) and doped multilayer graphene (DMLG), is a promising candidate to replace Cu due to its reduced resistivity (for doped MLG) and significantly higher melting point than conventional metals, including Cu and Co. Graphene belongs to a broader family of materials called two-dimensional (2D) van der Waals materials. 2. Graphene is also an excellent barrier material to prevent the diffusion of Cu and other metals. Graphene can also be employed as a seed layer for growing other electronic materials, including gallium nitride (GaN), to fabricate a variety of material heterostructures, including 2D-2D or 3D-2D structures, for various micro / nanoelectronic applications. However, compatibility with back-end-of-line (BEOL) CMOS processes is essential for employing any form of graphene (including single-layer (1L), few-layer (FLG), MLG, and DMLG) in interconnects and other BEOL structures (such as barrier / cap layers for Cu (or other conventional metal) interconnects) in CMOS integrated circuits, including Cu (or conventional metal) interconnects (Non-Patent Document 3), on-chip inductors (Non-Patent Document 4), or barrier / cap layers for monolithic 3D integration (Non-Patent Document 5). Single-layer or FLG can also be used as a canvas layer for area-selective fabrication of low-contact-resistance lateral heterojunction transistors (graphene-2D-semiconductor-graphene) and other active devices. Non-Patent Document 6. FLG can also be utilized to construct highly transparent electrodes for solar cells and other optical devices. Non-Patent Document 7. Previous efforts have attempted to adapt graphene to CMOS structures, but have encountered various obstacles, including the following:

[0007] Two previous publications disclose simulations showing that graphene nanoribbons can outperform Cu interconnects through intercalation doping. The proposed doping methods are impractical for CMOS fabrication because they rely on impractical (toxic) AsF5 doping. These publications are Non-Patent Document 8 and Non-Patent Document 9.

[0008] Another publication discloses doped graphene interconnects from transferred graphene by CVD growth at 900-1100°C. High temperature CVD and transfer are incompatible with state-of-the-art IC manufacturing processes. This publication is a non-patent document 10.

[0009] Others have proposed mechanical exfoliation to form graphene nanoribbon interconnects. Exfoliation is not suitable for large-scale manufacturing. In addition, the nanoribbons are undoped, providing low conductivity that is not comparable to current Cu interconnects. This exfoliation is disclosed in Non-Patent Document 11.

[0010] Patent Document 1 discloses a graphene ribbon wrapped around a conductive interconnect material. The carrier is a metal. This is a hybrid structure requiring a metal component, and the conductivity is limited by the contact resistance between the graphene and the metal, so it rarely matches the conductivity of Cu. Furthermore, the relatively low melting point of the metal component limits the current-carrying capacity of such a hybrid structure.

[0011] Patent Document 2 also discloses a hybrid metal-graphene interconnect structure. This interconnect also requires a barrier layer in the trench. The barrier material is selected from the group consisting of tantalum, tantalum nitride, and a graphene seed material selected from the group consisting of ruthenium, nickel, palladium, iridium, and copper. The same drawbacks mentioned in the previous paragraph apply.

[0012] Patent Document 3 discloses a graphene interconnect that requires an underlying catalyst film and an interconnect trench. The disclosed fabrication method involves a high-temperature (>800°C) graphene growth process that is incompatible with CMOS BEOL processes.

[0013] US Patent No. 5,999,233 discloses graphene connectors in trenches lined with Ru or Ta liners using a filler metal in elemental form or alloy containing one or more of copper, aluminum, silver, gold, calcium, platinum, tin, lithium, zinc, nickel, and tungsten. The graphene formation process is low-temperature CVD, which is known to produce poor quality graphene.

[0014] Patent Document 5 discloses a hybrid metal / graphene interconnect. Graphene is formed on a metal, such as copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), or palladium (Pd). High temperatures (which are incompatible with CMOS BEOL) are required to grow graphene on a metal surface.

[0015] Patent Document 6 also discloses a hybrid metal-graphene interconnect structure. The hybrid structure includes an interfacial bonding layer between a non-metallic material layer and a graphene layer, or between a metal layer and a graphene layer. The disclosed process is a high-temperature graphene growth process (>700°C), which limits it to only a few memory device applications. The same drawbacks as those mentioned above for the hybrid approach apply.

[0016] Patent Document 7 discloses a method for producing a graphene film. In this method, a catalytic metal film is formed on a substrate. A graphene film is formed on the catalytic metal film. The catalytic metal film is removed using an oxidizing agent. The graphene film is then transferred to the substrate. Such a transfer process is incompatible with CMOS fabrication and can increase the defect density of the film and the overall cost of fabrication.

[0017] Non-Patent Document 12 describes a method for forming MLG graphene interconnects in a single device layer. This method involves diffusing carbon from graphite powder through a nickel catalyst layer. This paper does not disclose any techniques for forming multiple device layers or for connecting MLGs to each other in different device layers. The use of graphite powder makes the process difficult to integrate into commercial CMOS fabrication factories, where extremely small particle counts are a critical requirement. Second, it is difficult to introduce the powder into fully automated equipment.

[0018] Figure 1 shows a conventional dual damascene (DD) process for forming a metal (line)-via-metal (line) structure. This process has been scaled down to line widths of less than 20 nm. This structure suffers from the aforementioned "size effect," which increases self-heating (SH) and reduces electromigration (EM) reliability, thereby limiting the current-carrying capacity of the interconnect. Figures 3A and 3B show that for via lines contacting the M1 layer at the bottom and the M2 layer at the top, current crowding and SH effects occur, primarily due to current redistribution caused by edge contact resistance between the via and the metal line. Furthermore, voids occur during the DD process when filling the metal into large-scale trenches and via holes, exacerbating reliability and variability issues. It should be noted that MLG lines cannot be fabricated using the DD process flow. As explained in the subsequent section, a subtractive etching (SE) process scheme must be used for MLG lines.

[0019] Representative papers that attempt to use graphene ([1]-[3]) and other materials ([4]-[6]) for single-layer interconnects include the following: [1] Non-Patent Document 13, [2] Non-Patent Document 14, [3] Non-Patent Document 15, [4] Non-Patent Document 16, [5] Non-Patent Document 17, and [6] Non-Patent Document 18. Although these processes ([4]-[6]) have achieved marginal improvements in reducing resistivity and improving current-carrying capacity, there remains a need for a practical process for fabricating via-connected multilayer MLGs in a CMOS-compatible manner.

[0020] One publication discusses multilevel MLG with carbon nanotube (CNT) vias [8]. In this structure, the fabrication of carbon nanotube vias requires very high temperatures for the entire process, which are not CMOS compatible. [Prior art documents] [Patent documents]

[0021] [Patent Document 1] U.S. Patent No. 8,952,258 [Patent Document 2] U.S. Patent No. 9,257,391 [Patent Document 3] U.S. Patent No. 9,159,615 [Patent Document 4] U.S. Patent No. 9,202,743 [Patent Document 5] U.S. Patent No. 9,209,136 [Patent Document 6] U.S. Patent No. 9,761,532 [Patent Document 7] U.S. Patent No. 10,079,209 [Non-patent literature]

[0022] [Non-Patent Document 1] K. Banerjee, et al., "Global (interconnect) warming," IEEE Circuits and Devices Magazine, vol.17, no. 5, pp. 16-32,

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[0023] A preferred embodiment provides a via-connected MLG (multilayer graphene) device layer structure. The structure includes an M1 MLG interconnect device layer on a dielectric layer. An interlayer dielectric separates the M1 MLG interconnect device layer. An M2 MLG interconnect device layer is on the interlayer dielectric. Metal vias penetrate the M2 MLG interconnect device layer, the interlayer dielectric, and the M1 MLG interconnect device layer, forming edge contacts across the thickness of both the M1 MLG layer and the M2 MLG layer. The method involves diffusing carbon from a solid-phase graphene precursor through a catalyst layer and applying mechanical pressure at a diffusion temperature to grow MLG directly on a dielectric or metal layer, forming multiple MLG layers. [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 (Prior Art) illustrates a Dual Damascene (DD) process for conventional metal wiring as vias. [Figure 2A] FIG. 2A illustrates a preferred method for forming an MLG-metal via-MLG structure in CMOS circuit fabrication using a subtractive etch process scheme. [Figure 2B]FIG. 2B illustrates a preferred method for forming an MLG-metal via-MLG structure in CMOS circuit fabrication using a subtractive etch process scheme. [Figure 2C] FIG. 2C illustrates a preferred method for forming an MLG-metal via-MLG structure in CMOS circuit fabrication using a subtractive etch process scheme. [Figure 2D] FIG. 2D illustrates a preferred method for forming an MLG-metal via-MLG structure in a CMOS circuit using a subtractive etch process scheme. [Figure 3] Figures 3A and 3B (Prior Art) show the via layout and current density profile for an M1-Via-M2 cross section fabricated by a conventional dual damascene (DD) process, while Figures 3C and 3D (Prior Art) show the via layout and current density profile for an MLG-Via-MLG cross section fabricated by a preferred subtractive etching (SE) process. [Figure 4] 4A and 4B illustrate this method for growing MLGs directly on a metal substrate (such as Cu). DETAILED DESCRIPTION OF THE INVENTION

[0025] The present invention provides multilayer graphene (MLG) and doped multilayer graphene (DMG) structures, interconnects, and fabrication methods for forming MLG and DMG structure interconnects. In preferred embodiment methods, MLG is grown in practical multilayer configurations directly on dielectric (SiO2) substrates at CMOS-compatible temperatures (e.g., 350°C) by pressure-assisted solid-phase precursor synthesis and connected using metal vias to achieve edge contact between the MLG and the interconnect vias in a process that meets all IC processing thermal budget requirements.

[0026] The present invention provides a method for joining two MLGs in an "edge contact" configuration, which is the most preferable method for connecting two MLGs to minimize the interface contact resistance and therefore the overall via resistance, thereby achieving faster signal propagation and clock distribution within the chip and significantly reducing the resistive loss (IR-drop) during on-chip power distribution.

[0027] In the preferred fabrication method, there is no diffusion of carbon through any metal or dielectric, so neither the lines (MLG or doped MLG) nor the metal vias require any diffusion barrier layers, unlike Cu lines which must be completely encapsulated by a high resistivity refractory metal which increases process complexity, cost, and the effective resistivity of the Cu lines.

[0028] The preferred growth technique is currently about 10 mm 2 The results show uniform large area coverage and can be easily scaled up to 8-inch or 12-inch wafers / substrates, demonstrating the great potential this process method has for direct integration into current CMOS processes.

[0029] The preferred method can also be used to grow MLG directly on metal substrates such as Cu (also demonstrated after some modifications), which can be employed to explore the potential benefits of using MLG as a barrier / cap layer for Cu (and other metals), eliminating the need for high-refractory metals that increase the effective resistivity of Cu interconnects along with their cost and process complexity.

[0030] The preferred multilevel MLG interconnect with metal via structures exhibits less than 2% conductivity degradation over 1000 hours at room temperature without encapsulation or barrier layers, and 200 MA / cm above 100°C. 2They exhibit negligible electromigration (EM) (a typical reliability issue for interconnects) under current density stresses of approximately 50 times greater than nanoscale Cu can safely withstand, making this via approach the most reliable process for transistor contacts among all currently available materials and process approaches.

[0031] The significantly higher current-carrying capacity of the preferred multilevel MLG interconnect structure allows for a significant reduction in MLG thickness compared to conventional dual damascene process schemes, leading to lower wiring volume, which can significantly improve IC speed, significantly reduce noise coupling, and significantly reduce switching energy or power consumption. This potential for MLG interconnects to lower power is particularly important, as up to two-thirds of the power consumption in modern microprocessors is due to interconnect capacitance. The preferred interconnect structure of the present invention can enable faster, smaller, lighter, more flexible, more reliable, more energy-efficient, and more cost-effective ICs.

[0032] In the preferred method, MLGs are grown in a multilayer configuration directly on a dielectric (SiO2) substrate at 350°C by pressure-assisted solid-state diffusion and connected using metal vias while meeting the thermal budget requirements of all IC processes.

[0033] The preferred method is to bond the MLG in an "edge contact" configuration, which is the most preferred way to connect to the MLG in order to minimize the interface contact resistance and therefore the overall via resistance, which leads to faster signal propagation and clock distribution within the chip, as well as significantly reduced resistive losses (IR-drop) in on-chip power distribution.

[0034] The preferred method avoids carbon diffusion through any metal or dielectric, and neither the interconnect (MLG or doped MLG) nor the metal vias require any diffusion barrier layers, unlike Cu interconnects, which must be fully encapsulated by a high resistivity refractory metal, which increases process complexity, cost, and the effective resistivity of the Cu interconnects.

[0035] A preferred method is to 2 Uniform and large coverage area of ​​1000 nm is experimentally demonstrated, which can be easily scaled up to 8-inch or 12-inch wafers / substrates, demonstrating that the method can be directly integrated into current state-of-the-art CMOS processes.

[0036] A suitable method (which has been experimentally demonstrated) is to grow MLG directly on a metal substrate such as Cu. One application of this method is to employ MLG as a capping layer for Cu, eliminating the need for a refractory metal, which increases the effective resistivity of the Cu interconnect, along with its cost and process complexity.

[0037] The preferred device structure for multilevel MLG interconnects using metal vias exhibits less than 2% conductivity degradation over 1000 hours at room temperature without encapsulation or barrier layers, and 200 MA / cm above 100°C. 2 They exhibit negligible electromigration (EM) (a typical reliability issue for interconnects) under current density stresses of approximately 50 times greater than nanoscale Cu can safely withstand. Such via structures are well beyond the most reliable current processes for contacting transistors, among all currently available materials and process schemes.

[0038] The preferred multilevel MLG interconnect via structure provides significantly higher current-carrying capacity than conventional structures, which allows for a significant reduction in MLG thickness compared to conventional dual damascene processes, resulting in reduced wiring volume, significantly improving IC speed, reducing noise coupling, and lowering power consumption. In particular, since two-thirds of the power consumption of modern microprocessors is due to wiring capacitance, the present multilevel MLG interconnect via structure can reduce power consumption.

[0039] In a preferred embodiment, different solid-state graphene precursors are used. One solid-state precursor is graphite powder. Another solid-state precursor is graphite slurry. An additional solid-state graphite precursor is an amorphous carbon (a-carbon) layer. Methods employing deposited a-carbon layers can offer significant advantages over graphite powder and graphite slurry for high-volume CMOS fabrication.

[0040] In our experiments, we deposited MLG on SiO2, a preferred and widely used dielectric. However, our method for forming MLG allows for the formation of MLG on any dielectric that can withstand the thermal demands of the process (approximately 350-400°C).

[0041] Preferred embodiments of the present invention will now be described with reference to the experiments and drawings. In view of the general knowledge in the art and the experimental descriptions set forth below, broader aspects of the present invention will be understood by those skilled in the art.

[0042] Figures 2A-2B show a preferred method for growing graphene directly on a dielectric at CMOS processing temperatures, and Figure 2C shows a preferred method for forming an MLG-via-MLG structure with metal vias and edge contacts between two connected MLG layers. The process in Figures 2A-2B reliably grows large-area, uniform, and high-quality MLG in multiple layers, while the process in Figures 2C-2D connects multiple layers with edge-contact metal vias. The uniform MLG can be patterned into interconnect patterns using conventional mask etching techniques. For example, in one experiment, the MLG layer was patterned by oxygen ICP etching using a metal mask, which was then removed by wet etching.

[0043] In FIG. 2A, the first step 20 is to clean a silicon dioxide layer on a silicon substrate. For example, 200 nm of SiO2 will serve as an interlayer dielectric in the MLG-Via-MLG structure to be formed. In step 22, a metal or alloy catalyst is deposited, for example, nickel. Other metals and alloys, such as Co, Fe, Cu, and Co-Ni alloys, can also be used for graphene growth. However, the thickness, quality, and coverage of the resulting graphene are important factors in the selection of the metal catalyst. Ni is the most viable and most preferred choice. In one experiment, approximately 3×10 -6A 100 nm thick Ni layer was deposited by electron beam evaporation at a chamber pressure of 1 Torr. Thicknesses ranging from approximately 50 nm to approximately 200 nm can also be applied. Generally, a thicker metal catalyst layer reduces the resulting MLG layer thickness, while a thinner metal catalyst layer increases the resulting MLG layer thickness (for the same growth time) because carbon atoms must diffuse through the metal catalyst grains and grain boundaries to nucleate at the Ni / SiO2 interface. Low-temperature annealing below 450 °C, e.g., annealing at approximately 350 °C for 2 hours in a H2 / Ar environment, improves the quality of the deposited metal catalyst (Ni). Annealing can be performed in vacuum, Ar, H2, N2, O2, or forming gas; however, the H2 / Ar combination is preferred because the presence of H2 against an inert Ar background helps significantly improve the metal quality (by enlarging the metal grain size). Annealing immediately prior to the actual growth step significantly improves coverage and growth quality. Annealing is preferably performed at the same temperature as other steps to reduce overall process complexity and meet the thermal budget requirements of CMOS BEOL. The next step, step 24, involves depositing a solid-phase graphene precursor. There are three options, as shown in Figure 2A: amorphous carbon, graphene slurry, and graphene powder. The powder can be sprinkled uniformly over the entire wafer to a thickness of approximately 100 μm. Amorphous carbon (approximately 10–15 nm thick) was experimentally deposited using electron beam evaporation, the same technique used to deposit the Ni metal catalyst. Generally, the relationship between the thickness of the amorphous carbon precursor and the thickness of the resulting MLG thin film is a function of the supersaturated carbon concentration in the selected catalyst. A 1:1 ratio between the thickness of the amorphous carbon thin film and the thickness of the resulting MLG is a reasonable guideline. The slurry is a solution of graphite powder in an organic solvent, which is uniformly spread over the wafer and heated to evaporate the organic solvent. The resulting thin film is approximately 10–20 nm thick.

[0044] The process continues at step 26 in FIG. 2B, where the formed graphene precursor is subjected to pressure and temperature sufficient to diffuse carbon through the Ni catalyst to form a graphene layer on the SiO2. By way of example, a mechanical pressure of about 65-80 psi at a temperature of at least about 350°C for about 60 minutes forms about 20 nm multilayer graphene (MLG). The mechanical pressure can be further increased to optimize graphene growth. The minimum temperature for diffusion can be as low as about 200°C. The maximum temperature to achieve diffusion can be as high as about 1000°C. However, CMOS compatibility requires a maximum temperature below 500°C. An oxygen rinse then removes excess graphene precursor in step 28, and the metal catalyst is etched away in step 30, leaving a high-quality graphene layer on the SiO2. A subtractive etch is then performed in step 32 to pattern the MLG interconnects.

[0045] The process in FIG. 2C can be used to fabricate lower MLG layer 40 and upper MLG layer 42 (which can be referred to as M1 and M2), which can be patterned by conventional mask etching techniques. M1 and M2 layers 40 and 42 are formed according to the process in FIGS. 2A-2B directly on dielectric layers, such as SiO2 layers 44 and 46. Plasma-enhanced chemical vapor deposition (PECVD) was used in the experiments to deposit the SiO2, but the dielectric can be formed by any other technique. While a dielectric with uniform coverage and thickness is typical, the method of the present invention is versatile enough to form MLGs on surfaces of any shape. An additional dielectric layer 48 can form part of the interconnect pattern of M2 MLG layer 42. In step 50, dielectric layer 46 is formed as an interlevel dielectric layer, preparing the upper MLG M2 layer 42 as shown in FIGS. 2A-2B, after which the additional dielectric 48 is formed. In step 52, holes 54 are opened through the layers down to the dielectric layer 44. In step 56, metal is deposited in the holes 54 to form vias 58, which advantageously form edge contacts through the full thickness of the lower 40 and upper 42 MLG M1 and M2 layers, respectively.

[0046] Various metals can be used for via 58. Density functional theory (DFT) simulations performed between Co, Ru, and W revealed that they have almost the same edge contact resistance to MLG. However, Co has a higher activation energy and lower resistivity compared to Ru and W, making it a more suitable metal and preferred choice for via 58 in multi-level MLG wiring via structures, as it has a higher resistance to EM (electromigration) and SH (self-heating).

[0047] This edge contact avoids current crowding at the top and bottom contacts (Figures 3A and 3B), as shown in Figures 3C and 3D. This edge contact structure, as shown in Figures 3B and 3D, significantly reduces current crowding and SH effects compared to conventional DD processes, primarily due to current redistribution caused by edge contact resistance between the via and MLG wiring. MLG offers higher conductivity and EM immunity compared to SE-Co and SE-Ru, especially at smaller aspect ratios. Therefore, although the edge contact resistance between the MLG and metal via increases the overall via resistance, experiments have shown that the FO4 delay is invariant to the overall via resistance.

[0048] The quality of the MLG layer and its via performance were experimentally tested. Single-point Raman spectroscopy data showed sharp G and 2D peaks. TEM imaging confirmed uniform, high-quality growth. The top MLG M2 42, fabricated on an underlying interlayer dielectric (ILD) 46, exhibited comparable quality and thickness to the bottom MLG 40, as evidenced by experimentally observed single-point Raman spectra and uniform large-area Raman maps. XPS measurements of the C1s content in the bottom MLG film revealed the correct peak position (1202.3 eV) and atomic composition (approximately 83%) corresponding to C=C sp2 bonds, also observed in conventional CVD-grown MLG, confirming the high-quality growth of solid-phase MLG without the need for the high, CMOS-incompatible temperatures (>800 °C) of CVD-grown MLG.

[0049] Experimental fabrication, consistent with Figures 2A–2C, demonstrated a two-layer SE (subtractive etch)-MLG interconnect structure using Co vias, where the via holes were etched through the wiring and ILD using a single damascene process. The experimental structure had 20 nm thick MLG for both layers. Although unintentional, the use of FeCl3 solution to remove the Ni catalyst in step 30 resulted in surface doping with Fe present on both the top and bottom MLG surfaces, potentially reducing the MLG resistivity. Via resistance measurements indicated that the minimum contact resistance was estimated to be 137 Ω·μm for the 20 nm thick Co-MLG edge contact. This value supports the assertion of partial surface doping of the MLG caused by FeCl3, as it lies between the theoretically estimated (DFT) edge contact resistance values ​​for Co-doped and undoped MLG. Constant current stress tests showed that the resistance increase through the vias was less than 2% over a period of more than 40 hours, indicating negligible EM in the Co vias and / or in the Co-MLG contacts.

[0050] 4A-4B illustrate a preferred method for forming MLG directly on a Cu layer. In step 60, a stack is formed including SiO2 on a silicon substrate, followed by a Cu layer, a thin amorphous carbon barrier layer, a nickel catalyst layer, and a solid-phase graphene precursor, which may be graphite powder, amorphous carbon, or graphite slurry, as shown in FIG. 2A. The thin amorphous carbon layer prevents interdiffusion of the Cu and Ni layers and assists the graphene growth process by acting as an additional source of readily available carbon at the Cu interface, which is completely consumed during MLG growth. Applying mechanical pressure in step 64, as in step 26 in FIG. 2B, causes carbon to diffuse through the Ni catalyst and form a graphene layer on the Cu. After graphene layer formation, cleaning of any remaining graphite or a-carbon on the nickel and nickel etching are performed, similar to steps 28 and 30 in FIG. 2B. Cleaning is performed using O2 plasma to remove any graphite formation on the Ni substrate. The nickel etch was performed using a wet etch with FeCl3 solution to remove the Ni catalyst metal layer, but other material removal processes, including dry etching, can be used. The MLG layer is then etched using a subtractive process, such as an oxygen plasma process, to form the MLG interconnects. The MLG can be doped using various methods to adjust its conductivity.

[0051] Experiments were also conducted to verify the method described in Figures 4A-4B. In these experiments, a 300 nm SiO2 layer was formed on a Si wafer, and then 100 nm Cu, 2 nm amorphous carbon, and 100 nm Ni layers were deposited on top of it by E-beam evaporation. A graphite precursor, such as 100 μm graphite powder, was then uniformly applied across the resulting stack. Raman spectra confirmed the formation of high-quality MLGs grown directly on Cu at approximately 350 °C, and the layered structure observed in TEM images was also verified. As mentioned above, patterned interconnect MLG layers that make edge contact with metal vias were also formed in additional experiments. In this example experiment, the bottom MLG was grown as shown in Figures 2A-2B, then patterned by oxygen ICP etching using a metal mask, which was then removed by wet etching. After defining the contacts and pads (15 nm Ni / 150 nm Au) to connect the bottom MLG, a 200 nm thick SiO2 layer was deposited. The upper MLG is patterned to form an overlapping area with the lower MLG, followed by patterning of the contacts and pads for the upper MLG. Via holes (200 nm to 2 μm wide) are opened using a photoresist mask in three steps: oxygen, CHF3, and oxygen-ICP etching to etch the upper MLG, ILD, and lower MLG, respectively. To fill the via holes, approximately 220 nm thick Co is deposited by thermal evaporation (<100 °C) at a slow deposition rate to ensure complete metal filling. Finally, the ILD above the bottom pad is etched to allow electrical contact. The line / via width can be further expanded using more advanced lithography techniques, as known in the art.

[0052] While particular embodiments of the present invention have been shown and described, it should be understood that other modifications, substitutions, and alternatives will be apparent to those skilled in the art, and such modifications, substitutions, and alternatives can be made without departing from the spirit and scope of the present invention, which should be determined from the appended claims.

[0053] Various features of the invention are set forth in the following claims.

[0054] [Note] [Appendix 1] 1. A method for forming MLG (multilayer graphene) device layers connected with vias directly on a dielectric or metal layer at CMOS (complementary metal oxide semiconductor) compatible process temperatures, comprising: providing a dielectric or metal layer; depositing a catalytic layer of a metal or alloy on said dielectric or metal layer; depositing a solid-phase graphene precursor on the catalyst layer; diffusing carbon from the graphene precursor through the catalyst layer and depositing MLG on the dielectric or metal layer by applying a diffusion pressure at a diffusion temperature to form an MLG layer; removing the catalyst layer; depositing an interlayer dielectric over the M1 MLG layer; forming an M2 MLG layer on the interlayer dielectric via depositing the catalyst layer, depositing the solid-phase graphene precursor layer, and diffusing the carbon; forming a via hole through the M2 MLG layer, the interlayer dielectric, and the M1 MLG layer; depositing a via metal in the via hole to form an edge contact across the thickness of the M1 MLG layer and the M2 MLG layer; A method comprising:

[0055] [Appendix 2] The diffusion pressure is about 65-80 psi, and the diffusion temperature is at least about 200°C. 2. The method according to claim 1,

[0056] [Appendix 3] The graphene precursor is graphite powder. 3. The method according to claim 1 or 2,

[0057] [Appendix 4] The graphene precursor is amorphous carbon. 3. The method according to claim 1 or 2,

[0058] [Appendix 5] The graphene precursor is a graphite slurry. 3. The method according to claim 1 or 2,

[0059] [Appendix 6] annealing the catalyst at a temperature less than 500°C prior to depositing the solid-phase graphene precursor. 6. The method according to any one of claims 1 to 5.

[0060] [Appendix 7] The via metal is one of Co, Ru, and W. 7. The method according to any one of claims 1 to 6.

[0061] [Appendix 8] The via metal is Co. 8. The method according to claim 7,

[0062] [Appendix 9] The catalyst layer is Ni. 9. The method according to any one of claims 1 to 8.

[0063] [Appendix 10] the dielectric layer and the interlayer dielectric comprise SiO2; 10. The method according to any one of claims 1 to 9.

[0064] [Appendix 11] 1. A method for forming MLG (multi-layer graphene) on a metal surface, comprising: forming an amorphous carbon barrier layer on the metal surface; depositing a metal or alloy catalyst layer on the amorphous carbon barrier layer; depositing a solid-phase graphene precursor on the catalyst layer; depositing MLG on the metal surface by diffusing carbon from the graphene precursor through the catalyst layer and applying a diffusion pressure at a diffusion temperature; A method comprising:

[0065] [Appendix 12] the metal surface is copper; 10. The method of claim 9,

[0066] [Appendix 13] The catalyst layer is nickel. 11. The method according to claim 9 or 10,

[0067] [Appendix 14] patterning and doping the M1 MLG and patterning and doping the M2 MLG layer; 2. The method according to claim 1,

[0068] [Appendix 15] A MLG (multi-layer graphene) device layer structure connected using vias, an M1 MLG interconnect device layer on the dielectric layer; an interlayer dielectric isolating the M1 MLG interconnect device layers; an M2 MLG interconnect device layer on the interlayer dielectric; a metal via through the M2 MLG interconnect device layer, the interlayer dielectric, and the M1 MLG interconnect device layer, the metal via forming an edge contact across the thickness of both the M1 MLG layer and the M2 MLG layer; 1. An MLG device layer structure comprising:

[0069] [Appendix 16] the M1 MLG layer and the M2 MLG layer are patterned; 16. The device layer structure of claim 15.

[0070] [Appendix 17] the dielectric layer and the interlayer dielectric comprise SiO2; 17. The device layer structure according to claim 15 or 16,

[0071] [Appendix 18] the M1 MLG layer and the M2 MLG layer are doped; 18. The device layer structure of any one of claims 15 to 17,

Claims

1. 1. A method for forming a via-connected MLG (multi-layer graphene) device layer directly on a dielectric or metal layer at CMOS (complementary metal oxide semiconductor) compatible process temperatures, comprising: (a) providing a dielectric or metal layer as a metal or dielectric surface; (b) depositing a catalytic layer of a metal or alloy on the dielectric or metal layer; (c) depositing a solid-phase graphene precursor on the catalyst layer; (d) diffusing carbon from the solid-phase graphene precursor through the catalyst layer and depositing MLG on the dielectric or metal layer via applying a diffusion pressure at a diffusion temperature to form an M1 MLG layer; (e) removing the catalyst layer; (f) depositing an interlayer dielectric over the M1 MLG layer; (g) forming an M2 MLG layer on the interlayer dielectric via depositing the catalyst layer, depositing the solid-phase graphene precursor, and diffusing the carbon; (h) forming a via hole through the M2 MLG layer, the interlayer dielectric, and the M1 MLG layer; (i) depositing via metal in the via hole to form an edge contact through the thickness of the M1 MLG layer and the M2 MLG layer; Including, The method wherein steps (b) through (i) are carried out at a temperature of at least about 200°C and less than 450°C.

2. the diffusion pressure is about 65-80 psi and the diffusion temperature is at least about 200°C; 2. The method of claim 1 .

3. The solid-phase graphene precursor is graphite powder.

2. The method of claim 1 .

4. The solid-phase graphene precursor is amorphous carbon.

2. The method of claim 1 .

5. The solid-phase graphene precursor is a graphite slurry.

2. The method of claim 1 .

6. annealing the catalyst layer at a temperature less than 500°C prior to depositing the solid-phase graphene precursor.

2. The method of claim 1 .

7. the via metal includes one of Co, Ru, and W; 7. The method according to any one of claims 1 to 6.

8. The via metal is Co.

8. The method of claim 7.

9. The catalyst layer is Ni.

7. The method of claim 6.

10. The dielectric layer and the interlayer dielectric are made of SiO ２ Including, 10. The method of claim 9.

11. the dielectric or metal layer is copper; 10. The method of claim 9.

12. patterning and doping the M1 MLG layer, and patterning and doping the M2 MLG layer; 2. The method of claim 1 .

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