SQUID stack pulse height bias level sensor for reciprocal quantum logic

Abstract

A power amplifier based reciprocal quantum logic (RQL) bias level sensor is used to measure and / or calibrate bias parameters of an AC bias signal and / or a DC bias signal supplied to an RQL circuit. The bias signal may include an output amplifier output bias current. The bias level sensor includes a stack of DC SQUIDs, with inputs supplied from the outputs of respective Josephson transmission lines (JTLs) that transformer-couple the SQUIDs. By stepping the relative strengths of the bias taps of the JTLs or the critical currents of the Josephson junctions in the DC SQUIDs, the output voltage signal of the bias level sensor can indicate whether the supplied bias value is an improved or optimized bias value when varied over a range. The outputs of two such bias level sensors driven by I and Q clocks can be compared to adjust the AC bias amplitude of the clocks. The relative clock phases can be adjusted as well.

Description

[Technical Field]

[0001] The present disclosure relates generally to superconducting circuits, and more particularly to a SQUID stack pulse height bias level sensor for reciprocal quantum logic. [Background technology]

[0002] In the field of digital logic, the well-known and highly developed complementary metal-oxide semiconductor (CMOS) technology is widely used. As CMOS begins to mature as a technology, interest is growing in alternative technologies that may offer higher performance in terms of speed, power consumption, computational density, and interconnect bandwidth. As an alternative to CMOS technology, single flux quantum (SFQ) circuits utilize superconducting Josephson junctions (JJs), which have typical signal powers of about 4 nanowatts (nW), typical data rates of 20 gigabits per second (Gb / s) or higher, and operating temperatures of about 4 Kelvin.

[0003] A family of SFQ circuits known as reciprocal quantum logic (RQL) uses one or more resonator networks and / or bias lines to distribute one or more bias signals. The bias signals serve to bias the JJs within the logic gates of the RQL circuit and the Josephson transmission lines (JTLs) found within the gates of the RQL circuit or as connecting lines between gates for propagating SFQ signals within the RQL circuit. The AC bias signals can serve as one or more global clock signals, which can help eliminate clock jitter, such as that exhibited by prior superconducting circuit technologies such as rapid single flux quantum (RSFQ) logic. For example, RQL can utilize a multiphase clock having an in-phase (I) clock signal and a quadrature (Q) clock signal that is approximately 90° out of phase with the I clock signal. Summary of the Invention

[0004] An exemplary RQL bias level sensor includes a stack of multiple direct current superconducting quantum interference devices (DC SQUIDs) coupled to each other between a first output terminal and a second output terminal of the RQL bias level sensor. Each DC SQUID in the stack includes a superconducting loop including two JJs. Each DC SQUID in the stack is transformer-coupled to a respective JTL and receives magnetic flux from the output of the respective JTL. The RQL bias level sensor is configured to output a voltage signal between the first output terminal and the second output terminal that is variable depending on the value of at least one bias parameter (AC bias amplitude or DC bias value) of the bias signal supplied to the RQL bias level sensor.

[0005] An exemplary system includes first and second instances of the RQL bias level sensor described above. The output of the first instance is coupled to a first input of bias parameter adjustment logic. The output of the second instance is coupled to a second input of the bias parameter adjustment logic. The bias parameter adjustment logic has a first output configured to direct an adjustment to a bias parameter of a first clock signal provided to the RQL system. The bias parameter adjustment logic has a second output configured to direct an adjustment to a bias parameter of a second clock signal provided to the RQL system, the second clock signal being approximately 90 degrees out of phase with the first clock signal.

[0006] An exemplary method for adjusting an RQL bias signal includes driving a first RQL bias parameter sensor with a first AC clocked bias signal of the RQL system and driving a second RQL bias parameter sensor with a second AC clocked bias signal of the RQL system. The second AC clocked bias signal is approximately 90° out of phase with the first AC clocked bias signal. Outputs of the first and second sensors are compared. Based on comparing the outputs of the first and second sensors, one or both of the AC amplitude of the first AC clocked bias signal or the AC amplitude of the second AC clocked bias signal are adjusted. The method may proceed to driving a third RQL bias parameter sensor with a third AC clocked bias signal of the RQL system. The third AC clocked bias signal is approximately 45° out of phase with the first AC clocked bias signal. Outputs of the first and third sensors may be compared. Based on comparing the outputs of the first and third sensors, one or both of the phase of the first AC clocked bias signal or the phase of the second AC clocked bias signal may be adjusted. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram of an exemplary RQL bias level detection and adjustment system. [Figure 2A] FIG. 10 is a block diagram of an exemplary set of RQL bias level sensors configured within a JTL-based RQL scan register bias level sensor wrapper for serial output. [Figure 2B] FIG. 1 is a block diagram of an exemplary set of RQL bias level sensors configured within a JTL-based bias level sensor wrapper for parallel outputs. [Figure 2C] FIG. 1 is a block diagram of an exemplary set of RQL bias level sensors configured within a ring oscillator wrapper. [Figure 3] 1 is a graph of an exemplary margin shmoo plot of nominal AC and DC bias level operating margins for an operational RQL circuit and RQL bias level sensor. [Figure 4A] 10 is a graph of an example margin shmoo plot of AC and DC bias level operating margins for an operational RQL circuit and RQL bias level sensor showing the effect of varying the AC amplitude of the applied bias signal. [Figures 4B-4D] 4B is a one-dimensional time plot of output pulse reception for a bias level sensor wrapper similar to that of FIG. 2A, showing the effect of varying the AC amplitude of the applied bias signal as shown in FIG. 4A. [Figure 5A] 10 is a graph of an example margin shmoo plot of AC and DC bias level operating margins for an operational RQL circuit and RQL bias level sensor showing the effect of changing the DC value of the applied bias signal. [Figure 5B-5D] 5B is a one-dimensional time plot of output pulse reception for a bias level sensor wrapper similar to that of FIG. 2A, showing the effect of varying the DC value of the applied bias signal as shown in FIG. 5A. [Figure 6] FIG. 2B is a circuit diagram of an exemplary sampler stage configured for use in a bias level sensor such as that shown in FIG. 2A, the sampler stage including a JTL with a bias supplied by a tap. [Figure 7] FIG. 2B is a block diagram of an example throttling logic as shown in FIG. 2A. [Figure 8] 7 is a block diagram of an example shift register including four instances of the example sampler stage of FIG. 6 that can be used as a bias level sensor as in FIG. 2A. [Figure 9] 7 is a block diagram of an example shift register including three instances of the example sampler stage of FIG. 6 that can be used as a bias level sensor as in FIG. 2A. [Figure 10] 7 is a block diagram of an example shift register including one instance of the example sampler stage of FIG. 6 that can be used as a bias level sensor as in FIG. 2A. [Figure 11]7 is a block diagram of an example shift register including one instance of the example sampler stage of FIG. 6 that can be used as a bias level sensor as in FIG. 2A. [Figure 12] FIG. 10 is a block diagram of an exemplary specific phase bias level sensor for a Q-clock. [Figure 13] FIG. 10 is a block diagram of an exemplary phase-specific bias level sensor for an I-clock. [Figure 14] FIG. 19 is a block diagram for explaining the symbols used in FIGS. 12, 13, 16, and 18. [Figure 15] FIG. 19 is a block diagram for explaining the symbols used in FIGS. 12, 13, 16, and 18. [Figure 16] FIG. 1 is a block diagram of an exemplary I-clock specific (Q-clock independent) bias level sensor. [Figure 17] 19 is a graph of an exemplary AC and DC bias margin shmoo plot for the specific I-clock (Q-clock independent) bias level sensor of FIGS. 16 and 18. FIG. [Figure 18] FIG. 10 is a block diagram of another exemplary specific I-clock (Q-clock independent) bias level sensor. [Figure 19] 10 is a graph of an exemplary minimum operational AC bias for a particular I-clock and a particular Q-clock bias level sensor as a function of Q-clock phase deviation from 90°. [Figure 20] FIG. 2 is a block diagram of an exemplary phase sampler. [Figure 21] FIG. 21 is a block diagram illustrating the symbols used in FIG. 20. [Figure 22] 21 is a graph illustrating an example clock amplitude versus phase error for the example phase sampler of FIG. 20. [Figure 23] 21 is a graph illustrating an example minimum operating bias signal AC amplitude for the phase sampler of FIG. 20. [Figure 24] FIG. 1 is a block diagram of a portion of a phase-mode logic (PML) bias level sensor. [Figure 25]2B is a block diagram of an exemplary pulse generator-based bias level sensor as shown in a portion of a wrapper similar to that of FIG. 2A. [Figure 26A] FIG. 1 is a block diagram of an exemplary configuration of a bias level sensor disposed within a DC SQUID-based bias level sensor. [Figure 26B] FIG. 1 is a block diagram of an example DC SQUID-based output amplifier configured as a sensor for measuring the level of an externally supplied output bias current IBIASOUT relative to an optimum level. [Figure 27A] FIG. 1 is a block diagram of an exemplary feedback system for sensing and tuning the AC amplitude of the I and Q clocks. [Figure 27B] FIG. 1 is a block diagram of an exemplary feedback system for detecting and tuning phase errors in I and Q clocks. [Figure 28] FIG. 1 is a flow diagram illustrating an exemplary method for adjusting or optimizing AC and DC bias points using bias level sensors integrated on the RQL IC. [Figure 29] FIG. 25 is a flow diagram illustrating an exemplary method for adjusting or optimizing the AC (or, with modifications, DC) bias point using a PML shift register similar to that of FIG. 24 integrated on an RQL IC. [Figure 30] 10 is a flowchart illustrating an exemplary method for adjusting or optimizing the relative phase difference between the I-clock and Q-clock using a phase-sensitive bias level sensor integrated on the RQL IC. [Figure 31] FIG. 10 is a flow diagram illustrating an exemplary method for adjusting or optimizing the AC bias amplitude of the I and Q clocks and the phase difference between the I and Q clocks on an RQL IC. DETAILED DESCRIPTION OF THE INVENTION

[0008] The computational functions of the RQL system may be performed at least in part by operable digital circuitry, which may include logic gates and JTLs. The operable circuitry includes JJs biased by one or more bias signals of the RQL system, which may include both AC and DC bias signals. The AC signals may serve as one or more clocks for the RQL system to synchronize data and / or provide a time-based flow of the RQL system's logic functions. The AC bias signals may provide clocks of different phases, such as a 0° clock or a 180° clock provided by an I-clock resonator, or a 90° clock or a 270° clock provided by a Q-clock resonator. The operational circuitry may operate correctly only within certain margins of various operational parameters. Some of these operational parameters are related to the bias signals (e.g., clocks) provided to the RQL system. For example, if the DC bias level of a clock is too high or too low, falling outside the DC bias operating margins of gates or JTLs in the RQL system, the RQL system may malfunction. As another example, if the amplitude of the AC bias signal of a clock is too large or too small and falls outside the AC bias operating margin of a gate or JTL in an RQL system, this may be another cause of malfunction of the RQL. As yet another example, if the relative phase difference between different clocks, such as the I clock and the Q clock, is too large or too small and falls outside the clock phase difference operating margin of a gate or JTL in an RQL system, this may be another cause of malfunction of the RQL.

[0009] Magnetic flux, the time integral of voltage, is the primary operating parameter controlling the function of RQL logic circuits, even when applied to conventional inductors or JJs. Due to manufacturing process variations and other factors, there can be significant variations in the AC and DC magnetic flux generated by the resonators and the tap transformers coupled to them, which provide bias signals to RQL logic circuits. Variations in the inductors, dielectrics, and JJs that comprise operating RQL circuits cause variations in the amount of AC and DC magnetic flux required by those circuits. Temperature changes, as well as aging, can affect the performance of RQL circuits. Given these changes and variations, the ideal values ​​of bias parameters such as AC amplitude, DC value, and gate flux bias current may not be the same for all RQL logic gates in a system.

[0010] While the clock signal or signals provided to an RQL system may be generated by a function generator circuit operating at approximately room temperature (approximately 300 K), the system's RQL operating circuitry may reside in a cryogenically cooled space operating at a much lower temperature, e.g., approximately 4 K or less, and may be several meters away from the function generator circuitry. Due to the low operating temperature and thermal isolation requirements of the RQL system, it may not be possible to directly probe the integrated circuit (IC) on which the RQL system is implemented to ascertain bias signal parameters (such as DC levels, AC amplitudes, and relative phase differences of AC clock signals) at various points on the IC to check that the bias signal parameters actually supplied to the RQL operating circuitry are those intended to be supplied or are otherwise within the operating margins of an operational circuit.

[0011] Measurements of supplied bias levels, e.g., AC voltages and DC currents supplied on RQL integrated circuits, as well as other bias parameters such as the relative phase difference between different bias signals, can provide the insight needed to adjust bias levels generated at bias sources outside the cooled space to ensure that the delivered bias levels and other parameters as delivered to an operational RQL circuit within the cooled space are consistent with optimal values ​​within, e.g., at the center of, the operating margins of the operational RQL circuit. The measurement results for each RQL IC, or a portion of each IC, can be used to adjust bias levels to improved, optimal, or near-optimal values ​​to provide more reliable performance of the operational RQL circuit.

[0012] Thus, bias level sensors can be provided as sensing circuits fabricated on an RQL IC along with the operational circuitry of the RQL system. The bias level sensors can sense signal parameters of bias signals supplied to the operational circuitry at various locations on the IC. The sensed signal parameters can be used in manual or automatic feedback loops to inform adjustments to the bias signals supplied to the RQL system so that the operational circuitry of the RQL system is supplied with a bias that remains within the operational margins of the operational circuitry. In some examples, multiple bias level sensors can be embedded within logic circuits, referred to herein as wrappers, which activate the bias level sensors by interrogating them with, for example, a sampling signal, and read the results. By way of example, the sensors can be incorporated into RQL scan registers or JTL testbed registers.

[0013] In some examples, the bias level sensing circuit architectures and related methods described herein enable the determination of improved, near-optimal, or optimal bias levels by observing pulses generated by an ensemble of bias level sensing circuits. Exemplary bias level sensing circuits, referred to as samplers, function as a proxy for the operational RQL circuit. The samplers may be configured as a whole such that, when the elements of the operational RQL circuit are at their optimal bias points, certain portions of the samplers or certain individual ones of the samplers operate to transmit or generate bias level sensing output pulses as expected, while other samplers do not operate to transmit or generate bias level sensing output pulses as expected. Which samplers and how many samplers generate bias level sensing output pulses reveal information about the current bias of the operational RQL circuit, e.g., the current bias point of the operational RQL circuit. Digital logic may be utilized to count, reorder, and / or sort the bias level sensing output pulses, and search and optimization algorithms may be used to adjust bias signal generation parameters (e.g., bias levels) to improve the delivered bias levels and / or move the operating point closer to the optimal value.

[0014] The bias level sensor's operating margin offset from the operational RQL circuit's nominal operating margin may, in some instances, allow bias level measurements to be made without shutting down the operational RQL circuit. As an example, the bias transformer flux may be altered from its normal level to ensure that the bias sensing circuit provides a useful output without having to move the bias level beyond the range in which the operational RQL circuit functions. One way to alter the bias transformer flux is to provide a bias level sensor with a transformer configured to generate a greater or lesser magnetic flux than normal by altering its mutual inductance with the clock resonator. Another way to alter the bias transformer flux is to insert more or less inductance than nominal between the transformer and the bias level sensor. As another example, a dedicated bias sensing circuit may be configured to start or stop operating at levels within the logic circuit's operating range. This may be done by increasing or decreasing the size of JJs and inductors in the circuit. When the performance of the bias transformers and their associated clock resonators is paramount, it may be preferable to drive the JJs directly from standard transformers, since the variability of the JJs adds only to the variability of the resonators and transformers. When the need for logic circuitry on the outputs of the clock resonators and bias transformers is noted, it may be advantageous to utilize sensing circuitry that differs minimally from the operational circuitry. This latter objective can be achieved by inserting additional inductance in series with the transformers, while maintaining the transformers and the remaining logic sensing circuitry in a standard configuration.

[0015] The operating margin offset can vary from sensor to sensor in a population of bias level sensors, and these sensors can be aggregated into a wrapper circuit configured to provide sampling inputs and outputs for bias level measurement. Variation in the operating margin offset between sensors can be intentionally introduced by design (staging), for example, to cover a range around the nominal operating point of the operational RQL circuit. In such a case, the population of bias level sensors can be configured so that a certain percentage of the bias level sensors (e.g., approximately half of the bias level sensors) generate pulses when the operational logic is optimally biased with respect to AC amplitude. Therefore, the AC amplitude bias level required by the operational RQL circuit can be determined by counting the pulses generated by the population. In another example, the spread in the operating levels of the bias level sensors caused by manufacturing process variations can be used to provide a pulse count detection output substantially equivalent to that using the above-described staged sensors, without the intentional staging of the operating margin offset of the bias level sensors. The reason for this is that when the operational circuit is optimally biased, if the bias on the sensor is such that the sensor is near its functional limit, even without design for intentionally staggering the sensor's margin, the operational RQL circuit will be near its optimal bias condition when approximately half of the bias level sensors are biased within their own operating margin, and therefore will generate a sense pulse when interrogated with a sample signal via the wrapper circuit.

[0016] FIG. 1 illustrates an exemplary RQL bias level sensing and adjustment system 100. An operational RQL circuit 102, which may include a JTL and logic gates, along with one or more associated clock resonators 104, may be fabricated as a chip on an IC 106, and the chip may be enclosed in a cryogenically cooled space configured to reduce the RQL operating temperature to, for example, low single-digit degrees Kelvin or below. As used herein, the term “operational RQL circuitry” refers to the logic and associated infrastructure circuitry used to perform the useful computational operations for which the RQL IC 106 or system is designed, and is distinct from circuitry 118 on the RQL IC 106 used to perform sensing of parameters related to the bias signal supplied to the RQL IC 106. Bias level sensors and wrappers 118 may be spatially distributed on the IC 106 (e.g., throughout the space on the IC occupied by the operational RQL circuitry) to improve bias level measurement accuracy.

[0017] The operational circuit 102 is coupled (e.g., inductively coupled) to one or more clock resonators 104 via multiple taps 108 to provide an AC bias to the operational circuit 102. The operational circuit may also be coupled to multiple DC bias lines 124 to provide a DC bias to the operational circuit 102. In some examples, the DC bias lines 124 may be configured to circulate around the clock resonator 104 to control the amount of DC bias applied to the operational RQL circuit 102 and / or the bias level sensor 118. In some examples, each bias tap 108 or 120 may have an AC transformer coupled to one or more ribs of the clock resonator 104, and another transformer may be coupled in series to the DC bias lines 124. Outside the cooled space, a bias signal generator 110 (or multiple bias signal generators, e.g., different signal generators for providing an I clock bias signal, a Q clock bias signal, and various DC bias signals) may generate one or more clock signals, such as an I clock 112 and a Q clock 114, for supply to the operational circuit 102 via a clock resonator 104 and associated tap 108 within the cooled space. The one or more bias signal generators 110 may also generate a DC bias signal for supply to the operational circuit 102 on the IC 106 via a DC bias line 124. The one or more clock signals and / or DC bias signals generated by the clock signal generator 110 may be based on different bias parameters 116, which may be in the form of adjustable or variable settings provided to or stored in the bias signal generator 110. Such bias parameters may include, by way of example, the clock frequency, the AC amplitude of the generated AC clocks (e.g., the I and Q clocks), or one or more DC values ​​of the generated DC bias, and the phase difference between the Q and I clocks at the time of clock generation (which may nominally be approximately 90°, but in some cases may not be exactly 90°).

[0018] Additionally, the bias level sensor 118 may be fabricated on the same IC 106 as the operational RQL circuit 102 and configured to sample one or more bias signals (AC clock signals and / or DC bias signals) provided by one or more resonators 104 via a number (N) of sampling taps 120 and / or provided via a DC bias line 124. The bias level sensor may be configured within a wrapper, which may be used to introduce sampling signals to the bias level sensor 118 and output signals based on the sampling signals indicative of measurements of various clock parameters obtained by the bias level sensor. Such parameters may include any or all of the above-mentioned parameters (parameters 116) used by the clock signal generator 110 to generate clock signals outside the cooled space. The output of the bias level sensor and / or associated sensor wrapper 118 may be used to adjust the parameters provided to the clock signal generator 110 via a feedback loop 122, thereby ensuring that the AC clock and / or DC bias signals provided in the operational RQL circuit 102 provide biases that meet the margin requirements of the operational RQL circuit 102. In some examples, the RQL bias level detection and adjustment system 100 can provide bias feedback and adjustment without requiring the operational RQL circuit 102 to be deactivated or otherwise disabled.

[0019] FIG. 2A shows an example configuration 200 of RQL bias level sensors 202-212 wrapped within a JTL-based RQL scan register bias level sensor wrapper, which is used to provide a serial output instead of the otherwise parallel output from a large number of bias level sensors. The bias level sensors 202-212, also referred to herein as samplers, can be thought of as residing on rungs of a ladder formed by the sensor wrappers. One such rung is labeled 214 in FIG. 2A. The rails of the ladder can be formed by JTLs 216-238, shown as triangles in FIG. 2A, or other circuitry configured to propagate SFQ pulses through the wrapper structure with inter-run propagation delays. While the example in FIG. 2A is shown as having one rail JTL between each ladder rung, each JTL 216-238 can be configured with one or as many repeating RQL JTL circuit structures as desired to generate SFQ signal propagation delays of one or many AC clock cycles.

[0020] The bias level sensors 202-212 can take many different forms and can be configured to measure any of many different parameters, including AC bias signal amplitude, DC bias value, and inter-clock phase. Depending on the form of the bias level sensors 202-212, the stage may include suppression logic (SL) 240-250 configured to prevent the assertion of multiple output pulses from propagating from the stage if the associated sampler is in a condition that causes it to spontaneously invert due to a manufacturing defect or excessive bias. In some examples, the suppression logic 240-250 may be omitted on some or all stages of the wrapper. The wrapper may also include an input transformer 252 configured to provide the wrapper with a sample signal consisting of at least one input SFQ pulse supplied from a positive input node INP and a negative input node INN. The wrapper may also include an output amplifier 254 configured to output a voltage signal between a positive output node OUTP and a negative output node OUTN. The output amplifier 254 may take the form of, for example, a binary vine tree (not shown) of JTLs configured to split the input SFQ signal to feed multiple stacked DC SQUIDs (e.g., four DC SQUIDs) arranged as a voltage adder.

[0021] In the exemplary configuration 200 of FIG. 2A , a sample signal provided as an SFQ pulse via input transformer 252 propagates along the top rail from the proximal end of the wrapper ladder to the distal end, branching along the ladder's stages to generate multiple time-separated output voltage pulses at the ladder output between output nodes OUTP and OUTN. Because each rail JTL 216-238 generates an inter-stage propagation delay of at least one AC clock cycle, the output pulses are spaced apart in time, with earlier arriving output pulses having propagated through more proximal stages of the wrapper ladder (stages closer to the input / output end of the wrapper ladder) and later arriving output pulses having propagated through more distal stages of the wrapper ladder (stages further from the input / output end of the wrapper ladder). Exactly how many output pulses are generated for a given sample input pulse depends on the number of samplers 202-212 functioning with the supplied bias signal(s) within the operating margins of the individual samplers 202-212. As will be described in more detail below, in some examples, the samplers 202-212 may include, for example, an AC bias amplitude X AC and a DC bias value X DC , or clock phase difference X phase The "X" in this nomenclature refers to a multiplier of the nominal bias level. For example, if the nominal bias level is 0.2 V, an actual applied bias level of 0.22 V would have an X of 1.1 (110%). In other examples, the sensing system may rely on manufacturing process variations to provide samplers 202-212 with wide (varying over a range) margins without intentionally designed in stepped settings.

[0022] In some examples, such as the example 200 shown in FIG. 2A, the first and last stages (the most proximal and most distal stages) of the wrapper ladder can be standard bias JTLs 256, 258 (without the self-inductance and / or mutual inductance correction of the sampler stage 600 of FIG. 6) so that the first and last pulses provided at the wrapper output represent the margin of a standard device for comparison with the margin of the samplers 202-212. The pulses generated by the standard bias JTLs 256, 258 provide pulses that serve to indicate the beginning and end of a pulse train generated when an input pulse is provided to the INP / INN. In other examples, not shown, additional standard JTL stages can be provided at other stage locations scattered along the wrapper ladder. Logic circuitry, e.g., room-temperature semiconductor logic (not shown), can evaluate the output of each sampler 202-212 individually, or the total number of functional samplers (each represented by its own pulse) can be used as a measure of the overall bias of the sensing system. As will be explained in more detail below, by introducing a gradation in the bias level sensed by the bias level sensors 202-212 contained in the stages of the RQL scan register 200, an output is generated that quantifies or digitizes the sensed bias parameter by generating a number of output pulses in the output pulse stream that is proportional to the sensed bias parameter, or by generating output pulses whose output timing is indicative of the sensed bias parameter.

[0023] FIG. 2B shows an example configuration 260 of RQL bias level sensors 262-272 arranged with parallel outputs. The configuration 260 is similar to the RQL scan register configuration 200 of FIG. 2A, except that the outputs are provided in parallel rather than serially. The parallel output configuration 260 can also include suppression logic (SL) 280-290 configured to prevent the assertion of multiple output pulses from propagating from each output if the associated sampler is in a condition that causes it to spontaneously flip due to a manufacturing defect or excessive bias. Each bias level sensor 262-272 can be located at a different location on the RQL IC 106 and can be tapped to one or more bias resonators 104 at different points along the resonator(s) 104 via a bias coupling transformer (not shown in FIG. 2C). An advantage of the serial output configuration of FIG. 2A over the parallel output configuration of FIG. 2B is that the configuration of FIG. 2A can, in some instances, conserve I / O on the RQL IC 106. In some examples, the parallel outputs OUTA-OUTZ of FIG. 2B may be provided to built-in self-test (BIST) readable registers implemented on the RQL IC 106 for storage and later retrieval in a serial or parallel manner.

[0024] FIG. 2C shows an example configuration 290 of bias level sensors (each labeled BLS) arranged as a ring oscillator. The number of bias levels in the ring oscillator can be arbitrarily large. The output of one bias level sensor serves as the sample signal input for the next bias level sensor in the ring. Each bias level sensor can be located at a different location on the RQL IC 106 and can be connected to one or more bias resonators 104 at different points along the resonators 104 via bias coupling transformers (not shown in FIG. 2C). Although not shown in FIG. 2C, the bias level sensors in the ring 290 can be interspersed with conventional JTLs on the ring to facilitate propagation of SFQ pulses between the bias level sensors in the ring.

[0025] In the ring configuration 290 of FIG. 2C, an initial sampling assertion signal (SFQ pulse or reciprocal pulse pair) can be provided on the input RINGIN. The sampling pulse or pulse pair can propagate indefinitely within the ring 290 as long as all of the bias level sensors are operational (as long as the provided bias point is within the operational region of all bias level sensors in the ring). If the bias parameters are adjusted such that the provided bias parameters are outside the operational region of any one bias level sensor in the ring, the entire ring "breaks" and the sampling signal no longer propagates within the ring, but instead stops at the first non-operating bias level sensor it encounters. The continued operation of the ring can be confirmed through the output RINGOUT; in full ring operation, it generates an SFQ pulse stream (or a stream of reciprocal pulse pairs) at a rate related to the size of the ring (one output pulse or pulse pair is generated for each rotation of the sample pulse within the ring), and stops outputting when the ring is deactivated due to a bias parameter adjustment. As explained in more detail below, X AC Parameter, X DC parameters, and X phase The parameters can be scanned (iteratively adjusted) in an optimization procedure to find the minimum X that keeps the ring oscillator functioning to produce an output at RINGOUT. AC The level provides an optimal bias for the operational RQL circuit 102. In some examples, more than one input sample pulse at a time can be supplied to the operational ring, for example, with multiple pulses separated in time, resulting in an increased frequency of output pulses.

[0026] 2A-2C, the bias level sensor may be a JTL-based bias level sensor as described with respect to FIGS. 6, 8A, 9A, 10A, 11A, 12, 13, 16, and 18, a PML flip-flop-based bias level sensor as described with respect to FIG. 25, a pulse generator-based bias level sensor as described with respect to FIG. 25, or other types of bias level sensors suitable for arrangement in a series configuration, a parallel configuration, or a ring output configuration. Different bias level sensors in the same arrangement may be arranged in series, parallel, or ring output configurations. AC , X DC , X phase , or other bias parameters.

[0027] The combined operating margins of an RQL circuit can be described by a shmoo plot. For example, the AC and DC operating margins can be described by a two-dimensional shmoo plot. Graph 300 of FIG. 3 shows a first exemplary shmoo plot 302 representing the nominal AC and DC bias level operating margins for an operating RQL circuit 102 and a second exemplary shmoo plot 304 representing the average of the AC and DC bias level operating margins 304 for the RQL bias level sensors (e.g., samplers 202-212). The operating margin 302 of an operating RQL circuit is expressed as X DC , X AC When expressed in space, the lower bound or X ACmin , where the amplitude of the AC clock is minimized in each margin shmoo plot 302. ACmin ) is the X of the sampler margin shmoo plot DC , X AC Since it is a unique point in space, it is x with respect to the sampler AC and X DCWithin the center of the nominal margin shmoo plot 302 (e.g., the centroid or geometric center of the nominal margin shmoo plot 302), the X DC , X AC There exists an optimal bias point 306 for a working RQL circuit that is a unique point in space. A sampler (e.g., samplers 202-212) is a circuit that achieves a lower bound (X) on the average of the sampler's margin shmoo plot 304, as shown in FIG. ACmin ) can be designed and positioned to be in the center of the nominal margin shmoo plot of the operating RQL circuit 102 at the optimum bias point 306.

[0028] One or more parameters of the bias signal (e.g., clock, DC bias) provided to the operational RQL circuit 102 (e.g., via one of the input lines 112, 114, 124 of FIG. 1), such as DC value or AC amplitude, can be adjusted until the output of the bias level sensor wrapper matches a desired, improved, or ideal bias condition. For example, if the AC amplitude and DC level parameters are adjusted to X (as shown in FIG. 4C ), AC X of a linearly phased set of samplers AC Only the proximal half of the sampler returns an output pulse, and (as shown in Figure 5C) X DC The X in the center of a linearly stepped set of samplers DC When only one or some of the samplers are configured to return an output pulse, the operational RQL circuit 102 is said to be ideally biased with respect to the AC and DC parameters of the provided clock. Setting the lower limit point of the sampler's shmoo 304 near the optimal bias point 306 of the operational circuit's shmoo 302, as an example, can be achieved by adjusting the self-inductance and / or DC mutual inductance (X and X, respectively) of the sampler to provide a corresponding bias signal to be measured in the JTL. AC or X DCSetting the lower limit point of the sampler's shmoo 304 near the optimal bias point 306 of the operational circuit's shmoo 302 can be achieved, for example, by setting one or more AC mutual inductances that provide one or more AC bias signals to the sampler's JTL, or, for example, by inserting a self-inductance between the JTL and a transformer (tap). An optimization procedure, such as procedure 2800 shown in FIG. 28 , can be used to calibrate the bias signals to an ideal or near-ideal calibration, for example. When the samplers are set such that their lower limits are near the optimal bias point 306, optimization procedure 2800 can be performed such that the adjusted parameters of the clock(s) and / or DC bias signals fall within the operating margins of the operational RQL circuit 102, meaning that calibration of the bias signals can be performed with the operational RQL circuit continuously operating, even while the bias parameters are being adjusted, improved, or optimized.

[0029] Graph 400 of FIG. 4A shows the relationship between an operational RQL circuit 102 and an AC bias level sensor (X AC Graph 400 shows exemplary shmoo plots 302, 404 of the operating margins at nominal AC and DC bias levels for a 1000 W power sampler (sampler). AC Including margin 404 for sampler, but X AC The number of samplers may be less than or more than eight in some examples. Graph 400, seen in conjunction with the one-dimensional time plots of FIGS. 4B-4D, illustrates an exemplary X-ray diffraction (XRD) diagram that can be performed without interruption to the operation of operational RQL circuit 102 with nominal operating margin 302. AC The performance of the optimization method is shown in Figure 4. The AC amplitude of the applied bias signal can be varied, essentially shifting the bias point vertically up or down on graph 400, until the optimal AC bias point 4C is determined. ACThe sampler may, for example, have a bias transformer with a self-inductance that varies in value to produce a varying offset in the AC response, and a nominal DC mutual inductance. AC The increased self-inductance between the sampler JTL and the corresponding sampler tap on the bias line causes the operating RQL circuit 102 to reverse as the clock amplitude increases, X AC This can have the additional beneficial effect of preventing the sampler from spontaneously inverting. AC The population of samplers may be configured such that the lower bound of each margin shmoo plot is centered around a bias point 306 that is initially considered or assumed to be optimal for the operation of the operational RQL circuit 102. As shown in FIG. AC The lower bound of the sampler's margin shmoo plot is centered near the middle of the nominal margin shmoo plot 302 of the operational RQL circuit.

[0030] 4B to 4D show, for example, a bias level sensor wrapper such as that shown in FIG. 2A, which uses X as its bias level sensors 202 to 212. AC If a sampler is provided, this indicates the reception or non-reception of an output pulse. In the example shown, X AC The sampler will generate those shmoo plots in X DC -X AC They are arranged in the wrapper in order of levels shifting upward in space. X DC -X AC The sampler with the lowest shmoo plot in space is located near the proximal end of the bias level sensor wrapper, X DC -X AC The sampler with the highest shmoo plot in space is located near the distal end of the bias level sensor wrapper. The dashed patterns of the output pulses in Figures 4B-4D correspond to the same dashed patterns in the margin shmoo plot 404 of Figure 4A, and pulses with a certain dashed pattern in Figures 4B-4D correspond to the X with margins depicted with the same dashed pattern in Figure 4A. AC4B-4D therefore show the wrapper output effect of varying the AC amplitude of the applied bias signal as shown in FIG. 4A. If the applied AC bias is too low, the AC bias point 4B will be at most X AC is too low to fall within the operating margin of the sampler. Therefore, the number of output pulses returned is relatively small, as shown in FIG. 4B. For example, as shown in FIG. AC If the samplers are arranged in a sequential (e.g., linear) cascade, with the sampler configured with the lowest AC operating margin located closest to the input / output end of the wrapper shown in FIG. 2A, the returning output pulses may be limited to the return of earlier pulses. In contrast, if the supplied AC bias is too high, the AC bias point 4D will be at the most X AC This is too high to be within the operating margin of the sampler. Therefore, the number of output pulses returned is relatively high, as shown in Figure 4D. For example, as shown in Figure 4B, AC If the samplers are linearly stepped, with the sampler configured with the highest AC operating margin positioned most distal to the input / output end of the wrapper as shown in FIG. 2A, the returning output pulses may include not only the return of earlier pulses, but also the return of some later pulses. The supplied AC bias 4C may be considered optimal, for example, when the number of returning output pulses is in the mid-range, an example of which is shown in FIG. 4C, approximately half X AC The sampler operates and returns the output pulse, approximately half the X AC The sampler is inactive and therefore does not return an output pulse. AC The sampler is designed to ensure that the lower bound of AC is X along the length of the RQL scan register wrapper as shown in Figure 2A. AC In other examples, the RQL scan register wrapper shown in Figure 2A is distributed in ascending order in the X dimension. ACThe samplers may be configured to be arranged in other orders, including descending order, or in any known arrangement without any particular order, and the order may be appropriately taken into account when analyzing the output of the RQL scan register wrapper to determine improved or optimal bias levels. In other examples where the analysis of the wrapper output involves counting the number of samplers operating under given bias conditions, such as when sampler margin spread is achieved solely by process variation, the order is not important and need not be taken into account when analyzing the wrapper output to determine improved or optimized bias levels.

[0031] Graph 500 of FIG. 5A shows the relationship between an operational RQL circuit 102 and a DC bias level sensor (X DC Graph 500 shows an example shmoo plot 302, 504 of the operating margins at nominal AC and DC bias levels for an eight X DC Including margin 504 for sampler, X DC The number of samplers may be less than or more than eight in some examples. Graph 500, seen in conjunction with the one-dimensional time plots of FIGS. 5B-5D, illustrates an exemplary X-ray diffraction (XRD) that can be performed without interruption to the operation of operational RQL circuit 102 with nominal operating margin 302. DC The performance of the optimization method is shown in Figure 5. The DC value of the applied bias signal can be varied, essentially shifting the bias point horizontally left or right on graph 500, until the optimal DC bias point 5C is determined. DC The sampler may, for example, measure the change in DC mutual inductance (M DC ) and a nominal AC mutual inductance. As an example, if the DC bias point of the nominal operating margin 302 is X DC The DC mutual inductance of the sampler is determined by the mutual inductance with the DC bias line in each of the sampler's corresponding transformers, such that X when the current in the DC bias line varies between 1.5 mA and 2.5 mA. DCThe sampler can be staged so that it is optimally biased. Such a change in DC mutual inductance can be achieved, for example, by DC For a sampler, given X DC This can be provided by changing the distance at which a DC transformer in the bias tap of the sampler couples with the corresponding DC bias line, thus shortening or lengthening such coupling distance. AC As with the sampler, X DC The samplers may be arranged in groups such that the lower bound of their margin shmoo plots are centered around a bias point 306 that is initially considered or assumed to be optimal for the operation of the operational RQL circuit 102. As shown in FIG. DC The lower bound of the sampler margin shmoo plot is centered near the middle of the nominal margin shmoo plot 302 for the operational RQL circuit.

[0032] 5B to 5D show bias level sensor wrappers such as those shown in FIG. 2A, each of which has X as its bias level sensors 202 to 212. DC 5B-5D correspond to the same dashed line pattern in the margin shmoo plot 504 of FIG. 5A, and pulses of a certain dashed line pattern in FIG. 5B-5D correspond to X 100 with a margin depicted by the same dashed line pattern in FIG. 5A. DC 5B-5D show the wrapper output effect of varying the DC value of the applied bias signal as shown in FIG. 5A. Optimization of the bias signal DC value can be performed with the bias signal AC amplitude set to its optimum level or slightly higher than its optimum level. If the applied DC bias is too low, X DCIf the samplers are arranged in a sequential (e.g., linear) cascade, with the sampler configured with the lowest DC operating margin located closest to the input / output end of the wrapper shown in Figure 2A, the returning output pulses will be limited to the return of one or several earlier pulses, as shown in Figure 5B. In contrast, if the supplied DC bias is too high (5D), only the last one or several output pulses will return in time, which is the one or several X most distal to the input / output end of the wrapper shown in Figure 2A, as shown in Figure 5D. DC The DC bias 5C supplied is optimal when only one or a few of the output pulses are returned, as shown in FIG. 5C, which means that only one or a few of the central X DC Only the sampler is operational and therefore returns an output pulse, while the other X DC The sampler is not returned. DC The sampler is designed so that the lower bound of AC is X along the length of the RQL scan register wrapper as shown in Figure 2A. DC In other examples, the RQL scan register wrapper shown in Figure 2A is distributed in ascending order in the X dimension. DC The samplers may be configured to be arranged in other orders, including descending order, or in any known arrangement without any particular order, and the order may be appropriately taken into account when analyzing the output of the RQL scan register wrapper to determine improved or optimal bias levels. In other examples where the analysis of the wrapper output involves counting the number of samplers operating under given bias conditions, such as when sampler margin spread is achieved solely by process variation, the order is not important and need not be taken into account when analyzing the wrapper output to determine improved or optimized bias levels.

[0033] In various instances, the wrapper AC Sampler only, X DC It may be configured to include only samplers or a mix of different types of samplers. ACor X DC The margin offset stepwise configuration can be reversed from the ascending order described above, so that high-margin samplers are positioned proximal on the wrapper ladder and low-margin samplers are positioned distal on the wrapper ladder, or the stepwise configuration can adopt a pattern other than an ordered stepwise configuration, with changes in the expected pulse output. The linearly ordered low-to-high stepwise configuration described above is provided as an illustrative example only. In either example, whether the sampler is located distal or proximal to the input / output end of the bias level sensor wrapper is not a factor in determining the significance of bias level adjustment / optimization of the corresponding output pulse; rather, the margin offset set for the sampler is a factor in determining the significance of bias level adjustment / optimization of the sampler's corresponding output pulse.

[0034] 4B-4D, which varies only the applied AC bias, is first performed to find an improved or optimal applied AC bias level, and then the one-dimensional scanning procedure shown in FIGS. 5B-5D, which varies only the applied DC bias, leads to a more accurate assessment or calibration of the applied DC bias level. Similarly, the one-dimensional scanning procedure shown in FIGS. 5B-5D, which varies only the applied DC bias, is first performed to find an improved or optimal applied DC bias level, and then the one-dimensional scanning procedure shown in FIGS. 4B-4D, which varies only the applied AC bias, leads to a more accurate assessment or calibration of the applied AC bias level. Thus, these two one-dimensional scanning procedures are AC and X DC 2A-2C may be implemented using the RQL scan registers 200, 260, 290 of FIGS. 2A-2C, for example, as bias level sensors 202-212 (or 262-272 or BLS) to provide outputs indicative of AC or DC bias levels. AC Sampler and X DC It may be used with either or both samplers. ACWhen used to measure X, any of the scan registers 200, 260, and 290 will generate a specific number of pulses when an optimum level is reached. DC When used to measure , the result output by any of the scan registers 200, 260, 290 is the X DC The RQL scan registers 200, 260, and 290 each indicate an average position of the sampler. Each of the RQL scan registers 200, 260, and 290 can provide a numerical result in some exemplary modes of operation, or in other exemplary modes, the output can indicate the bias level in other ways. For example, the RQL scan registers 200, 260, and 290 can enable examination of the output of a single bias level sensor located in the scan register to find its improved or optimal bias point by varying the applied AC and DC biases. In some examples, this procedure can be performed individually for multiple or all bias level sensors located in the scan register. In some examples, this procedure can be performed for individual bias level sensors located in various locations across the chip, not necessarily for a single scan register or for all elements of any scan register. In such examples, average values ​​of the individually measured improved or optimal applied AC and DC bias levels can be calculated and used as setpoints for the bias sources.

[0035] X DC -X AC Different methods can be used to scan the space to find improved or optimal AC and DC applied bias levels. A first exemplary scanning method is to scan all X DC -X AC Sampling at points, X DC -X ACA second exemplary scanning method may include creating a complete two-dimensional map of the space. A second exemplary scanning method may include limiting the scan to the discovered boundary of the operating area, essentially "walking" in and out around the perimeter of the margin shmoo plot in a zigzag fashion to determine the boundary or perimeter contour. This second exemplary scanning method is a complete X-ray scan of the first exemplary scanning method. DC -X AC A third exemplary scanning method may have the advantage of time efficiency over spatial sampling. DC -X AC This may include traversing space with a spiral scan or a conical scan. A fourth exemplary scanning method may implement a successive approximation method such as that used in analog-to-digital converters (ADCs). A fifth exemplary scanning method may implement a delta-sigma algorithm. Other exemplary scanning methods may implement variations or combinations of the above methods to approach improved or optimal applied AC and / or DC bias levels. In any of these examples, the selected scanning method may use a closed loop to find and stabilize bias levels, regardless of the type of scan(s) used and the on-chip configuration or placement of bias level sensors used in the scanning method.

[0036] A sampler, such as bias level sensors 202-212 of FIG. 2A, can have any of a number of different forms. In some examples, a sampler consists of one or more JTLs or logic gates configured in series with one another, e.g., as a shift register, with at least one of the JTLs or logic gates in the shift register specially configured to be sensitive to bias in a manner different from the other JTLs or logic gates in operational RQL circuit 102. FIG. 6 shows an exemplary sampler stage 600 having a sampler JTL 602 coupled to a sampler bias tap 604 configured for use with a bias level sensor, such as any of bias level sensors 202-212 of FIG. 2A. An SFQ-based sample signal provided at sampler JTL input terminal ai can be transmitted (i.e., propagated) to sampler JTL output terminal qo when sampler JTL 602 is operational. The operability of sampler JTL 602 depends at least on sampler JTL 602 being biased within its operational margin. Bias is provided to sampler JTL 602 via bias line 606, which in the illustrated example includes bias lines 614, 616, and 618. Sampler JTL 602 is inductively coupled to bias line 606 via sampler tap 604. In the example shown in FIG. 6, sampler tap 604 includes DC coupling transformer 608 for inductively coupling sampler JTL 602 to DC bias line 614, I clock coupling transformer 610 for inductively coupling sampler JTL 602 to I clock bias line 616, and Q clock coupling transformer 612 for inductively coupling sampler JTL 602 to Q clock bias line 618. The following table shows the relationship between normalized mutual inductance and tap phase of sampler tap 204, where normalized AC mutual inductance M I , M Q We show how the normalized M can be modified to provide different clock phase biases to the sampler JTL602. DC is X DC It can vary (from 1) for the sampler.

[0037] [Table 1]

[0038] In contrast to the JTL or gate found in the operational RQL circuit 102, the sampler JTL 602 is fed from the sampler bias tap 604 through a larger self-inductance, which in some instances may be provided by an expansion of the bias inductor L2, or in other instances, by an AC offset inductor L2 between the sampler JTL 602 and the tap 604, as shown in FIG. offsetAC In this latter example, the AC offset inductor L offsetAC The sampler JTL 602 configured to exclude , may otherwise be identical to the standard bias JTL used in the operational RQL circuit 102. Compared to the JTL found in the operational RQL circuit 102, the DC bias transformer 608 of the bias tap 604 may, in some examples, have a larger or smaller mutual inductance M that couples the sampler JTL 602 to the DC bias line 614. DC In order to provide a larger self-inductance of the sampler stage 600, the bias inductor L2 may be enlarged, or the AC offset inductor L offsetAC By including this, the margin shmoo plot is X for the nominal margin 302. DC -X AC 4A, which is vertically shifted upward in space. In some examples, an AC offset inductor L offsetAC By omitting the bias inductor L2 and making it smaller than normal (smaller than JTL in the operational RQL circuit 102), the operating margin shmoo plot of the bias level sensor will be substantially (X AC A reverse offset (not shown) can be realized that is shifted downward (in the 1000 kHz to 1000 kHz dimension). The bias inductor L2 and, if present, the AC offset inductor L offsetAC can be provided, for example, by an induction network.

[0039] In an exemplary bias level sensor with reduced AC response, the AC offset inductor L in the sampler stage 600 offsetAC may be, for example, about 1.5 times the self-inductance of the sampler tap 604. The AC offset inductor L offsetAC This self-inductance value of aligns the bottom corner of the shmoo plot of the corresponding sampler with the X of the shmoo plot 302 of the operational RQL circuit 102. AC As an example, the AC offset inductor L in sampler stage 600 may have the effect of placing it at approximately the midpoint of the offsetAC may be about 29.25 pH, or may provide about 1.5 times the self-inductance of the sampler tap 604, which may be, for example, about 19.3 pH. AC In an example implemented as bias level sensors 202-212 in the context of the wrapper shown in FIG. 2A to function for relatively low values ​​of SFQ, the bias level sensors may respond to high AC bias levels by outputting a steady stream of RQL-encoded logic "1s" (positive SFQ pulses followed by negative SFQ pulses) that flip every AC clock cycle. Corresponding suppression logic 240-250 prevents this steady stream of RQL-encoded logic "1s" by generating a stream of RQL-encoded logic "0s" (no SFQ pulses) in response. Detection of the lower limit of the bias level sensor's margin shmoo plot can be used to calibrate AC bias amplitude parameters to stabilize the RQL clock in an operating RQL system, as described above with respect to FIGS. 4A-4D.

[0040] Margin Shmoo Plot with Higher X AC In the exemplary bias level sensor, the AC offset inductor L in the sampler stage 600 of the bias level sensor is shifted to a offsetACcan be, for example, in the range of about 0.5 to 10 times the nominal tap self-inductance value, e.g., the tap self-inductance value of the JTL or gate used in the operational RQL circuit 102. For example, the AC offset inductor L in the sampler stage 600 of the bias level sensor offsetAC can be approximately 1.5 times larger than the tap self-inductance of the JTL and gates used in the operational RQL circuit 102. As an example, if the nominal self-inductance value of the bias taps providing to the JTLs or gates used in the operational RQL circuit 102 is approximately 19.3 pH, then the AC offset inductor L in the sampler stage 600 of the bias level sensor of FIG. offsetAC The inductance value of the sampler stage 600 may be between about 9.65 pH and about 193 pH, for example, between about 40 pH and about 50 pH, for example, about 29.0 pH. AC In an example implemented as bias level sensors 202-212 in the context of the wrapper shown in FIG. 2A to function for relatively high values ​​of , the bias level sensors may respond to low AC bias levels by outputting a continuous stream of RQL-encoded logic "1s" (positive SFQ pulses followed by negative SFQ pulses) that flip every AC clock cycle. Corresponding suppression logic 240-250 prevents this continuous stream of RQL-encoded logic "1s" by generating a stream of RQL-encoded logic "0s" (no SFQ pulses) in response. Thus, the upper edge of the bias level sensor's margin shmoo plot can be detected without flooding the RQL shift register wrapper output with a continuous stream of "1s." While detecting the upper edge of the bias level sensor's margin shmoo plot may not be required to calibrate the AC bias amplitude parameters in an operating RQL system, in some examples, it may be used as a diagnostic tool.

[0041] 6 provides an example in which JTL 602 is used as the sample signal transmitting device. Although not shown, other exemplary sampler stages may be similar to sampler stage 600 of FIG. 6, but have an RQL gate as the sample signal transmitting device instead of sampler JTL 602. The RQL gate provides a desired mutual inductance M to the AC bias line to provide the desired clock phase. Q , M I and the desired X DC The RQL gate is biased by a modified bias of the sampler tap, such as sampler tap 604, with a mutual inductance to the DC bias line to provide an offset. The RQL gate can, in some instances, shift the shmoo plot (operating region) to a higher X AC In order to raise the level of offsetAC The RQL gate, like sampler JTL602, operates within its modified operating margins and fails (produces unexpected output or no output) outside of its modified operating margins.

[0042] FIG. 7 illustrates an exemplary suppression logic 700 that can be used to implement any instance of the suppression logic 240-250 of FIG. 2A. The suppression logic 700 includes a first superconducting path to the non-inverting input of an RQL A-NOT-B gate 704 (a two-input AND gate with a single inverting input) and a second path through several (e.g., four) JTLs 702 to generate a one-cycle delay to the inverting input of the A-NOT-B gate. If the bias to the sampler is too high, the sampler can "spin" (generating a continuous stream of logic "1" outputs) that can disable the RQL scan register wrapper of FIG. 2A. The suppression logic 700 prevents such spins (repeated triggering). The A-NOT-B gate 704 passes the first logic "1" from the sampler but does not pass subsequent "1"s from the sampler that generate a stream of reciprocal SFQ pulses due to defects or excessive bias. In some examples, the throttle logic 700 can be omitted. Excessive AC bias amplitude is limited by a lower limit (X ACmin ) is higher than the standard X AC The standard logic in the read register spins about 2 dB faster before the raised sampler spins. Additionally, the suppression logic circuitry itself may have a defect and start spinning, for example due to the use of the RQLA-NOT-B gate 704, which has a narrow operating margin.

[0043] Some examples can use multiple instances of sampler stage 600 arranged in series as a shift register to provide a bias level sensor. Because a single JTL receives a substantial portion of its operating flux from the cells that drive it and from the cells it drives, it may be necessary to arrange several sensing JTLs 600 (with similarly shifted bias margins) in series before the true effects of bias shift appear at the output of the shift register that constitutes the bias level sensor. As an example, four or more sensing JTLs in series may be sufficient for the sensing elements to operate independently from the JTLs before and after them.

[0044] FIG. 8 shows an example shift register 800 configured as a bias level sensor, including four instances 804, 806, 808, and 810 of the example sampler stage 600 of FIG. 6 . The shift register 800 may further include an input stage 802 and an output stage 812, each of which may be implemented as one or more JTLs and / or logic gates with a standard bias (e.g., without the self-inductance and / or mutual inductance correction of the sampler stage 600 of FIG. 6 ). FIG. 9 shows an example shift register 900, including three instances 904, 906, and 908 of the example sampler stage 600 of FIG. 6 . The shift register 900 may further include an input stage 902 and an output stage 912, each of which may be implemented as one or more JTLs and / or logic gates with a standard bias (e.g., without the self-inductance and / or mutual inductance correction of the sampler stage 600 of FIG. 6 ). FIG. 10 shows an example shift register 1000 that includes one instance 1004 of the example sampler stage 600 of FIG. 6. The shift register 1000 may further include an input stage 1002 and an output stage 1012, each of which may be implemented as one or more JTL and / or logic gates with standard biases (e.g., without the self-inductance and / or mutual inductance correction of the sampler stage 600 of FIG. 6). FIG. 11 shows an example shift register 1100 that includes one instance 1104 of the example sampler stage 600 of FIG. 6. The shift register 1100 may further include an input stage 1102, which may be implemented as one or more JTL and / or logic gates with standard biases (e.g., without the self-inductance and / or mutual inductance correction of the sampler stage 600 of FIG. 6). As an example, any of the shift registers 800, 900, 1000, or 1100 may be implemented as any of the bias level sensors 202, 204, 206, 208, 210, 212 of FIG. 2A, any of the bias level sensors 262, 264, 266, 268, 270, 272 of FIG. 2B, or any of the bias level sensors BLS of FIG. 2C.

[0045] FIG. 12 illustrates an exemplary specific phase bias level sensor 1200 for the Q clock. Accordingly, the specific phase Q sampler 1200 of FIG. 12 provides a sampler that responds to variations in the amplitude of the Q clock but not to variations in the amplitude of the I clock. FIG. 13 illustrates an exemplary specific phase bias level sampler 1300 for the I clock. Accordingly, the specific phase I sampler 1300 of FIG. 13 provides a sampler that responds to variations in the amplitude of the I clock but not to variations in the amplitude of the Q clock. Thus, the samplers 1200, 1300 allow for independent adjustment of the I and Q clock AC amplitudes. FIGS. 14 and 15 explain the sensing designations used in FIGS. 12, 13, 16, and 18.

[0046] In the specific-phase Q sampler 1200 of FIG. 12, four quad ("×4") sampler stages 1202, 1204, 1206, and 1208 are arranged in series with each other, and each of the four quad sampler stages 1202, 1204, 1206, and 1208 is biased by a different phase of the RQL clock signal. The first quad sampler stage 1202 comprises a configuration of four JTL and / or logic gates with standard biasing, which does not have the self-inductance and / or mutual inductance correction of the sampler stage 600 of FIG. 6. An extension of such a standard-bias quad sampler stage is shown as standard-bias JTL and / or series gates 1400 in FIG. 14. The first quad sampler stage 1202 is biased by a 0° clock. The second quad sampler stage 1204 comprises a configuration of four JTLs and / or logic gates with a modified AC bias that corrects for the self-inductance and / or mutual inductance of the sampler stage 600 of FIG. 6 . An extension of such a modified-bias quad sampler stage is shown as modified-bias JTLs and / or series gates 1500 in FIG. 15 . The second quad sampler stage 1204 is biased by a 90° clock (an AC waveform shifted by 90° relative to the AC waveform of the 0° clock). The third quad sampler stage 1206 is a quad standard-bias sampler stage 1400 biased by a 180° clock. The fourth quad sampler stage 1208 is a quad standard-bias sampler stage 1400 biased by a 270° clock. As described above in Table 1, the 0° and 180° clocks may be provided by an I clock resonator, and the 90° and 270° clocks may be provided by a Q clock resonator. While sampler stages 1202, 1204, 1206, and 1208 are shown in the illustrated exemplary configuration 1200 as quad sampler stages each having four serial JTLs and / or logic gates, the number of JTLs and / or logic gates in each sampler stage may be greater or less in other examples. The number of JTLs and / or logic gates in each sampler stage may be determined as a design parameter.In one example (not shown), sampler stage 1204 has four or more series JTLs and / or logic gates to prevent current sharing effects from sampler stages 1202 and 1206, and sampler stages 1202, 1206, and 1208 are composed of fewer than four series JTLs and / or logic gates.

[0047] In the specific phase I sampler 1300 of Figure 13, four quad sampler stages 1302, 1304, 1306, and 1308 are arranged in series with each other, and each of the four quad sampler stages 1302, 1304, 1306, and 1308 is biased by a different phase of the RQL clock signal. The first quad sampler stage 1302 is a quad standard bias sampler stage 1400 biased by a 0° clock. The second quad sampler stage configuration 1304 is a quad standard bias sampler stage 1400 biased by a 90° clock. The third quad sampler stage 1306 is a quad modified bias sampler stage 1500 biased by a 180° clock. The fourth quad sampler stage 1308 is a quad standard bias sampler stage 1400 biased by a 270° clock. Although sampler stages 1302, 1304, 1306, and 1308 are shown in the illustrated exemplary configuration 1300 as quad sampler stages each having four series JTLs and / or logic gates, the number of JTLs and / or logic gates in each sampler stage may be greater or less in other examples. The number of JTLs and / or logic gates in each sampler stage may be determined as a design parameter. In one example (not shown), sampler stage 1306 has four or more series JTLs and / or logic gates to prevent current sharing effects from sampler stages 1304 and 1308, and sampler stages 1302, 1304, and 1308 each consist of fewer than four series JTLs and / or logic gates.

[0048] In the quad standard bias sampler stage extension 1400 shown in FIG. 14, each individual component stage 1402, 1404, 1406, 1408 of each sampler stage 1202, 1206, 1208, 1302, 1304, 1308 has a standard value of bias tap self-inductance, i.e., the same value of bias tap self-inductance used to feed the JTL and gates in the operational RQL circuit 102 (e.g., AC offset inductance L offsetAC The JTLs or gates of each individual component stage 1402, 1404, 1406, 1408 are biased with an AC clock signal of the same phase ("phase°").

[0049] In the quad-corrected bias sampler stage extension 1500 shown in FIG. 15, each individual component stage 1502, 1504, 1506, 1508 of each sampler stage 1204, 1306 includes an AC offset inductor L inserted between the JTL or gate and its corresponding bias tap. offsetAC (or equivalently, an expanded bias tap inductor L2), and an AC offset inductor L offsetAC provides a bias self-inductance that is greater than the bias self-inductance in the JTLs and gates in the operational RQL circuit 102. Thus, each individual component stage 1502, 1504, 1506, 1508 provides a bias self-inductance that is greater than the bias self-inductance in the JTLs and gates in the operational RQL circuit 102. DC -X AC With a margin shmoo plot elevated in space, the JTLs or gates of each individual component stage 1502, 1504, 1506, 1508 are biased with an AC clock signal of the same phase ("phase°").

[0050] Because of the tendency for flux sharing between the driven JTL or driven logic gate and the driving JTL or logic gate, if a single JTL or logic gate operates with a clock phase that is 90° behind the JTL or logic gate that drives it and 90° ahead of the JTL or logic gate it drives, an accurate measurement of the amplitude of the clock of a particular phase biasing that JTL or logic gate may not be obtained. However, by using four or more individual component stages (e.g., sampler stages 1502, 1504, 1506, 1508, or 1402, 1404, 1406, 1408) biased with a clock signal of the phase to be sampled, flux sharing can be effectively limited to the first and last JTL or logic gates, leaving the remaining JTLs and / or logic gates largely unaffected by flux sharing. In this way, the phase to be detected can be accurately measured. In the particular phase samplers 1200, 1300 shown in FIGS. 12 and 13, the serial arrangement 1204, 1306 of the individual component stages 1402, 1404, 1406, 1408 may be, for example, X AC The AC offset inductor L exists to raise the lower limit of offsetAC The component stages 1202, 1206, 1208, 1302, 1304, 1308 of the sensing sampler stage 1204 or 1306 are biased through weakened bias taps using a standard bias tap, while the series arrangements 1202, 1206, 1208, 1302, 1304, 1308 of the individual component stages 1502, 1504, 1506, 1506 have standard bias taps to form a support infrastructure. The individual component stages 1502, 1504, 1506, 1508 of the sensing sampler stage 1204 or 1306 respond independently to either the I or Q clock bias. When the I / Q phase angle is close to the nominal 90°, the phase sensitivities of the JTLs or gates of the I and Q weakened taps have opposite slopes.

[0051] 16 shows an exemplary I-clock specific (Q-clock independent) bias level sensor 1600. The standard bias quad sampler stages 1602, 1606, and 1610 are similar to those expanded in FIG. 14, and the modified bias quad sampler stages 1604 and 1608 are similar to those expanded in FIG. 15. Thus, the exemplary sampler 1600 includes 20 JTLs and / or gates in series with each other. In the exemplary I-clock specific (Q-clock independent) bias level sensor 1600, the X of the sensing sampler stages (sensing JTLs and / or gates in the quad configurations 1604, 1608) to which the 0° and 180° clocks are provided are shown. AC The operating margin can be achieved by adding an AC offset inductor L of, for example, 1.5 times the nominal tap self-inductance (e.g., 1.5 × 19.3 pH). offsetAC By inserting X DC -X AC Only at these sensed JTLs or gates is the AC amplitude of the I clock changed during a margin sweep optimization procedure that determines the optimal AC bias level for the I clock signal. In contrast, sampler stages 1602, 1606, and 1610 have an AC offset inductance L offsetAC is equal to 0 (AC offset inductor L offsetAC does not exist), so the X of the sampler stage JTL and / or gates in sampler stages 1602, 1606, 1610 AC The margin is the X of the JTL and gate in the operational circuit 102. AC The amplitude of the Q clock supplied to quad sampler stages 1602, 1606, and 1610 remains fixed during the margin sweep optimization procedure (while sweeping the AC amplitude of the I clock supplied to the sampling JTLs or gates in quad sampler stages 1604 and 1608).

[0052] The graph in Figure 17 shows an example AC and DC bias margin shmoo plot for the specific I-clock (Q-clock independent) bias level sensor 1600 of Figure 16.AC When bias levels (nominal, 1 dB below nominal, 2 dB below nominal) are applied, the effect on the margin shmoo plot of a particular I sampler 1600 can be observed as different plot curves in Figure 17. The lower limit 1702 of the margin shmoo plot of the I sampler 1600 remains constant with variations in Q bias (it is not affected by the strength of the clock signal applied to the Q wrapper), confirming that the I bias level can be measured independently of variations in the Q bias level.

[0053] 18 shows another exemplary I-clock specific (Q-clock independent) bias level sensor. The standard bias quad sampler stages 1802, 1806 are similar to those expanded in FIG. 14, and the modified bias quad sampler stage 1804 is similar to that expanded in FIG. 15. In the exemplary I-clock specific (Q-clock independent) bias level sensor 1800, the margin shmoo plot for the sampler stage provided with a 180° clock (sampler stage in quad configuration 1804) shows, for example, an AC offset inductor L having a value of 1.5 times the nominal tap self-inductance (e.g., 1.5 × 19.3 pH). offsetAC By inserting X DC -X AC The sampler stages 1802 and 1806 are shifted upward in space. No AC offset inductors are used in the standard biased sampler stages 1802 and 1806 (as are the JTLs and gates in operational circuit 102). Sampler 1800 achieves the structural simplification of sampler 1600 without incurring a loss in performance. Sampler 1800 has a margin shmoo plot similar to sampler 1600 shown in FIG. 17. In contrast to sampler 1600, sampler 1800 has a margin shmoo plot similar to that of sampler 1600 shown in FIG. 17. AC Only the 180° phase clock is used, and not the 0° phase clock, to define the lower limit 1702 of I sampler 1800. The lower limit 1702 of the margin shmoo plot for I sampler 1800 remains constant with variations in Q bias, confirming that the I bias level can be measured independently of variations in Q bias level.

[0054] A challenge with RQL circuits is that I and Q clock signals 112, 114, generated to be 90° apart and in quadrature when measured at signal generator 110 in warm space, may not be 90° apart from each other at the level of RQL IC 106 in cold space due to components in clock resonator network 104 that introduce undesirable phase shifts. An offset from 90° in the phase difference between the I and Q clock signals at the level of RQL IC 106 can cause operational problems, including reduced operating margins, in operational RQL circuit 102. The circuits described herein can provide an indirect measurement of phase error by measuring the effect on sampler operation for different clock phase differences, effectively converting phase variations into amplitude variations.

[0055] In addition to being sensitive to the I and Q clock amplitudes, the specific phase samplers 1200, 1300, 1600, and 1800 of Figures 12, 13, 16, and 18 are also sensitive to the phase difference between the I and Q clocks. When the phase difference between the I and Q clocks in the RQL IC 106 is 90°, the minimum X AC are equal. Therefore, I and Q specific phase samplers 1200, 1300, 1600, and 1800 can be used to determine the optimum phase difference between the I and Q clocks, as generated by source 110, required to obtain an exact 90° phase difference between the I and Q clocks in RQL IC 106. The graph in FIG. 19 shows the deviation of the Q clock phase from 90° (X at the lower margin shmoo plot for the I and Q specific samplers). AC 19 shows an exemplary minimum operational AC bias for a particular I clock and a particular Q clock bias level sensor as a function of the AC offset inductance L of the I and Q sensing JTLs or gates. offsetACis 1.5 times the nominal tap self-inductance (the tap self-inductance used for the JTL or gate in the operational RQL circuit 102). The phase difference between the I and Q clocks varies ±45° around a nominal value of 90°. The horizontal axis of the graph in FIG. 19 is the deviation of the inter-clock phase difference from 90°. X ACmin is equal at 1902 for both I and Q sensing JTLs or gates when the I / Q phase difference is 90°.

[0056] FIG. 20 is a diagram of the X phase 20 shows a 45° shift register 2000 with JTL or logic gates clocked at 45°, 135°, 225°, and 315° that can be used as a phase sampler, also called a phase sampler. phase The sampler can indirectly detect the phase difference between two AC clocks (e.g., between an I clock and a Q clock). In the phase sampler 2000 of FIG. 20, four hex sampler stages 2002, 2004, 2006, and 2008 are arranged in series with one another, and each of the four hex sampler stages 2002, 2004, 2006, and 2008 is biased by a clock signal of a different phase, which may be generated, for example, as a combination of other clock signals (e.g., as shown in Table 1 above). FIG. 21 shows the hex sampler stage code expansion used for each of the hex sampler stages 2002, 2004, 2006, and 2008 of FIG. 20. The first hex sampler stage 2002 is biased by a 45° clock. The second hex sampler stage 2004 is biased by a 135° clock. The third hex sampler stage 2006 is biased by a 225° clock. The fourth hex sampler stage 2008 is biased by a 315° clock. Combination clock waveforms providing clocks of 45°, 135°, 225°, or 315° phase can be provided by transformer coupling to both the I (0° or 180°) and Q (90° or 270°) clock resonators (as shown in Table 1 above). X in FIG. phaseUsing sampler 2000 to directly measure the phase error between the I and Q clock signals may involve first equalizing the amplitudes of the I and Q clock signals using separate sensors (e.g., an I-independent clock amplitude sensor such as specific-phase I sampler 1300 of FIG. 13 and a Q-independent clock amplitude sensor such as specific-phase Q sampler 1200 of FIG. 12).

[0057] In the expansion 2100 of each of the hex sampler stages 2002, 2004, 2006, 2008 of FIG. 21, each individual component stage 2102, 2104, 2106, 2108, 2110, 2112 of each sampler stage 2002, 2004, 2006, 2008 includes an AC offset inductor L inserted between the JTL or gate and its corresponding bias tap. offsetAC (or equivalently, an expanded bias tap inductor L2), and an AC offset inductor L offsetAC provides a bias self-inductance that is greater than the bias self-inductance of the JTLs and gates in the operational RQL circuit 102. Thus, each sampler stage 2102, 2104, 2106, 2108, 2110, 2112 provides a bias self-inductance that is greater than the bias self-inductance of the JTLs and gates in the operational RQL circuit 102. DC -X ACThe margin shmoo plot is elevated in space. The JTLs or gates of each sampler stage 2102, 2104, 2106, 2108, 2110, and 2112 are biased with an AC clock signal of the same phase ("Phase°"). As described above, concatenating several sampler stages all biased with the same AC clock phase mitigates the effects of current (or, alternatively, magnetic flux) sharing between adjacent JTLs biased by clock signals of different clock phases. The specific number of sensing JTLs required to provide this insensitivity depends on the details of the JTLs and / or gates and their individual bias taps. In some examples, concatenating between four and six sampler stages may be sufficient to provide the desired flux sharing mitigation. Although FIG. 20 shows an example of a phase sampler 2000 having six sampler stages driven by the same clock phase in each set 2002, 2004, 2006, 2008, i.e., each sampler stage 2002, 2004, 2006, 2008 includes a set of six sampler stages driven by the same clock phases directly coupled in series to each other, other examples may have more or fewer sampler stages driven by the same clock phases directly coupled in series to each other, for example, four, five, or seven JTLs or gates driven by the same clock phases directly coupled in series to each other in each set, or various numbers of JTLs or gates driven by the same clock phases directly coupled in series to each other in different sets.

[0058] min x ACThe clock amplitude, i.e., the amplitude of the AC magnetic flux provided by the transformers for the 45° and 135° combined clocks, is plotted in FIG. 22 as a function of phase error (phase difference between the I and Q clocks). The sampler stage responds to these differences in clock amplitude. Thus, the phase error can be calibrated based on information about the operating margin observed in the sampler stage while varying the I / Q phase. In the 45° shift register 2000 of FIG. 20, as the inter-clock phase difference (phase error) increases relative to 90°, the clock amplitude of the 45° and 225° converters decreases, and the clock amplitude of the 135° and 315° converters increases. The clock amplitude vs. phase error graph of FIG. 22 illustrates this relationship for the exemplary phase sampler 2000 of FIG. 20. The AC amplitude graph of the minimum operating bias signal in FIG. 23 shows how this characteristic is applied to the phase-sensitive X phase The formation of a sampler is shown in the form of phase sampler 2000 in Figure 20. As shown in Figure 23, the lower limit (X ACmin ) is the minimum X when the phase difference (phase error) between the I clock and Q clock measured on the RQL IC106 is 90°. AC 20 shows an example with six sampler stages, each with a specific phase 2002, 2004, 2006, 2008, but with X phase Other exemplary shift registers configured as samplers may have more or fewer sampler stages per configuration 2102, 2104, 2106, 2108. A method 3000 for calibrating the phase of a clock signal using a phase-sensitive sampler such as the phase sampler 2000 shown in Figure 20 is shown in Figure 30 and described in more detail below.

[0059] Figure 24 shows a representative portion of a phase mode logic (PML) bias level sensing configuration 2400 that can sense and read out bias amplitude using flip-flops (e.g., flip-flops 2402, 2404, 2406) and phase mode shift registers (e.g., shift registers 2408, 2410, 2412, 2414, 2416, 2418, 2420, 2422, 2424). Thus, the PML bias level sensing configuration 2400 of Figure 24 can provide functionality similar to the ladder wrapper configuration of Figure 2A, providing sensors that are individually testable for their operating range under variable RQL bias conditions and that can be placed in multiple locations on the RQL IC 106, but that have a different structure and method of use than the configuration of Figure 2A. Testing and adjusting bias levels using configuration 2400 of Figure 24 involves changing the AC level in the resonator under test, in different examples, in the I resonator (as shown) or the Q resonator (not shown). Similar to the RQL scan register or JTL testbed of Figure 2A, multiple sensors are activated and their responses are read out using a shift register circuit structure.

[0060] 24 forms a shift register, and each time a logic clock assertion signal (e.g., provided as a reciprocal pair of SFQ pulses, or in some cases as the first positive SFQ pulse of such a pulse pair) travels through logic clock path 2426 (right to left in the orientation of FIG. 24) and is provided to the clocking inputs of D flip-flops (e.g., D flip-flops 2402, 2404, 2406), a pattern signal provided on data path 2428 travels one shift register element through shift register 2400 (left to right in the orientation of FIG. 24). A single element of shift register 2400 is enclosed by dashed box 2430, which includes one D flip-flop 2416 and JTL-based shift registers 2410, 2416, 2422. Register 2400 can include any desired number of elements, such as element 2430, arranged in series with one another, with each element located at a location on RQL IC 106 such that it connects to a clock resonator in that portion of IC 106. Thus, each element sees a different physical connection (tap) 120 to AC clock network 104 within RQL IC 106. In Figure 24, each small triangle represents a buffer, e.g., a JTL-based buffer. The flip-flops (e.g., flip-flops 2402, 2404, 2406) of shift register 2400 may be implemented, for example, as PML flip-flops, examples of which are described in U.S. Pat. No. 10,615,783, entitled "RQL D Flip-Flops," and U.S. Pat. No. 10,756,712, entitled "RQL Phase-Mode Flip-Flop," both of which are incorporated herein by reference. The number (in degrees) above each flip-flop or buffer represents the phase of the clock provided to the flip-flop or buffer below it. Clocks of different phases can be provided by connecting different clock resonators 104 on the RQL IC 106 through different transformers, or possibly by connecting different combinations of transformers.

[0061] In some examples of shift register 2400, the elements of the shift register may be designed and manufactured to each have different operating margin offsets, and these offsets may be linearly or otherwise stepped, similar to how the bias level sensors 202-212 of the ladder wrapper configuration 200 of FIG. 2A may be intentionally configured with stepped operating margin offsets, as described above. In some examples, the bias transformers connecting the AC clock network to the D flip-flops in shift register 2400 may be changed from their normal values ​​so that the D flip-flops of shift register 2400 are all under-biased or over-biased by the same amount, or by different degrees of under-biasing or over-biasing. Therefore, a D flip-flop can be expected to fail (cancele due to an AC bias point outside the D flip-flop's AC operating margin) with a fluctuating AC bias at a larger AC bias amplitude (at a higher AC bias point) than the AC amplitude at which a JTL-based buffer would fail with the same fluctuating AC bias. Because D flip-flops are not as robust as JTLs with respect to their operating margins, even if the D flip-flop is not intentionally under-biased, the D flip-flop may fail at a higher AC bias point than the AC bias point at which a JTL-based buffer would fail for the same fluctuating AC bias.

[0062] The PML flip-flop-based bias sampler in the shift register configuration 2400 of Figure 24 is responsive to variations in the clock resonator, bias coupling transformer, and all other circuit parameters. Therefore, use of the PML flip-flop-based bias sampler in the shift register configuration 2400 of Figure 24 can help identify the bias levels required for an operating RQL circuit 102, which may be expected to be affected by variations in all process parameters. Specifically, the PML flip-flop-based bias sampler is sensitive to the self-inductance of the bias coupling transformer, the mutual inductance between the bias coupling transformer and the corresponding clock resonator, the magnitude of the current in the clock line, the inductance of the coupling transformer, the inductance in the JTL and gate, and the critical current of the Josephson junction (JJ).

[0063] In the example 2400 illustrated in FIG. 24 , the Q clock resonator may be driven at a nominal bias level to ensure that logic clock signals are provided to all of the flip-flops (e.g., flip-flops 2402, 2404, 2406) in the shift register 2400, while the I resonator may be driven with varying AC amplitudes to test whether the shift operation is successful across a range of different AC amplitudes. For example, the operating range of each of the flip-flops may be independently determined for each flip-flop by performing the method 2900 illustrated in the flow diagram of FIG. 29 . With the AC amplitudes of the Q and I clocks set to nominal values ​​(2902) and the logic clock running, a test data bit pattern may be shifted in (2904) onto the data path 2428. The logic clock may be implemented by inputting a continuous stream of reciprocal pulse pairs into the logic clock path 2426. Thus, the initial data shifting in (2904) is performed while driving the I resonator at the nominal AC bias amplitude level. After the test data bit pattern is shifted into the PML shift register 2400, with the logic clock subsequently stopped (2906), the I resonator AC bias amplitude may be varied (2908) to test for AC bias amplitude levels greater than or less than nominal. A single logic clock assertion (e.g., a single positive SFQ pulse or reciprocal pulse pair) may then be input (2910) into the logic clock path 2426. The I resonator AC bias amplitude may then be returned to the nominal value (2912), and the logic clock may be restarted to shift out the output data bit pattern onto the data path 2428 (2914). The output data bit pattern may be observed (2916), for example, following output of the data bit pattern via the input / output circuitry of the RQL IC 106. Observation may be performed, for example, by conventional semiconductor circuitry (e.g., CMOS circuitry) outside the cooling space of the RQL IC 106.

[0064] If the output data bit pattern does not match the input data bit pattern, it can be determined that at least one of the elements 2430 of the PML shift register 2400 is outside its operating margin under the changed I-resonator AC bias amplitude conditions, and precisely which element 2430 is outside its operating margin can be identified by the point in the output data bit pattern where the output data bit pattern no longer matches the input data bit pattern (e.g., by a single bit error found in the output data bit stream). In some examples, multiple shift errors in the data bit pattern (e.g., multiple single bit errors between the input and output data bit streams) can be used to identify multiple shift register elements operating outside their respective margins.

[0065] By observing the data output when one of the elements of shift register 2400 fails (e.g., due to the provided 2908 bias point being outside the operating margin of that element), and comparing the output data bit pattern with the input data bit pattern, for example, it may become clear which bit failed to progress through shift register 2400 at some point in the output bit data stream. For example, if the input data bit pattern consists of alternating pairs of "0"s and "1"s, the output data bit pattern may contain, somewhere in the bit stream, three "0"s followed by a "1" ("0001"), or three "1"s followed by a "0" ("1110"). The location of the extra bit may indicate the identity of the element of shift register 2400 that was outside its operating margin during the progression of a single clock. An exemplary input data bit pattern may consist of a series of alternating pairs, triplets, etc. of logical "1"s and "0"s depending on the length of the PML shift register 2400, such as "0011001100110011" for a 16-bit shift register. The method 2900, or portions thereof, may be repeated in some examples with a bit pattern offset, which can ensure that transitions arrive at different flip-flops of the shift register 2400, providing complete data probing of the shift register 2400. For example, a "0011001100110011" or "1100110011001100" bit pattern may be capable of detecting only errors caused by odd-numbered elements of shift register 2400, while a "1001100110011001" or "0110011001100110" bit pattern may be capable of detecting only errors caused by even-numbered elements of shift register 2400. Other input data bit patterns may also be used.A conventional semiconductor circuit (e.g., a CMOS circuit) outside the cooling space of the RQL IC 106 can perform a comparison between the input data bit pattern and the output data bit pattern or otherwise detect anomalies in the output data bit pattern that indicate a flip-flop failure due to bias parameter variations.

[0066] 29, after the output data bit pattern provided on data path 2428 of shift register 2400 of FIG. 24 is observed 2916 for differences from the input data bit pattern, it can be evaluated 2918 whether the AC bias amplitude parameter has been optimized. For example, if a number of different AC bias amplitudes are provided to shift register 2400, data can be compiled indicating which AC bias amplitude is furthest from a value that would cause an error in the output data bit pattern, from which a conclusion can be drawn regarding which AC bias amplitude is optimal. As an example, an AC bias amplitude (e.g., an average value) that is between two extreme values ​​of the AC bias amplitude that are within the operating margin can be selected as the optimal AC bias amplitude. As another example, if the bias tap values ​​of D flip-flops are set in stages to provide different amounts of AC bias per flip-flop, the output data bit stream can be analyzed to determine which D flip-flops failed the AC bias adjustment and which did not, and the optimal AC bias can be determined based on the respective operating margins of the working and failing flip-flops during the test. If insufficient data is collected to draw a conclusion regarding the optimality of the bias parameters, the test can be repeated by resetting the AC bias amplitude to the nominal value (2902), restarting the logic clock (2904), and shifting in the same or a different input data bit pattern (2904), and repeating portions of the test process (2902-2918). This portion of the test process can be repeated iteratively as many times as necessary to be confident that the AC bias amplitude has been optimized (2920) for the AC clock resonator under test (e.g., the I resonator in the example shown in FIG. 24). In some instances, the AC bias amplitude is not optimized, but is improved, for example, from a starting or nominal value.

[0067] 29 is outlined with respect to AC bias adjustment or optimization, similar methods may be used for DC bias adjustment or optimization, or for phase error adjustment or optimization. In DC bias adjustment or optimization, the DC bias value of the bias signal supplied to the D flip-flop may be changed (2908) rather than the AC amplitude value, and in some examples, the transformer coupling strength to the DC bias line of the D flip-flop of the phase-mode shift register under test may be stepped so that multiple flip-flops, each with a different strength of DC bias coupling, are aligned X relative to each other, as shown in FIG. DC 22. In phase error adjustment or optimization, in addition to the AC amplitude value, the phase difference between the I and Q clock signals fed to the D flip-flop can be changed (2908) to produce a two-dimensional X-axis shmoo plot as shown in FIG. AC -X phase A search can be performed in which each D flip-flop is biased by an AC bias signal that is a mixture of the I and Q clock signals. In some examples, the transformer coupling strength to the AC bias lines of the D flip-flops of the phase-mode shift register under test is stepped so that each D flip-flop has a different strength of AC bias coupling to the clock signal of the mixed resonator, causing the flip-flops to have an X bias with respect to each other, as shown in Figure 5A. AC 10 shows different operating margin shmoo plots shifted in dimension.

[0068] While a conventional RQL shift register can travel at least four phases (e.g., 0°, 90°, 180°, and 270°) in all paths, PML shift register 2400 is configured such that logical clock path 2426 is coupled to clock resonator 104 to receive only two phases (90° and 270° in the illustrated example) in logical clock path trunks 2420, 2422, and 2424, and data path 2428 is coupled to clock resonator 104 to receive only two other phases (0° and 180° in the illustrated example). Thus, the trunk of logical clock path 2426 is powered by only one clock resonator (the Q resonator in the illustrated example), and data path 2428 is powered by only the other clock resonator (the I resonator in the illustrated example). This configuration ensures that even if data path 2428 is stressed and fails by varying the bias parameters for one or more shift register elements outside the data path's operating margins, logic clock path 2426 remains functional, thus ensuring that the logic clock signal reaches all flip-flops in shift register 2400, even those that have failed due to bias parameter adjustments. Thus, the phase assignment isolates the operation of the flip-flops to one AC clock resonator, while the logic clocks that drive the flip-flops are isolated to different AC clock resonators. The 0° buffers in branches 2414, 2416, and 2418 in the logic clock path can be considered part of the corresponding flip-flop circuits 2406, 2404, and 2402 for purposes of the above discussion. In the illustrated example 2400, the buffers driving the clock pins of individual flip-flops may be required to be on the same clock phase as the flip-flops.

[0069] Buffers shown in dashed lines in Figure 24, such as buffers 2432, 2434 in logical clock path 2426 and buffer 2436 in data path 2428, may be of a different design than the buffers shown in solid lines in Figure 24. Each of the buffers shown in dashed lines in Figure 24 may include an additional Josephson junction connected to ground at the input of the respective JTL, allowing them to reliably operate at a 180° phase delta from the previous cell. Without this additional Josephson junction, there may be ambiguity as to whether an SFQ pulse waiting at a boundary will propagate in the forward or reverse direction when the AC bias signal supplied to the corresponding buffer increases.

[0070] In another exemplary PML shift register similar to shift register 2400, but not shown, a 90° AC clock phase can be added to all phase values ​​shown in FIG. 24 to provide a bias level sensing configuration that tests the Q clock resonator instead of the I clock resonator. In such an example, the trunk of the logic clock path is driven by the I resonator, and the data path is driven by the Q resonator. In such an example, the “resonator under test” in method 2900 of FIG. 29, and the resonator whose AC amplitude is changed (2908) as part of method 2900, is the Q resonator instead of the I resonator. In another exemplary modification of PML shift register 2400, the JTL-based buffer in the logic clock path can be equipped with an offset bias transformer as shown in and described above with respect to FIG. 6. Such a modification can effectively shift the operating margin of the clock supply, which may allow samples to be taken when the operating logic is closer to the nominal AC bias.

[0071] In other exemplary PML shift registers similar to shift register 2400 but not shown, a 45° or 135° AC clock phase can be added to all phase values ​​shown in FIG. 24 to provide a bias level sensing configuration in which the trunks of the data and logic clock paths receive bias signals that are a mixture of a 0° I clock and a 90° Q clock. For example, the data path can be driven by AC signals of 45° and 225° phase, and the trunks of the logic clock paths can be driven by 135° and 315° signals. As another example, the data path can be driven by AC signals of 135° and 315° phase, and the trunks of the logic clock paths can be driven by 45° and 225° signals. Such an example can be useful for determining the phase error between the I and Q clock signals and for improving or optimizing the phase of the I and Q clocks to true quadrature. In another exemplary modification of PML shift register 2400, the JTL-based buffers in the logic clock path can be equipped with offset bias transformers as shown in and described above with respect to Figure 6. Such a modification can effectively shift the operating margin of the clock supply, which may allow samples to be taken when the operating logic is closer to the nominal AC bias.

[0072] Figure 25 shows an example proximal portion of a configuration 2500 in which pulse generators 2502, 2508 are connected to RQL gates (AND gates 2504, 2510 in the illustrated example) to form a bias level sensor (sampler). A portion of a wrapper for a pulse generator-based bias level sensor is shown in Figure 25, which resembles the ladder configuration shown in Figure 2A, with a repeating circuit pattern of runs (e.g., the first two runs 2512, 2514) and rails (2516, 2518) between a proximal input / output end (shown at the bottom of Figure 25) and a distal end (not shown in Figure 25), with the runs located between the input rail 2516 and the output rail 2518 of the wrapper ladder. The rails 2516, 2518 may extend the entire length of the clock resonators connected by the wrapper, for example. As an example, the wrapper may have approximately 2,000 stages, each with a pulse generator-based sampler that individually samples the clock resonator at a different location along the clock resonator. The JTL, represented as a triangle in FIG. 25, provides the timing delay. A sample signal input 2506 provides an SFQ pulse as a sample signal to the wrapper ladder, which propagates along input rail 2516 (upward in the orientation of FIG. 25), branches and replicates along each stage, and either returns to output OUT along output rail 2518 (downward in the orientation of FIG. 25) or not, depending on whether the individual samplers embedded in the stages of the wrapper ladder are within their operating margins. Thus, in the wrapper shown in FIG. 25, a single sample SFQ pulse provided at input 2506 results in a series of time-separated output SFQ pulses at output OUT.

[0073] Each pulse generator (e.g., pulse generators 2502, 2508) in configuration 2500 comprises a Josephson junction having a first end connected to ground via an inductor and a second end inductively coupled to an AC bias transformer (e.g., via a coupling transformer). The second end substantially provides the pulse generator's output. Each pulse generator outputs an SFQ pulse to its corresponding ladder stage for each cycle of an AC clock driving the pulse generator, provided the pulse generator is driven within its operating range, e.g., provided the amplitude of the AC clock driving the pulse generator is within the pulse generator's AC operating margin. To help reduce the dispersion of the pulse generator's Josephson junctions, the pulse generator's Josephson junctions can be larger in size and therefore have a larger critical current than the Josephson junctions used in the JTLs and gates of the operational RQL circuit 102. The output of each pulse generator is gated by a sample signal via a corresponding gate (e.g., gates 2504, 2510 in FIG. 25). Thus, each pulse generator operates continuously to provide repeated SFQ outputs to its corresponding stage as long as the provided AC bias is within the operating margin of the pulse generator, but only the SFQ outputs generated substantially simultaneously with the arrival of a sample signal pulse on the same stage (e.g., within the same AC clock cycle or half clock cycle) propagate down the output rail 2518 to the output OUT.

[0074] The operating range of each pulse generator in the sensing system of Figure 25 can be individually set, for example, by configuring each pulse generator to have stronger or weaker coupling to one or more AC clock resonators and / or DC bias lines that provide bias (drive) the pulse generator. For example, the X ACShifting (offsetting) the margin allows the pulse generator to start and stop operating in response to varying levels of AC bias provided (varying amplitude of the driving AC clock), and bias point variations that allow sensing can determine those operating levels even while still allowing the operating RQL circuit 102 to stay within its operating margin.

[0075] X AC The margin shift can be implemented in some instances by increasing the critical current of the JJ in the pulse generator. Increasing the critical current of the JJ in the pulse generator in a pulse generator-based sampler is achieved by increasing the X DC -X AC In the plot, this has the effect of shifting the margin shmoo plot of the corresponding sampler upward and to the right, because higher DC and AC bias amplitudes than normal are required to invert the pulse generator's JJ due to the increased critical current. The JJ critical current is increased when the AC and DC biases generated by the pulse generator's bias coupling transformer fall within the margin shmoo plot (operating region) of the operational JTL circuit 102. DC -X AC The bias point may be selected to be the threshold that triggers the pulse generator's JJ every AC clock cycle. For example, the margin shmoo plot (operating region) of the pulse generator-based sampler may be located within the margin shmoo plot of the operational JTL circuit 102, so that the pulse generator-based sampler may be driven into and out of the operating region that generates pulses by varying the bias delivered to both the pulse generator-based sampler and the operational RQL circuit 102, while the bias delivered remains within the operating region of the operational RQL circuit 102, so that the operational RQL circuit 102 continues to function. As with the example of FIG. 2A, the pulse generator-based sampler of FIG. 25 may be driven into and out of the operating region that generates pulses by varying the bias delivered to both the pulse generator-based sampler and the operational RQL circuit 102, so that the operational RQL circuit 102 continues to function. AC and / or X DCThe operating margin offsets may be set in steps, such as linearly along a ladder from the lowest AC margin to the highest AC margin, or from the highest AC margin to the lowest AC margin, or any other arrangement that can be taken into account when evaluating the output. DC The stepwise setting of X is shown in FIG. 25A, for example, by changing the length of the DC portion of the coupling transformer. DC -X AC This may be provided by a substantial left-right shift in space.

[0076] The pulse generator-based sampler of Figure 25 may be disposed on the RQL IC 106 to connect to the clock resonator 104 at various points along the resonator. Although not shown in Figure 25, the input sample SFQ pulse may be provided to the input 2506 using an input transformer coupled to the input 2506 similar to the input transformer 252 shown in Figure 2A, and the output SFQ pulse may be converted to a voltage pulse using an output amplifier coupled to the output OUT similar to the output amplifier 254 shown in Figure 2A.

[0077] The pulse generators in configuration 2500 (e.g., pulse generators 2502, 2508) are sensitive to manufacturing variations in the JJs that comprise them, as well as variations in the clock resonators and coupling transformers, but are relatively less sensitive to other circuit parameters than JTL or gate-based samplers that have large self-inductances, such as those discussed above with respect to FIGS. 6, 8A, 9A, 10A, 11A, 12, 13, 16, and 18. For example, the pulse generator-based sampler of FIG. 25 is not particularly sensitive to variations in the inductance of the circuit side of the ground plane in RQL IC 106. Thus, configuration 2500 is particularly well suited for evaluating the performance of clock resonators and coupling transformers, and is useful, for example, in evaluating the self-inductance of coupling transformers, the mutual inductance between coupling transformers and the clock resonators to which they are coupled, and the magnitude of currents in the clock resonators.

[0078] The pulse generators in configuration 2500 may be configured to measure a specific I (Q-independent) or a specific Q (I-independent) reading by coupling the sampler to an appropriate clock bias resonator, as described above with respect to FIGS. 12, 13, 16, and 18 and listed in Table 1. The pulse generators in configuration 2500 may also be configured to measure the phase difference between the I and Q clocks (in some examples, with the AC bias amplitudes first calibrated for both the I and Q clock bias signals), which may be measured by driving multiple pairs of pulse generators in a single wrapper, or by driving multiple pulse generators in different wrappers with a mixed clock signal separated by 90°, for example, a first pulse generator (or a first pair in a first wrapper of a pulse generator-based bias level sensor). This can be achieved by clocking one pulse generator (or the first set of pulse generators in the first wrapper of the pulse generator-based bias level sensor) at 45° and clocking the second pulse generator (or the second set of pulse generators in the second wrapper of the pulse generator-based bias level sensor) at 135°, or by clocking the first pulse generator (or the first set of pulse generators in the first wrapper of the pulse generator-based bias level sensor) at 225° and clocking the second pulse generator (or the second set of pulse generators in the second wrapper of the pulse generator-based bias level sensor) at 315°. The outputs of the pulse generators driven at 45° and 135° (or pulse generators driven at 225° and 315°, etc.) will be equal only if the phase difference between the two driving clocks is 90° and the AC amplitudes of the AC signals provided by the I and Q clock resonators are equal. This mixed clock setup can therefore be used to determine the true quadrature phase between the I and Q clock signals and can be used to inform or direct adjustments to the I and Q clock phases, or adjustments to the phase difference between the I and Q clock phases, to improve or optimize the orthogonality for a 90 degree phase difference between the I and Q clocks.As an example, the process described with reference to FIG. 30 can be used in configuration 2500 to determine the optimal phase difference between the I and Q clocks at which to drive them in the warm space to achieve true quadrature (90° phase separation) between the clocks in the operating RQL circuit 102 on the RQL IC 106 in the cooled space.

[0079] FIG. 26A shows an example configuration of samplers 2602-2610 arranged in a DC SQUID-based bias level sensor 2600. The samplers 2602-2610 can be based on JTL or RQL gates, as described above with respect to FIG. 6, and can comprise one or more sampler stages in series with each other, as described above with respect to FIGS. 15 and 21. The samplers 2602-2610 act as triggers for the DC SQUIDs 2612-2620. Each sampler 2602-2610 controls its parameter (X ) so that when an input pulse is applied to the sample signal input on the left side of FIG. 26A, the number of DC SQUIDs 2612-2620 activated in the stack varies depending on the bias level supplied to the sampler 2602-2610. AC or X DCOne of the DC SQUIDs 2612-2620 is configured to bias one of the DC SQUIDs 2612-2620 in a stepwise fashion. Thus, the voltage level of the output pulse generated by the stack of DC SQUIDs 2612-2620 varies depending on the bias level applied. Thus, configuration 2600 can be considered a single bias level sensor, with a voltage output that varies depending on the number of individual samplers 2602-2610 biased within their operating region when a sample signal pulse is applied to the sample signal input. The output voltage may be indicative of the sensed bias parameter (AC bias amplitude or DC bias value) that sensor 2602 is configured to measure, given the appropriate stepwise configuration of the bias coupling strengths of sensors 2600-2610, as described above with respect to FIGS. 4A and 5A, for example. Because sensor 2600 can measure the outputs of individual sensors 2602-2610 in parallel and simultaneously, sensor 2600 may have a higher output throughput than the configurations of FIGS. 2A-2C. The sensor 2600 generates an output voltage pulse each time an input SFQ pulse is applied to the sample signal input, which may be as frequent as once per AC clock cycle.

[0080] Each DC SQUID 2612-2620 in the DC SQUID stack of sensor 2600 receives input from a respective sampler 2602-2610 via a respective transformer coupling to the DC SQUID. Each respective transformer coupling is shown in FIG. 26A as a dashed line between each sampler 2602-2610 and the respective DC SQUID 2612-2620 that is transformer coupled to the sampler. Each sampler can be, for example, a JTL. The JTL adjusts the desired X from the nominal AC A separate AC offset inductor L is used to provide both the offset (as shown in FIG. 3) and the desired step setting (sampler-to-sampler variation). offsetACThe sizes of the samplers 2602-2610 are adjusted. In the example of FIG. 26A, the DC SQUID stack is shown as including multiple stages (five samplers 2602-2610 and five corresponding DC SQUIDs 2612-2620), but in other examples, the stack can include more or fewer stages (more or fewer samplers and corresponding DC SQUIDs), with more stages providing finer resolution of the output voltage signal or allowing for sensing of multiple bias parameters. For example, some of the samplers 2602-2610 can be configured to sense AC bias amplitude and other samplers can be configured to sense DC bias values, or some of the samplers 2602-2610 can be configured to sense AC bias amplitude of one clock resonator, I or Q, or some combination of clock signals, and other samplers can be configured to sense AC bias amplitude of a different clock resonator or some different combination of clock signals. In different examples, the structure of sensor 2600 of FIG. 26A can have 5 to 10 stages.

[0081] A sample signal input may be provided to each of the samplers 2602-2610, for example, via a binary vine tree (not shown) of a JTL, such that the sample signal arrives at each of the samplers 2602-2610 substantially simultaneously in some examples. Similar to the examples described above (e.g., the examples of FIGS. 2A and 25), the samplers may use the variation in mutual inductance for individual AC resonators or DC bias lines measured by the individual samplers to calculate X AC Shift and / or X AC Staged setting and / or X DC The DC bias current I, which is insufficient by itself to trigger any of the SQUIDs 2612-2620, can be set in stages. BIASOUT is supplied between OUTP and OUTN to bias the SQUID stack so that the current provided by the input sample pulse distributed to SQUIDs 2612-2620 via samplers 2602-2610 is sufficient to trigger the individual SQUIDs. BIASOUTcan be supplied external to the RQL IC 106 in which the sensor 2600 is implemented, and the voltage signal between OUTP and OUTN is made available at a pad on the RQL IC 106, so that the signal from the sensor of FIG. 26A can be available for direct measurement by external test equipment, for example, and no logic is required to process or interpret its output.

[0082] In the example shown in FIG. 26A, five samplers 2602-2610 are represented by the values ​​X AC1 ~X ACN X due to AC amplitude margin variation given by AC For example, a resonator clock network can be fabricated on the RQL IC106 to operate under the samplers 2602-2610, with different AC offset inductors L offsetAC can be provided for each sampler 2602-2610 to cross-couple power to the individual samplers based on the I and Q bias signals required for the clock phase desired to be provided to the sampler. AC The value indicates the nominal bias level of the sampler, and X AC The variations in value represent greater or lesser AC bias levels coupled to the sampler. Figure 26A shows X values ​​of 75%, 87.5%, 100%, 112.5%, and 125%. AC The values ​​are shown as an example of a linearly stepped configuration of five sampler configurations as shown in Figure 26A. In operation, when a sample signal input pulse is applied to the sensor 2600, the magnitude of the bias level applied to all samplers 2602-2610 can be externally varied, with different strengths of bias to each of the samplers 2602-2610 resulting in different numbers of SQUIDs 2612-2620 contributing to the potential difference between the output voltage terminals OUTP and OUTN depending on how many samplers are operating under the bias conditions provided.

[0083] For example, the sampler 2610 may generate an AC offset inductor L of suitable inductance value.offsetAC 125% X due to being configured to be biased through AC The sampler 2610 with a value of 1000 requires a higher AC bias level to transfer the input sampler pulse to its corresponding DC SQUID 2620, while the sampler 2602 has a smaller AC offset inductor L offsetAC 75% X due to the fact that it is configured to be biased through AC The sampler 2602 with a value requires a relatively low AC bias level to operate. In contrast, a 75% X AC The sampler 2602 with the value 125% of X AC Even if the sampler 2610 with the value cannot continue to operate (because the AC bias level is below and therefore outside its operating region), it can continue to operate at a higher bias current (because a higher supply bias current is within its operating region).

[0084] For example, in configuration 2600 of Figure 26A, if each SQUID 2612-2620 generates a potential difference of approximately 0.5 mV when activated by a corresponding operating sampler 2602-2610, the voltage output between OUTP and OUTN is approximately 2.5 mV when the applied bias levels are within the respective operating regions of all samplers 2602-2610. This output voltage decreases when fewer than all of the samplers 2602-2610 are biased within their respective operating regions. For example, the output voltage of the configuration 2600 may be approximately 2 mV when only four samplers 2602-2610 are operating at the applied bias level, approximately 1.5 mV when only three samplers 2602-2610 are operating at the applied bias level, approximately 1 mV when only two samplers 2602-2610 are operating at the applied bias level, approximately 0.5 mV when only one of the samplers 2602-2610 is operating at the applied bias level, and approximately 0 mV when none of the samplers 2602-2610 are operating at the applied bias level. In the five stage example of FIG. 26A, the AC bias amplitude can be considered calibrated when the amplitude is changed to obtain approximately three-fifths of the maximum output voltage pulse height. In the five-stage example of FIG. 26A, the AC bias amplitude can be considered calibrated if samplers 2602 and 2604 are within their operating range and therefore provide split input sample signals to their corresponding SQUIDs 2612, 2614, samplers 2608 and 2610 are outside their operating range and therefore do not provide split input sample signals to their corresponding SQUIDs 2618, 2620, and sampler 2606 is exactly within its operating range and therefore provides split input sample signals to its corresponding SQUID 2616.

[0085] The operational RQL circuit 102 of FIG. 1 provides an output bias current I at an appropriate current level. BIASOUT26A, which may require biasing at a current level that may vary with variations in circuit fabrication process and / or system setup. BIASOUT The applied level of the output bias current I BIASOUT The output bias current I can be used to sense how well it meets the requirements of the output amplifier to which it is applied. BIASOUT 26B illustrates an exemplary DC SQUID-based output amplifier 2650 configured as a level sensor. The configuration 2650 of FIG. 26B is similar to the configuration 2600 of FIG. 26A, but with the addition of AC offset inductors L of the corresponding samplers 2602-2610. offsetAC The inductance values ​​of the standard bias samplers 2652 to 2660 are not set in stages, but rather the self-inductances of the standard bias samplers 2652 to 2660 are set to have the same value (for example, the AC offset inductor L offsetAC Instead, the critical currents Ic of the JJs of the corresponding DC SQUIDs 2662-2670 are stepped to individual offsets relative to a nominal value. In the exemplary configuration 2650 shown in FIG. 26B, the JJ of SQUID 2666 is stepped to a nominal value (I C3 = 100%), while other SQUIDs in the stack have lower critical currents (e.g., SQUIDs 2662 and 2664 each have a critical current I C1 =75% and I C2 = 87.5% J) or higher critical current (e.g., SQUID 2668, 2670 have critical current I C4 =112.5% ​​and I CN = 125% JJ). Similar to the example shown in Figure 26A, the example of Figure 26B can have more or fewer DC SQUIDs in its DC SQUID stack, with more stages providing finer output voltage signal resolution.

[0086] In the example 2650 of FIG. 26B, an output bias current I is supplied between the output terminals OUTP and OUTN. BIASOUTcan be varied to determine the optimum DC bias on the bias line of the output amplifier, i.e., the optimum bias current for SQUIDs 2662, 2664, 2666, 2668, and 2670. For example, if a five SQUID stack is used as shown in FIG. 26B, the output bias current I of the output amplifier can be varied to obtain approximately three-fifths of the full output voltage pulse height with each sample SFQ pulse provided to the sample signal input. BIASOUT 26B does not separate the respective effects of AC and DC bias on the samplers 2652-2660 that trigger the SQUIDs 2662-2670 or other JTLs in the circuit. The example configuration 2650 may, for example, vary the output bias current I BIASOUT can be used to calibrate X AC and X DC is first independently adjusted, improved, or optimized, and the output bias current I of the output amplifier is BIASOUT can then be adjusted, improved, or optimized.

[0087] Because the power amplifier-based configurations 2600, 2650 of FIGS. 26A and 26B instantaneously indicate the number of active samplers in the configuration for each provided sample signal, these configurations improve output throughput of bias level detection compared to RQL scan register configurations such as those of FIGS. 2A or 25, ring oscillator configurations such as those of FIG. 2C, or PML shift register configurations such as those of FIG. 24, each of which may require a longer time than the power amplifier-based configuration to provide a complete output indicative of the bias parameter being sensed. In some examples (not shown), different amounts of time delay can be added to each branch of the power amplifier-based configurations 2600, 2650 of FIGS. 26A and 26B to enable time division multiplexing (e.g., by adding different numbers of additional standard bias JTLs to the samplers in each branch of the power amplifier-based configurations 2600, 2650 of FIGS. 26A and 26B). For example, phase shifts can be added in 90° increments or 45° increments. In one example, each branch of the output amplifier structure 2600 or 2650 of FIG. 26A or FIG. 26B has a time delay (e.g., from top to bottom) to assign a phase of 0°, 45°, 90°, 135°, 180°, etc. This exemplary configuration provides a time-based step function signal at the output, which either increases or does not increase by 0.5 mV increments with each time step depending on whether the SQUID in the corresponding stage of the output amplifier configuration was induced to operate, which in the example of FIG. 26A depends on whether the corresponding JTL-based sampler 2602-2610 is within its operating range. The time-shifted outputs can then be used to identify which of the samplers 2602-2610 delivered a signal to and triggered the corresponding SQUID 2612-2620.

[0088] A serial output ladder wrapper (RQL scan register) structure such as that of FIG. 2A can also be used to calibrate the output bias current of an output amplifier by implementing its bias level sensors 202-212 as output amplifier emulators. A JTL-based bias level sensor configured as an output amplifier emulator can have the following distinctive properties. First, each bias level sensor configured as an output amplifier emulator can ensure that the AC bias transformer(s) of the corresponding JTL(s) can be coupled to the clock resonator via a lower-than-standard mutual inductance. Second, each bias level sensor configured as an output amplifier emulator can ensure that the DC bias transformer(s) of the corresponding JTL(s) can be coupled to the output amplifier's output bias current (I in FIG. 26B) rather than to a separate DC bias line. BIASOUT ) in the output amplifier of the RQL IC 106. Each output amplifier emulator thus derives its DC bias from the output bias line of the output amplifier of the RQL IC 106. Third, the sensitivity of the JTL in each output amplifier emulator to the output bias current of the output amplifier can be set to be similar to the sensitivity of the SQUID in the output amplifier that the output amplifier emulator is configured to emulate. For example, the JJ in the JTL of the output amplifier emulator can be sized to have a critical current that approximates the critical current of the JJ in the DC SQUID of the output amplifier that the output amplifier emulator is configured to emulate. When the bias level sensors 202-212 of the series output ladder configuration 200 of FIG. 2A are configured as output amplifier emulators having the above three characteristics, the pulse count provided at the output of the ladder configuration 200 configured with the output amplifier emulator as the bias level sensor 202-212 indicates how well the output amplifier's output bias current is adjusted to the SQUID in the output amplifier that the output amplifier emulator is configured to emulate.

[0089] As described above with respect to the bias level sensing configurations configured to calibrate the AC bias amplitude or DC bias value, the mutual inductance of each bias level sensor configured as an output amplifier emulator with respect to the output bias line of the output amplifier is adjusted so that each output amplifier emulator has a desired X OA 2A , if each bias level sensor 202-212 is implemented as an output amplifier emulator, output amplifier emulator 202 can have a lower mutual inductance to the output bias line of the output amplifier than output amplifier emulator 204, which can have a lower mutual inductance to the output bias line of the output amplifier than output amplifier emulator 206, and so on for each stage in wrapper ladder configuration 200. Thus, changing the output bias of the output amplifiers causes more or fewer output amplifier emulators 202-212 to generate pulses, changing the pulse count at the serial output of the wrapper.

[0090] With respect to the example of the output amplifier emulator described above, the output bias current of an output amplifier can be adjusted, improved, or optimized by directly observing the output of the output amplifier without using the output amplifier emulator. Such variations in the output bias current of the output amplifier when directly observing the output amplifier's output may require varying the output bias current of the output amplifier over a range that may include disabling the output amplifier being observed. After the optimal bias is determined by such a method, pulse counts from the serial output wrapper ladder sensor with bias level sensors 202-212 configured as the output amplifier emulator can be recorded and used to maintain the optimal output amplifier output bias current, even while the output amplifier is continuously operating. This is possible because the output amplifier's output bias current is maintained within the operating range of the emulated output amplifier. In such cases, the output amplifier emulator does not need to emulate the critical current characteristics of the JJ of the SQUID of the emulated output amplifier, i.e., the output amplifier emulator does not need to be configured to meet the third characteristic described above.

[0091] Figures 27A and 27B show example feedback systems 2700, 2750 that may be used to sense and tune the AC amplitude (Figure 27A) and phase (Figure 27B) of the I-clock and Q-clock. In each of Figures 27A and 27B, two RQL bias level sensors 2702, 2704, 2708, 2710 may be implemented as shown in Figure 26A or 26B. The sensors 2702, 2704, 2708, 2710 may be implemented as all or part of the sensor 118 on the RQL IC 106 in the cooling space.

[0092] In the example shown in FIG. 27A , the first sensor 2702 is powered by the 90° clock (Q clock). The second sensor 2704 is powered by the 0° clock (I clock). The AC bias amplitudes supplied to the I and Q clocks can be sensed simultaneously by the two sensors 2702, 2704. The outputs OUTPQ, OUTPI of the sensors 2702, 2704 have the form of a voltage pulse train whose voltage amplitude varies over time. The pulses of the pulse train can be configured to be generated, for example, once per AC clock cycle. The individual output signals OUTPQ, OUTPI provided by the sensors 2702, 2704 are each of sufficiently large voltage amplitude so that they can be analyzed by AC amplitude adjustment logic 2706, which can be provided, for example, as part of a feedback loop 122 to the bias signal generator(s) 110 located outside the cooling space. The AC amplitude adjustment logic 2706 can be implemented, for example, in conventional semiconductor circuitry (e.g., CMOS circuitry). A third input to the AC amplitude adjustment logic 2706, labeled AMPREF, provides an AC or DC signal representing the desired ideal nominal level to be provided from the two sensors 2702, 2704. An output QOUT at the top of the logic 2706 directs a change in the output of the clock source for the Q clock (the 90° clock source), an output IOUT at the bottom of the logic 2706 directs a change in the output of the clock source for the I clock (the 0° clock source), and an amplitude reference signal AMPREF describes or represents the level to which the clock sources should be regulated. The reference signal AMPREF may, for example, represent the height of the pulses generated by the sensors 2702 and 2704.

[0093] The AC amplitude adjustment logic 2706 may be configured to perform a voltage comparison of the provided bias sense signals OUTPQ, OUTPI and generate one or more control signals based on the comparison of the OUTPQ and OUTPI signals. For example, if the AC amplitudes of the 0° I clock and the 90° Q clock sensed on the RQL IC 106 by the sensors 2702, 2704 are close to or coincide with the optimal AC bias point 306, the outputs OUTPQ, OUTPI of the sensors 2704, 2702 will be equal and the outputs QOUT, IOUT of the logic 2706 will not direct a change in the AC amplitude of either of the clocks 112, 114. However, if the AC amplitudes of the 0° I clock and the 90° Q clock sensed on the RQL IC 106 by sensors 2702, 2704 are different, or if either does not match the optimal AC bias setting for the corresponding clock, then the outputs OUTPQ, OUTPI of sensors 2704, 2702 will not be equal and one or both of the outputs QOUT, IOUT of logic circuit 2706 will indicate a change in the AC amplitude of either clock 112, 114.

[0094] Following the AC amplitude calibration of the I and Q clocks performed by the configuration of Figure 27A, the configuration of Figure 27B can be used to sense and calibrate the relative phase of the I and Q clocks to ensure a 90° phase difference between the I and Q clocks supplied to the operating RQL circuit 102 on the RQL IC 106 in the cooled space. The bias level sensor configuration of Figure 27B is structurally identical to the configuration of Figure 27A, except that the first sensor 2708 of Figure 27B is supplied with a 45° clock formed by connecting both the I and Q resonators, rather than a 90° clock formed by connecting only the Q resonator as in sensor 2702 of Figure 27A, and the second sensor 2710 of Figure 27B is supplied with a -45° (315°) clock formed by connecting both the Q and I resonators, rather than a 0° clock formed by connecting only the I resonator. The clock signal generated by the 45° or 135° transformer on the RQL IC 106 depends on both the phase difference and amplitude of the I and Q clocks. Phase mismatch between the I and Q clocks at the RQL IC 106 level in the cooling space can cause AC amplitude variations in the 45° and 135° signals. As shown in FIG. 27B, by powering the sampler in the sensor 2708 with a 45° clock, the output voltage mismatch between the 45° sensor 2708 output OUTPIQ and the -45° sensor 2710 output OUTPQI indicates a phase difference between the I and Q clocks that is different from 90°. This is because, once the AC amplitudes of the I and Q clocks are equal, the only factor that can cause an output voltage difference in such sensors is a phase error between the clocks.

[0095] Thus, the AC phase adjust logic 2712 may be configured to perform a voltage comparison of the provided bias sense signals OUTPIQ, OUTPQI and generate one or more control signals based on the comparison of the OUTPIQ and OUTPQI signals. For example, if the phase error between the 0° I clock and the 90° Q clock sensed on the RQL IC 106 by the sensors 2708, 2704 indicates true quadrature (exactly 90° phase difference), then the outputs OUTPIQ, OUTPQI of the sensors 2708, 2710 will be equal and the outputs QOUT, IOUT of the logic 2712 will not command a change in the AC phase of either of the clocks 112, 114. However, if the phase error between the 0° I clock and the 90° Q clock sensed on the RQL IC 106 by sensors 2708, 2702 is different, the outputs OUTPIQ, OUTPQI of sensors 2708, 2710 will not be equal and one or both of the outputs QOUT, IOUT of the AC phase adjustment logic 2712 will indicate a change in the phase of either clock 112, 114.

[0096] The power amplifier-based structures of Figures 26A and 26B have the advantage of being able to generate relatively large output voltages at relatively high throughputs, which can be used to adjust AC amplitude and phase and tune the resonator clock, as shown in Figures 27A and 27B.

[0097] 28 illustrates an example optimization method 2800 that may be used to calibrate a bias signal, for example, to or near an ideal calibration, using one or more configurations of bias level sensors. AC The signal is input to a sampler wrapper having a sampler (2802). By way of example, the wrapper can be a serial-output RQL scan register as shown in FIG. 2A or FIG. 25, a parallel-output configuration as shown in FIG. 2B, a ring oscillator as shown in FIG. 2C, a DC SQUID-based configuration as shown in FIG. 26A or FIG. 26B, or a PML shift register configuration as shown in FIG. 24. ACThe sampler may be, by way of example, a JTL-based or RQL-gate-based sampler such as that shown in FIG. 6, a shift register-based sampler such as that shown in any of FIGS. 8, 9, 10, 11, 12, 13, 16, or 18, a PML flip-flop-based sampler such as that shown in FIG. 24, or a pulse generator-based sampler such as that shown in FIG. 25. AC The sampler output may be observed (2804), for example, by a circuit that counts pulses in the output pulse train generated by the sampler wrapper, such as the pulses shown in FIGS. 4A-4D, in the case of a serial pulse output by a wrapper such as that shown in FIG. 2A; by a circuit that compares the input pulse stream to the output pulse stream, in the case of a PML shift register configuration such as that shown in FIG. 24; or by a voltage comparison circuit, in the case of a DC SQUID-based configuration such as that shown in FIG. 26A or 26B, which outputs voltage pulses having values ​​on the order of millivolts. The circuit that observes the bias level sensor output may be a conventional semiconductor circuit (e.g., a CMOS circuit) operating in the warm space of the system 100 and need not be implemented on the RQL IC 106 or otherwise in a cooled space. Observation (2804), in some examples, may be performed by a human user using a human-in-the-loop feedback technique, where the human user monitors the X AC The sampler output is observed (2804), optimization decisions are made (2806), and the AC clock amplitude is manually varied (2808).

[0098] As an example, X AC Two or more of the samplers (AC bias samplers) include at least one JTL or pulse generator with a weakened AC clock resonator bias tap to the AC clock resonator of the RQL IC compared to the AC clock resonator bias tap of the JTL in the operational RQL circuit 102. A weakened AC clock resonator bias tap means that a larger amplitude AC bias signal is required to drive the JTL or pulse generator within its respective AC operating margin, thus increasing the X of the AC bias sampler.DC -X AC The margin shmoo plot is shifted upward relative to the margin shmoo plot of the operational RQL circuit 102, for example, as shown in FIG. AC Two or more of the samplers include pulse generators having Josephson junctions with critical currents greater than the Josephson junctions in the operational RQL circuit.

[0099] X AC Based on the observation of the sampler output (2804), it may be evaluated whether the AC bias amplitude parameter has been optimized (2806). For example, if a number of different AC bias amplitudes are provided to the sampler wrapper, data may be compiled indicating which AC bias amplitude produces optimal or near-optimal output results. For example, an X 0 bias with a linearly stepped AC operating margin offset may be used. AC For the serial output wrapper of FIG. 2A with bias level sensors, a moderate number of X AC When the sampler is operational, optimal results are produced. If insufficient data has been collected to draw such a conclusion, the AC clock amplitude of the AC clock resonator under test may be changed to a different value (2808) and a new sample signal may be input (2802). Portions of this process (2802-2808) may be repeated iteratively as many times as necessary to provide confidence that the AC bias amplitude has been optimized (2810) for the AC clock resonator under test (e.g., I resonator or Q resonator). In some exemplary methods similar to method 2800, the AC bias amplitude is not optimized at 2810, but is improved. The improvement in AC bias amplitude may be indicated by a value X indicating results consistent with the AC clock amplitude provided at 2808 approaching the optimal bias point 306 for the operational RQL circuit 102. AC This can be determined by observing the sampler output (2804).

[0100] After the AC bias signal is calibrated at 2098, the process 2800 may continue to calibrate the DC bias. DCThe sampler is input to a sampler wrapper with a sampler 2812. The wrapper can be the same wrapper or a different wrapper than the wrapper used to calibrate the AC bias amplitude in the AC bias calibration portion of method 2800. X DC The sampler may similarly be of the types listed and described above. DC The sampler output may be observed (2814), for example, by a circuit that counts pulses in the output pulse train generated by the sampler wrapper, such as the pulses shown in FIGS. 4A-4D, in the case of a serial pulse output by a wrapper such as that shown in FIG. 2A; by a circuit that compares the input pulse stream to the output pulse stream, in the case of a PML shift register configuration such as that shown in FIG. 24; or by a voltage comparison circuit, in the case of a DC SQUID-based configuration such as that shown in FIG. 26A or 26B, which outputs voltage pulses having values ​​on the order of millivolts. The circuit that observes the bias level sensor output can be a conventional semiconductor circuit (e.g., a CMOS circuit) operating in the warm space of the system 100 and need not be implemented on the RQL IC 106 or otherwise in a cooled space. Observation 2814 may also be performed by a human user using a human-in-the-loop feedback technique, where the human user can monitor the X DC The sampler output is observed (2814), optimization decisions are made (2816), and the DC bias value is manually varied (2818).

[0101] X DC Based on the observation of the sampler output (2814), it may be evaluated whether the DC bias value parameter has been optimized (2816). For example, if a number of different DC bias values ​​are provided to the sampler wrapper, data may be compiled indicating which DC bias value produces optimal or near-optimal output results. X with linearly stepped DC operating margin offsets DC For the serial output wrapper of FIG. 2A with a bias level sensor, for example, the mid-offset range X DCOptimal results are produced when only the sampler is operating. If insufficient data has been collected to draw such a conclusion, the DC bias value supplied to the DC bias line under test may be changed to a different value (2818) and a new sample signal may be input (2812). Portions of this process (2812-2818) may be repeated iteratively as many times as necessary to provide confidence that the DC bias value has been optimized (2820) for the DC bias line under test. Thus, both the AC and DC bias signals are calibrated (2820). Calibration method 2800, or any portion thereof, may, in some examples, be performed while the operational RQL circuit 102 is continuously operating, even while its bias parameters are being adjusted, improved, or optimized. In some exemplary methods similar to method 2800, the DC bias value is improved even if it is not optimized in 2820. The improvement in the DC bias value is indicated by an X, which indicates results consistent with the DC bias value provided in 2818 approaching the optimal bias point 306 of the operational RQL circuit 102. DC This can be determined by observing the sampler output (2814).

[0102] The PML-based optimization method 2900 of Figure 29 is described above in connection with the description of the PML shift register structure shown in part in Figure 24. While the illustrated and described method 2900 relates to calibrating the AC bias amplitude, method 2900 may be modified to provide for calibration of the DC bias value, i.e., by using various PML shift register element flip-flops with graduated DC bias operating margin offsets (e.g., by fabricating flip-flop bias transformers with different, e.g., graduated, DC bias line-coupled transformer lengths), stopping the logic clock (2906), changing the DC bias value rather than the AC amplitude (2908), advancing a single clock cycle (or half cycle) (2910), and restarting the logic clock (2914), observing the output data bit pattern (2916), and then calibrating the X AC X, not optimization DC This is fixed by checking optimization (2918).

[0103] 30 shows an example optimization method 3000 that can be used to calibrate the phase difference between different AC clock bias signals, e.g., between the I clock and the Q clock. In some examples, the AC amplitudes of the I and Q clocks are first calibrated 3002, 3004 independently of each other, which can be done using either method 2900 or 2900, for example, by using a bias level sensor that is I clock independent or Q clock independent, as shown in FIG. 12, 13, 16, 18, or 24. In method 3000, a sample signal, e.g., an SFQ pulse or a reciprocal pulse pair, is calibrated using the X phase Sampler or multiple X phase The signal is input to a sampler wrapper having a sampler (3002). The wrapper can be a serial output RQL scan register as shown in FIG. 2A or FIG. 25, a parallel output configuration as shown in FIG. 2B, a ring oscillator as shown in FIG. 2C, or an output amplifier-based configuration as shown in FIG. 26A or FIG. 26B (e.g., configured as shown in FIG. 27B). X phase The sampler(s) can be, for example, a JTL-based sampler as shown in Figure 21, with four mixed-resonator clock inputs that are 90° out of phase with each other. phase The most weakly biased JTL or gate in the sampler is X phase The minimum AC operating point (X ACmin ) is defined as X phase The sampler output may be observed, for example, by circuitry that counts pulses in the output pulse train produced by the sampler wrapper 3004. Such circuitry may be conventional semiconductor circuitry (e.g., CMOS circuitry) that operates within the warm space of system 100 and need not be implemented on RQL IC 106 or otherwise within the cooled space.

[0104] X phaseBased on the observation of the sampler output (3004), it may be evaluated whether the clock phase difference parameter has been optimized (3006). For example, multiple clock phase difference values ​​may be found in one or more X values ​​in the sampler wrapper over multiple AC bias amplitudes in a two-dimensional search. phase When provided to the sampler, data can be compiled that indicates which clock phase difference values ​​produce optimal or near-optimal output results. For example, X phase When the sampler 2000 is used, X phase The lower limit of the Sampler 2000 operating margin is X ACmin (X phase The lowest AC bias amplitude at which the Sampler 2000 continues to operate is ACmin Optimal results are produced when the phase error is lowest over a range that depends on the phase error at the point. As another example, X at a particular I or a particular Q as shown in FIG. 12, FIG. 13, FIG. 16, or FIG. 18 AC If a sampler is used, the X of the particular sampler, as shown at point 1902 in Figure 19, ACmin The phase error dependence plot of X for a particular Q sampler ACmin Optimal results are produced when the phase error is such that it intersects the phase error dependence plot of . As another example, an X oscilloscope with mixed resonator clocks spaced 90° apart, such as a 45° clock sampler and a 135° sampler, AC If a sampler is used, the X of the first mixing resonator sampler is ACmin The phase error dependence plot of X for the second mixing cavity sampler is fed with an AC bias signal that is 90° out of phase with the AC bias signal fed to the first mixing cavity sampler. ACmin The best results are produced when the phase error is such that it intersects the phase error dependence plot of .

[0105] X phase If insufficient data was collected to draw a conclusion that the value was optimized, X AC and X phaseMore data can be collected by performing a two-dimensional search of the values ​​of each X phase For the value, X AC Varying the X of the phase sampler(s) ACmin X AC If the sweep is not complete for the current X phase value (3008), a different X AC To provide an input value to the phase sampler(s), the AC amplitude of the applied bias (whether the I clock resonator, the Q clock resonator, or both) is changed (3010) and a new input sample signal is provided to the sampler wrapper (3002). The AC sweep portion 3002-3010 of the process is phase X for the phase sampler(s) relative to the value ACmin This can be repeated until the X for the phase sampler is determined for the current phase difference between the I and Q clocks. ACmin Once X is found, the phase difference between the I and Q clocks can be changed to a different value (3012) and a new sample signal can be input (3002). phase The process portion 3002-3012 of the sweep is the X of the phase sampler(s). ACmin The number of times required to find X required to provide confidence that the clock phase difference has been optimized for the AC clock resonator under test (3014) phase It can be repeated as many times as the number of values ​​of X. AC Sweep and X phase The sweep does not have to be a linear sweep, for example, a binary search process can be used to search for each X phase X in value ACmin and X phase X as a function of ACmin X where is minimum phase X ACmin , or the phase offset at which X is smallest (e.g., point 2302 in FIG. 23 using phase sampler 2000 in FIG. 20), or the X ACThe phase offset where the plots intersect (e.g., points 1902 or 2202 in Figures 19 and 22, respectively) indicates the optimum phase offset between the I and Q clocks in the warm space, at which the clocks should be driven to obtain true quadrature (90° separation) in the operating RQL circuit 102 on the RQL IC 106 in the cold space. DC Level: X ACmin Therefore, X AC Similarly to X DC By searching for the value of X AC Once the minimum of is found, X DC The optimum value of will also be found.

[0106] FIG. 31 illustrates an exemplary optimization method 3100 that can be used to calibrate I and Q clock AC amplitude parameters and I and Q clock phase parameters to optimize the clock bias signal delivered to the RQL IC 106, for example, using the output amplifier-based sensor 2600 or 2650 shown in FIGS. 26A and 26B and the two-sensor feedback system shown in FIGS. 27A and 27B. First and second sensors are driven with I and Q clock signals, respectively (3102). Each sensor may be supplied with a sample signal, e.g., an SFQ pulse, at a corresponding input and may provide an output voltage signal at a corresponding output. The outputs of the first and second sensors may be compared (3104). The comparison 3104 may be performed, for example, outside the cooled space in which the RQL IC 106 resides, for example, by a conventional semiconductor circuit (e.g., a CMOS circuit) configured to receive the output voltage signals of the first and second sensors and perform the comparison 3104. Based on the comparison (3104) of the outputs of the first and second sensors, and in some examples further based on the reference signal, it may be evaluated (3106) whether the AC clock amplitude parameters of the I and Q clocks have been optimized. For example, if the comparison (3104) indicates that there is no difference between the sensor outputs (e.g., OUTPQ and OUTPI in FIG. 27A ) of the first and second sensors and that both outputs are within an acceptable range of values ​​indicated by the reference signal, it may be determined that the AC amplitude parameters are calibrated (3110), and method 3100 may proceed to calibrating the phase error between the I and Q clocks. However, if the comparison (3104) indicates a difference between the sensor outputs, one or both of the AC clock amplitudes for the I and Q clocks may be changed (3108), for example, based on the output of a comparison circuit in the room temperature space, and the outputs of the first and second sensors may be re-compared (3104). Portions 3102-3108 of this process may be repeated iteratively as many times as necessary to provide confidence that the AC clock amplitudes of the I and Q clock signals have been optimized (3110).

[0107] Once the AC clock amplitudes of the I and Q clock signals have been optimized (3110), the first and second sensors may be biased with 90° phase-separated clock signals formed from a mix of the I and Q resonator signals. For example, the first sensor may be driven with a 45° AC clock signal, and the second sensor may be driven with a −45° (315°) AC clock signal. The mixed resonator AC clock signal may be formed according to Table 1 above. The first and second sensors driven with the 90° phase-separated mixed resonator clock signal (3112) may be the same sensors as the sensors driven with the I and Q clock signals (3102) (in which case a mechanism is provided for switchably coupling those sensors to different resonators or combinations of resonators), or one or both may be different from the sensors driven with the I and Q clock signals (3102). As an example, a first sensor (e.g., sensor 2710 of FIG. 27B) may be driven 3112 with a nominal -45° clock signal (e.g., by transformer coupling the first sensor to both the Q and I clock resonators), and a second sensor (e.g., sensor 2708 of FIG. 27B) may be driven 3112 with a nominal 45° clock signal (e.g., by transformer coupling the second sensor to both the I and Q clock resonators). In another example, the 90° phase-separated clock signals biasing the first and second sensors may be pure I and Q clock signals, respectively (e.g., 0° and 90°, 90° and 180°, or 180° and 270°). A method for detecting phase by comparing the outputs of a pair of bias parameter sensors whose clock signals are formed from a combination of I and Q clock signals (e.g., ±45°, or 45° and 135°, 135° and 225°, etc.) has the advantage of being more sensitive to phase matching than a configuration consisting of a pair of bias parameter sensors operating with pure I and Q clock signals (e.g., at 0° and 90°, 90° and 180°, or 180° and 270°).

[0108] The outputs of the first and second sensors may be compared 3114. The comparison 3114 may be performed, for example, outside the cooled space in which the RQL IC 106 resides, and may be performed, for example, by a conventional semiconductor circuit (e.g., a CMOS circuit) configured to receive the output voltage signals of the first and second sensors and perform the comparison 3114. The comparison circuit may be the same or different from the circuit used to perform the comparison 3104 of the AC amplitude-indicating outputs in the first portion of the method 3100. Based on the comparison 3114 of the outputs of the first and second sensors, and in some examples further based on the reference signal, it may be evaluated 3116 whether the phase error of the AC clock is optimized to provide true quadrature between the I and Q clock phases, i.e., whether there is a 90° separation of the Q clock phase from the I clock phase, as observed on the RQL integrated circuit 106. For example, if the comparison (3114) indicates no difference between the sensor outputs of the first and second sensors (e.g., OUTPIQ and OUTPI in FIG. 27B), it may be determined that the AC phase error parameters are calibrated (3120). However, if the comparison (3114) indicates a difference between the sensor outputs of the first and second sensors, then one or both of the AC clock phases for the I and Q clocks may be changed (3118), e.g., based on the output of the comparison circuit in room temperature space, and the outputs of the first and second sensors may be re-compared (3114). Portions 3112-3118 of this process may be repeated iteratively as many times as necessary to provide confidence that the AC clock phase error of the I and Q clock signals has been optimized (3120).

[0109] In the exemplary circuit structures and methods described above, the operating region of the test circuit can be established by electronic testing, in which bias levels are varied to determine the individual operating range of the test circuit. The operating range of the test circuit can differ from the operating range of the operational RQL circuit due to manufacturing variations, such as differences in mutual inductance values ​​of the AC clock resonator or DC bias line-coupled transformer, and the addition of self-inductance between the tap and the individual JTL or gate driven by the tap. In each of the different examples described, the electronic testing involves applying stimuli in the form of logic signals and observing the presence or absence of expected logic outputs indicative of test circuit operation. The boundaries of the operating region can be determined by verifying that each test circuit operates correctly or fails at various applied bias levels.

[0110] In some examples, the bias level sensor and associated methods of the present application can advantageously determine how close the operating point of an operational RQL circuit is to its optimal operating point while the operational RQL circuit continues to operate, i.e., without causing bias-related failures in the operational RQL circuit. By placing a sampler in the RQL IC 106 having an operating range configured to systematically vary relative to the operating ranges of the other samplers, it is possible to numerically ascertain the currently applied bias level of the RQL IC 106 as observed on the RQL IC 106. If the sampler is provided within a wrapper having a ladder configuration such as that shown in FIG. 2A or FIG. 25, a numerical determination of the current bias level can be made, for example, by counting the number of pulses provided at the output of the sampler wrapper each time a sampler pulse is provided to the input of the sampler wrapper. Thus, the bias level sensor and associated methods of the present application can assess the bias condition on the RQL IC 106 without interfering with the operation of the operational RQL circuit 102 on the IC 106. The bias level sensor and related methods of the present application are particularly useful in calibrating the bias operating points of RQL systems with multiple RQL ICs. The bias level sensor and related methods of the present application can function as process control monitors, i.e., on-chip devices for evaluating circuit performance as affected by variations in circuit (wafer) processing. The bias level sensor and related methods of the present application can be implemented in human-in-the-loop feedback control or in fully automated feedback control, using a combination of RQL circuitry inside the cooled space and non-RQL circuitry (e.g., CMOS or other semiconductor circuitry) outside the cooled space to continuously or periodically measure and direct adjustments to bias signal parameters.

[0111] The above description is an example of the present invention. It is, of course, not possible to describe every possible combination of elements or methodologies for describing the invention, but one skilled in the art will recognize that many further combinations and permutations of the invention are possible. Accordingly, the invention is intended to encompass all such changes, modifications, and variations that are within the scope of this application, including the appended claims. Additionally, when this disclosure or claims recite "a," "an," "a first," or "another" element, or the equivalent thereof, it should be construed as including one or more such elements, and does not require or exclude two or more such elements. As used herein, the term "includes" means including, but not limited to, and the term "including" means including, but not limited to. The term "based on" means based at least in part on. The technical concepts that can be understood from the above-described embodiment will be described below as supplementary notes. [Appendix 1] A reciprocal quantum logic (hereinafter referred to as RQL) bias level sensor, a stack of a plurality of direct current superconducting quantum interference devices (hereinafter referred to as DC SQUIDs) coupled to each other between a first output terminal and a second output terminal of the RQL bias level sensor, each DC SQUID in the stack comprising a superconducting loop including two Josephson junctions (hereinafter referred to as JJs), each DC SQUID in the stack being transformer coupled to a respective Josephson transmission line (hereinafter referred to as JTL) for receiving magnetic flux from an output of the JTL; The RQL bias level sensor is configured to output a voltage signal between the first output terminal and the second output terminal, the voltage signal being variable depending on the value of at least one bias parameter of a bias signal supplied to the RQL bias level sensor, the bias parameter being one of an AC bias amplitude or a DC bias value. [Appendix 2] 2. The RQL bias level sensor of claim 1, wherein the plurality of JTLs transformer-coupled to the respective plurality of DC SQUIDs are transformer-coupled to a bias signal source configured to provide the bias signal stronger or weaker than the transformer coupling to the bias signal source of a JTL in an operational RQL circuit that is not part of the RQL bias level sensor. [Appendix 3] 3. The RQL bias level sensor of claim 2, wherein a bias tap inductor of each of the plurality of JTLs transformer-coupled to the respective plurality of DC SQUIDs is larger than a bias tap inductor of the JTL in the operational RQL circuit, and the plurality of JTLs transformer-coupled to the respective DC SQUIDs are more weakly coupled to the bias signal source than the JTL in the operational RQL circuit. [Appendix 4] each of the plurality of JTLs transformer-coupled to the respective plurality of DC SQUIDs is coupled to the bias signal source more weakly than the JTLs in the operational RQL circuit; 3. The RQL bias level sensor of claim 2, wherein the coupling strengths of the plurality of JTLs transformer-coupled to the respective plurality of DC SQUIDs are different from one another. [Appendix 5] 5. The RQL bias level sensor of claim 4, wherein the coupling strengths of the plurality of JTLs transformer-coupled to each of the plurality of DC SQUIDs are set in linear steps. [Appendix 6] 6. The RQL bias level sensor of claim 5, wherein a lower limit of each AC bias amplitude of the operating range of each of the plurality of JTLs transformer-coupled to the respective plurality of DC SQUIDs is centered around a center of gravity of the operating range of the operating RQL circuit. [Appendix 7] 2. The RQL bias level sensor of claim 1, wherein a JJ of a first DC SQUID of the plurality of DC SQUIDs in the stack has a higher critical current than a JJ of a second DC SQUID of the plurality of DC SQUIDs in the stack, and a JJ of a second DC SQUID of the plurality of DC SQUIDs in the stack has a higher critical current than a JJ of a second DC SQUID of the plurality of DC SQUIDs in the stack. [Appendix 8] 8. The RQL bias level sensor of claim 7, wherein the critical currents of the JJs of the DC SQUIDs in the stack are linearly stepped. [Appendix 9] 2. The RQL bias level sensor of claim 1, wherein the RQL bias level sensor is configured to measure an output amplifier output bias current supplied between the first output terminal and the second output terminal. [Appendix 10] 2. The RQL bias level sensor of claim 1, further comprising a plurality of JTL-based buffers coupled to inputs of a plurality of JTLs transformer-coupled to a respective one of the plurality of DC SQUIDs, the plurality of buffers providing different amounts of time delay to each of the plurality of JTLs transformer-coupled to a respective one of the plurality of DC SQUIDs, such that the voltage signal output between the first output terminal and the second output terminal is made up of a series of time-shifted step functions, with the timing of each step function corresponding to the operation of an individual one of the plurality of DC SQUIDs in the stack. [Appendix 11] 2. The RQL bias level sensor of claim 1, having 5 to 10 DC SQUIDs in the stack. [Appendix 12] 1. A system comprising: a first instance and a second instance of the RQL bias level sensor of claim 1, an output of the first instance coupled to a first input of bias parameter adjustment logic, and an output of the second instance coupled to a second input of the bias parameter adjustment logic; the bias parameter adjustment logic has a first output configured to indicate an adjustment to a bias parameter of a first clock signal provided to the RQL system; The bias parameter adjustment logic has a second output configured to direct an adjustment to a bias parameter of a second clock signal provided to the RQL system, the second clock signal being approximately 90° out of phase with the first clock signal. [Appendix 13] 13. The system of claim 12, wherein the bias parameter adjustment logic is a complementary metal-oxide semiconductor (CMOS) logic located outside of a cryogenically cooled space in which the first and second instances of the RQL bias level sensor are located. [Appendix 14] a plurality of JTLs transformer-coupled to the respective plurality of DC SQUIDs in the first instance of the RQL bias level sensor are biased by the first clock signal; the plurality of JTLs transformer-coupled to the respective DC SQUIDs in the first instance of the RQL bias level sensor are biased by the second clock signal; the first output of the bias parameter adjustment logic is configured to indicate an adjustment to an AC amplitude of the first clock signal; 13. The system of claim 12, wherein the second output of the bias parameter adjustment logic is configured to indicate an adjustment to an AC amplitude of the second clock signal. [Appendix 15] 15. The system of claim 14, wherein the bias parameter adjustment logic further comprises a third input configured to provide a reference signal for comparing the output of the first instance and the output of the second instance. [Appendix 16] A method for adjusting a reciprocal quantum logic (hereinafter referred to as RQL) bias signal, comprising: Driving a first RQL bias parameter sensor with a first AC clock bias signal of the RQL system; driving a second RQL bias parameter sensor with a second AC clock bias signal of the RQL system, the second AC clock bias signal being approximately 90 degrees out of phase with the first AC clock bias signal; comparing the outputs of the first and second RQL bias parameter sensors; and adjusting one or both of an AC amplitude of the first AC clock bias signal or an AC amplitude of the second AC clock bias signal based on comparing the outputs of the first and second RQL bias parameter sensors. [Appendix 17] 17. The method of claim 16, wherein the step of comparing the outputs of the first and second RQL bias parameter sensors is performed by a logic circuit located outside of a cryogenically cooled space in which the first and second RQL bias parameter sensors are located. [Appendix 18] 18. The method of claim 17, wherein comparing the outputs of the first and second RQL bias parameter sensors includes comparing the outputs of the first and second RQL bias parameter sensors to each other and comparing the output of each of the first and second RQL bias parameter sensors to a reference signal provided to the logic circuit. [Appendix 19] driving a third RQL bias parameter sensor with a third AC clock bias signal of the RQL system, the third AC clock bias signal being approximately 45 degrees out of phase with the first AC clock bias signal; comparing the outputs of the first and third RQL bias parameter sensors; adjusting one or both of a phase of the first AC clock bias signal or a phase of the second AC clock bias signal based on comparing outputs of the first and third RQL bias parameter sensors. [Appendix 20] 20. The method of claim 19, wherein the step of comparing the outputs of the first and third RQL bias parameter sensors is performed by a logic circuit located outside of a cryogenically cooled space in which the first and third RQL bias parameter sensors are located.

Claims

1. A reciprocal quantum logic (RQL) bias level sensor, a stack of direct current superconducting quantum interference devices (hereinafter referred to as DC SQUIDs) coupled to each other between a first output terminal and a second output terminal of the RQL bias level sensor, each DC SQUID in the stack comprising a superconducting loop including two Josephson junctions (hereinafter referred to as JJs), each DC SQUID in the stack being transformer coupled to a respective Josephson transmission line (hereinafter referred to as JTL) for receiving magnetic flux from the output of the JTL; The RQL bias level sensor is configured to output a voltage signal between the first output terminal and the second output terminal, the voltage signal being variable depending on the value of at least one bias parameter of a bias signal supplied to the RQL bias level sensor, the bias parameter being one of an AC bias amplitude or a DC bias value.

2. 2. The RQL bias level sensor of claim 1, wherein the plurality of JTLs transformer-coupled to a respective plurality of DC SQUIDs are transformer-coupled to a bias signal source configured to provide the bias signal stronger or weaker than the transformer coupling to the bias signal source of a JTL in an operational RQL circuit that is not part of the RQL bias level sensor.

3. 3. The RQL bias level sensor of claim 2, wherein a bias tap inductor of each of the plurality of JTLs transformer coupled to the respective plurality of DC SQUIDs is larger than a bias tap inductor of the JTL in the operating RQL circuit, and the plurality of JTLs transformer coupled to the respective DC SQUIDs are coupled to the bias signal source more weakly than the JTL in the operating RQL circuit.

4. each of the plurality of JTLs transformer-coupled to the respective plurality of DC SQUIDs is coupled to the bias signal source more weakly than the JTLs in the operational RQL circuit; The coupling strengths of the plurality of JTLs transformer-coupled to the respective plurality of DC SQUIDs are different from one another; The coupling strengths of the plurality of JTLs transformer-coupled to each of the plurality of DC SQUIDs are set in linear steps, 3. The RQL bias level sensor of claim 2, wherein a lower limit of each AC bias amplitude of an operating range of each of the plurality of JTLs transformer-coupled to the respective plurality of DC SQUIDs is centered about a center of gravity of the operating range of the operating RQL circuit.

5. a JJ of a first DC SQUID of the plurality of DC SQUIDs in the stack has a higher critical current than a JJ of a second DC SQUID of the plurality of DC SQUIDs in the stack, and a JJ of a second DC SQUID of the plurality of DC SQUIDs in the stack has a higher critical current than a JJ of a second DC SQUID of the plurality of DC SQUIDs in the stack; 2. The RQL bias level sensor of claim 1, wherein the critical currents of each of the plurality of JJs of the plurality of DC SQUIDs in the stack are linearly stepped.

6. 2. The RQL bias level sensor of claim 1, wherein the RQL bias level sensor is configured to measure an output amplifier output bias current provided between the first output terminal and the second output terminal.

7. 2. The RQL bias level sensor of claim 1, further comprising a plurality of JTL-based buffers coupled to inputs of a plurality of JTLs transformer-coupled to a respective plurality of DC SQUIDs, the plurality of buffers providing different amounts of time delay to each of the plurality of JTLs transformer-coupled to the respective plurality of DC SQUIDs, such that the voltage signal output between the first output terminal and the second output terminal is made up of a series of time-staggered step functions, with the timing of each step function corresponding to the operation of a respective one of the plurality of DC SQUIDs in the stack.

8. 1. A system comprising:

10. A system comprising a first and second instance of the RQL bias level sensor of claim 1, wherein an output of the first instance is coupled to a first input of bias parameter adjustment logic and an output of the second instance is coupled to a second input of the bias parameter adjustment logic; the bias parameter adjustment logic has a first output configured to indicate an adjustment to a bias parameter of a first clock signal provided to an RQL system; the bias parameter adjustment logic has a second output configured to direct an adjustment to a bias parameter of a second clock signal provided to the RQL system, the second clock signal being approximately 90 degrees out of phase with the first clock signal.

9. 10. The system of claim 8, wherein the bias parameter adjustment logic is a complementary metal oxide semiconductor (CMOS) logic located outside of a cryogenically cooled space in which the first and second instances of the RQL bias level sensor are located.

10. a plurality of JTLs transformer-coupled to the respective plurality of DC SQUIDs in the first instance of the RQL bias level sensor are biased by the first clock signal; the plurality of JTLs transformer-coupled to the respective DC SQUIDs in the first instance of the RQL bias level sensor are biased by the second clock signal; the first output of the bias parameter adjustment logic is configured to indicate an adjustment to an AC amplitude of the first clock signal; the second output of the bias parameter adjustment logic is configured to indicate an adjustment to an AC amplitude of the second clock signal; 9. The system of claim 8, wherein the bias parameter adjustment logic further comprises a third input configured to provide a reference signal for comparing the output of the first instance and the output of the second instance.

11. A method for adjusting a reciprocal quantum logic (hereinafter referred to as RQL) bias signal, comprising: Driving a first RQL bias parameter sensor with a first AC clock bias signal of the RQL system; driving a second RQL bias parameter sensor with a second AC clock bias signal of the RQL system, the second AC clock bias signal being approximately 90 degrees out of phase with the first AC clock bias signal; comparing the outputs of the first and second RQL bias parameter sensors; and adjusting one or both of the AC amplitude of the first AC clock bias signal or the AC amplitude of the second AC clock bias signal based on comparing the outputs of the first and second RQL bias parameter sensors.

12. 12. The method of claim 11, wherein the step of comparing the outputs of the first and second RQL bias parameter sensors is performed by a logic circuit located outside of a cryogenically cooled space in which the first and second RQL bias parameter sensors are located.

13. 13. The method of claim 12, wherein comparing the outputs of the first and second RQL bias parameter sensors comprises: comparing the outputs of the first and second RQL bias parameter sensors to each other; and comparing the output of each of the first and second RQL bias parameter sensors to a reference signal provided to the logic circuit.

14. driving a third RQL bias parameter sensor with a third AC clock bias signal of the RQL system, the third AC clock bias signal being approximately 45 degrees out of phase with the first AC clock bias signal; comparing the outputs of the first and third RQL bias parameter sensors; and adjusting one or both of a phase of the first AC clock bias signal or a phase of the second AC clock bias signal based on comparing outputs of the first and third RQL bias parameter sensors.

15. 15. The method of claim 14, wherein the step of comparing the outputs of the first and third RQL bias parameter sensors is performed by a logic circuit located outside of a cryogenically cooled space in which the first and third RQL bias parameter sensors are located.

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