A single function to perform multiple operations with validation of individual operation parameters

Abstract

An indication of a function to be executed is obtained, where the function is a function of the instructions and is configured to perform a plurality of operations. An operation of the plurality of operations to be executed is determined, and a set of function-specific parameters is validated using a set of values ​​and a corresponding set of relationships. The set of values ​​and the corresponding set of relationships are based on the operation to be executed. One set of values ​​and the corresponding set of relationships are used for the operation to be executed, and another set of values ​​and the corresponding set of relationships are used for another operation of the plurality of operations.

Description

[Technical Field]

[0001] One or more aspects relate generally to facilitating processing within a computing environment, and in particular to improving such processing. [Background technology]

[0002] To enhance processing in data- and / or computation-intensive computing environments, coprocessors such as artificial intelligence accelerators (also referred to as neural network processors or neural network accelerators) are utilized. Such accelerators provide enormous computing power that is used in performing complex calculations, such as calculations on matrices or tensors.

[0003] Tensor calculus is used in complex processes, including, by way of example, deep learning, which is a subset of machine learning. Deep learning or machine learning, an aspect of artificial intelligence, is used in a variety of technologies, including, but not limited to, engineering, manufacturing, medical technology, automotive technology, computer processing, etc.

[0004] Deep learning uses a variety of operations that operate on tensor data, each of which is implemented independently, increasing development and validation effort. Summary of the Invention

[0005] Shortcomings of the prior art are overcome and additional advantages are provided through the provision of a computer program product to facilitate processing within a computing environment. The computer program product includes one or more computer-readable storage media and program instructions collectively stored on the one or more computer-readable storage media for performing a method. The method is performed by ShouldThe method includes obtaining an indication of a function, where the function is a function of the instructions and is configured to perform a plurality of operations. An operation to be performed of the plurality of operations is determined, and a set of function-specific parameters is validated using a set of values ​​and a corresponding set of relationships. The set of values ​​and the corresponding set of relationships are based on the operation to be performed. For example, one set of values ​​and the corresponding set of relationships are used for the operation to be performed, and another set of values ​​and the corresponding set of relationships are used for another operation of the plurality of operations.

[0006] By using a single function, e.g., a single function of designed instructions, to perform multiple operations with validation for each operation parameter, code complexity, code duplication, and / or verification effort is reduced, improving system performance.

[0007] In one example, Should Determining the operation includes checking one or more function-specific parameters against at least one particular value. One or more function-specific parameters to at least one specific value On the other hand Has a first-choice relationship thing Based on, the operation is one operation, One or more function-specific parameters to at least one specific value On the other hand Has a second selection relationship thing Based on, the operation is another operation.

[0008] The same function is executed using specific parameters, but with different relationships. Should By determining the operations, code complexity and verification effort is reduced.

[0009] By way of example, the function may include an average pooling function, the one or more function-specific parameters may include one or more stride values, where the stride value is an amount by which a sliding window moves over the input tensor when calculating one or more adjacent output tensor elements, at least one particular value may include zero, the first selection relationship may include equality, and the operation may include averaging based on the one or more stride values ​​being equal to zero. contraction (mean-reduce) operation.

[0010] Furthermore, in one example, the second selection relationship includes greater than, and the operation is a pooling operation based on one or more stride values ​​being greater than zero.

[0011] By way of example, the set of function-specific parameters may include one or more selected dimension window size values ​​that specify the number of elements in the selected dimension that a sliding window includes, the sliding window configured to move over the input tensors of the function to generate an output tensor.

[0012] In one example, the function comprises an average pool function and the operation is an average contraction The set of values ​​and corresponding relationships used to include the operation and validate the set of function-specific parameters includes one value of one dimension of the selected input tensor and the corresponding relationship of being equal, another value of another dimension of the selected input tensor and the corresponding relationship of being equal, and a selected value and the corresponding relationship of being less than or equal.

[0013] Validating may include, for example, checking that the dimension 2 window size value is equal to the dimension 2 value of the first input tensor, that the dimension 3 window size value is equal to the dimension 3 value of the first input tensor, that the dimension 2 window size value is less than or equal to a selected value, and that the dimension 3 window size value is less than or equal to a selected value.

[0014] In one example, the function includes an average pool function, the operation includes a pooling operation, and the set of values ​​and corresponding relationships used to validate the set of function-specific parameters includes one value in one dimension of the selected input tensor and a corresponding relationship of being less than or equal to it, and another value in another dimension of the selected input tensor and a corresponding relationship of being less than or equal to it.

[0015] Validating may include, for example, checking that the dimension 2 window size value is less than or equal to the dimension 2 value of the first input tensor, and that the dimension 3 window size value is less than or equal to the dimension 3 value of the first input tensor.

[0016] In one example, a determination is made as to whether the padding type is set to a particular type, where the padding type indicates which elements of the window are used to compute the output, and in one or more embodiments, validation is performed based on the padding type being set to the particular type. Further, in one example, one or more checks related to one or more dimensions of the output tensor are performed based on the padding type not being set to the particular type.

[0017] In one example, determining the operation is based on at least one sliding window stride value of the input tensor, and the set of function-specific parameters includes at least one sliding window dimension of the input tensor.

[0018] Computer-implemented methods and systems relating to one or more aspects are also described and claimed herein. Additionally, services relating to one or more aspects may also be described and claimed herein.

[0019] Additional features and advantages are realized through the techniques described herein. Other embodiments and aspects are described in detail herein and are considered a part of the claimed aspects. [Brief explanation of the drawings]

[0020] One or more aspects are particularly pointed out and individually claimed as examples in the claims at the end of this specification. The above, as well as other objects, features, and advantages of one or more aspects, will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Figure 1A] 1 illustrates an example computing environment for incorporating and using one or more aspects of the present invention. [Figure 1B] 1B illustrates further details of the processor of FIG. 1A in accordance with one or more aspects of the present invention. [Figure 2] 1 illustrates an example of processing associated with executing a single function of an instruction configured to perform multiple operations but capable of checking individual parameter conditions for the multiple operations, in accordance with one or more aspects of the present invention. [Figure 3A] 1 illustrates an example format of neural network processing assistance instructions in accordance with one or more aspects of the present invention. [Figure 3B] 1 illustrates an example of a general purpose register used by neural network processing assistance instructions in accordance with one or more aspects of the present invention. [Figure 3C]1 illustrates an example of function code supported by neural network processing assistance instructions in accordance with one or more aspects of the present invention. [Figure 3D] 10 illustrates an example of another general purpose register used by neural network processing assistance instructions in accordance with one or more aspects of the present invention. [Figure 3E] 1 illustrates an example of a parameter block used by a query function of a neural network processing assistance instruction in accordance with one or more aspects of the present invention. [Figure 3F] 1 illustrates an example of a parameter block used by one or more non-query functions of neural network processing assistance instructions, in accordance with one or more aspects of the present invention. [Figure 3G] 1 illustrates an example of a tensor descriptor used by neural network processing assistance instructions in accordance with one or more aspects of the present invention. [Figure 4] 1 illustrates an example of a format for a Neural Network Processing (NNP) Data Type 1 data type, according to one or more aspects of the present invention. [Figure 5A] 1 illustrates an example of an input data layout used by neural network processing assistance instructions, in accordance with one or more aspects of the present invention. [Figure 5B] 1 illustrates an example of an input data layout used by neural network processing assistance instructions, in accordance with one or more aspects of the present invention. [Figure 5C] 1 illustrates an example of an input data layout used by neural network processing assistance instructions, in accordance with one or more aspects of the present invention. [Figure 6A] 5A-5C illustrate exemplary outputs corresponding to the input data layouts of FIGS. 5A-5C, in accordance with one or more aspects of the present invention. [Figure 6B] 5A-5C illustrate exemplary outputs corresponding to the input data layouts of FIGS. 5A-5C, in accordance with one or more aspects of the present invention. [Figure 6C] 5A-5C illustrate exemplary outputs corresponding to the input data layouts of FIGS. 5A-5C, in accordance with one or more aspects of the present invention. [Figure 7A] 1 illustrates an example of facilitating processing in a computing environment in accordance with one or more aspects of the present invention. [Figure 7B] 1 illustrates an example of facilitating processing in a computing environment in accordance with one or more aspects of the present invention. [Figure 7C] 1 illustrates an example of facilitating processing in a computing environment in accordance with one or more aspects of the present invention. [Figure 8A] 1 illustrates another example of a computing environment for incorporating and using one or more aspects of the present invention. [Figure 8B] 8B illustrates an example of further details of the memory of FIG. 8A, in accordance with one or more embodiments of the present invention. [Figure 8C] 8B illustrates another example of further details of the memory of FIG. 8A, in accordance with one or more aspects of the present invention. [Figure 9A] 1 illustrates yet another example of a computing environment for incorporating and using one or more aspects of the present invention. [Figure 9B] 9B illustrates further details of the memory of FIG. 9A in accordance with one or more embodiments of the present invention. [Figure 10] 1 illustrates one embodiment of a cloud computing environment in accordance with one or more aspects of the present invention. [Figure 11] 1 illustrates an example of abstraction model layers, in accordance with one or more aspects of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] According to one or more aspects of the present invention, capabilities are provided for facilitating processing within a computing environment. By way of example, instructions configured to implement multiple functions are provided, with at least one function configured to perform multiple operations with separate parameter validation for each operation. Using one function to perform multiple operations but being able to check different parameter boundary conditions among the multiple operations reduces code complexity, code duplication, and / or validation effort.

[0022] By way of example, the function configured to implement the plurality of operations is an average pooling function, and the plurality of operations is, for example, an average function used in deep learning. contraction The average pooling functions are algorithmically reduced to common algorithm functions that perform different operations but use the same input tensors and function-specific parameters, but with different relative constraints.

[0023] In one example, a function configured to perform multiple operations is initiated by an instruction. Illustratively, the instruction is a neural network processing support instruction that is a single instruction (e.g., a single architecture hardware machine instruction at a hardware / software interface) configured to perform multiple functions. Each of the functions is configured as part of a single instruction (e.g., a single architecture instruction) to reduce system resource usage and complexity and improve system performance. Additionally, at least one of the functions, an example of which is the AVGPOOL2D function described below, performs multiple operations (e.g., average) based on input data such as values ​​of function-specific parameters (e.g., function-specific parameters 2 and 3 described below) provided by the instruction. contraction and pooling).

[0024] The instructions may be part of a general purpose processor instruction set architecture (ISA) that is dispatched by a program on a processor, such as a general purpose processor. instruction may be executed by a general-purpose processor, and / or one or more functions of the instructions may be associated with or part of a specific function of the general-purpose processor. For The method may be performed by a dedicated processor, such as a processor configured in a processor. Other variations are also possible.

[0025] Incorporating one or more aspects of the present invention andOne embodiment of a computing environment for use is described with reference to Figure 1A. By way of example, the computing environment may be based on the z / Architecture® instruction set architecture offered by International Business Machines Corporation of Armonk, New York. One embodiment of the z / Architecture instruction set architecture is described in IBM Publication No. SA22-7832-12, 13th Edition, September 2019, entitled "z / Architecture Principles of Operation," which is incorporated herein by reference in its entirety. However, the z / Architecture instruction set architecture is merely one exemplary architecture, and International Business Machines Corporation and / or other entities may also use the z / Architecture instruction set architecture. of Other architectures and / or other types of computing environments but , may include and / or use one or more aspects of the present invention. z / Architecture and IBM are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction.

[0026] 1A, for example, computing environment 100 includes computer system 102, shown, for example, in the form of a general-purpose computing device. Computer system 102 may include, but is not limited to, one or more general-purpose processors or processing units 104 (e.g., central processing units (CPUs)), at least one special-purpose processor such as neural network processor 105, memory 106 (i.e., system memory, main memory, main storage, central storage, or storage, for example), and one or more input / output (I / O) interfaces 108 coupled to each other via one or more buses and / or other connections. For example, processors 104, 105 and memory 106 are coupled to I / O interface 108 via one or more buses 110, and processors 104, 105 are coupled to each other via one or more buses 111.

[0027] Bus 111 is, for example, a memory or cache coherence bus, and bus 110 is, for example, M Memory bus or memory controller, peripheral bus, accelerated graphics port, and using any of a variety of bus architectures It represents any one or more of several types of bus structures, including processor or local buses. By way of example and not limitation, such architectures include Industry Standard Architecture (ISA), Micro Channel Architecture (MCA), Enhanced ISA (EISA), Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI).

[0028] By way of example, one or more application-specific processors (e.g., neural network processors) may be implemented in combination with one or more general-purpose processors. It is separate from but one or more general-purpose processors and / or may be incorporated within one or more general purpose processors. Many variations are possible.

[0029] For example, memory 106 may include a cache 112, such as a local cache 114 of processor 104 and / or a shared cache that may be coupled to neural network processor 105, e.g., via one or more buses 111. Further, memory 106 may include one or more programs or applications 116 and at least one operating system 118. Exemplary operating systems include the z / OS® operating system offered by International Business Machines Corporation of Armonk, New York. z / OS is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Other operating systems offered by International Business Machines Corporation and / or other entities may also be used. Memory 106 may also include one or more computer-readable program instructions 120 that may be configured to perform functions of embodiments of aspects of the present invention.

[0030] In one or more embodiments, memory 106 also includes processor firmware 122. Processor firmware includes, for example, the microcode or millicode of the processor. Processor firmware includes, for example, hardware level instructions and / or data structures used in a higher level machine code implementation. Processor firmware includes, for example, trusted software, microcode, or millicode that is specific to the underlying hardware, including proprietary code that is typically supplied as microcode or millicode that controls the operating system's access to the system hardware.

[0031] The computer system 102 may communicate with one or more external devices 130, such as, for example, a user terminal, a tape drive, a pointing device, a display, and one or more data storage devices 134, via the I / O interface 108. The data storage devices 134 may store one or more programs 136, one or more computer-readable program instructions 138, and / or data, etc. The computer-readable program instructions may be configured to perform functions of embodiments of aspects of the invention.

[0032] The computer system 102 may also communicate, for example via the I / O interface 108, with a network interface 132 that enables the computer system 102 to communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet), to provide communication with other computing devices or systems.

[0033] Computer system 102 may include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, it may include and / or be coupled to non-removable, non-volatile magnetic media (commonly referred to as a "hard drive"), a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), and / or an optical disk drive for reading from or writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM, or other optical media. It should be understood that other hardware and / or software components may be used in connection with computer system 102. Examples include, but are not limited to, microcode or millicode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data archive storage systems, and the like.

[0034] Computer system 102 is capable of operation with numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations that may be suitable for use with computer system 102 include: Pa personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and Including any of the above systems or devices and the like Including, but not limited to, distributed cloud computing environments.

[0035] In one example, a processor (e.g., processor 104 and / or processor 105) includes multiple functional components (or a subset thereof) used to execute instructions. As shown in FIG. 1B , these functional components include, for example, an instruction fetch component 150 for fetching instructions to be executed; an instruction decode unit 152 for decoding the fetched instructions and obtaining operands for the decoded instructions; one or more instruction execution components 154 for executing the decoded instructions; a memory access component 156 for accessing memory for instruction execution, if necessary; and a writeback component 158 ​​for providing results of the executed instructions. One or more of the components may access and / or use one or more registers 160 in processing the instructions. Additionally, one or more of the components may, according to one or more aspects of the present invention, include or have access to at least a portion of one or more other components used to perform multiple operations with separate parameter checks based on the execution of a single function, as described herein, and / or to perform neural network processing-assisted processing, for example, of neural network processing-assisted instructions (or other processing that may employ one or more aspects of the present invention). The one or more other components may include, for example, a single function, multiple operations—separate parameter validation component 170, and / or neural network processing-assisted component 172 (and / or one or more other components).

[0036] According to one or more aspects of the present invention, instructions capable of performing multiple functions are executed, with at least one function implementing multiple operations with separate parameter validations, an example of which is further described with reference to FIG.

[0037] 2, in one example, an instruction, such as a neural network processing aid (NNPA) instruction (or another instruction), is initiated 200 in a processor, such as general-purpose processor 104. ShouldA determination is made as to the function, for example by checking the function code of the instruction. Should If the function is not a select function code, such as a function code that specifies an average pooling function (eg, NNPA_AVGPOOL2D), then other processing is performed 204 .

[0038] However, returning to inquiry 202 the law of nature , where the function code specifies a selected function code, e.g., a function code specifying an average pooling function, as described herein. Place Processing continues. In one example, processing is performed by a general-purpose processor that initiates the instruction. However, in other embodiments, processing may be performed by a special-purpose processor, such as a neural network accelerator (e.g., neural network accelerator 105), or by another general-purpose processor, a special-purpose processor, or other processor. Other variations are also applicable.

[0039] In one example, an input tensor, e.g., input tensor 1, is specified based on specifying the AVGPOOL2D function: finger By the specified operation contraction And, The input window is aggregated A window is, for example, a selected portion of an input tensor with a defined size. The window of input is selected, for example, by moving a 2D sliding window across dimensions 2 and 3 of the input tensor. Aggregation are elements in the output tensor. The sliding window dimension is determined by, for example, the function-specific parameters provided by the instruction, e.g., function-specific parameter 4 and function-specific parameter 5. Description And, Function-specific parameters Examples of are described herein.

[0040] In processing a function, in one embodiment, the function is configured to perform multiple operations, so that Should A determination is made as to the operation. Should The determination of the operation is made by checking the selection function specific parameters provided as input to the instruction (e.g., in a parameter block used with the instruction). By way of example, the selection function specific parameters are function specific parameter 2 (i.e., fn.sp2) and function specific parameter 3 (i.e., fn.sp3), each of which specifies, for example, a sliding window stride. The sliding window stride or stride may be: adjacent The amount by which the sliding window moves over the input tensor 1 when computing the output tensor elements.

[0041] In one example, a determination is made 206 whether the values ​​of function-specific parameter 2 and function-specific parameter 3 are equal to a selected value, such as zero. For example, the dimension 2 stride specified by fn.sp2 Value of , and if the value of the dimension 3 stride specified by fn.sp3 is equal to the selected value (e.g., zero), the average contraction The calculation is performed should be , therefore, the average Contraction specific Tests are performed 210. These tests include, for example, checking whether:

[0042] The padding type is equal to the selected padding type, such as Valid. For example, provided to the function as input Parameters specific to a particular function, e.g. Seki Number-specific parameters 1 (i.e. fn.sp1) Value of but check And If the specified padding type is Valid, all elements in the window are added to the set used to compute the resulting output elements.

[0043] Function-specific parameters 4 (fn.sp4) Value of teeth, equal to the dimension 2 value (e.g., e2) of the first input tensor (e.g., check that fn.sp4 == in1.e2). For example, the dimension 2 window size (i.e., sliding window value) in fn.sp4 is checked against the value of in1.e2.

[0044] Function-specific parameters5 (fn.sp5) Value of but , equal to the value of dimension 3 of the first input tensor (e.g., e3) (e.g., check that fn.sp5 == in1.e3). For example, the dimension 3 window size (i.e., sliding window value) in fn.sp5 is checked against the value of in1.e3.

[0045] The value of function-specific parameter 4 is the value of your choice (e.g., 1024) Yo Less than or equal to (e.g. fn.sp4<=1024) For example, the dimension 2 window size is compared to a selected value, say 1024.

[0046] The value of function-specific parameter 5 is the value of your choice (e.g., 1024). Yo Less than or equal to (e.g. fn.sp5<=1024) For example, a dimension 3 window size is compared to a selected value, say 1024.

[0047] addition Fewer and / or other tests may be performed.

[0048] If the test is insufficient 212, error handling is performed 214. However, if the test is sufficient 212, the function / selected operation (e.g., the average of the AVGPOOL2D function) is contraction The operations are executed 216. For example, in one embodiment, a general-purpose processor (e.g., general-purpose processor 104) initiates the neural network processing assistance instructions, and for certain functions, such as non-query functions like the AVGPOOL2D function, the general-purpose processor executes ShouldIt provides information such as an indication of the function / operation and memory address information of the input data (e.g., one or more input tensors) to a dedicated processor (e.g., neural network processor 105) so that the dedicated processor can perform the function / operation as described herein. 、 Processing returns to the general purpose processor to complete the instruction. In other embodiments, a general purpose or special purpose processor initiates the instruction, performs the function / operation, and completes the instruction. Other variations are possible.

[0049] Returning to query 206, for example, if the values ​​of function-specific parameter 2 and function-specific parameter 3 are not equal to a selected value, such as zero, then fn.sp2 Value of A further check is made (220) as to whether the value of fn.sp3 is greater than a selected value (e.g., zero). Value of , and if the value of the dimension 3 stride specified by fn.sp3 is not greater than the selected value (e.g., 0), error handling is performed 214. However, if the dimension 2 stride specified by fn.sp2 Value of and if the value of dimension 3 stride specified by fn.sp3 is greater than the selected value (e.g., zero), a pooling operation is performed. should be , and therefore pooling-specific tests are performed 230. Examples of these tests include, for example, checking whether:

[0050] fn.sp2 Value of and the value of fn.sp3 is less than or equal to a certain value, such as 30. For example, dimension 2 Stride value of and Dimension 3 of The stride value is compared to a specific value, for example 30.

[0051] The padding type specified by function-specific parameter 1 (fn.sp1) is equal to the selected padding type, such as Valid. If the value in fn.sp1 is, for example, Valid, a check is made whether the sliding window value (also referred to as dimension 2 window size) specified in fn.sp4 is less than or equal to the value of dimension 2 of the first input tensor (in1.e2), and whether the sliding window value (also referred to as dimension 3 window size) specified in fn.sp5 is less than or equal to the value of dimension 3 of the first input tensor (in1.e3).

[0052] In one example, if the padding type specified in fn.sp1 is not equal to the selected padding type, such as Valid, the output tensor has dimension 2 (e2), e.g. (e.g., out.e2) Value of but , the check for equality to the cell values ​​(in1.e2 / fn.sp4) is performed, and the dimension of the output tensor is 3 (e3). (e.g., out.e3) Value of but A check is made to see if it is equal to the cell value (in1.e3 / fn.sp5).

[0053]

number

[0054]

number

[0055] where:

[0056] IxDyIS: Dimension y index size of input tensor x defined in tensor descriptor x

[0057] OxDyIS: Dimension y index size of output tensor x defined in tensor descriptor x

[0058] D2S: Dimension 2 Stride

[0059] D3S: Dimension 3 Stride

[0060] addition Fewer and / or other tests may be performed.

[0061] If the tests are not sufficient, error handling is performed 214. However, if these tests are sufficient 212, then the function / selected operation (e.g., the pooling operation of the AVGPOOL2D function) is performed 216 as described herein.

[0062] Once the function / operation is complete, processing returns to the general purpose processor and the instruction is completed 240 .

[0063] As shown, in one example, the AVGPOOL2D function is implemented as part of instructions such as neural network processing support instructions. contractionFurther details relating to the register and pooling operations are described with reference to FIGS. 3A-3G. Referring first to FIG. 3A, in one example, a neural network processing assistance instruction 300 has an RRE format that describes registers and register operations using extended operation codes (opcodes). In one example, the neural network processing assistance instruction 300 includes an operation code (opcode) field 302 (e.g., bits 0-15) that indicates a neural network processing assistance operation. In one example, bits 16-31 of the instruction are reserved and contain zero. In the description herein, the instruction, the function and / or operation of the instruction, a particular location, a particular field, and / or a particular size of a field is indicated (e.g., a particular byte and / or bit). However, other locations, fields, and / or sizes may be provided. Furthermore, while it may be specified that a bit be set to a particular value, e.g., 1 or 0, this is merely an example. If a bit is set, it may in other examples be set to a different value, such as the opposite value or another value. Many variations are possible.

[0064] In one example, an instruction uses multiple general purpose registers that are implicitly specified by the instruction. For example, neural network processing assistance instruction 300 uses implicit registers, general purpose register 0 and general purpose register 1, an example of which is described with reference to Figures 3B and 3D, respectively.

[0065] Referring to FIG. 3B, in one example, general register 0 is: Seki Number code field and May be updated upon completion of the command The fields include a status field. By way of example, general register 0 includes a response code field 310 (e.g., bits 0-15), an exception flags field 312 (e.g., bits 24-31), and a function code field 314 (e.g., bits 56-63). Additionally, in one example, bits 16-23 and 32-55 of general register 0 are reserved and contain zeros. One or more fields are used by the particular function performed by the instruction. In one example, not all fields are used by all functions. Each of the fields is described below.

[0066] Response Code (RC) 310: This field (e.g., bit positions 0-15) contains a response code. When execution of a neural network processing support instruction completes with a condition code of, for example, 1, the response code is stored. When an invalid input condition is encountered, Indicates the cause of invalid input conditions recognized during execution A non-zero value is stored in the response code field, Selection The selected condition code, e.g., 1, is set. R The codes stored in the response code field are defined as follows in one example:

[0067] Response Code Meaning

[0068] 0001 The parameter block format specified by the parameter block version number is not supported by the model.

[0069] 0002 The specified function is not defined or installed on the machine.

[0070] 0010 The specified tensor data layout format is not supported.

[0071] 0011 The specified tensor data type is not supported.

[0072] 0012 The specified single tensor dimension is larger than the maximum dimension index size.

[0073] 0013 The specified tensor size is larger than the maximum tensor size.

[0074] 0014 The specified tensor address is not aligned on a 4K byte boundary.

[0075] 0015 Function specific save area address is not aligned on a 4K byte boundary.

[0076] F000~FFFF Function-specific response code. These response codes are defined for specific functions.

[0077] Exception Flags (EF) 312: This field (e.g., bit positions 24-31) contains exception flags. If an exception condition is detected during the execution of the instruction, the corresponding exception flag control (e.g., bit) is set, e.g., to 1; otherwise, the control remains unchanged. The exception flags field is initialized to zero before the first invocation of the instruction. The reserved flags remain unchanged during the execution of the instruction. The flags stored in the exception flags field are defined as follows in one example:

[0078] EF (bit) meaning

[0079] 0 Range violation. This flag is set when a non-numeric value is either detected in an input tensor or stored in an output tensor. This flag is only valid, for example, when the instruction completes with a condition code of, say, 0.

[0080] 1~7 Reserved

[0081] Function Code (FC) 314: This field (e.g., bit positions 56-63) contains the function code. Examples of assigned function codes for neural network processing support instructions are shown in FIG. 3C. All other function codes are unassigned. If an unassigned or uninstalled function code is specified, a response code of, e.g., 0002 hex and a selection condition code of, e.g., 1 are set. This field is not modified during execution.

[0082] As shown, in addition to general purpose register 0, the neural network processing assistance instructions also use general purpose register 1, an example of which is illustrated in Figure 3D. By way of example, bits 40-63 in 24-bit addressing mode, bits 33-63 in 31-bit addressing mode, or bits 0-63 in 64-bit addressing mode are used to store the address of the parameter block. 320 The contents of general register 1 specify, for example, the logical address of the leftmost byte of the parameter block in storage. The parameter block is specified on a double-word boundary; otherwise, an exception to the specification is recognized. For all functions, the contents of general register 1 are not modified.

[0083] In access register mode, access register 1 specifies an address space that includes, for example, the parameter block, input tensors, output tensors, and function-specific storage areas.

[0084] In one example, the parameter block may have different formats depending on the function specified by the instruction being executed. For example, a query function of the instruction has a parameter block in one format, and other functions of the instruction have a parameter block in another format. In another example, all functions use the same parameter block format. Other variations are also applicable.

[0085] By way of example, the parameter blocks and / or the information in the parameter blocks may be stored in memory, hardware registers, and / or a combination of memory and / or registers. Other examples are also possible.

[0086] An example of a parameter block used by a query function such as an NNPA-Query Available Functions (QAF) operation is described with reference to Figure 3E. As shown, in one example, the NNPA-Query Available Functions parameter block 330 includes, for example:

[0087] Vector of installed functions 332: This field (e.g., bytes 0-31) of the parameter block contains a vector of functions to be installed. In one example, bits 0-255 of the vector of installed functions correspond to function codes 0-255 of the neural network processing support command, respectively. When a bit is, for example, 1, the corresponding function is installed; otherwise, the function is not installed.

[0088] Vector of installed parameter block formats 334: This field (e.g., bytes 32-47) of the parameter block contains a vector of parameter block formats to be installed. In one example, bits 0-127 of the vector of installed parameter block formats correspond to parameter block formats 0-127 for non-query functions of the neural network processing assistance instruction. When a bit is, for example, 1, the corresponding parameter block format is installed; otherwise, the parameter block format is not installed.

[0089] Installed Data Types 336: This field of the parameter block (e.g., bytes 48-49) contains a vector of installed data types. R Bits 0 through 15 of the data type vector correspond to the data types to be installed. When a bit is, for example, 1, the corresponding data type is installed; otherwise, the data type is not installed. Example data types include: Additional , fewer and / or other data types are possible).

[0090] Bit Data Type

[0091] 0 NNP Data Type 1

[0092] 1~15 Reserved

[0093] Installed Data Layout Formats 338: This field (e.g., bytes 52-55) of the parameter block contains a vector of installed data layout formats. R Bits 0-31 of the data layout format vector correspond to the data layout formats to be installed. When a bit is, for example, 1, the corresponding data layout format is installed; otherwise, the data layout format is not installed. Exemplary data layout formats include ( addition (Of which, fewer and / or other data types are possible).

[0094] Bit Data Layout Format

[0095] 0 4D feature tensor

[0096] 1. 4D Kernel Tensor

[0097] 2~31 Reserved

[0098] Maximum Dimension Index Size 340: This field (e.g., bytes 60-63) of the parameter block specifies, for example, the maximum dimension index size for any specified tensor. Essential Basic number In another example, the maximum dimension index size is the number of elements in a given dimension index size for any given tensor. maximum byte number Other examples are also possible.

[0099] Maximum Tensor Size 342: This field of the parameter block (e.g., bytes 64-71) includes any pad bytes required by the tensor format, e.g. 、 In any given tensor most large byte In another example, the maximum tensor size is the number of elements in any specified tensor, including any padding required by the tensor format. Total number of Maximum of value Other examples are also possible.

[0100] Installed NNP Data Type 1 Transformation Vector 344: This field (e.g., bytes 72-73) of the parameter block contains the installed NNP Data Type 1 Transformation Vector. In one example, bits 0-15 of the installed NNP Data Type 1 Transformation Vector are: to and from NNP Data Type 1 format Installed De When a bit is 1, the corresponding conversion is installed; otherwise, the conversion is not installed. addition More, fewer and / or other transformations may be specified.

[0101] Bit Data Type

[0102] 0 Reserved

[0103] 1 BFP small format

[0104] 2 BFP Short Format

[0105] 3-15 Reserved

[0106] Although an example of a parameter block for a query function is described with reference to FIG. 3E, other formats of a parameter block for a query function, including the NNPA-Query Available Functions operation, may be used. The format, in one example, may depend on the type of query function being performed. Furthermore, the parameter block and / or each field of the parameter block may be: addition The information may include less and / or other information.

[0107] In addition to the parameter block for query functions, in one example there is a parameter block format for non-query functions, such as the non-query functions of the Neural-Network Processing Assist instructions. An example of a parameter block used by a non-query function, such as the AVGPOOL2D function of the Neural-Network Processing Assist instructions, is described with reference to FIG. 3F.

[0108] As shown, in one example, parameter block 350 employed by, for example, a non-query function of a neural network processing aid instruction includes, for example:

[0109] Parameter Block Version Number 352: This field (e.g., bytes 0-1) of the parameter block specifies the version and size of the parameter block. In one example, bits 0-8 of the parameter block version number are reserved and contain zeros, and bits 9-15 of the parameter block version number contain an unsigned binary integer that specifies the format of the parameter block. The query function provides a mechanism to indicate available parameter block formats. When a specified parameter block size or format is not supported by the model, a response code of, for example, 0001 hex is stored in general register 0, and the instruction is completed by setting a condition code, for example, condition code 1. The parameter block version number is specified by the program and is not modified during instruction execution.

[0110] Model Version Number 354: This field (e.g., byte 2) of the parameter block is an unsigned binary integer that identifies the model that executes the instruction (e.g., a particular non-query function). When the Continue Flag (described below) is 1, the Model Version Number may be input to an operation that interprets the contents of the Continuation State Buffer field (described below) of the parameter block to resume operation.

[0111] Continuation flag 356: This field (e.g., bit 63) of the parameter block, when set to 1, indicates that the operation is partially complete and the contents of the continuation state buffer can be used to resume the operation. Programs should initialize the continuation flag to zero and not modify it if an instruction is re-executed to resume the operation; otherwise, the results are unpredictable.

[0112] If the continue flag is set at the beginning of the operation and the contents of the parameter block have changed since the initial call, the results are unpredictable.

[0113] Function-specific save area address 358: This field of the parameter block (e.g., bytes 56-63) contains the logical address of the function-specific save area. In one example, the function-specific save area address is aligned on a 4K byte boundary; otherwise, a response code of, e.g., 0015 hex is set in general register 0 and the instruction completes with a condition code of, e.g., 1. The address is affected by the current addressing mode. The size of the function-specific save area depends on the function code.

[0114] When the entire function-specific save area overlaps with a Program Event Record (PER) storage area specification, PER storage modification events are recognized for the function-specific save area, when applicable. When only a portion of the function-specific save area overlaps with a PER storage area specification, it is model-dependent which of the following occurs:

[0115] * When applicable, PER storage modification events are recognized for the entire function-specific save area.

[0116] * When applicable, PER storage modification events are recognized for portions of the stored function-specific save area.

[0117] When an entire parameter block overlaps with a PER storage area specification, a PER storage change event is recognized for the parameter block, when applicable. When only a portion of a parameter block overlaps with a PER storage area specification, it is model-dependent which of the following occurs:

[0118] * When applicable, PER storage change events are recognized for the entire parameter block.

[0119] * When applicable, PER storage change events are recognized for parts of the stored parameter block.

[0120] When applicable, a PER zero address detection event is recognized for parameter blocks. Zero address detection, in one example, does not apply to tensor addresses or function-specific save area addresses.

[0121] Output tensor descriptor (e.g., 1-2) 360 / Input tensor descriptor (e.g., 1-3) 365: An example of a tensor descriptor is described with reference to Figure 3G. In one example, the tensor descriptors 360, 365 include:

[0122] Data Layout Format 382: This field (e.g., byte 0) of the tensor descriptor specifies the data layout format. Valid data layout formats include, for example: addition (More, fewer and / or other data layout formats are possible).

[0123] Format Description Alignment (bytes)

[0124] 0 4D feature tensor 4096

[0125] 1 4D kernel tensor 4096

[0126] 2-255 Reserved

[0127] If an unsupported or reserved data layout format is specified, a response code of, for example, 0010 hex is stored in general register 0 and the instruction completes by setting a condition code, for example, 1.

[0128] Data Type 384: This field (e.g., byte 1) specifies the data type of the tensor. Examples of supported data types are described below ( addition (Of which, fewer and / or other data types are possible).

[0129] Value Data type Data size (bits)

[0130] 0 NNP data type 1 16

[0131] 1~255 Reserved

[0132] If an unsupported or reserved data type is specified, a response code, for example 0011 hex, is stored in general register 0 and the instruction completes by setting a condition code, for example 1.

[0133] Dimension 1-4 Index Size 386: Dimension index sizes 1-4 collectively specify the shape of a 4D tensor. Each dimension index size is greater than zero and less than or equal to the maximum dimension index size (340, Figure 3E); otherwise, a response code, e.g., 0012 hex, is stored in general register 0 and the instruction completes by setting a condition code, e.g., 1. The total tensor size is less than or equal to the maximum tensor size (342, Figure 3E); otherwise, a response code, e.g., 0013 hex, is stored in general register 0 and the instruction completes by setting a condition code, e.g., 1.

[0134] In one example, to determine the number of bytes in a 4D feature tensor with elements of NNPA data type 1 (i.e., the total tensor size), the following is used: dimension index 4 * dimension index 3 * cell(dimension index 2 / 32) * 32 * cell(dimension index 1 / 64) * 64 * 2, as shown below.

[0135] Tensor Address 388: This field of the tensor descriptor (e.g., bytes 24-31) contains the logical address of the leftmost byte of the tensor. The address is affected by the current addressing mode.

[0136] If the address is not aligned on a boundary of the associated data layout format, a response code, for example 0014 hex, is stored in general register 0 and the instruction completes by setting a condition code, for example 1.

[0137] In Access Register mode, Access Register 1 contains all active registers in storage. Na input tensor and specify the address space containing the output tensor.

[0138] Returning to FIG. 3F, parameter block 350 also includes (370), in one example, function-specific parameters 1-5 that may be used by particular functions as described herein.

[0139] Additionally, parameter block 350 includes a continuation state buffer field 375, which in one example contains data (or the location of data) to be used if operation of this instruction is resumed.

[0140] As input to the operation, the reserved fields of the parameter block should contain zero. When the operation finishes, the reserved fields may be stored as zero or may remain unchanged.

[0141] Although an example of a parameter block for a non-query function is described with reference to FIG. 3F, other formats of parameter blocks for non-query functions may be used, including non-query functions of neural network processing assistance instructions. The format may, in one example, depend on the type of function being performed. Furthermore, although an example of a tensor descriptor is described with reference to FIG. 3G, other formats may be used. Furthermore, the input tensor and different formats for the output tensors may be used. Other variations are possible.

[0142] Further details regarding the various functions supported by one embodiment of the neural network processing assistance instructions are provided below.

[0143] Function code 0: NNPA-QAF (Query Available Functions)

[0144] The Neural Network Processing Assistant (NNPA) query function provides a mechanism for indicating selected information, such as the availability of functions to be installed, parameter block formats to be installed, data types to be installed, data layout formats to be installed, maximum dimension index sizes, and maximum tensor sizes. The information is retrieved and placed in selected locations, such as parameter blocks (e.g., parameter block 330). When the operation is complete, reserved fields in the parameter blocks may be stored as zeros or may remain unchanged.

[0145] In performing one embodiment of the query function, a processor, such as general-purpose processor 104, obtains information related to a particular processor, such as a particular model of a neural network processor, such as neural network processor 105. A particular model of a processor or machine has particular capabilities. Another model of a processor or machine may addition and / or additionThe retrieved information may be of a different generation (e.g., current or future generations) having fewer and / or different capabilities. The retrieved information is placed in a parameter block (e.g., parameter block 330) or other structure for accessibility to and / or use with one or more applications that may use this information in further processing. In one example, the parameter block and / or information in the parameter block is maintained in memory. In other embodiments, the parameter block and / or information may be maintained in one or more hardware registers. As another example, the query function may be a privileged operation executed by an operating system, Privileged Operations teeth, child Information on a Make it available to applications or non-privileged programs Provides an application programming interface for In still a further example, the query function is executed by a dedicated processor, such as the neural network processor 105. Other variations are possible.

[0146] The information is obtained, for example, by firmware of the processor executing the query function. The firmware has knowledge of the attributes of the particular model of the particular processor (e.g., neural network processor). This information may be stored, for example, in control block registers and / or memory and / or otherwise accessible to the processor executing the query function.

[0147] The obtained information includes, for example, model-dependent detailed information regarding at least one or more data attributes of a particular processor, including, for example, one or more installed or supported data types, one or more installed or supported data layout formats, and / or one or more installed or supported data sizes of a selected model of a particular processor. This information is model-dependent in that other models (e.g., previous models and / or future models) may not support the same data attributes, such as the same data types, data sizes, and / or data layout formats. When execution of a query function (e.g., an NNPA-QAF function) is completed, a condition code of 0 is illustratively set. Condition codes 1, 2, and 3 are not applicable to the query function, in one example. Further information related to the obtained information is described below.

[0148] As shown, in one example, the obtained information includes model-dependent information about one or more data attributes, for example, of a particular model of a neural network processor. One example of a data attribute is the installed data type of the neural network processor. For example, a particular model of a neural network processor (or other processor) may support one or more data types, such as, for example, the NNP Data Type 1 data type (also referred to as the Neural Network Processing Data Type 1 data type) and / or other data types. The NNP Data Type 1 data type is a 16-bit floating-point format that provides several advantages to deep learning training and inference calculations, including, for example, maintaining the accuracy of deep learning networks; eliminating non-normalized formats that simplify rounding modes and corner case handling; automatic rounding to nearest for arithmetic operations; and the special entities of infinity and not-a-number (NaN) being combined into a single value (NINF) that is accepted and handled by arithmetic operations. NINF provides better defaults for exponent overflow and invalid operations (such as division by zero). This allows many programs to continue executing without hiding such errors and without using dedicated exception handlers. Other model-dependent data types are possible.

[0149] An example of the format of the NNP Data Type 1 data type is illustrated in Figure 4. As shown, in one example, NNP Data Type 1 data may be represented in a format 400 that includes, for example, a sign 402 (e.g., bit 0), an exponent +31 404 (e.g., bits 1-6), and a fraction 406 (e.g., bits 7-15).

[0150] Exemplary characteristics of the NNP Data Type 1 format are illustrated below.

[0151] Characteristics NNP Data Type 1

[0152] Format length (bits) 16 bits

[0153] Biased exponent length (bits) 6 bits

[0154] Fraction length (bits) 9 bits

[0155] Precision (p) 10 bits

[0156] Maximum left unit exponent (Emax) 32

[0157] Minimum left unit display exponent (Emin) -31

[0158] Left Unit Display (LUV) Bias 31

[0159] Nmax (1-2 -9 )×2 33 ≒8.6×10 9

[0160] Nmin (1+2 -9 )×2 -31 ≒4.6×10 -10

[0161] Dmin――― where ≒ indicates that the value is approximate, Nmax is the largest representable finite number (in magnitude), and Nmin is the smallest representable number (in magnitude).

[0162] Further details relating to the NNP Data Type 1 data type are explained below.

[0163] Biased Exponent: The bias used to allow the exponent to be expressed as an unsigned number is shown above. The biased exponent is similar to the properties of the binary floating-point formats, except that no special meaning is attached to biased exponents of all zeros and all ones, as explained below with reference to the NNP Data Type 1 data type class.

[0164] Mantissa: The binary point of an NNP data type 1 number is considered to be to the left of the leftmost fraction bit. To the left of the binary point there is an implied unit bit that is considered to be one for normal numbers and zero for zero. The fraction with the implied unit bit appended to the left is the mantissa of the number.

[0165] A typical NNP data type 1 value is the mantissa multiplied by a base 2 number raised to the power of an unbiased exponent.

[0166] Non-zero Number Values: Non-zero number values ​​are shown below.

[0167] Number Class Value

[0168] Normal number ±2 e-31 ×(1.f) where e is the biased exponent in decimal and f is the fraction in binary.

[0169] In one embodiment, there are three classes of NNP Data Type 1 data, including numeric values ​​and associated non-numeric entities. Each data item includes a sign, an exponent, and a mantissa. The exponent is biased so that all biased exponents are non-negative unsigned numbers, with the minimum biased exponent being zero. The mantissa includes an explicit fraction and an implicit unit bit to the left of the binary point. The sign bit is zero for positive and one for negative.

[0170] Every allowable non-zero finite number has a unique NNP data type 1 representation. There are no denormalized numbers, which are numbers that may allow multiple representations of the same value, and there are no denormalized arithmetic operations. The three classes include, for example:

[0171] Data Class Sign Biased Exponent Unit Bits* Fraction

[0172] Zero ± 0 0 0

[0173] Normal number ± 0 1 non-0

[0174] Normal number ± non-zero, not all ones 1 Any

[0175] Normal number ± all ones not all ones

[0176] NINF ± All 1 All 1 where - indicates not applicable, * indicates the unit bit is implicit, and NINF is not a number or infinity.

[0177] Further details regarding each of the classes are described below.

[0178] Zero: Zero has a biased exponent of zero and a fraction of zero. The implicit unit bit is zero.

[0179] Normal Numbers: Normal numbers can have a biased exponent of any value. When the biased exponent is 0, the fraction is non-zero. When the biased exponent is all ones, the fraction is not all ones. Other biased exponent values ​​can have any fractional value. The implicit unit bit is of normal numbers In , 1.

[0180] NINF: NINF is represented by a biased exponent of all ones and a fraction of all ones. NINF represents values ​​that are not in the range of representable values ​​in the NNP data type 1 (i.e., 16-bit floating point designed for deep learning, with 6 exponent bits and 9 fraction bits). Typically, NINF is only propagated during computation so that it remains represented until the end.

[0181] While the NNP Data Type 1 data type is supported in one example, other proprietary or non-standard data types may be supported, as well as one or more standard data types, including, but not limited to, IEEE 754 short precision, binary floating point 16-bit, IEEE half precision floating point, 8-bit floating point, 4-bit integer format, and / or 8-bit integer format, to name a few. These data formats have different qualities for neural network processing. For example, smaller data types (e.g., fewer bits) can be processed faster and use less cache / memory, while larger data types provide higher accuracy results in neural networks. Supported data types may have one or more allocated bits in the query parameter block (e.g., in the installed data types field 336 of the parameter block 330). For example, proprietary or non-standard data types supported by a particular processor are indicated in the installed data types field, while standard data types are not. In other embodiments, one or more standard data types are also indicated. Other variations are possible.

[0182] In one particular example, bit 0 of installed data types field 336 is reserved for the NNP Data Type 1 data type, and when set to, for example, 1, indicates that the processor supports NNP Data Type 1. By way of example, a bit vector of installed data types may be configured to represent up to 16 data types, with a bit assigned to each data type. However, bit vectors in other embodiments may support more or fewer data types. Additionally, vectors may be configured in which one or more bits are assigned to a data type. Many examples are possible, and / or addition Fewer and / or other data types may be supported and / or represented in vectors.

[0183] In one example, the query function obtains an indication of the data types installed on the model-dependent processor and places the indication in the parameter block, e.g., by setting one or more bits in the installed data type field 336 of the parameter block 330. Additionally, in one example, the query function obtains an indication of the installed data layout format (another data attribute) and places the information in the parameter block, e.g., by setting one or more bits in the installed data layout format field 338. Exemplary data layout formats include, for example, a 4D feature tensor layout and a 4D kernel tensor layout. The 4D feature tensor layout is used in one example by the functions shown herein, and in one example, the convolution function uses the 4D kernel tensor layout. These data layout formats arrange data in storage for tensors in a manner that increases processing efficiency in the execution of the functions of the neural network processing assistance instructions. For example, to operate efficiently, the neural network processing assistance instructions use input tensors that are provided in a particular data layout format. Show The layout is provided, addition Fewer and / or other layouts may be provided for the functions described herein and / or other functions.

[0184] The use or availability of layouts for a particular processor model is provided by a vector of installed data layout formats (e.g., field 338 of parameter block 330). The vector may be, for example, a bit vector of installed data layout formats that allows the CPU to communicate which layouts are supported to an application. For example, bit 0 is reserved for the 4D feature tensor layout and, when set to 1, indicates that the processor supports the 4D feature tensor layout; bit 1 is reserved for the 4D kernel tensor layout and, when set to 1, indicates that the processor supports the 4D kernel tensor layout. In one example, the bit vector of installed data layout formats is configured to represent up to 16 data layouts, with a bit assigned to each data layout. However, bit vectors in other embodiments may support more or fewer data layouts. Furthermore, vectors may be configured in which one or more bits are assigned to a data layout. Many examples are possible. Further details regarding the 4D feature tensor layout and the 4D kernel tensor layout are described below. Here as well ,To optimize performance, other layouts are the current or may be used in the future.

[0185] In one example, the neural network processing assistance instructions operate with 4D tensors, i.e., tensors with four dimensions. These 4D tensors are obtained from the general-purpose input tensors described herein, e.g., row-major, i.e., when enumerating the tensor elements in order of increasing memory address, the inner dimension, called E1, is first stepped up through the E1 index size value starting from 0 to E1 index size - 1, then the index of the E2 dimension is incremented and the step through the E1 dimension is repeated. The index of the outer dimension, called the E4 dimension, is incremented last.

[0186] twist few Tensors with several dimensions (e.g., 3D or 1D tensors) are represented as 4D tensors, exceeding the dimensions of the original tensor One or more dimensions of a 4D tensor set to 1 And do.

[0187] Converting a row-major generalized 4D tensor with dimensions E4, E3, E2, E1 to a 4D feature tensor layout (also referred to herein as an NNPA data layout format 0 4D feature tensor) is described herein.

[0188] For example, the resulting tensor can be e.g. a 64 element vector As a 4D tensor consisting of or below 5D tensor with dimensions and It can be expressed as:

[0189]

number

number

[0190] The elements [e4][e3][e2][e1] of the generic tensor can be mapped to the following elements of the resulting 5D tensor:

[0191]

number

number

number

number

number

[0192] The resulting tensor can be larger than the generalized tensor. Elements of the resulting tensor that do not have a corresponding element in the generalized tensor are called pad elements.

[0193] NNPA Data Layout Format for 64 Element Vectors Consider an element [fe4][fe1][fe3][fe2][fe0] or equivalent representation of a 4D feature tensor as a 5D tensor of elements. This element is a pad element, or its corresponding element in a generalized 4D tensor of dimensions E4, E3, E2, E1 can be determined by the following formula:

[0194] If fe2≧E2, then this is an E2 (or page) pad element.

[0195] Otherwise, if fe1*64+fe0≧E1, then this is an E1 (or row) pad element.

[0196] Otherwise, the corresponding element in the generic 4D tensor is

[0197] [fe4][fe3][fe2][fe1*64+fe0].

[0198] For convolutional neural network-based artificial intelligence models, the meaning of the four dimensions of a feature tensor can roughly be mapped to the following:

[0199] E4:N - Minibatch size

[0200] E3:H - 3D tensor / image height

[0201] E2:W - Width of 3D tensor / image

[0202] E1:C - Channel or class of 3D tensor

[0203] For machine learning or recurrent neural network based artificial intelligence models, the meaning of the four dimensions of a 4D feature tensor can be roughly mapped to the following:

[0204] E4:T - Number of time steps or models

[0205] E3: Reserved, typically set to 1

[0206] E2:N mb -Minibatch size

[0207] E1:L-Feature

[0208] NNPA Data Layout Format 0, for example, provides two-dimensional data locality with 4K byte blocks (pages) of data, and 4K byte block data alignment for the outer dimensions of the generated tensors.

[0209] Pad element bytes are ignored in input tensors and are unpredictable in output tensors. PER storage changes on pad bytes are unpredictable.

[0210] An example of an input data layout for a 4D feature tensor layout having dimensions E1, E2, E3, and E4 is shown in FIGS. 5A-5C, and an example output for the 4D feature tensor layout is illustrated in FIGS. 6A-6C. Referring to FIG. 5A, a 3D tensor 500 is shown having dimensions E1, E2, and E3. In one example, each 3D tensor includes multiple 2D tensors 502. Numbers in each 2D tensor 502 describe the memory offset of where each of its elements is located in memory. The input is used to layout the data of the original tensor (e.g., the original 4D tensor of FIGS. 5A-5C) in memory as shown in FIGS. 6A-6C, which correspond to FIGS. 5A-5C.

[0211] 6A , by way of example, a unit of memory 600 (e.g., a memory page) includes a preselected number (e.g., 32) of rows 602, each identified, for example, by e2_page_idx, and each row has a preselected number (e.g., 64) of elements 604, each identified, for example, by e1_page_idx. If a row does not include the preselected number of elements, it is padded 606, also referred to as row or E1 padding; if the memory unit does not have the preselected number of rows, it is padded 608, also referred to as page or E2 padding. By way of example, row padding may be, for example, zero or another value, and page padding may be, for example, an existing value, zero, or another value.

[0212] In one example, output elements for a row are provided in memory (e.g., in a page) based on the element position in the E1 direction of its corresponding input. For example, referring to FIG. 5A, element positions 0, 1, and 2 (e.g., element positions at the same position in each matrix) of the three matrices shown are shown in row 0 of page 0, such as in FIG. 6A. In this example, the 4D tensor is small, and all of the elements of each 2D tensor representing the 4D tensor fit on one page. However, this is merely an example. A 2D tensor may include one or more pages. If a 2D tensor is generated based on reformatting a 4D tensor, the number of pages for the 2D tensor is based on the size of the 4D tensor. In one example, one or more cell functions are used to determine the number of rows in the 2D tensor and the number of elements in each row, which indicates how many pages will be used. Other variations are possible.

[0213] In addition to 4D feature tensor layouts, in one example, a neural network processor may support 4D kernel tensors that rearrange elements of a 4D tensor to reduce the number of memory accesses and data collection stages when performing certain artificial intelligence (e.g., neural network processing aids) operations such as convolution. As an example, a row-major generalized 4D tensor with dimensions E4, E3, E2, E1 is converted to the NNPA data layout format 1 4D kernel tensor described herein.

[0214] The resulting tensor can be represented as a 4D tensor, for example a 64 element vector, or as a 5D tensor with the following dimensions:

[0215]

number

number

[0216] The elements [e4][e3][e2][e1] of the generic tensor can be mapped to the following elements of the resulting 5D tensor:

[0217]

number

number

number

number

number

[0218] The resulting tensor can be larger than the generalized tensor. Elements of the resulting tensor that do not have a corresponding element in the generalized tensor are called pad elements.

[0219] NNPA Data Layout Format for 64 Element Vectors Consider an element [fe1][fe4][fe3][fe2][fe0] of a 4D feature tensor, or an equivalent representation, as a 5D tensor of elements. This element is a pad element, or its corresponding element in a generalized 4D tensor with dimensions E4, E3, E2, E1 can be determined by the following formula:

[0220] If fe2≧E2, then this is an E2 (or page) pad element.

[0221] Otherwise, if fe1*64+fe0≧E1, then this is an E1 (or row) pad element.

[0222] Otherwise, the corresponding element in the generic 4D tensor is

[0223] [fe4][fe3][fe2][fe1*64+fe0]

[0224] For convolutional neural network-based artificial intelligence models, the meaning of the four dimensions of the kernel tensor can roughly be mapped to the following:

[0225] E4:H - 3D tensor / image height

[0226] E3:W - Width of 3D tensor / image

[0227] E2: Number of channels in the C-3D tensor

[0228] E1:K - Number of kernels

[0229] NNPA Data Layout Format 1, for example, provides two-dimensional kernel parallelism within 4k-byte blocks of data (pages) and 4k-byte block data alignment on the outer dimensions of the generated tensor for efficient processing.

[0230] Pad bytes are ignored for input tensors; PER storage changes on pad bytes are unpredictable.

[0231] Here too Similarly, exemplary data layout formats include a 4D feature tensor layout and a 4D kernel tensor layout, although other data layout formats may be supported by a processor (e.g., neural network processor 105). An indication of the supported data layouts is obtained and placed in the query parameter block, for example, by setting one or more bits in field 338.

[0232] The query parameter block also includes other data attribute information, including, for example, supported size information for the data, in accordance with one or more aspects of the present invention. Processors, such as neural network processors, typically have limitations based on internal buffer sizes, processing units, data bus structures, firmware limitations, etc., that may limit the maximum size of tensor dimensions and / or the overall size of tensors. Therefore, the query function provides fields to communicate these limitations to the application. For example, the processor may determine the maximum dimension index size (e.g., 65,536 elements) based on the execution of the query function. and the maximum tensor size (e.g., 8GB) Various data sizes such as of 3. Obtain and store the parameter values ​​in fields 340 and 342 of a parameter block (e.g., parameter block 330). Each of to child Information on include . additionFewer and / or other size information may also be supported by a processor (e.g., neural network processor 105) and thus obtained and placed in the parameter block, e.g., fields 340, 342 and / or other fields. In other embodiments, the limits may be smaller or larger, and / or the size may be in other units, such as bytes rather than elements, elements rather than bytes, etc. Furthermore, other embodiments allow for different maximum sizes for each dimension, rather than the same maximum for all dimensions. Many variations are possible.

[0233] According to one or more aspects of the present invention, a query function is provided that conveys detailed information related to a particular model of a selected processor (e.g., neural network processor 105). The detailed information includes, for example, model-dependent information related to a particular processor. (The processor may also support standard data attributes, such as standard data types, standard data layouts, etc., that are implicit and not necessarily represented by the query function; in other embodiments, the query function may indicate all or various selected subsets of the data attributes, etc.) While exemplary information is provided, other information may be provided in other embodiments. The obtained information, which may be different for different models of processors and / or different processors, is used to perform artificial intelligence and / or other processing. The artificial intelligence and / or other processing may employ one or more non-query functions of, for example, neural network processing-aided instructions. A particular non-query function employed in a process may execute the neural network processing-aided instructions one or more times, The specific Non-query Seki This is done by specifying a number.

[0234] Examples of non-query functions supported by neural network processing assistance instructions include the AVGPOOL2D and MAXPOOL2D functions, each of which is described below ( addition (Of which, fewer and / or other functions may be supported in one or more embodiments).

[0235] Function code 80:NNPA-MAXPOOL2D Function code 81: NNPA-AVGPOOL2D

[0236] When either the NNPA-MAXPOOL2D or NNPA-AVGPOOL2D function is specified 、 by input tensor 1 descriptor (see e.g. Figure 3G) Description Input tensor 1 to be teeth , finger By the specified operation contraction And aggregates the input window The window of inputs is selected by moving a 2D sliding window on dimensions 2 and 3. Aggregation is the output tensor 1 The sliding window dimension is determined, for example, by function-specific parameter 4 and function-specific parameter 5. Description Next door contact The amount by which the sliding window moves over the input tensor 1 when computing the output tensor elements is called the stride. of The stride is specified, for example, by function-specific parameter 2 and function-specific parameter 3. When the NNPA-MAXPOOL2D operation is specified, the Max operation defined below is performed on the window. When the NNPA-AVGPOOL2D operation is specified, the AVG operation defined below is performed on the window. If the specified padding type is Valid, all elements in the window are added to the set used to compute the resulting output elements. If the specified padding type is identical, depending on the position of the window, only a subset of elements from the window may be added to the set used to compute the resulting output elements (e.g., those elements outside the bounds of the tensor may be ignored).

[0237] In one example, the CollectElements operation adds elements to a collection of elements and increments the number of elements in the collection. Each time the window start position is moved, the collection is emptied. It is unpredictable whether elements not needed to perform the operation are accessed.

[0238] Max Operation: In one example, the maximum value of a set of elements in a window is calculated by comparing all elements in the set with each other and returning the maximum value.

[0239] AVG (average) operation: In one example, the average value of a set of elements in a window is calculated, e.g., by dividing all elements in the set by the sum of of Essential Divided by a prime number and It is calculated as follows.

[0240] In one example, the fields are assigned as follows:

[0241] * Pooling function specific parameter 1 controls the padding type. For example, bits 29-31 of function specific parameter 1 contain a pad field that specifies the padding type. Example types include, for example:

[0242] Pads, padding type

[0243] 0 Enabled

[0244] 1 Same

[0245] 2~7 Reserved

[0246] Reserved values ​​are entered in the pad field. finger If so, a response code of, for example, F000 hex is reported and the operation completes with a condition code of, for example, 1.

[0247] In one example, bit positions 0-28 of Function Specific Parameter 1 are reserved and contain zeros.

[0248] * Function-specific parameter 2 contains, for example, a 32-bit unsigned binary integer specifying the dimension 2 stride (D2S), which specifies the number of elements (also referred to as e2) that the sliding window moves in dimension 2.

[0249] * Function-specific parameter 3 contains, for example, a 32-bit unsigned binary integer specifying the dimension 3 stride (D3S), which specifies the number of elements (also referred to as e3) that the sliding window moves in dimension 3.

[0250] * Function-specific parameter 4 contains a 32-bit unsigned binary integer that specifies, for example, the dimension 2 window size (D2WS), which specifies the number of elements in dimension 2 that the sliding window will contain.

[0251] * Function-specific parameter 5 contains, for example, a 32-bit unsigned binary integer that specifies the dimension 3 window size (D3WS), which specifies the number of elements in dimension 3 that the sliding window will contain.

[0252] In one example, the values ​​specified in function-specific parameters 2-5 are less than or equal to the maximum dimension index size, and the values ​​specified in function-specific parameters 4-5 are greater than, for example, zero; otherwise, a response code, for example, 0012 hex, is reported and the operation completes with a condition code, for example, 1.

[0253] If both the dimension 2 stride and the dimension 3 stride are zero, and either the dimension 2 window size or the dimension 3 window size is greater than, for example, 1024, a response code, for example, F001 hex, is stored. If both the dimension 2 stride and the dimension 3 stride are greater than, for example, zero, and either the dimension 2 window size or the dimension 3 window size is greater than, for example, 64, a response code, for example, F002 hex, is stored. If both the dimension 2 stride and the dimension 3 stride are greater than, for example, zero, and either the dimension 2 stride or the dimension 3 stride is greater than, for example, 30, a response code, for example, F003 hex, is stored. If both the dimension 2 stride and the dimension 3 stride are greater than, for example, zero, and either the input tensor dimension 2 index size or the input tensor dimension 3 index size is greater than, for example, 1024, a response code, for example, F004 hex, is stored. For all of the above conditions, the instruction completes with a condition code, for example, 1.

[0254] In one example, if the specified data layout in any of the specified tensor descriptors does not specify a 4D feature tensor (e.g., data layout = 0), or if the data type in any of the specified tensor descriptors does not specify an NNP data type 1 (e.g., data type = 0), a response code, e.g., 0010 hex or 0011 hex, respectively, is set in general register 0, and the instruction completes with a condition code, e.g., 1.

[0255] In one example, the following conditions are true otherwise a general operand data exception is recognized:

[0256] * The dimension 4 index size and dimension 1 index size of the input and output tensors are identical.

[0257] * The data layout and data types of the input and output tensors are identical.

[0258] * When both dimension 2 stride and dimension 3 stride are zero (for example, the average of the AVGPOOL2D function) contraction (specifying an operation), in one example, the following additional conditions are true:

[0259] * The input tensor dimension 2 index size is equal to the dimension 2 window size.

[0260] The input tensor dimension 3 index size is equal to the dimension 3 window size.

[0261] The output tensor's dimension 2 index size and dimension 3 index size are 1.

[0262] * The specified padding is valid.

[0263] *If either the dimension 2 stride or the dimension 3 stride is non-zero, then in one example both strides are non-zero.

[0264] * If both dimension 2 stride and dimension 3 stride are greater than zero (e.g., specifying a pooling operation for the AVGPOOL2D function), then in one example the following additional condition is true:

[0265] When the specified padding is in effect, the dimension 2 window size is less than or equal to the dimension 2 index size of the input tensor.

[0266] When the specified padding is in effect, the dimension 3 window size is less than or equal to the dimension 3 index size of the input tensor.

[0267] * When the specified padding is identical, the following relationship between the dimension 2 index size and dimension 3 index size of the input and output tensors is satisfied (Pooling Same Padding).

[0268]

number

[0269]

number

[0270] where:

[0271] IxDyIS: Dimension y index size of input tensor x defined in tensor descriptor x

[0272] OxDyIS: Dimension y index size of output tensor x defined in tensor descriptor x

[0273] D2S: Dimension 2 Stride

[0274] D3S: Dimension 3 Stride

[0275] * When the specified padding is valid, the input tensor and the following relationship between the dimension 2 index size and dimension 3 index size of the output tensor is satisfied (Pooling Valid Padding):

[0276]

number

[0277]

number

[0278] where D2WS is the dimension 2 window size and D3WS is the dimension 3 window size.

[0279] Output tensor descriptor 2, Input tensor descriptor 2 and 3. and The function-specific save area address field is ignored.

[0280] For neural network processing assistance instructions, in one embodiment, the output tensor is Any Input tensor or parameter block and If they overlap, the results are unpredictable.

[0281] As an example, When an attempt is made to execute a neural network processing aid instruction and the parameter block is rewritten, for example, on a double word boundary, finger When not specified, a specification exception is recognized.

[0282] When an attempt is made to execute a neural network processing assistance instruction and there is, for example, a tensor descriptor mismatch, a general operand data exception is recognized.

[0283] Resulting condition codes for neural network processing assistance instructions include, for example, 0 - successful completion; 1 - response code is set; 2 -; 3 - amount of data determined by the CPU is processed.

[0284] In one embodiment, execution priorities for neural network processing assistance instructions include, for example:

[0285] 1-7. Exceptions with the same priority as the program interrupt condition for the general case

[0286] 8.A Condition Code 1 resulting from specifying an unassigned or uninstalled function code

[0287] 8.B Specification Exception Caused by Parameter Block Not Aligned on Double-Word Boundary

[0288] 9. Access exception for accessing parameter blocks

[0289] 10. Condition code 1 due to the specified format of the parameter block not being supported by the model.

[0290] 11.A Condition code 1 due to the specified tensor data layout being unsupported

[0291] 11.B Generic operand data exception due to different data layouts between tensor descriptors

[0292] 12.A Condition Code 1 resulting from conditions other than those included in items 8.A, 10, and 11.A above and 12.B.1 below.

[0293] 12.B.1 Condition Code 1 due to invalid output tensor data type for NNPA-RELU and NNPA-CONVOLUTION

[0294] 12.B.2 General Operand Data Exception for Invalid Values ​​for NNPA-RELU Function-Specific Parameter 1 and NNPA-CONVOLUTION Function-Specific Parameter 4

[0295] 13.A Access Exception for Accessing Output Tensors

[0296] 13.B Access Exception for Accessing Input Tensors

[0297] 13.C Access exception for access to function-specific storage area

[0298] 14. Condition Code 0

[0299] As described herein, a single instruction (e.g., a neural network processing assistance instruction) is configured to perform multiple functions, including a query function and multiple non-query functions. At least one non-query function, the AVGPOOL2D function, performs multiple operations (e.g., average contraction and pooling). By using one function to perform multiple operations, for example, redundant encoding and verification are eliminated. Should The particular operation depends on the value of a select input parameter to the function. The same input parameter is used for both operations of the function, but different values ​​of the select parameter indicate the operation to be performed and result in different bounds checking of the other input parameters. Contraction Operations and pooling operations are performed differently And However, they use the same input tensors and function-specific parameters. Use, They can be algorithmically reduced to a common algorithmic operation with different relative constraints. One difference is that different conditions (e.g., stride, window size) are checked between the two operations. As described herein, multiple operations can be performed. and implement different bounds checks for both operations on some of the parameters. A single function of instruction is provided R This at least reduces code complexity, code duplication, and verification effort.

[0300] One or more aspects of the present invention are closely tied to computer technology and facilitate processing within computers and improve their performance. The use of a single architecture machine instruction configured to perform various functions improves performance within a computing environment by reducing complexity, reducing resource usage, and increasing processing speed. The use of a single function to implement multiple operations reduces complexity, resource usage, coding and / or verification effort, and improves system performance. The instructions, functions, and / or operations may be used in many technical fields, such as computer processing, medical processing, engineering, automotive technology, manufacturing, etc. By providing optimizations, these technical fields are improved, for example, by reducing errors and / or execution times.

[0301] Further details of one embodiment for facilitating processing within a computing environment in accordance with one or more aspects of the present invention are described with reference to Figures 7A-7C.

[0302] Referring to FIG. 7A, Should An indication of the function is obtained, where: The relevant The function is a function of instructions and is configured to perform a plurality of operations 700. An operation of the plurality of operations to be performed is determined 702, and a set of function-specific parameters is validated 704 using a set of values ​​and a corresponding set of relationships. Should Based on the operation 706. For example, a set of values ​​and a corresponding set of relations may be performed. Should The set of values ​​and corresponding set of relationships are used in another one of the operations 710 .

[0303] By using a single function, e.g., a single function of designed instructions, to perform multiple operations with validation for each operation parameter, code complexity, code duplication, and / or verification effort is reduced, improving system performance.

[0304] In one example, Should Determining the operation includes checking 720 one or more function-specific parameters against at least one particular value. 1 or multiple function-specific parameters has a first selection relationship to at least one particular value ,The operation is one operation,722, 1 or multiple function-specific parameters has a second selection relationship to at least one particular value Based on, the operation is another operation 724.

[0305] The same function is executed using specific parameters, but with different relationships. Should By determining the operations, code complexity and verification effort is reduced.

[0306] By way of example, the function may include an average pooling function, the one or more function-specific parameters may include one or more stride values, where the stride value is an amount by which a sliding window moves over the input tensor when calculating one or more adjacent output tensor elements, at least one particular value may include zero, the first selection relationship may include equality, and the operation may include averaging based on the one or more stride values ​​being equal to zero. contraction (mean-reduce) operation 726.

[0307] Further, in one example, referring to FIG. 7B, the second selection relation includes greater than and the operation is a pooling operation based on one or more stride values ​​being greater than zero 728.

[0308] By way of example, the set of function-specific parameters includes one or more select dimension window size values ​​730. The select dimension window size values ​​specify the number of elements in the select dimension that a sliding window will include 732, and the sliding window is configured to move over the input tensors of the function to generate an output tensor 734.

[0309] In one example, the function comprises an average pool function and the operation is an average contractionThe set of values ​​and corresponding relationships used to include operations and validate the set of function-specific parameters includes one value of one dimension of the selected input tensor and a corresponding relationship of equality, another value of another dimension of the selected input tensor and a corresponding relationship of equality, and a selected value and a corresponding relationship of less than or equality 740.

[0310] Validating may include, for example, checking that the dimension 2 window size value is equal to the dimension 2 value of the first input tensor, that the dimension 3 window size value is equal to the dimension 3 value of the first input tensor, that the dimension 2 window size value is less than or equal to a selected value, and that the dimension 3 window size value is less than or equal to a selected value 746.

[0311] In one example, FIG. three In accordance with the present invention, the function includes an average pool function, the operation includes a pooling operation, and the set of values ​​and corresponding relationships used to validate the set of function-specific parameters includes one value in one dimension of the selected input tensor and a corresponding relationship of being less than or equal to it, and another value in another dimension of the selected input tensor and a corresponding relationship of being less than or equal to it 750.

[0312] Validating may include, for example, checking that the dimension 2 window size value is less than or equal to the dimension 2 value of the first input tensor, and that the dimension 3 window size value is less than or equal to the dimension 3 value of the first input tensor 756.

[0313] In one example, a determination is made as to whether the padding type is set to a particular type, where the padding type indicates which elements of the window are used to compute the output, and in one or more embodiments, e.g., in a pooling operation, based on the padding type being set to a particular type, validation is performed 760. Further, in one example, based on the padding type not being set to a particular type, one or more checks related to one or more dimensions of the output tensor are performed 762.

[0314] In one example, determining the operation is based on at least one sliding window stride value of the input tensor 770, and the set of function-specific parameters includes at least one sliding window dimension of the input tensor 772.

[0315] Other variations and embodiments are possible.

[0316] Aspects of the present invention can be used with many types of computing environments. Another example of a computing environment for incorporating and using one or more aspects of the present invention is described with reference to Figure 8A. By way of example, the computing environment of Figure 8A is based on the z / Architecture® instruction set architecture offered by International Business Machines Corporation of Armonk, New York. However, the z / Architecture instruction set architecture is just one exemplary architecture. Here too Similarly, the computing environment may be based on other architectures, including, but not limited to, the Intel® x86 architecture, other architectures from International Business Machines Corporation, and / or architectures from other companies. Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0317] In one example, computing environment 10 includes a central electronic processing unit (CEC) 11. Central electronic processing unit 11 includes one or more processors, such as, for example, one or more general-purpose processors (i.e., central processing unit (CPU) 13) and one or more application-specific processors (e.g., neural network processor 31), and multiple components, such as memory 12 (i.e., system memory, main memory, main storage, central storage, storage) coupled to an input / output (I / O) subsystem 14.

[0318] By way of example, the one or more special purpose processors may be separate from the one or more general purpose processors and / or at least one For specific applications The processor may be incorporated within at least one general-purpose processor. Other variations are also possible.

[0319] I / O subsystem 14, which may be part of or separate from the central electronic processing unit, directs the flow of information between main storage 12 and input / output control 15 and input / output (I / O) devices 16 coupled to the central electronic processing unit.

[0320] Many types of I / O devices may be used. One particular type is a data storage device 17. The data storage device 17 may store one or more programs 18, one or more computer-readable program instructions 19, and / or data, etc. The computer-readable program instructions may be configured to perform the functions of embodiments of aspects of the present invention.

[0321] Central electronic processing unit 11 may be included in and / or coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, it may be included in and / or coupled to non-removable, non-volatile magnetic media (commonly referred to as a "hard drive"), a magnetic disk drive for reading from or writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), and / or an optical disk drive for reading from or writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM, or other optical media. It should be understood that other hardware and / or software components may be used in conjunction with central electronic processing unit 11. Examples include, but are not limited to, microcode or millicode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data archive storage systems, and the like.

[0322] Additionally, central electronic processing unit 11 may be operational with numerous other general purpose or special purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations that may be suitable for use with central electronic processing unit 11 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments, including any of the above systems or devices and the like.

[0323] Central electronic processing unit 11, in one or more embodiments, provides logical partition and / or virtualization support. In one embodiment, as shown in FIG. 8B, memory 12 includes, for example, one or more logical partitions 20, a hypervisor 21 that manages the logical partitions, and processor firmware 22. One example of hypervisor 21 is Processor Resource / System Manager (PR / SM™) offered by International Business Machines Corporation of Armonk, New York. PR / SM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0324] Each logical partition 20 is capable of functioning as a separate system. That is, each logical partition can be reset independently, run a guest operating system 23, such as the z / OS® operating system offered by International Business Machines Corporation of Armonk, New York, or other control code 24, such as Coupling Facility Control Code (CFCC), and operate using different programs 25. An operating system or application program running in a logical partition appears to have access to the entire and complete system, although in reality, only a portion of it is available. While the z / OS operating system is provided as an example, other operating systems offered by International Business Machines Corporation and / or other companies can be used in accordance with one or more aspects of the present invention.

[0325] Memory 12 is coupled to, for example, CPU 13 (FIG. 8A), which is a physical processor resource that can be assigned to a logical partition. For example, logical partition 20 can include one or more logical processors, each of which represents all or a portion of physical processor resource 13 that can be dynamically assigned to a logical partition.

[0326] In yet another embodiment, the central electronic processing unit provides virtual machine support (either with or without logical partition support). As shown in FIG. 8C, memory 12 of central electronic processing unit 11 includes, for example, one or more virtual machines 26, a virtual machine manager, such as hypervisor 27, that manages the virtual machines, and processor firmware 28. One example of hypervisor 27 is the z / VM® hypervisor offered by International Business Machines Corporation of Armonk, New York. A hypervisor is sometimes referred to as a host. z / VM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0327] The virtual machine support of the central electronic processing unit provides the ability to operate a large number of virtual machines 26, each capable of operating with a different program 29 and running a guest operating system 30, such as the Linux® operating system. Each virtual machine 26 can function as a separate system; that is, each virtual machine can be reset independently, run a guest operating system, and operate with different programs. An operating system or application program running in a virtual machine appears to have access to the entire and complete system, although in reality, only a portion of it is available. While z / VM and Linux are provided as examples, other virtual machine managers and / or operating systems may be used in accordance with one or more aspects of the present invention. The registered trademark Linux® is used pursuant to a sublicense from the Linux Foundation, an exclusive licensee of Linus Torvalds, owner of such trademark worldwide.

[0328] Another embodiment of a computing environment for incorporating and using one or more aspects of the present invention is described with reference to FIG. 9A. In this example, computing environment 36 includes, for example, a native central processing unit (CPU) 37, memory 38, and one or more input / output devices and / or interfaces 39, coupled together, for example, via one or more buses 40 and / or other types of connections. By way of example, computing environment 36 may include a PowerPC® processor offered by International Business Machines Corporation of Armonk, New York; an HP Superdome using an Intel® Itanium® II processor offered by Hewlett-Packard Company of Palo Alto, California; and / or other machines based on architectures offered by International Business Machines Corporation, Hewlett-Packard, Intel Corporation, Oracle, and / or others. (PowerPC is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.) Itanium is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0329] The native central processing unit 37 includes one or more native registers 41, such as one or more general purpose registers and / or one or more special purpose registers, that are used during processing within the environment. These registers contain information that represents the state of the environment at any particular time.

[0330] Additionally, native central processing unit 37 executes instructions and code stored in memory 38. In one particular example, central processing unit executes emulator code 42 stored in memory 38. This code allows a computing environment configured in one architecture to emulate another architecture. For example, emulator code 42 allows a machine based on an architecture other than the z / Architecture instruction set architecture, such as a PowerPC processor, HP Superdome server, or others, to emulate the z / Architecture instruction set architecture and execute software and instructions developed based on the z / Architecture instruction set architecture.

[0331] Further details related to emulator code 42 are described with reference to FIG. 9B . Guest instructions 43 stored in memory 38 comprise software instructions (e.g., correlated with machine instructions) developed to execute on an architecture other than native CPU 37. For example, guest instructions 43 may be designed to execute on a processor based on the z / Architecture instruction set architecture, but are instead emulated on native CPU 37, which may be, for example, an Intel Itanium II processor. In one example, emulator code 42 includes an instruction fetch routine 44 for retrieving one or more guest instructions 43 from memory 38 and optionally providing local buffering for the retrieved instructions. It also includes an instruction conversion routine 45 for determining the type of the retrieved guest instruction and translating the guest instruction into one or more corresponding native instructions 46. This translation may include, for example, identifying a function performed by the guest instruction and selecting a native instruction to perform the function.

[0332] Additionally, emulator code 42 includes an emulation control routine 47 for causing native instructions to be executed. Emulation control routine 47 may cause native CPU 37 to execute a routine of native instructions that emulates one or more previously fetched guest instructions, and upon completion of such execution, return control to an instruction fetch routine for emulating the fetch of the next guest instruction or group of guest instructions. Execution of native instructions 46 may include loading data from memory 38 into registers; storing data from registers back to memory; or performing some type of arithmetic or logical operation as determined by a translation routine.

[0333] Each routine may be implemented, for example, in software stored in memory and executed by native central processing unit 37. In other examples, one or more of the routines or operations may be implemented in firmware, hardware, software, or some combination thereof. The emulated processor's registers may be emulated using the native CPU's registers 41 or using locations in memory 38. In embodiments, guest instructions 43, native instructions 46, and emulator code 42 may reside in the same memory or may be distributed among different memory devices.

[0334] The instructions that may be emulated include the neural network assisted processing instructions described herein in accordance with one or more aspects of the present invention. Additionally, other instructions, functions, operations, and / or one or more aspects of neural network processing may be emulated in accordance with one or more aspects of the present invention.

[0335] The computing environments described above are merely examples of computing environments that may be used. Other environments may be used, including, but not limited to, non-partitioned, partitioned, cloud, and / or emulated environments, and embodiments are not limited to any one environment. While various examples of computing environments are described herein, one or more aspects of the present invention may be used with many types of environments. The computing environments provided herein are merely examples.

[0336] Each computing environment can be configured to include one or more aspects of the present invention.

[0337] One or more aspects may relate to cloud computing.

[0338] Although this disclosure includes detailed descriptions of cloud computing, it should be understood that implementation of the teachings described herein is not limited to a cloud computing environment. Rather, embodiments of the present invention can be implemented in conjunction with any other type of computing environment now known or later developed.

[0339] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with the service provider. The cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

[0340] The features are as follows:

[0341] On-Demand Self-Service: Cloud consumers can unilaterally provision computing capacity, such as server time and network storage, automatically as needed, without requiring human interaction with the provider of the service.

[0342] Wide network access: Capabilities are available over the network and accessed through standard mechanisms that facilitate use by heterogeneous thin or thick client platforms (e.g., cell phones, laptops, and PDAs).

[0343] Resource Pooling: Provider computing resources are pooled to serve multiple consumers using a multi-tenant model, with various physical and virtual resources dynamically allocated and reallocated in line with demand. Consumers generally have no control or knowledge over the exact location of the resources provided, although there is a type of location independence in that they may be able to specify location at a higher level of abstraction (e.g., country, state, or data center).

[0344] Rapid scalability: Capacity is provisioned quickly and elastically, sometimes automatically, and can be instantly scaled out or quickly released and instantly scaled in. To the consumer, the capacity available for provisioning often appears unlimited and can be purchased in any quantity at any point in time.

[0345] Metered Services: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities at a level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of utilized services.

[0346] The service model is as follows:

[0347] Software as a Service (SaaS): The consumer is offered the ability to use a provider's applications running on a cloud infrastructure. The applications are accessible from a variety of client devices through a thin-client interface such as a web browser (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.

[0348] Platform as a Service (PaaS): The ability offered to consumers is to deploy applications they create or acquire, written using programming languages ​​and tools supported by the provider, onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but does have control over the deployed applications and, in some cases, the application hosting environment configuration.

[0349] Infrastructure as a Service (IaaS): The ability provided to consumers is to provision processing, storage, network, and other basic computing resources onto which they can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but does have control over the operating systems, storage, deployed applications, and in some cases, limited control over selected networking components (e.g., host firewalls).

[0350] The deployment model is as follows:

[0351] Private Cloud: Cloud infrastructure is operated solely for the organization. It may be managed by the organization or a third party and may exist on-premise or off-premise.

[0352] Community Cloud: Cloud infrastructure is shared by multiple organizations to support a specific community with common interests (e.g., mission, security requirements, policies, and regulatory compliance considerations). Community clouds may be managed by those organizations or by a third party and may exist on-premises or off-premises.

[0353] Public Cloud: Cloud infrastructure is made available to the general public or large industry organizations and is owned by organizations that sell cloud services.

[0354] Hybrid Cloud: Cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain distinct entities but are bound together by standardized or proprietary technologies that allow for data and application portability (e.g., cloud bursting to load balance between clouds).

[0355] Cloud computing environments are service-oriented with an emphasis on statelessness, low coupling, modularity, and semantic interoperability. At the core of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0356] Referring now to FIG. 10 , an exemplary cloud computing environment 50 is shown. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 52 with which local computing devices used by cloud consumers may communicate, such as, for example, a personal digital assistant (PDA) or cellular phone 54A, a desktop computer 54B, a laptop computer 54C, and / or an automobile computer system 54N. The nodes 52 may communicate with each other. They may be physically or virtually grouped (not shown) in one or more networks, such as a private cloud, a community cloud, a public cloud, or a hybrid cloud, or a combination thereof, as described above. This allows the cloud computing environment 50 to provide infrastructure, platforms, and / or software as a service for which cloud consumers do not need to maintain resources on their local computing devices. The types of computing devices 54A-N shown in FIG. 10 are intended to be illustrative only, and it will be understood that the computing nodes 52 and the cloud computing environment 50 may communicate with any type of computerized device via any type of network and / or network-addressable connection (e.g., using a web browser).

[0357] 11, a set of functional abstraction layers provided by cloud computing environment 50 (FIG. 10) is shown. It should be understood in advance that the components, layers, and functions shown in FIG. 11 are intended to be exemplary only, and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0358] Hardware and software layer 60 comprises hardware and software components. Examples of hardware components include mainframe 61; RISC (reduced instruction set computer) architecture-based servers 62; servers 63; blade servers 64; storage devices 65; and networks and networking components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0359] The virtualization layer 70 provides an abstraction layer within which examples of virtual entities can be provided: virtual servers 71, virtual storage 72, virtual networks including virtual private networks 73, virtual applications and operating systems 74, and virtual clients 75.

[0360] In one example, management layer 80 may provide the functions described below. Resource provisioning 81 provides dynamic procurement of computing and other resources utilized to execute tasks within the cloud computing environment. Metering and pricing 82 provides cost tracking as resources are utilized within the cloud computing environment and billing or invoicing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides identity verification of cloud consumers and tasks, as well as protection of data and other resources. User portal 83 provides access to the cloud computing environment for consumers and system administrators. Service level management 84 provides cloud computing resource allocation and management to ensure required service levels are met. Service level agreement (SLA) planning and fulfillment 85 provides proactive provisioning and procurement of cloud computing resources to anticipate future requirements according to SLAs.

[0361] The workload tier 90 provides examples of functions for which a cloud computing environment may be utilized. Examples of workloads and functions that may be provided from this tier include mapping and navigation 91, software development and lifecycle management 92, virtual classroom instruction delivery 93, data analytics processing 94, transaction processing 95, and neural network processing support processing 96.

[0362] Aspects of the invention may be systems, methods and / or computer program products at any possible level of technical detail integration. A computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions that cause a processor to perform aspects of the invention.

[0363] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves on which instructions are recorded, and any suitable combination thereof. As used herein, computer-readable storage media should not be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted over wires.

[0364] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may comprise copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions to a computer-readable storage medium in the respective computing / processing device for storage.

[0365] The computer-readable program instructions for carrying out the operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk® or C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer-readable program instructions may run entirely on the user's computer, as a standalone software package, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry in order to perform aspects of the present invention.

[0366] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0367] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, whereby the instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium that can instruct a computer, programmable data processing apparatus and / or other device to function in a particular manner, whereby the computer-readable storage medium having instructions stored therein has an article of manufacture including instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0368] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be executed on the computer, other programmable apparatus, or other device to generate a computer-implemented process, whereby the instructions executing on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0369] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may actually be implemented as a single step, executed concurrently, substantially concurrently, partially, or fully in an overlapping manner, or the blocks may possibly be executed in reverse order, depending on the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system that performs the specified functions or operations or executes a combination of special-purpose hardware and computer instructions.

[0370] Further to the above, one or more aspects may be provided, offered, deployed, managed, serviced, etc. by a service provider offering to manage a customer environment. For example, the service provider may create, maintain, support, etc., computer code and / or computer infrastructure that implements one or more aspects for one or more customers. In return, the service provider may receive payments from customers under, by way of example, subscription and / or commission agreements. Additionally or alternatively, the service provider may receive payments from the sale of advertising content to one or more third parties.

[0371] In one aspect, an application may be deployed to perform one or more embodiments. As one example, deploying an application includes providing a computer infrastructure operable to perform one or more embodiments.

[0372] As a further aspect, a computing infrastructure may be deployed that includes computer-readable code integrated into a computing system, where the code in combination with the computing system is capable of performing one or more embodiments.

[0373] As yet another aspect, a process for integrating a computing infrastructure may be provided that includes integrating computer-readable code into a computer system that includes a computer-readable medium, where the computer medium includes one or more embodiments, and the code combined with the computer system is capable of executing one or more embodiments.

[0374] Although various embodiments are described above, these are merely examples. For example, computing environments of other architectures may be used to incorporate and / or use one or more aspects. Furthermore, different instructions, functions, and / or operations may be used. Additionally, different types of registers and / or different registers may be used. Furthermore, other data formats, data layouts, and / or data sizes may be supported. In one or more embodiments, one or more general-purpose processors, one or more application-specific processors, or a combination of general-purpose and special-purpose processors may be used. Many variations are possible.

[0375] Various aspects are described herein. Furthermore, many variations can be made without departing from the spirit of the aspects of the present invention. It should be noted that, unless otherwise inconsistent, each aspect or feature described herein and variations thereof may be combined with any other aspect or feature.

[0376] Additionally, other types of computing environments may be used to advantage. By way of example, a data processing system suitable for storing and / or executing program code may be used, including at least two processors coupled directly or indirectly to memory elements through a system bus. The memory elements may include, for example, local memory utilized during the actual execution of the program code, mass storage devices, and cache memory that provides temporary storage of at least some of the program code to reduce the number of times the code must be retrieved from mass storage devices during execution.

[0377] Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, DASDs, tapes, CDs, DVDs, thumb drives, and other memory media) may be coupled to the system either directly or through intervening I / O controllers. Network adapters may also be coupled to the system to enable the data processing system to be coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems, and Ethernet cards are just a few of the types of network adapters available.

[0378] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It is further understood that the terms "comprises" and / or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof, or combinations thereof.

[0379] The corresponding structure, material, and acts of any means- or step-plus-function element in the following claims, and their equivalents, where available, are intended to include that structure, material, or act for performing that function in combination with other claimed elements as specifically claimed. The description of one or more embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the precise form disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to best explain various aspects and practical applications, and to enable those skilled in the art to recognize various embodiments with various modifications as suitable for the particular use contemplated. [Item 1] One or more computer-readable storage media and program instructions collectively stored on the one or more computer-readable storage media wherein the program instructions include: obtaining an indication of a function to be executed, wherein said function is a function of one of the instructions and is configured to perform a plurality of operations; determining which of the plurality of operations is to be performed; and a procedure for validating a set of function-specific parameters using a set of values ​​and corresponding sets of relationships, wherein said set of values ​​and corresponding sets of relationships are based on said operations to be performed, and wherein one set of values ​​and corresponding sets of relationships are used for said operations to be performed and another set of values ​​and corresponding sets of relationships are used for another operation of said plurality of operations; for carrying out a method comprising: A computer program product for facilitating processing within a computing environment. [Item 2] Item 10. The computer program product of item 1, wherein the step of determining the operation to be performed includes checking one or more function-specific parameters against at least one particular value, wherein the operation is one operation based on the one or more function-specific parameters having a first preferential relationship with respect to the at least one particular value, and the operation is another operation based on the one or more function-specific parameters having a second preferential relationship with respect to the at least one particular value. [Item 3] The function comprises an average pooling function, the one or more function-specific parameters comprise one or more stride values, where the stride value is an amount by which a sliding window moves over the input tensor when computing one or more adjacent output tensor elements, the at least one particular value comprises zero, the first selection relationship comprises equality, and the operation comprises averaging based on one or more stride values ​​being equal to zero. contraction Item 3. The computer program product of item 2, wherein the calculation is [Item 4] 4. The computer program product of claim 3, wherein the second selection relationship includes greater than, and the operation is a pooling operation based on the one or more stride values ​​being greater than zero. [Item 5] 5. The computer program product of claim 1, wherein the set of function-specific parameters includes one or more selected dimension window size values, where the selected dimension window size values ​​specify the number of elements in the selected dimension that a sliding window includes, and the sliding window is configured to move over input tensors of the function to generate an output tensor. [Item 6] The function comprises an average pool function, and the operation is an average contraction6. The computer program product of item 5, wherein the set of values ​​and the set of corresponding relationships used to validate the set of function-specific parameters includes one value of one dimension of a selected input tensor and the corresponding relationship of being equal to it, another value of another dimension of the selected input tensor and the corresponding relationship of being equal to it, and a selected value and the corresponding relationship of being less than or equal to it. [Item 7] 7. The computer program product of claim 6, wherein the step of validating includes checking that a value of a dimension 2 window size is equal to a value of dimension 2 of a first input tensor, that a value of a dimension 3 window size is equal to a value of dimension 3 of the first input tensor, that the value of the dimension 2 window size is less than or equal to the selected value, and that the value of the dimension 3 window size is less than or equal to the selected value. [Item 8] 6. The computer program product of item 5, wherein the function comprises an average pool function, the operation comprises a pooling operation, and the set of values ​​and corresponding relationships used to validate the set of function-specific parameters comprises one value in one dimension of a selected input tensor and the corresponding relationship of being less than or equal to it, and another value in another dimension of the selected input tensor and the corresponding relationship of being less than or equal to it. [Item 9] 9. The computer program product of claim 8, wherein the step of validating includes checking that the dimension 2 window size value is less than or equal to the dimension 2 value of the first input tensor, and that the dimension 3 window size value is less than or equal to the dimension 3 value of the first input tensor. [Item 10] 9. The computer program product of claim 8, wherein the method further includes a step of determining whether a type of padding is set to a particular type, where the type of padding indicates which elements of a window are used to calculate an output, and the step of validating is performed based on the type of padding being set to the particular type. [Item 11] Item 11. The computer program product of item 10, wherein, based on the type of padding not being set to the particular type, one or more checks related to one or more dimensions of an output tensor are performed. [Item 12] 12. The computer program product of claim 1, wherein the step of determining the operation is based on at least one sliding window stride value of an input tensor, and the set of function-specific parameters includes at least one sliding window dimension of an input tensor. [Item 13] 1. A computer system for facilitating processing in a computing environment, the computer system comprising: memory; and at least one processor in communication with said memory; the computer system is configured to execute a method, the method comprising: obtaining an indication of a function to be executed, wherein said function is a function of one of the instructions and is configured to perform a plurality of operations; determining which of the plurality of operations is to be performed; and a procedure for validating a set of function-specific parameters using a set of values ​​and corresponding sets of relationships, wherein said set of values ​​and corresponding sets of relationships are based on said operations to be performed, and wherein one set of values ​​and corresponding sets of relationships are used for said operations to be performed and another set of values ​​and corresponding sets of relationships are used for another operation of said plurality of operations; A computer system comprising: [Item 14] Item 14. The computer system of item 13, wherein the step of determining the operation to be performed includes checking one or more function-specific parameters against at least one particular value, wherein the operation is one operation based on the one or more function-specific parameters having a first preferential relationship with respect to the at least one particular value, and wherein the operation is another operation based on the one or more function-specific parameters having a second preferential relationship with respect to the at least one particular value. [Item 15] The function comprises an average pooling function, the one or more function-specific parameters comprise one or more stride values, where a stride value is an amount by which a sliding window moves over an input tensor when computing one or more adjacent output tensor elements, the at least one particular value comprises zero, the first selection relationship comprises equality, and the operation comprises averaging based on the one or more stride values ​​being equal to zero. contraction Item 15. The computer system of item 14, wherein the second selection relationship includes being greater than, and the operation is a pooling operation based on the one or more stride values ​​being greater than zero. [Item 16] 16. The computer system of claim 13, wherein the step of determining the operation is based on at least one sliding window stride value of an input tensor, and the set of function-specific parameters includes at least one sliding window dimension of an input tensor. [Item 17] 1. A computer-implemented method for facilitating processing in a computing environment, comprising: obtaining an indication of a function to be executed, wherein said function is a function of one of the instructions and is configured to perform a plurality of operations; determining which of the plurality of operations is to be performed; and validating a set of function-specific parameters using a set of values ​​and corresponding sets of relationships, wherein said set of values ​​and corresponding sets of relationships are based on said operations to be performed, and wherein one set of values ​​and corresponding sets of relationships are used for said operations to be performed and another set of values ​​and corresponding sets of relationships are used for another operation of said plurality of operations; 1. A computer-implemented method comprising: [Item 18] Item 18. The computer-implemented method of item 17, wherein determining the operation to be performed includes checking one or more function-specific parameters against at least one particular value, wherein the operation is one operation based on the one or more function-specific parameters having a first preferential relationship with respect to the at least one particular value, and wherein the operation is another operation based on the one or more function-specific parameters having a second preferential relationship with respect to the at least one particular value. [Item 19] The function comprises an average pooling function, the one or more function-specific parameters comprise one or more stride values, where a stride value is an amount by which a sliding window moves over an input tensor when computing one or more adjacent output tensor elements, the at least one particular value comprises zero, the first selection relationship comprises equality, and the operation comprises averaging based on the one or more stride values ​​being equal to zero. contraction Item 19. The computer-implemented method of item 18, wherein the second selection relationship includes being greater than, and the operation is a pooling operation based on the one or more stride values ​​being greater than zero. [Item 20] 20. The computer-implemented method of any one of items 17 to 19, wherein the step of determining the operation is based on at least one sliding window stride value of an input tensor, and the set of function-specific parameters includes at least one sliding window dimension of an input tensor.

Claims

1. To a computer obtaining an indication of a function to be executed, said function being a function of an instruction and configured to perform a plurality of operations; determining an operation to be performed from among the plurality of operations; and for executing a procedure for validating a set of function-specific parameters using a set of values ​​and a corresponding set of relationships, the set of values ​​and the corresponding set of relationships being based on the operation to be performed, one set of values ​​and one set of corresponding relationships being used for the operation to be performed and another set of values ​​and another set of corresponding relationships being used for another operation of the plurality of operations; A computer program for facilitating processing within a computing environment.

2. 2. The computer program product of claim 1, wherein the step of determining the operation to be performed includes checking one or more function-specific parameters against at least one particular value, wherein the operation is one operation based on the one or more function-specific parameters having a first preferential relationship to the at least one particular value, and the operation is another operation based on the one or more function-specific parameters having a second preferential relationship to the at least one particular value.

3. 3. The computer program product of claim 2, wherein the function comprises an average pooling function, the one or more function-specific parameters comprise one or more stride values, a stride value being an amount by which a sliding window moves across an input tensor when computing one or more adjacent output tensor elements, the at least one particular value comprises zero, the first selection relationship comprises equality, and the operation is an average contraction operation based on the one or more stride values ​​being equal to zero.

4. The computer program product of claim 3 , wherein the second selection relationship includes being greater than, and the operation is a pooling operation based on the one or more stride values ​​being greater than zero.

5. 2. The computer program product of claim 1 , wherein the set of function-specific parameters includes one or more selected dimension window size values ​​that specify a number of elements in a selected dimension that a sliding window includes, the sliding window configured to move over input tensors of the function to generate an output tensor.

6. 6. The computer program product of claim 5, wherein the function comprises an average pooling function, the operation comprises an average contraction operation, and the set of values ​​and the set of corresponding relationships used to validate the set of function-specific parameters comprises one value of one dimension of a selected input tensor and the corresponding relationship of being equal, another value of another dimension of the selected input tensor and the corresponding relationship of being equal, and a selected value and the corresponding relationship of being less than or equal.

7. 7. The computer program product of claim 6, wherein the step of validating comprises checking that a value of a dimension 2 window size is equal to the number of elements in dimension 2 of a first input tensor, that a value of a dimension 3 window size is equal to the number of elements in dimension 3 of the first input tensor, that the value of the dimension 2 window size is less than or equal to the selected value, and that the value of the dimension 3 window size is less than or equal to the selected value.

8. 6. The computer program product of claim 5, wherein the function comprises an average pool function, the operation comprises a pooling operation, and the set of values ​​and the set of corresponding relationships used to validate the set of function-specific parameters comprises one value in one dimension of a selected input tensor and a corresponding relationship of being less than or equal to it, and another value in another dimension of the selected input tensor and a corresponding relationship of being less than or equal to it.

9. 9. The computer program product of claim 8, wherein the step of validating comprises checking that a dimension 2 window size value is less than or equal to the number of elements in dimension 2 of the first input tensor, and that a dimension 3 window size value is less than or equal to the number of elements in dimension 3 of the first input tensor.

10. 9. The computer program product of claim 8, further causing the computer to perform a procedure for determining whether a padding type is set to a particular type, the type of padding indicating which elements of a window are used to calculate an output, and wherein the validating procedure is performed based on the type of padding being set to the particular type.

11. The computer program product of claim 10 , further comprising: performing one or more checks related to one or more dimensions of an output tensor based on the type of padding not being set to the particular type.

12. 2. The computer program product of claim 1, wherein the procedure for determining the operation is based on at least one sliding window stride value of an input tensor, and the set of function-specific parameters includes at least one sliding window dimension of an input tensor.

13. 1. A computer system for facilitating processing in a computing environment, the computer system comprising: memory; and at least one processor in communication with the memory; the computer system is configured to execute a method, the method comprising: obtaining an indication of a function to be executed, said function being a function of an instruction and configured to perform a plurality of operations; determining an operation to be performed from among the plurality of operations; and a procedure for validating a set of function-specific parameters using a set of values ​​and corresponding sets of relationships, said set of values ​​and said set of corresponding relationships being based on said operation to be performed, one set of values ​​and one set of corresponding relationships being used for said operation to be performed and another set of values ​​and another set of corresponding relationships being used for another operation of said plurality of operations; A computer system comprising:

14. 14. The computer system of claim 13, wherein the step of determining the operation to be performed includes checking one or more function-specific parameters against at least one particular value, the operation being one operation based on the one or more function-specific parameters having a first preferential relationship to the at least one particular value, and the operation being another operation based on the one or more function-specific parameters having a second preferential relationship to the at least one particular value.

15. 15. The computer system of claim 14, wherein the function comprises an average pooling function, the one or more function-specific parameters comprise one or more stride values, a stride value being an amount a sliding window moves over an input tensor when computing one or more adjacent output tensor elements, the at least one particular value comprises zero, the first selection relationship comprises equality, and the operation is an average contraction operation based on the one or more stride values ​​being equal to zero, and the second selection relationship comprises greater than, and the operation is a pooling operation based on the one or more stride values ​​being greater than zero.

16. 16. The computer system of claim 13, wherein the procedure for determining the operation is based on at least one sliding window stride value of an input tensor, and the set of function-specific parameters includes at least one sliding window dimension of an input tensor.

17. 1. A computer-implemented method for facilitating processing in a computing environment, comprising: obtaining an indication of a function to be executed, said function being a function of one of the instructions and configured to perform a plurality of operations; determining an operation of the plurality of operations to be performed; and validating a set of function-specific parameters using a set of values ​​and corresponding sets of relationships, wherein the set of values ​​and the set of corresponding relationships are based on the operation to be performed, and one set of values ​​and one set of corresponding relationships is used for the operation to be performed and another set of values ​​and another set of corresponding relationships is used for another operation of the plurality of operations; 1. A computer-implemented method comprising:

18. 18. The computer-implemented method of claim 17, wherein determining the operation to be performed comprises checking one or more function-specific parameters against at least one particular value, wherein the operation is one operation based on the one or more function-specific parameters having a first preferential relationship to the at least one particular value, and wherein the operation is another operation based on the one or more function-specific parameters having a second preferential relationship to the at least one particular value.

19. 19. The computer-implemented method of claim 18, wherein the function comprises an average pooling function, the one or more function-specific parameters comprise one or more stride values, a stride value being an amount a sliding window moves over an input tensor when computing one or more adjacent output tensor elements, the at least one particular value comprises zero, the first selection relationship comprises equality, and the operation is an average contraction operation based on the one or more stride values ​​being equal to zero, and the second selection relationship comprises greater than, and the operation is a pooling operation based on the one or more stride values ​​being greater than zero.

20. 20. The computer-implemented method of claim 17, wherein the determining the operation is based on at least one sliding window stride value of an input tensor, and the set of function-specific parameters includes at least one sliding window dimension of an input tensor.

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