Implementing matrix value instructions

Abstract

Apparatus, systems, and techniques for performing an operation to indicate one or more non-zero values ​​in one or more matrices of data, performing an API to compress one or more matrices of data, performing a matrix multiply-accumulate (MMA) operation on two or more matrices of data, where at least one of the two or more matrices includes compressed data, and / or performing an API to decompress one or more matrices of data. In at least one embodiment, one or more circuits are configured to receive and compile one or more instructions to perform a computation operation for sparse matrix multiplication.

Description

[Technical Field]

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 188,406 (Attorney Docket No. 0112912-291PR0), filed May 13, 2021, entitled "PROCESSOR AND SYSTEM TO CONFIGURE A COMPILER TO RECEIVE AND GENERATE INSTRUCTIONS FOR COMPUTATIONAL OPERATIONS," the entire contents of which are incorporated herein by reference.

[0002] At least one embodiment relates to processing resources used to perform one or more matrix operations. For example, at least one embodiment relates to a processor or computing system implementing a compiler to generate instructions for storing index values ​​of non-zero elements of a sparse matrix, instructions for storing a compressed array with values ​​of non-zero elements of the sparse matrix, instructions for performing a matrix multiplication operation, and instructions for decompressing a result of the matrix multiplication operation to generate a resulting sparse matrix (e.g., including zero and non-zero values). [Background technology]

[0003] A matrix is ​​a set of numbers arranged in rows and columns, or more generally, matrix elements are indexed by two indices. These numbers are called the matrix elements, entries, or values. Matrices have a wide range of applications, including neural networks and machine learning. To compute mathematical operations for neural networks or machine learning algorithms, a processor can perform several operations, such as addition and multiplication, using one or more matrices, which correspond to computing intermediate or final results. Some neural networks include layers with matrices that store millions or even billions of elements. The amount of memory, computing power, or computing resources required to perform matrix operations can be improved. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 1 is an overview schematic diagram of a computing architecture for performing matrix operations, according to at least one embodiment. [Figure 2] FIG. 10 illustrates an example of a matrix represented in sparse format, according to at least one embodiment. [Figure 3] FIG. 1 illustrates an example of sparse metadata for a sparse matrix, according to at least one embodiment. [Figure 4A] FIG. 1 illustrates an example process for generating and implementing sparse matrix instructions or operations, according to at least one embodiment. [Figure 4B] FIG. 1 illustrates an example process for generating and implementing sparse matrix instructions or operations, according to at least one embodiment. [Figure 4C] FIG. 1 illustrates an example process for generating and implementing sparse matrix instructions or operations, according to at least one embodiment. [Figure 4D] FIG. 1 illustrates an example process for generating and implementing sparse matrix instructions or operations, according to at least one embodiment. [Figure 4E]FIG. 1 illustrates an example process for generating and implementing sparse matrix instructions or operations, according to at least one embodiment. [Figure 5] FIG. 1 illustrates an exemplary data center, according to at least one embodiment. [Figure 6] FIG. 1 illustrates a processing system according to at least one embodiment. [Figure 7] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 8] FIG. 1 illustrates a system according to at least one embodiment. [Figure 9] FIG. 1 illustrates an exemplary integrated circuit according to at least one embodiment. [Figure 10] FIG. 1 illustrates a computing system according to at least one embodiment. [Figure 11] FIG. 1 illustrates an APU, according to at least one embodiment. [Figure 12] FIG. 1 illustrates a CPU according to at least one embodiment. [Figure 13] FIG. 2 illustrates an exemplary accelerator integration slice, according to at least one embodiment. [Figure 14A] FIG. 1 illustrates an exemplary graphics processor according to at least one embodiment. [Figure 14B] FIG. 1 illustrates an exemplary graphics processor according to at least one embodiment. [Figure 15A] FIG. 1 illustrates a graphics core according to at least one embodiment. [Figure 15B] FIG. 1 illustrates a GPGPU, according to at least one embodiment. [Figure 16A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 16B] FIG. 1 illustrates a processing cluster, according to at least one embodiment. [Figure 16C]FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 17] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Figure 18] FIG. 1 illustrates a processor according to at least one embodiment. [Figure 19] FIG. 1 illustrates a processor according to at least one embodiment. [Figure 20] FIG. 1 illustrates a graphics processor core according to at least one embodiment. [Figure 21] FIG. 1 illustrates a PPU, according to at least one embodiment. [Figure 22] FIG. 1 illustrates a GPC, according to at least one embodiment. [Figure 23] FIG. 1 illustrates a streaming multiprocessor according to at least one embodiment. [Figure 24] FIG. 1 illustrates a software stack for a programming platform according to at least one embodiment. [Figure 25] FIG. 25 illustrates a CUDA implementation of the software stack of FIG. 24, according to at least one embodiment. [Figure 26] FIG. 25 illustrates an ROCm implementation of the software stack of FIG. 24 according to at least one embodiment. [Figure 27] FIG. 25 illustrates an OpenCL implementation of the software stack of FIG. 24 according to at least one embodiment. [Figure 28] FIG. 1 illustrates software supported by a programming platform according to at least one embodiment. [Figure 29] FIG. 28 illustrates compiling code for execution on the programming platform of FIGS. 24-27, according to at least one embodiment. [Figure 30]FIG. 28 illustrates in more detail compiling code for execution on the programming platform of FIGS. 24-27, according to at least one embodiment. [Figure 31] FIG. 1 illustrates translating source code prior to compiling the source code, according to at least one embodiment. [Figure 32A] FIG. 1 illustrates a system configured to compile and execute CUDA source code using different types of processing units, according to at least one embodiment. [Figure 32B] FIG. 32B illustrates a system configured to compile and execute the CUDA source code of FIG. 32A using a CPU and a CUDA-enabled GPU, according to at least one embodiment. [Figure 32C] FIG. 32B illustrates a system configured to compile and execute the CUDA source code of FIG. 32A using a CPU and a non-CUDA-enabled GPU, according to at least one embodiment. [Figure 33] FIG. 32D illustrates an example kernel translated by the CUDA-to-HIP translation tool of FIG. 32C, in accordance with at least one embodiment. [Figure 34] FIG. 32D illustrates the non-CUDA GPU of FIG. 32C in more detail, according to at least one embodiment. [Figure 35] FIG. 35 illustrates how threads of an exemplary CUDA grid are mapped to different compute units of FIG. 34, according to at least one embodiment. [Figure 36] FIG. 1 illustrates how to migrate existing CUDA code to Data Parallel C++ code, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0005] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concept may be practiced without one or more of these specific details.

[0006] In at least one embodiment, matrix multiplication involving sparse matrices involves a processor performing multiplication with many zero values ​​as inputs, and thus the processor wastes computational resources computing trivial multiplication operations, such as 0 times a non-zero value. In at least one embodiment, a sparse matrix is ​​a matrix with many zero values, e.g., with a majority of zero values ​​(e.g., 50% of the matrix values ​​are zero, more than 60% of the values ​​in the matrix are zero, or more than 70% of the values ​​in the matrix are zero). In at least one embodiment, even when values ​​are zero, they still need to be stored in memory. In at least one embodiment, for high precision data types (e.g., floating point), storing zero values ​​may be meaningful even if the zeros contribute little to the computation.

[0007] In at least one embodiment, algorithms related to performing computational operations such as matrix multiply and accumulate (MMA), integer matrix multiply and accumulate (IMMA), and half-precision matrix multiply and accumulate (HMMA) can involve sparse matrices. In at least one embodiment, the sparse matrix multiplication operations are performed as part of training or performing a neural network, convolution, or machine learning operation.

[0008] To improve computational operations involving sparse matrices, in at least one embodiment, a system receives one or more instructions that reduce the computational load for performing multiplications involving sparse matrices by reducing the number of zero multiplication operations to complete the operations. In at least one embodiment, a programmer writes such instructions into one or more source files for performing one or more sparse matrix multiplication operations. In at least one embodiment, the matrix multiplication operations are executed in one or more graphics processing cores based at least in part on one or more indications of non-zero values ​​in the sparse matrices. For example, one or more processors may receive parallel thread instructions (PTX) for a graphics processing unit, which are compiler-generated, platform-independent instructions similar to assembly instructions. In at least one embodiment, when an application is running, a just-in-time (JIT) further compiles the PTX instructions into GPU-specific machine instructions (e.g., executable instructions). In at least one embodiment, one or more graphics processing cores perform the sparse matrix multiplication operations, and the one or more graphics processing cores are capable of performing the sparse matrix operations in parallel.

[0009] In at least one embodiment, one or more first instructions (referred to as "gather instructions") are for indicating which values ​​of a matrix are non-zero. In at least one embodiment, performing the gather instructions returns an array of indices indicating which values ​​are non-zero. For example, if the first, fourth, and ninth elements of a matrix are the only non-zero values, performing the gather instruction returns 1, 4, and 9. In at least one embodiment, a compiler receives the one or more first instructions and generates executable instructions for one or more graphics processing units (e.g., that are accessible to one or more drivers configured to perform operations on the one or more GPUs).

[0010] In at least one embodiment, second instructions (referred to as "compress instructions" or reduction instructions) are for generating a compressed representation of a matrix. In at least one embodiment, implementing the compress instructions causes non-zero elements of a matrix to be stored with an index (without the zeros) from the first instruction. For example, the compress instruction may cause one or more processors to generate a compressed array that stores values ​​for non-zero elements of a sparse matrix. In at least one embodiment, a compiler receives the one or more second instructions and generates executable instructions (e.g., PTX instructions, lower-level instructions) for one or more graphics processing units.

[0011] In at least one embodiment, a third instruction (also referred to as an "MMA instruction") is for performing an MMA operation on two or more matrix operands, where at least one of the operands is compressed using a second (compression) instruction. In at least one embodiment, implementing the third instruction uses an index to perform the MMA operation (e.g., without unnecessary multiplication by zero). In at least one embodiment, a compiler receives the one or more third instructions and generates executable instructions (e.g., PTX instructions, lower-level instructions) for one or more graphics processing units.

[0012] In at least one embodiment, a fourth instruction (called a "scatter instruction") is for storing a matrix (with zero values) from the non-zero values ​​and indices from the second (compression) instruction. In at least one embodiment, the fourth instruction is for decompressing the compressed matrix, which may be implemented or generated by an API, where the API is part of a library of APIs for performing sparse matrix multiplication operations. In at least one embodiment, the decompression includes adding zero values ​​to the matrix based on index values ​​for the zero values ​​in the input sparse matrix (e.g., storing zero values ​​at indices not included in the compressed matrix or compressed array).

[0013] In at least one embodiment, the first, second, third, and fourth instructions are received by a compiler, parsed, translated, or otherwise compiled into lower-level instructions, such as x86, ARM (e.g., ARMv7, 32-bit), reduced instruction set computer (RISC) instructions, and / or precompiled instructions, where the lower-level (e.g., machine-readable or executable instructions) may be used by a driver configured to execute the instructions on one or more graphics processing units to perform a matrix multiplication operation involving a sparse matrix. In at least one embodiment, the compiled or executable instructions include operands that indicate where in the sparse matrix a non-zero value is to be stored (e.g., an index) and the value of the non-zero value.

[0014] In at least one embodiment, the instructions and / or techniques disclosed herein apply to matrices, but also to data structures such as arrays, tables, columns, rows, or other data structures that store values ​​in an organized format. In at least one embodiment, the instructions and / or techniques disclosed herein apply to more general linear operations such as tensors.

[0015] FIG. 1 depicts an overview schematic diagram illustrating a computing architecture 100 according to at least one embodiment. In at least one embodiment, FIG. 1 includes a first source file 102, a second source file 104, a first compiler 106, an intermediate source file 108, a second compiler 110, executable code 112, a driver 114, and a GPU 116. In at least one embodiment, system 100 is implemented in accordance with the present disclosure and is utilized to configure second compiler 110 to compile program instructions for execution on one or more processing cores in GPU 116 to perform computational operations (e.g., sparse matrix-matrix multiplication and accumulation (SMA), sparse HMMA, sparse IMMA, etc.), thereby reducing the number of operations performed by one or more GPUs 116.

[0016] In at least one embodiment, the first source file 102 is a direct source file, such as one written directly by a programmer in the PTX language to create a source file. In at least one embodiment, the first source file 102 is a PTX source file 108. In at least one embodiment, an API (e.g., a CUDA API) receives the second source file 104 from an application and provides the source file to the first compiler 106, which compiles the first source code 106 into an intermediate source file 108 (e.g., PTX code). In at least one embodiment, the first source file 102 and the second source file 104 include operations for neural network operations, such as convolution or multiplication. In at least one embodiment, the first source file 102 becomes the intermediate source file 108 (e.g., a PTX file) upon execution of the files. In at least one embodiment, first compiler 106 translates code written in a human-readable format (e.g., CUDA, HIP, C++, and other formats listed below), such as second source file 104, into PTX source file 108. In at least one embodiment, first compiler 106 and how it is used to compile code are described in more detail below in at least Figures 24-32A and their corresponding descriptions. In at least one embodiment, intermediate source file 108 includes instructions such that a graphics driver uses second compiler 110 to translate the PTX instructions into binary code 112 that can be run on cores of a parallel processing unit (PPU), such as graphics processing unit (GPU) 116 (through the use of driver 114).

[0017] In at least one embodiment, GPU 116 supports a wide range of operations beyond graphics-oriented operations. In at least one embodiment, for example, GPU 116 is capable of executing any program instruction. In at least one embodiment, GPU 116 includes a compiler that uses a driver, such as driver 114, to compile program instructions for execution on one or more processing cores included within GPU 116. In at least one embodiment, driver 114 is software or includes a software library configured to execute code on one or more graphics processing units (e.g., a CUDA driver). In at least one embodiment, each such core executes a particular thread of execution in parallel with other processing cores that execute that thread. In at least one embodiment, while FIG. 1 shows one GPU 116, two or more GPUs may be used. In at least one embodiment, GPU 116 includes one or more arithmetic logic units (ALUs), where the one or more ALUs are configured to store operands (e.g., non-zero values ​​of a sparse matrix or metadata about indices of a sparse matrix), and where the ALUs can operate on these operands to perform instructions (e.g., to complete a matrix multiplication operation).

[0018] In at least one embodiment, sparsity is expressed in an additional operand that is added to an existing MMA instruction, as opposed to a dense version of the MMA instruction. In at least one embodiment, the additional operand is presented to and processed by second compiler 110 (e.g., an Application Programming Interface (API)). In at least one embodiment, second compiler 110 and how it is used to compile code are described in more detail below in at least Figures 24-32A and their corresponding descriptions.

[0019] In at least one embodiment, additional operands are created to represent the sparsity information, which are added to an API (e.g., a Directed Acyclic Graph (DAG) interface) with an assembler for Parallel Thread Execution (PTXA) as a front end, as well as to a compiler intermediate representation (IR) for MMA instructions. In at least one embodiment, second source files 104 (e.g., device code) are received by a first compiler 106 and compiled into intermediate source files 108 (e.g., PTX source files). In at least one embodiment, intermediate source files 108 are then compiled at runtime by a second compiler 110 into executable code 112 (e.g., binary code in CUDA). In at least one embodiment, in the case of the Compute Uniform Device Architecture (CUDA), a second compiler 110 compiles non-hardware-specific intermediate source files 108 (e.g., PTX IR code) into executable code 112 for a particular target at runtime. Communication with the underlying device via the compiler is described in more detail below in Figures 24-32A.

[0020] In at least one embodiment, the GPU 116 supports HMMA and IMMA with sparse properties, which may be exposed in the intermediate source files 108 (e.g., as internal or intermediate instructions). In at least one embodiment, the DAG interface between the intermediate source files 108 (e.g., PTX source files) and an optimized code generator (OCG) is configured to support sparse HMMA and sparse IMMA. In at least one embodiment, the DAG interface is a software interface implemented by one or more processors (e.g., host processor, CPU) to generate an interface for a compiler or DAG in other software. In at least one embodiment, a programmer can modify the DAG so that the compiler is modified, for example, to perform different operations when compiling. In at least one embodiment, the sparse HMMA and sparse IMMA in the intermediate source files 108 (e.g., PTX source files) are similar to regular MMA, with additions described below.

[0021] In at least one embodiment, the GPU 116 is designed to support HMMA and IMMA extensions. In at least one embodiment, the extensions require modifications to the front end (to expose the new features) and the OCG. In at least one embodiment, the OCG is a low-level compiler for graphics code. In at least one embodiment, the OCG handles register allocation, scheduling, and peephole optimization. In at least one embodiment, a high-level optimizer handles compute code and performs traditional global optimizations before piping the output to the OCG. In at least one embodiment, the OCG generates efficient code for the graphics processor (e.g., the GPU 116). In at least one embodiment, the DAG interface between the intermediate source file 108 (e.g., a PTX source file) and the OCG is configured to support sparse HMMA and IMMA. In at least one embodiment, the intermediate source file 108 exposes the features to allow users to take advantage of hardware-supported MMA operations. In at least one embodiment, the GPU 116 is designed to extend the operations by adding sparse modes and additional matrix shapes. In at least one embodiment, the new features are exposed in a front end (e.g., PTX source files 108). In at least one embodiment, an intermediate source file 108, such as a PTX source file, exposes the new shapes and sparse modes along with sparse metadata input and other operands. In at least one embodiment, instructions are translated by the intermediate source file 108 front end into DAG intermediate instructions (IR), which are translated back to IR. In at least one embodiment, the DAGs and intermediate source files 108 for existing IMMA and HMMA operations are updated to support the new features.In at least one embodiment, the intermediate source file 108 passes through several phases of OCG to be legalized, optimized, allocated, and scheduled before being translated into Syntactically Awesome Style Sheet (SASS) encoding.

[0022] In at least one embodiment, the techniques described herein are designed to implement HMMA and IMMA extensions with technical advantages in the second compiler 110. In at least one embodiment, the techniques are designed to extend HMMA and IMMA intermediate source files 108 (e.g., PTX files) to take one additional input representing sparse metadata, extend HMMA and IMMA IR to represent sparse mode and sparse ID inputs in info, extend IR to allow for different shapes for HMMA and IMMA, teach interfaces such as ORI to deal with operands (e.g., using various query routines and scheduling constraints), enable the DAG-ORI translator to accurately deal with the new additions, support encoding, decoding, and IR discarding for the new additions, update documentation to reflect the new IR format, and Direct2IR builder support.

[0023] In at least one embodiment, an operation code (e.g., opcode) representation is modified to have an input operand representing sparse metadata. In at least one embodiment, an operation code may also be referred to as an instruction code, instruction machine code, instruction syllable, instruction parcel, or opstring. In at least one embodiment, an operation code is a portion of a machine instruction that specifies the operation to be performed. In at least one embodiment, the input operand may include a field "info," which is enabled to have two additional fields representing a sparse mode and a sparseID (e.g., identifying the sparse mode of the operation). In at least one embodiment, sparseMode and sparseID are added to support sparse matrix multiplication.

[0024] In at least one embodiment, one example format of HMMA is as follows: HMMA Rd=Ra,Rb,Rc,info. In at least one embodiment, the techniques described herein enable the second compiler 110 to receive and compile instructions, where, as an example, the HMMA format has changed to HMMA Rd=Ra,Rb,Rc,Re,info. In at least one embodiment, Re is a single 32-bit register representing sparse metadata. In one embodiment, "info" includes at least two new fields: sparseMode and sparseID. In at least one embodiment, sparseMode is set as NONE (implying no sparseness), TID, or REGOFFSET. In at least one embodiment, sparseID is an immediate value that can be encoded as is.

[0025] In at least one embodiment, the compiler generates instructions for the MMA with query routines to access sparseMode, sparseID, and sparseMetaDataIndex, and encode / decode routines for the GPU to enable instruction execution and use of metadata and operands. In at least one embodiment, support for matrix shapes (160832 for HMMA and 8864 for IMMA) allows matrix input sizes / vector lengths to be accurately inferred, latencies to be used (latencies vary based on shape), and validation to check combinations to be accurately used.

[0026] In at least one embodiment, an MMA instruction involving a sparse matrix (e.g., for sparse HMMA or sparse IMMA) is written as follows: _mma.sp{.spformat}.shape.row.col.dtype.atype.btype.ctype.etype{.satfinite} d,a,b,c,e,#id2, where the additions to regular MMA include “.sp{.spformat}”, “e”, and “#id2”. In at least one embodiment, HMMA is used as an example described herein; IMMA may also be used and follow a similar approach. In at least one embodiment, other matrix operations such as general sparse matrix-matrix multiplication (SpGEMM), sparse matrix-matrix multiplication (SPMM), or similar operations are applicable. In at least one embodiment, sparse HMMA may be represented using the existing HMMA DAG, with minor modifications to the DAG. In at least one embodiment, the modifications may include making the HMMA DAG a QuinaryDag (which takes five inputs, for example) instead of a QuadnaryDag (which takes four inputs), and additional sub-operations for sparse mode (".sp{.spformat}" in the syntax shown above) and sparse id ("#id2" in the syntax shown above). In at least one embodiment, a fifth input is supplied by a sparse metadata value (input "e" in the syntax shown above).

[0027] In at least one embodiment, there are different circumstances in which a DAG is created. For example, in at least one embodiment, a DAG is created when chaining is not required. For example, in at least one embodiment, chaining is not required for the following MMA instruction: HMMA.F R.F16X2.xyzw,A.F16X2.xy--,B.F16X2.xy--,C.F16X2.xyzw,DF----,EUx. In at least one embodiment, the non-chains are as follows: <matrix A>, <matrix B>, <matrix C>, <dummy input: CONST DAG> (required to maintain consistency with respect to F32 macro calculations described below), and input "E" (sparsity metadata).

[0028] In at least one embodiment, for example, a DAG is created when chaining is needed. In at least one embodiment, chaining is needed for the following MMA instructions: HMMA.F RFxyzw (top 4x32b of result D), A.F16X2.xy--, B.F16X2.xy--, CFxyzw, DFxyzw, EUx---. In at least one embodiment, the chain is as follows: <matrix A>, <matrix B>, <top 4x32b of matrix C>, HMMA.F RFxyzw(bottom 4x32b of result D), A.F16X2.xy, B.F16X2.xy,CFxyzw,DF(dummy input),EUx,<matrix A>, <matrix B>, <bottom 4x32b of matrix C>, <dummy input: CONST DAG>, where there is also an input "E" (sparsity metadata) and the same "E" sparsity metadata DAG.

[0029] In at least one embodiment, a sub-op (e.g., a subop) is configured on an HMMA DAG node for sparse formatting and sparse IDs. In at least one embodiment, the sparse mode is set to one of ISUBOP_FERMI_MMA_SP_MODE_NONE, ISUBOP_FERMI_MMA_SP_MODE_TID, or ISUBOP_FERMI_MMA_SP_MODE_REGOFFSET. In at least one embodiment, ISUBOP_FERMI_MMA_SP_MODE_NONE refers to no sparseness and is the default. In at least one embodiment, ISUBOP_FERMI_MMA_SP_MODE_TID refers to sparse TID mode. In at least one embodiment, ISUBOP_FERMI_MMA_SP_MODE_REGOFFSET refers to sparse REGOFFSET mode.

[0030] In at least one embodiment, a mapping format intermediate source file 108 (e.g., PTX source file) modifier to the SP_MODE enum is enabled. In at least one embodiment, a .sp assigned "off" is an .spformat and is assigned an SP mode of "SP_MODE_NONE". In at least one embodiment, a .sp assigned "on" is an .spformat of TID and is assigned an SP mode of "SP_MODE_TID". In at least one embodiment, a .sp assigned "on" is an .spformat of REGOFFSET and is assigned an SP mode of "SP_MODE_REGOFFSET".

[0031] In at least one embodiment, the sparse mode is set on the HMMA DAG as follows: SetISubopField_Fermi(fOp, ISUBOP_FERMI_MMA_SP_MODE, ISUBOP_FERMI_MMA_SP_MODE_TID). In at least one embodiment, the sparse ID is set on the HMMA DAG as follows: SetISubopField_Fermi(fOp, ISUBOP_FERMI_MMA_SP_ID, <id imm value>). In at least one embodiment, shape enums are added for HMMA and IMMA and they can be set as follows: SetISubopField_Fermi(fOp, ISUBOP_FERMI_HMMA_SHAPE, ISUBOP_FERMI_HMMA_160832); SetISubopField_Fermi(fOp, ISUBOP_FERMI_IMMA_SHAPE, ISUBOP_FERMI_IMMA_8816).

[0032] FIG. 2 shows an example of a matrix (e.g., 16×16) represented in a sparse format and a sparsity selector indicating which threads in a group of threads store metadata, according to at least one embodiment. In at least one embodiment, different granularities for different matrix shapes and data types are used instead of those illustrated and described in FIG. 2. In at least one embodiment, the compiler is configured to receive sparsity information to generate (and how to represent) sparse MMA instructions. In at least one embodiment, an interface (e.g., a DAG interface) is modified to receive sparsity information. For reference only as shown in FIG. 2, the gray area highlights the portion of the original sparse matrix 202 corresponding to Opd A206 and metadata 208.

[0033] In at least one embodiment, original sparse matrix 202 is a sparse matrix. In at least one embodiment, original sparse matrix 202 is the sparse matrix described in FIG. 1, e.g., it has mostly zero values ​​(e.g., elements with zero values) as shown in FIG. 2. In at least one embodiment, input operand 204 to sparse MMA instruction comprises at least Opd A 206 and metadata 208. In at least one embodiment, Opd A 206 and metadata 208 are compressed versions of original sparse matrix 202. In at least one embodiment, input operand 204 to sparse MMA instruction is similar to the input operand to the sparse MMA instruction described in FIG. 1 above. In at least one embodiment, metadata 208 points to a matrix in which an index of each non-zero element in a sub-chunk in original sparse matrix 202 is stored. In at least one embodiment, the index in metadata 208 is a pointer to a location in original sparse matrix 202. In at least one embodiment, metadata 208 is the same as the metadata described in Figure 1 above. In at least one embodiment, Opd A 206 refers to a matrix in which the non-zero elements in original sparse matrix 202 are stored. In at least one embodiment, Opd A 206 is similar to the non-zero elements described in Figure 1 above. In at least one embodiment, elements of metadata 208 map the locations of elements of Opd A 206 in original sparse matrix 202. In at least one embodiment, compressed 210 is a compressed matrix, in conjunction with Figure 1 above.

[0034] In at least one embodiment, the data types of the original sparse matrix 202 and the input operands 204 to the sparse MMA instruction are 64-bit floating-point (FP64), 32-bit floating-point (FP32), half-precision floating-point (FP16), Brian floating-point (bfloat16 or BF16), FlexPoint, TensorFloat-32 (TF32), integer, or similar matrix multiplication operations. In at least one embodiment, the techniques described herein may be used for data types such as BF16. In at least one embodiment, during the m16n8k16 and m16n8k32mma.sp operations, matrix A is structured sparse at a 2:4 granularity. In at least one embodiment, each chunk of four adjacent elements in a row of matrix A has two zeros and two non-zero elements. In at least one embodiment, only two non-zero elements are stored in the operand representing matrix A, and their positions in a 4-wide chunk of matrix A are indicated by two 2-bit indices in the metadata operand. In at least one embodiment, a sparsity selector indicates which threads contribute to the metadata. In at least one embodiment, in m16n8k16, one thread in a group of four consecutive threads may contribute metadata for the entire group. In at least one embodiment, the threads may be indicated by a value in {0, 1, 2, 3}. In at least one embodiment, in m16n8k32, a pair of threads in a group of four consecutive threads may contribute to the sparsity metadata. Thus, in at least one embodiment, the sparsity selector may be either 0 (e.g., threads T0, T1) or 1 (threads T2, T3); other values ​​may result in undefined behavior.

[0035] In at least one embodiment, the techniques described herein may be used for data types such as TF32. In at least one embodiment, for example, when matrix A has TF32 elements, matrix A is structured sparse at a 1:2 granularity. In at least one embodiment, each chunk of two adjacent elements in a row of matrix A has one zero and one non-zero element. In one embodiment, only non-zero elements are stored in the operands for matrix A, and their location in the two-wide chunk in matrix A is indicated by a 4-bit index in the metadata as shown in FIG. 3. In at least one embodiment, a sparsity selector indicates which threads contribute to the metadata. In at least one embodiment, in m16n8k8, one thread in a group of four consecutive threads contributes to the metadata for the entire group. In at least one embodiment, the threads are indicated by a value in {0, 1, 2, 3}. In at least one embodiment, in m16n8k16, thread pairs within groups of four consecutive threads contribute to sparsity metadata. Therefore, in at least one embodiment, the sparsity selector must be either 0 (threads T0, T1) or 1 (threads T2, T3); other values ​​may result in undefined behavior.

[0036] In at least one embodiment, the techniques described herein may be used for data types such as integers. In at least one embodiment, for example, when matrices A and B have .u8 / .s8 elements, matrix A is structured sparse at a 2:4 granularity. In at least one embodiment, for example, each chunk of four adjacent elements in a row of matrix A has two zeros and two non-zero elements. In at least one embodiment, only two non-zero elements are stored in the sparse matrix, and their positions in the four-wide chunk are indicated by two 2-bit indices in the metadata. In at least one embodiment, when matrices A and B have .u4 / .s4 elements, matrix A is pair-wise structured sparse at a 4:8 granularity. In at least one embodiment, each chunk of eight adjacent elements in a row of matrix A has four zeros and four non-zero values. In at least one embodiment, zero and non-zero values ​​are clustered in sub-chunks of two elements each within an 8-wide chunk; for example, each 2-wide sub-chunk within an 8-wide chunk must be either all zero or all non-zero. In at least one embodiment, only four non-zero values ​​are stored in the sparse matrix, and the locations of the two 2-wide sub-chunks with non-zero values ​​within the 8-wide chunk of a row of matrix A are indicated by two 2-bit indices in the metadata. In at least one embodiment, a sparsity selector indicates which threads contribute to the metadata. In at least one embodiment, for example, m16n8k32 in .u8 / .s8 types and m16n8k64 in .u4 / .s4 types, i.e., thread pairs within groups of four consecutive threads contribute to the sparsity metadata. In at least one embodiment, the sparsity selector must be either 0 (threads T0, T1) or 1 (threads T2, T3); any other value results in undefined behavior. In at least one embodiment, for m16n8k32 in .u8 / .s8 types and m16n8k64 in .u4 / .s4 types, all threads in a group of four consecutive threads contribute to the sparsity metadata.In at least one embodiment, the sparsity selector must be 0 in this case. In at least one embodiment, any other value of the sparsity selector results in undefined behavior.

[0037] In at least one embodiment, the techniques described herein are directed to a compiler implementation for supporting sparse MMA instructions. In at least one embodiment, dense MMA instructions are supported by a compiler, such as the second compiler 110 in FIG. 1 . In at least one embodiment, extended features may be added to a compiler to handle sparse MMA instructions. In at least one embodiment, sparse information is represented in a metadata register (denoted as “Re” in the syntax above). In at least one embodiment, the techniques described herein are directed to configuring a back-end compiler for a GPU. In at least one embodiment, a metadata register “Re” is added, and additional information is added to the last operand (denoted as “info” in the syntax above), where info includes at least two fields (e.g., sparseMode and sparseID). In at least one embodiment, the added sparse metadata and info provide a machine with information about how it must compress or pack data Ra into its original dense format and then compute the MMA instruction. In at least one embodiment, a compiler receives a programming language (including information regarding sparsity information) for compilation into HMMA machine instructions.

[0038] In at least one embodiment, a compiler is configured to compile the code with the added operands and information into executable code (e.g., parallel thread executable assembly "PTXAs" language). In at least one embodiment, the compiler interfaces with a front-end compiler parsing the PTX language, such as intermediate source files 108, which may be PTX source files described in FIG. 1 above. In at least one embodiment, the back-end compiler obtains both Re and info from the PTXAs front-end using a DAG interface. In at least one embodiment, the sparse MMA includes at least HMMA (e.g., half-floating-point format) and IMMA (e.g., integer type operands, such as 8-bit integers or 4-bit integers). In at least one embodiment, an instruction (e.g., genMetadata) is used to generate a sparse metadata operand (Re). In at least one embodiment, other instructions (e.g., 4:2 compression and / or 2:1 compression) may be used to compress or decompress matrix elements used for sparse matrix multiplication.

[0039] In at least one embodiment, a dense matrix is ​​represented in a sparse matrix format in which non-zero elements are compressed to half or less of their original size. In at least one embodiment, the non-zero elements are represented using an index (Re). In at least one embodiment, as described above, in the HMMA format, Ra is a sparse matrix and the other matrices are dense matrices. In at least one embodiment, Ra is compressed by half (e.g., 4:2 or 2:1) after compression, where four elements are compressed to two elements or two elements are compressed to one element. In at least one embodiment, when non-zero elements are compressed, their index (Re) helps keep track of their positions in the original dense matrix. In at least one embodiment, with a sparse matrix, fewer computational operations occur while also using less memory. In at least one embodiment, reducing the non-zero elements by half results in a doubling of the computation speed. In at least one embodiment, by implementing the techniques described herein, the increased processing speed also results in faster end-to-end training and inference times when used across a wide variety of neural networks and / or various GPUs. In at least one embodiment, after the compression and sparse matrix operations are performed, decompression is performed to reflect the operations that were performed.

[0040] In at least one embodiment, Ra is a 1x4 submatrix consisting of a position for each element as position numbers [0,0], [0,1], [1,0], and [1,1]. In at least one embodiment, if positions [0,0] and [1,1] are selected to be in the Ra register, then Re contains [0,0] and [1,1], the indices of the non-zero elements in the Ra register.

[0041] FIG. 3 illustrates an example of sparse metadata for a sparse matrix, according to at least one embodiment. In at least one embodiment, 2-wide chunk 302 from a row in matrix A indicates a compressed matrix. In at least one embodiment, 2-wide chunk 302 from a row in matrix A is similar to the chunks described above in FIGS. 1 and 2. In at least one embodiment, 2-wide chunk 302 from a row in matrix A is a 2-wide chunk from a row in matrix A. In at least one embodiment, the numbering below the array (e.g., 0, 31, 63) refers to the corresponding columns of matrix A. In at least one embodiment, 2-wide chunk 302 from a row in matrix A is compressed data from columns 0 through 63. In at least one embodiment, 2-wide chunk 302 from a row in matrix A indicates that there are only zero elements in columns 0 through 31 (e.g., no non-zero elements are contained in columns 0 through 31). In at least one embodiment, a two-wide chunk 302 from a row in matrix A indicates that there is a non-zero element between columns 31 and 63, represented by "x." In at least one embodiment, "x" acts as a placeholder for the non-zero element. In at least one embodiment, "x" has a data type depending on the implementation. In at least one embodiment, the data type of x may be configured. In at least one embodiment, the data type may be 64-bit floating point (FP64), 32-bit floating point (FP32), half-precision floating point (FP16), Brian floating point (bfloat16 or BF16), flexpoint, TensorFloat-32 (TF32), integer, or similar operations. In at least one embodiment, "x" is similar to the non-zero element described in FIG. 1 above.

[0042] In at least one embodiment, element indices 306 within 2-wide chunk refer to individual indices corresponding to location-related elements within 2-wide chunk 302 from a row in matrix A. In at least one embodiment, the numbering below the array (e.g., 0, 31, 63) refers to corresponding columns in matrix A. In at least one embodiment, element indices 306 within 2-wide chunk operate in conjunction with FIG. 1. In at least one embodiment, element indices 306 11 and 10 within 2-wide chunk have non-zero values, “x,” between columns 31 and 63, as shown in 2-wide chunk 302 from a row in matrix A.

[0043] In at least one embodiment, sparse matrix operand 304 is a sparse matrix operand corresponding to a 2-wide chunk 302 from a row in matrix A. In at least one embodiment, sparse matrix operand 304 is similar to OpdA described above in FIG. 2. In at least one embodiment, metadata 308 is metadata corresponding to a 2-wide chunk 302 from a row in matrix A. In at least one embodiment, metadata 308 is similar to the metadata described above in FIG. 1. In at least one embodiment, only 0b1110 and 0b0100 are meaningful index values; other values ​​result in undefined behavior.

[0044] FIG. 4 illustrates an example process 400 for performing sparse matrix operations according to instructions, according to at least one embodiment. In at least one embodiment, the systems disclosed in FIGS. 1-3 may perform some or all of process 400. In at least one embodiment, process 400 is comprised of processes 435, 445, 455, and / or 465. In at least one embodiment, one or more circuits, one or more processors (e.g., CPU, GPU), one or more APIs, or one or more systems may perform process 400 or portions of processes 400, 435, 445, 455, and 465 (denoted by "B," "C," "D," and "E" in FIGS. 4A, 4B, 4C, 4D, and 4E). In at least one embodiment, some or all of processes 400, 435, 445, 455, and 465 (or any other processes described herein, or variations and / or combinations thereof) are performed under the control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that collectively execute on one or more processors via hardware, software, or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some computer-readable instructions usable to implement process 400 are not stored using only transitory signals (e.g., propagating transitory electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of a transitory signal.

[0045] In at least one embodiment, processes 400, 435, 445, 455, and 465 comprise one or more processes utilized to cause sparse matrix operations (e.g., MMA, IMMA, HMMA) to be performed in accordance with the generated instructions. In at least one embodiment, processes 400, 435, 445, 455, and 465 are performed by one or more systems (e.g., a host processor such as a CPU and a device processor such as a GPU), such as those described in this disclosure. In at least one embodiment, processes 400, 435, 445, 455, and 465 are performed by a system, such as that described with respect to FIG. 1. In at least one embodiment, one or more operations of processes 400, 435, 445, 455, and 465 are performed in any suitable order, including serially, in parallel, and / or variations thereof, and using any suitable processing unit, such as a CPU, a GPGPU, a GPU, a PPU, and / or variations thereof. In at least one embodiment, processes 400, 435, 445, 455, and 465 are performed simultaneously on one or more neural networks.

[0046] In at least one embodiment, the system performing at least a portion of process 400 receives 410 instructions to perform sparse matrix operations, as described with respect to Figure 1. In at least one embodiment, the system generates the instructions to perform one or more computational operations. In at least one embodiment, a compiler, such as second compiler 110 in Figure 1, is configured to receive sparsity information. In at least one embodiment, the sparsity information is represented in additional operands that are added to an existing matrix multiply-accumulate (MMA) instruction and processed by the compiler to generate executable instructions for a GPU.

[0047] In receive instruction operation 410, a host processor, system-on-chip, or processor receives instructions to perform a matrix multiplication operation involving a sparse matrix (e.g., as disclosed in FIGS. 1-3). In at least one embodiment, a programmer creates a source code file with one or more gather instructions, pack instructions, multiply instructions, and decompress (e.g., or scatter) instructions as part of a neural network operation or machine learning operation. For example, a programmer can create first, second, third, and fourth instructions in CUDA to perform a matrix operation involving a sparse matrix, including functions for gather, pack, multiply, and decompress. In at least one embodiment, the programmer's instructions are received by an API (e.g., a CUDA API) that causes the instructions to be converted into lower-level instructions (e.g., PTX readable source code). In at least one embodiment, a programmer directly writes in the lower-level instructions to generate a source file (e.g., PTX code such as the PTX source file shown in FIG. 1). In at least one embodiment, the act of receiving instructions is performed prior to compilation of source code into executable device code (e.g., for one or more GPUs), where the instructions are received by a compiler (e.g., a PTX compiler) or device code (e.g., a compiler for generating GPU executable code). In at least one embodiment, one or more APIs performed by one or more processors perform all or a portion of the act of receiving instructions 410.

[0048] In a generate compressed array operation 415, a processor, system-on-chip, or processor receives, generates, or implements a compress instruction. In at least one embodiment, one or more circuits implement an API to compress one or more matrices, where compressing is an operation that causes one or more processors to store only non-zero values ​​for a sparse matrix in memory accessible to one or more processor cores or units (e.g., one or more GPUs or graphics processing cores). In at least one embodiment, the compress operation includes generating a compressed array (e.g., a CUDA array) with non-zero values ​​from the sparse matrix. In at least one embodiment, the compress operation can generate a compressed data structure, such as a compressed row, a compressed column, a compressed vector, or other data structure, such as a matrix, having a particular shape or size. In at least one embodiment, generate compressed array operation 415 causes a processor, system-on-chip, or processor to receive and generate an array or metadata that stores non-zero indices of the sparse matrix in memory accessible to the GPU or one or more graphics processing cores (e.g., so that it can be accessed during MMA operations performed by one or more threads executing on the GPU). In at least one embodiment, the compress array operation 415 causes the one or more processors to store the non-zero indices in a binary or compressed format.

[0049] In generating a compressed array operation 415, in at least one embodiment, one or more drivers executing instructions on one or more graphics processing units can access the stored compressed non-zero values ​​and indices for the non-zero values. In at least one embodiment, a compiler compiles instructions including the compressed array operation 415 to generate intermediate or executable instructions for indicating which values ​​of a matrix are non-zero. In at least one embodiment, performing the gather instruction returns an array of indices indicating which values ​​are non-zero. For example, if the first, fourth, and ninth elements of a matrix are the only non-zero values, performing the gather instruction returns 1, 4, and 9. In at least one embodiment, a second instruction (referred to as a "compress instruction" or reduce instruction) is for generating a compressed representation of the matrix. In at least one embodiment, performing the compress instruction causes the non-zero elements of the matrix to be stored with the indices (without the zeros) from the first instruction. For example, execution of a pack instruction by one or more processors causes the one or more processors to generate a packed array that stores values ​​for non-zero elements of a sparse matrix. In at least one embodiment, one or more APIs implemented by one or more processors perform the packed array operation 415.

[0050] In performing 420 a sparse matrix operation, a processor, one or more circuits, systems on chip, or processing cores implements an instruction to perform matrix multiplication (e.g., implements an “MMA instruction”). In at least one embodiment, performing 420 a sparse matrix operation includes performing an MMA operation on two or more matrix operands, where at least one of the operands is packed using a pack instruction (see operation 415). In at least one embodiment, implementing the instruction uses an index to perform the MMA operation (e.g., without unnecessary multiplication by zero). In at least one embodiment, one or more APIs implemented by one or more processors implement the sparse matrix operation 420. In at least one embodiment, the sparse matrix operation 420 includes an operation disclosed in FIGS. 1-3, such as HMMA, IMMA, or other matrix multiplication operations involving sparse matrices.

[0051] In the generate decompressed data structure operation 425, one or more processors or one or more circuits generate or receive a fourth instruction, which then generates a “scatter instruction” for storing the matrix (with zero values) from the non-zero values ​​and the index from the second (compression instruction). In at least one embodiment, one or more processors execute the scatter instruction and store the decompressed matrix in a data structure (e.g., a matrix). In at least one embodiment, the fourth instruction is for decompressing a compressed matrix, which may be executed or generated by an API executed by one or more processors, where the API is part of a library of APIs for implementing sparse matrix multiplication operations. In at least one embodiment, the decompressed data structure operation 425 includes an operation disclosed in FIGS. 1-3, such as HMMA, IMMA, or other matrix multiplication operations involving sparse matrices.

[0052] In operation 430 of determining, in at least one embodiment, a processor, one or more circuits, a system on a chip, or a system performing at least a portion of process 400 determines whether there are additional sparse matrix operations to perform based at least on the performed sparse matrix operations 425. In at least one embodiment, if the system performing at least a portion of process 400 determines that there are additional sparse matrix operations to perform, the system performing at least a portion of process 400 performs sparse matrix operations 420 until all sparse matrix operations are completed. In at least one embodiment, if the system performing at least a portion of process 400 determines that there are no additional sparse matrix operations to perform, process 400 ends.

[0053] As shown in FIG. 4B , in at least one embodiment, one or more circuits implement process 435 for performing an operation to indicate one or more non-zero values ​​in one or more matrices of data. In at least one embodiment, the one or more circuits implement process 435 as part of performing process 400. In operation 437 of obtaining instructions to compress, in at least one embodiment, a processor receives instructions, API output, performs API calls, or receives a source code file (e.g., as disclosed in FIG. 1 ) to compress a data structure such as a sparse matrix. In operation 439 of determining indices of non-zero values ​​in the data structure, in at least one embodiment, one or more circuits or one or more processors (e.g., a host processor, a GPU, or a CPU) determine whether elements of the matrix are non-zero and store indices for the non-zero values ​​in memory (e.g., memory accessible to one or more graphics processing cores). For example, a processor may determine whether each element of a matrix is ​​a zero value or a non-zero value, and if the processor determines that an element is non-zero, it may generate metadata to store an index of the non-zero value, including an index in indexing operation 439. For example, one or more circuits may determine that a matrix [0 0 3 0] has one non-zero value, which is 3, and it may store that (1,3) to indicate that the non-zero value has an index in row 1 and column 3. In at least one embodiment, storing the index value may include a compiler receiving instructions to compress a sparse data structure, and the compiler generating an operand including the index value. In at least one embodiment, in generating operation 441, a processor, one or more circuits, a system on a chip, or a system implementing at least a portion of process 435 determines whether all values ​​in the matrix have been analyzed to determine non-zero values ​​and corresponding indices.In at least one embodiment, if the system performing at least a portion of process 435 determines that there are more matrices to analyze, it may continue analyzing the matrices. In at least one embodiment, if the system performing at least a portion of process 435 determines that there are no additional values ​​to analyze, process 435 ends.

[0054] As shown in FIG. 4C , in at least one embodiment, one or more circuits perform process 445 for implementing an API to compress one or more matrices of data. In operation 447 of obtaining instructions to compress, in at least one embodiment, a processor receives instructions, API outputs, performs API calls, or receives a source code file (e.g., as disclosed in FIG. 1 ) to compress a data structure such as a sparse matrix. In operation 449 of determining non-zero values ​​of a data structure, in at least one embodiment, one or more circuits or one or more processors (e.g., a host processor, a GPU, or a CPU) determine whether elements of the matrix are non-zero. For example, a processor determines whether each element of a matrix is ​​zero or non-zero, and if the processor determines an element is non-zero, it performs operation 449 of generating a compressed data structure and for storing the non-zero values. For example, one or more circuits may determine that the matrix [0 0 3 0] has one non-zero value, which is 3, and it may store that value in an array. In at least one embodiment, in determining operation 452, a processor, one or more circuits, a system on a chip, or a system performing at least a portion of process 445 determines whether all values ​​in the matrix have been analyzed to determine non-zero values. In at least one embodiment, if the system performing at least a portion of process 445 determines that there are more matrices to analyze, it may continue analyzing the matrix. In at least one embodiment, if the system performing at least a portion of process 445 determines that there are no additional values ​​to analyze, process 445 ends.

[0055] As shown in FIG. 4D , in at least one embodiment, one or more circuits perform process 455 for performing a matrix multiply-accumulate (MMA) operation on two or more matrices of data, where at least one of the two or more matrices includes compressed data. In at least one embodiment, the two or more matrices are generated by processes 435 and 445, where one matrix is ​​a matrix including index values ​​for non-zero values ​​and another is the compressed matrix. In an obtaining operation 457, the one or more circuits receive instructions for performing the matrix multiplication operation, for example, by receiving instructions from a compiler or by receiving instructions from source code or an API call. In a receiving operation 459, the one or more circuits receive the non-zero values ​​in the compressed array and the index values ​​for the non-zero values ​​from processes 435 and 445. In operation 461 to perform multiplication, one or more circuits perform a matrix multiplication operation using two or more matrices of data, where at least one of the two or more matrices contains compressed data (e.g., a compressed array with index values).

[0056] As shown in FIG. 4E , in at least one embodiment, one or more circuits process 465 for implementing an API to decompress one or more matrices of data. In at least one embodiment, one or more circuits perform process 465 for implementing an API to decompress one or more matrices of data. In an obtain instruction to compress operation 467, in at least one embodiment, a processor receives instructions, API outputs, performs API calls, or receives a source code file (e.g., as disclosed in FIG. 1 ) to decompress a data structure such as a sparse matrix. For example, after matrix multiplication of the sparse matrix in process 455, the processor receives instructions to generate an expanded matrix and perform a distribution operation. In a receiving operation 469, one or more circuits receive index values ​​for non-zero values ​​in the matrix multiplication result. In a generate decompressed matrix operation, one or more circuits generate a decompressed matrix by performing the distribution operation disclosed in process 400. In at least one embodiment, if the system performing at least a portion of process 465 determines that there are more matrices to decompress, it can continue to decompress the matrices. In at least one embodiment, if the system performing at least a portion of process 465 determines that there are no additional values ​​to analyze, process 465 ends.

[0057] Data Center Figure 5 illustrates an exemplary data center 500, according to at least one embodiment. In at least one embodiment, data center 500 includes the systems disclosed in Figures 1-3 and may implement some or all of process 400 in Figure 4. In at least one embodiment, data center 500 includes, but is not limited to, a data center infrastructure layer 510, a framework layer 520, a software layer 530, and an application layer 540.

[0058] In at least one embodiment, as shown in FIG. 5, data center infrastructure layer 510 may include a resource orchestrator 512, grouped computing resources 514, and node computing resources (“node CR”) 516(1) through 516(N), where “N” represents any positive integer. In at least one embodiment, nodes CR 516(1)-516(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including, but not limited to, accelerators, field programmable gate arrays (“FPGAs”), data processing units (“DPUs”) in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid state or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, cooling modules, etc. In at least one embodiment, one or more nodes CR from among nodes CR 516(1)-516(N) may be a server having one or more of the computing resources described above.

[0059] In at least one embodiment, the grouped computing resources 514 may include a distinct grouping of node CRs housed within one or more racks (not shown), or many racks housed in a data center at various geographic locations (also not shown). The distinct groupings of node CRs within the grouped computing resources 514 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0060] In at least one embodiment, resource orchestrator 512 may configure or otherwise control one or more nodes CR 516(1)-516(N) and / or grouped computing resources 514. In at least one embodiment, resource orchestrator 512 may include a software design infrastructure (“SDI”) management entity for data center 500. In at least one embodiment, resource orchestrator 512 may include hardware, software, or some combination thereof.

[0061] 5, framework layer 520 includes, but is not limited to, a job scheduler 532, a configuration manager 534, a resource manager 536, and a distributed file system 538. In at least one embodiment, framework layer 520 may include a framework for supporting software 552 in software layer 530 and / or one or more applications 542 in application layer 540. In at least one embodiment, software 552 or application(s) 542 may include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure, respectively. In at least one embodiment, framework layer 520 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark™ (hereinafter “Spark”), which may utilize distributed file system 538 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 532 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 500. In at least one embodiment, configuration manager 534 may be capable of configuring different tiers, such as software tier 530 and framework tier 520, which includes Spark and distributed file system 538 to support large-scale data processing. In at least one embodiment, resource manager 536 may be capable of managing clustered or grouped computing resources mapped or allocated to support distributed file system 538 and job scheduler 532. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 514 in data center infrastructure tier 510.In at least one embodiment, resource manager 536 may manage these mapped or allocated computing resources in coordination with resource orchestrator 512.

[0062] In at least one embodiment, software 552 included in software layer 530 may include software used by nodes CR 516(1)-516(N), grouped computing resources 514, and / or at least a portion of distributed file system 538 of framework layer 520. The one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0063] In at least one embodiment, the application(s) 542 included in the application layer 540 may include one or more types of applications used by the nodes CR 516(1)-516(N), the grouped computing resources 514, and / or at least a portion of the distributed file system 538 of the framework layer 520. At least one or more types of applications may include, but are not limited to, CUDA applications.

[0064] In at least one embodiment, any of configuration manager 534, resource manager 536, and resource orchestrator 512 may implement any number and types of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may relieve data center operators of data center 500 from determining potentially faulty configurations and potentially avoiding underutilized and / or underperforming portions of the data center.

[0065] Computer-Based Systems The following diagram describes an exemplary computer-based system that may be used to implement at least one embodiment, but is not limited to the embodiment.

[0066] FIG. 6 illustrates a processing system 600 according to at least one embodiment. In at least one embodiment, processing system 600 includes the systems disclosed in FIGS. 1-3 and may perform some or all of process 400 in FIG. 4. In at least one embodiment, processing system 600 includes one or more processors 602 and one or more graphics processors 608 and may be a single-processor desktop system, a multiprocessor workstation system, or a server system having multiple processors 602 or processor cores 607. In at least one embodiment, processing system 600 is a processing platform integrated into a system-on-a-chip ("SoC") integrated circuit for use in a mobile, handheld, or embedded device.

[0067] In at least one embodiment, processing system 600 may include or be incorporated within a server-based gaming platform, a game console, a media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, processing system 600 is a mobile phone, a smartphone, a tablet computing device, or a mobile internet device. In at least one embodiment, processing system 600 may also include, be coupled to, or be incorporated within a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 600 is a television or set-top box device having one or more processors 602 and a graphical interface generated by one or more graphics processors 608.

[0068] In at least one embodiment, the one or more processors 602 each include one or more processor cores 607 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 607 is configured to process a particular instruction set 609. In at least one embodiment, the instruction set 609 may facilitate Complex Instruction Set Computing ("CISC"), Reduced Instruction Set Computing ("RISC"), or computing via Very Long Instruction Words ("VLIW"). In at least one embodiment, the processor cores 607 may each process a different instruction set 609, and the instruction set 609 may include instructions to facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 607 may also include other processing devices, such as a digital signal processor ("DSP").

[0069] In at least one embodiment, processor 602 includes cache memory (“cache”) 604. In at least one embodiment, processor 602 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 602. In at least one embodiment, processor 602 also uses an external cache (e.g., a level 3 (“L3”) cache or a last level cache (“LLC”)) (not shown), which may be shared among processor cores 607 using known cache coherency techniques. In at least one embodiment, processor 602 additionally includes a register file 606, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 606 may include general-purpose registers or other registers.

[0070] In at least one embodiment, one or more processors 602 are coupled to one or more interface buses 610 for transmitting communication signals, such as address, data, or control signals, between the processors 602 and other components in the processing system 600. In at least one embodiment, the interface bus 610 in one embodiment may be a processor bus, such as a version of a Direct Media Interface ("DMI") bus. In at least one embodiment, the interface bus 610 is not limited to a DMI bus, but may include one or more peripheral component interconnect buses (e.g., Peripheral Component Interconnect, PCI Express ("PCIe")), a memory bus, or other types of interface buses. In at least one embodiment, the processor(s) 602 include an integrated memory controller 616 and a platform controller hub 630. In at least one embodiment, memory controller 616 facilitates communication between memory devices and other components of processing system 600, and platform controller hub (“PCH”) 630 provides connection to I / O devices via a local input / output (“I / O”) bus.

[0071] In at least one embodiment, memory device 620 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, a phase-change memory device, or any other memory device with performance suitable for serving as processor memory. In at least one embodiment, memory device 620 may operate as system memory for processing system 600 to store data 622 and instructions 621 for use when one or more processors 602 execute applications or processes. In at least one embodiment, memory controller 616 also couples to an optional external graphics processor 612, which may communicate with one or more graphics processors 608 in processor 602 to perform graphics and media operations. In at least one embodiment, display device 611 may be connected to processor(s) 602. In at least one embodiment, display device 611 may include one or more of an internal display device, such as in a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, display device 611 may include a head mounted display ("HMD"), such as a stereoscopic display device for use in virtual reality ("VR") or augmented reality ("AR") applications.

[0072] In at least one embodiment, platform controller hub 630 allows peripherals to connect to memory device 620 and processor 602 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 646, a network controller 634, a firmware interface 628, a wireless transceiver 626, a touch sensor 625, and a data storage device 624 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, data storage device 624 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as PCI or PCIe. In at least one embodiment, touch sensor 625 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, wireless transceiver 626 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution ("LTE") transceiver. In at least one embodiment, firmware interface 628 enables communication with system firmware and may be, for example, a unified extensible firmware interface ("UEFI"). In at least one embodiment, network controller 634 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples to interface bus 610. In at least one embodiment, audio controller 646 is a multi-channel high-definition audio controller.In at least one embodiment, processing system 600 includes an optional legacy I / O controller 640 for coupling legacy (e.g., Personal System 2 (“PS / 2”)) devices to processing system 600. In at least one embodiment, platform controller hub 630 can also connect to one or more Universal Serial Bus (“USB”) controller 642-connected input devices, such as a keyboard and mouse 643 combination, a camera 644, or other USB input devices.

[0073] In at least one embodiment, instances of memory controller 616 and platform controller hub 630 may be embedded in a discreet external graphics processor, such as external graphics processor 612. In at least one embodiment, platform controller hub 630 and / or memory controller 616 may be external to one or more processors 602. For example, in at least one embodiment, processing system 600 may include external memory controller 616 and platform controller hub 630, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset in communication with processor(s) 602.

[0074] FIG. 7 illustrates a computer system 700 according to at least one embodiment. In at least one embodiment, computer system 700 may include one or more systems disclosed in FIGS. 1-3 and may perform some or all of process 400 in FIG. 4. In at least one embodiment, computer system 700 may be a system with interconnected devices and components, a SOC, or some combination. In at least one embodiment, computer system 700 is formed with a processor 702 that may include an execution unit for executing instructions. In at least one embodiment, computer system 700 may include components such as, but not limited to, processor 702 to employ an execution unit that includes logic for implementing algorithms for processing data. In at least one embodiment, computer system 700 may include a processor such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 700 may run a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces may also be used.

[0075] In at least one embodiment, computer system 700 may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (DSP), an SoC, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system capable of performing one or more instructions.

[0076] In at least one embodiment, computer system 700 may include, but is not limited to, a processor 702, which may include one or more execution units 708 that may be configured to execute, but is not limited to, Compute Unified Device Architecture (“CUDA”) (CUDA® is developed by NVIDIA Corporation of Santa Clara, California) programs. In at least one embodiment, the CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 700 is a single-processor desktop or server system. In at least one embodiment, computer system 700 may be a multiprocessor system. In at least one embodiment, processor 702 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as, for example, a digital signal processor. In at least one embodiment, processor 702 may be coupled to a processor bus 710 that may transmit data signals between processor 702 and other components in computer system 700.

[0077] In at least one embodiment, processor 702 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 704. In at least one embodiment, processor 702 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 702. In at least one embodiment, processor 702 may also include a combination of both internal and external cache. In at least one embodiment, register file 706 may store different types of data in various registers, including, but not limited to, integer registers, floating-point registers, status registers, and instruction pointer registers.

[0078] In at least one embodiment, an execution unit 708, including logic for performing integer and floating-point operations, may also be present in the processor 702. The processor 702 may also include a microcode ("u-code") read-only memory ("ROM") that stores microcode for some macroinstructions. In at least one embodiment, the execution unit 708 may include logic for dealing with a packed instruction set 709. In at least one embodiment, by including the packed instruction set 709, along with associated circuitry for executing the instructions, in the instruction set of the general-purpose processor 702, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 702. In at least one embodiment, many multimedia applications may be accelerated and run more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0079] In at least one embodiment, the execution unit 708 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuitry. In at least one embodiment, the computer system 700 may include, but is not limited to, a memory 720. In at least one embodiment, the memory 720 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other memory device. The memory 720 may store instruction(s) 719 and / or data 721 represented by data signals that may be executed by the processor 702.

[0080] In at least one embodiment, a system logic chip may be coupled to the processor bus 710 and the memory 720. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 716, and the processor 702 may communicate with the MCH 716 via the processor bus 710. In at least one embodiment, the MCH 716 may provide a high-bandwidth memory path 718 to the memory 720 for instruction and data storage, and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 716 may direct data signals between the processor 702, the memory 720, and other components in the computer system 700, and may bridge data signals between the processor bus 710, the memory 720, and the system I / O 722. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 716 may be coupled to memory 720 through a high-bandwidth memory path 718, and the graphics / video card 712 may be coupled to the MCH 716 via an Accelerated Graphics Port (“AGP”) interconnect 714.

[0081] In at least one embodiment, computer system 700 may use system I / O 722, a proprietary hub interface bus, to couple MCH 716 to I / O controller hub (“ICH”) 730. In at least one embodiment, ICH 730 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripherals to memory 720, a chipset, and processor 702. Examples may include, but are not limited to, an audio controller 729, a firmware hub (“flash BIOS”) 728, a wireless transceiver 726, data storage 724, a legacy I / O controller 723 including a user input interface 725 and a keyboard interface, a serial expansion port 727 such as USB, and a network controller 734. Data storage 724 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0082] In at least one embodiment, FIG. 7 illustrates a system including interconnected hardware devices or "chips." In at least one embodiment, FIG. 7 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in FIG. 7 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 700 are interconnected using a Compute Express Link ("CXL") interconnect.

[0083] 8 illustrates a system 800 according to at least one embodiment. In at least one embodiment, system 800 may include one or more of the systems disclosed in FIGS. 1-3 and may perform some or all of process 400 in FIG. 4. In at least one embodiment, system 800 is an electronic device utilizing processor 810. In at least one embodiment, system 800 may be, for example, but not limited to, a notebook, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more on-premise or cloud service providers, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0084] In at least one embodiment, system 800 may include a processor 810 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices, without limitation. In at least one embodiment, processor 810 is coupled using a bus or interface, such as an I2C bus, a System Management Bus (“SMBus”), a Low Pin Count (“LPC”) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, USB (versions 1, 2, and 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 8 illustrates a system including interconnected hardware devices or “chips.” In at least one embodiment, FIG. 8 may illustrate an exemplary SoC. In at least one embodiment, the devices shown in Figure 8 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of Figure 8 are interconnected using a CXL interconnect.

[0085] In at least one embodiment, FIG. 8 includes a display 824, a touch screen 825, a touch pad 830, a Near Field Communication (NFC) unit 845, a sensor hub 840, a thermal sensor 846, an Express Chipset (EC) 835, a Trusted Platform Module (TPM) 838, a BIOS / firmware / flash memory (BIOS,FW flash) 822, a DSP 860, a Solid State Disk (SSD) or Hard Disk Drive (HDD) 820, a Wireless Local Area Network (WLAN) unit 850, a Bluetooth unit 852, a Wireless Wide Area Network (WWAN) unit 856, a Global Positioning System (GPS), a Bluetooth module 852, a Bluetooth-enabled Bluetooth device 854, a Bluetooth-enabled Bluetooth device 856, a Bluetooth-enabled Bluetooth device 858 ... The memory may include a USB 3.0 Camera ("USB 3.0 Camera") 854, a USB 3.0 Camera, or a Low Power Double Data Rate ("LPDDR") memory unit ("LPDDR3") 815, implemented, for example, in the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0086] In at least one embodiment, other components may be communicatively coupled to processor 810 through the components described above. In at least one embodiment, an accelerometer 841, an ambient light sensor (“ALS”) 842, a compass 843, and a gyroscope 844 may be communicatively coupled to sensor hub 840. In at least one embodiment, a thermal sensor 839, a fan 837, a keyboard 836, and a touchpad 830 may be communicatively coupled to EC 835. In at least one embodiment, a speaker 863, headphones 864, and a microphone (“mic”) 865 may be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 862, which may be communicatively coupled to DSP 860. In at least one embodiment, audio unit 862 may include, for example, without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 857 can be communicatively coupled to the WWAN unit 856. In at least one embodiment, components such as the WLAN unit 850 and the Bluetooth unit 852, and the WWAN unit 856 can be implemented in a Next Generation Form Factor (“NGFF”).

[0087] FIG. 9 illustrates an exemplary integrated circuit 900, according to at least one embodiment. In at least one embodiment, the integrated circuit 900 may be included in one or more systems disclosed in FIGS. 1-3 and may perform some or all of the processes 400 in FIG. 4. In at least one embodiment, the exemplary integrated circuit 900 is an SoC that may be fabricated using one or more IP cores. In at least one embodiment, the integrated circuit 900 includes one or more application processors 905 (e.g., CPU, DPU), at least one graphics processor 910, and may additionally include an image processor 915 and / or a video processor 920, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 900 includes a USB controller 925, a UART controller 930, an SPI / SDIO controller 935, and an I / O controller 940. 2 S / I 2 The integrated circuit 900 may include peripheral or bus logic including a HDMI controller 940. In at least one embodiment, the integrated circuit 900 may include a display device 945 coupled to one or more of a high-definition multimedia interface ("HDMI") controller 950 and a mobile industry processor interface ("MIPI") display interface 955. In at least one embodiment, storage may be provided by a flash memory subsystem 960 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 965 for access to an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits additionally include an embedded security engine 970.

[0088] FIG. 10 illustrates a computing system 1000 according to at least one embodiment. In at least one embodiment, computing system 1000 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of process 400 in FIG. 4. In at least one embodiment, computing system 1000 includes a processing subsystem 1001 having one or more processors 1002 and system memory 1004 that communicate via an interconnection path that may include a memory hub 1005. In at least one embodiment, memory hub 1005 may be a separate component within a chipset component or may be incorporated within one or more processors 1002. In at least one embodiment, memory hub 1005 couples to an I / O subsystem 1011 via a communication link 1006. In at least one embodiment, the I / O subsystem 1011 includes an I / O hub 1007 that can enable the computing system 1000 to receive input from one or more input devices 1008. In at least one embodiment, the I / O hub 1007 can enable a display controller, which can be included in one or more processors 1002, to provide output to one or more display devices 1010A. In at least one embodiment, the one or more display devices 1010A coupled with the I / O hub 1007 can include local, internal, or embedded display devices.

[0089] In at least one embodiment, the processing subsystem 1001 includes one or more parallel processors 1012 coupled to a memory hub 1005 via a bus or other communication link 1013. In at least one embodiment, the communication link 1013 may be one of any number of standards-based communication link technologies or protocols, such as, but not limited to, PCIe, or may be a vendor-specific communication interface or fabric. In at least one embodiment, the one or more parallel processors 1012 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many-integrated-core processor. In at least one embodiment, the one or more parallel processors 1012 form a graphics processing subsystem that can output pixels to one of one or more display devices 1010A coupled via the I / O hub 1007. In at least one embodiment, the one or more parallel processors 1012 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1010B.

[0090] In at least one embodiment, a system storage unit 1014 may connect to an I / O hub 1007 to provide a storage mechanism for the computing system 1000. In at least one embodiment, an I / O switch 1016 may be used to provide an interface mechanism to enable connections between the I / O hub 1007 and other components, such as a network adapter 1018 and / or a wireless network adapter 1019, which may be embedded in the platform, as well as various other devices that may be added via one or more add-in devices 1020. In at least one embodiment, the network adapter 1018 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1019 may include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more wireless radios.

[0091] In at least one embodiment, computing system 1000 may include other components not expressly shown that may also be connected to I / O hub 1007, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the communication paths interconnecting the various components in FIG. 10 may be implemented using any suitable protocol, such as a PCI-based protocol (e.g., PCIe), or other bus or point-to-point communication interface and / or protocol(s), or interconnection protocol, such as an NVLink high-speed interconnect.

[0092] In at least one embodiment, one or more parallel processors 1012 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, to form a graphics processing unit ("GPU"). In at least one embodiment, one or more parallel processors 1012 incorporate circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 1000 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1012, memory hub 1005, processor(s) 1002, and I / O hub 1007 may be integrated into an SoC integrated circuit. In at least one embodiment, components of computing system 1000 may be integrated into a single package to form a system-in-package ("SIP") configuration. In at least one embodiment, at least a portion of the components of computing system 1000 may be incorporated into a multi-chip module ("MCM"), which may be interconnected with other multi-chip modules to form a modular computing system. In at least one embodiment, I / O subsystem 1011 and display device 1010B are omitted from computing system 1000.

[0093] Processing System The following figures describe exemplary processing systems that may be used to implement, but are not limited to, at least one embodiment.

[0094] FIG. 11 illustrates an accelerated processing unit ("APU") 1100 according to at least one embodiment. In at least one embodiment, the APU 1100 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of the processes 400 in FIG. 4. In at least one embodiment, the APU 1100 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the APU 1100 may be configured to execute application programs, such as CUDA programs. In at least one embodiment, the APU 1100 includes, but is not limited to, a core complex 1110, a graphics complex 1140, a fabric 1160, an I / O interface 1170, a memory controller 1180, a display controller 1192, and a multimedia engine 1194. In at least one embodiment, APU 1100 may include, in any combination, without limitation, any number of core complexes 1110, any number of graphics complexes 1150, any number of display controllers 1192, and any number of multimedia engines 1194. For purposes of explanation, multiple instances of similar objects are referred to herein with a reference number identifying the object and, where necessary, a parenthetical number identifying the instance.

[0095] In at least one embodiment, the core complex 1110 is a CPU, the graphics complex 1140 is a GPU, and the APU 1100 is a processing unit incorporating the core complex 1110 and the graphics complex 1140 on a single chip, without limitation. In at least one embodiment, some tasks may be assigned to the core complex 1110 and other tasks may be assigned to the graphics complex 1140. In at least one embodiment, the core complex 1110 is configured to execute main control software associated with the APU 1100, such as an operating system. In at least one embodiment, the core complex 1110 is the master processor of the APU 1100 and controls and coordinates the operation of the other processors. In at least one embodiment, the core complex 1110 issues commands that control the operation of the graphics complex 1140. In at least one embodiment, the core complex 1110 may be configured to execute host executable code derived from CUDA source code, and the graphics complex 1140 may be configured to execute device executable code derived from CUDA source code.

[0096] In at least one embodiment, core complex 1110 includes, but is not limited to, cores 1120(1)-1120(4) and an L3 cache 1130. In at least one embodiment, core complex 1110 may include, but is not limited to, any number of cores 1120 and any number and type of caches, in any combination. In at least one embodiment, cores 1120 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1120 is a CPU core.

[0097] In at least one embodiment, each core 1120 includes, but is not limited to, a fetch / decode unit 1122, an integer execution engine 1124, a floating-point execution engine 1126, and an L2 cache 1128. In at least one embodiment, the fetch / decode unit 1122 fetches instructions, decodes such instructions, generates micro-ops, and dispatches separate micro-instructions to the integer execution engine 1124 and the floating-point execution engine 1126. In at least one embodiment, the fetch / decode unit 1122 can simultaneously dispatch one micro-instruction to the integer execution engine 1124 and another micro-instruction to the floating-point execution engine 1126. In at least one embodiment, the integer execution engine 1124 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1126 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch decode unit 1122 dispatches microinstructions to a single execution engine that replaces both the integer execution engine 1124 and the floating-point execution engine 1126 .

[0098] In at least one embodiment, each core 1120(i), where i is an integer representing a particular instance of core 1120, may access an L2 cache 1128(i) included in core 1120(i). In at least one embodiment, each core 1120 included in a core complex 1110(j), where j is an integer representing a particular instance of core complex 1110, is connected to the other cores 1120 included in core complex 1110(j) via an L3 cache 1130(j) included in core complex 1110(j). In at least one embodiment, a core 1120 included in a core complex 1110(j), where j is an integer representing a particular instance of core complex 1110, may access all of the L3 caches 1130(j) included in core complex 1110(j). In at least one embodiment, the L3 cache 1130 may include, without limitation, any number of slices.

[0099] In at least one embodiment, the graphics complex 1140 may be configured to perform compute operations in a highly parallel manner. In at least one embodiment, the graphics complex 1140 is configured to execute graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations related to rendering an image to a display. In at least one embodiment, the graphics complex 1140 is configured to execute non-graphics related operations. In at least one embodiment, the graphics complex 1140 is configured to execute both graphics related and non-graphics related operations.

[0100] In at least one embodiment, the graphics complex 1140 includes, but is not limited to, any number of compute units 1150 and an L2 cache 1142. In at least one embodiment, the compute units 1150 share the L2 cache 1142. In at least one embodiment, the L2 cache 1142 is partitioned. In at least one embodiment, the graphics complex 1140 includes, but is not limited to, any number of compute units 1150 and any number and type of cache (including zero). In at least one embodiment, the graphics complex 1140 includes, but is not limited to, any amount of dedicated graphics hardware.

[0101] In at least one embodiment, each compute unit 1150 includes, but is not limited to, any number of SIMD units 1152 and shared memory 1154. In at least one embodiment, each SIMD unit 1152 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each compute unit 1150 may execute any number of thread blocks, with each thread block executing on a single compute unit 1150. In at least one embodiment, a thread block includes, but is not limited to, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1152 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication may be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize with each other and communicate via shared memory 1154.

[0102] In at least one embodiment, fabric 1160 is a system interconnect that facilitates data and control transmission across core complex 1110, graphics complex 1140, I / O interface 1170, memory controller 1180, display controller 1192, and multimedia engine 1194. In at least one embodiment, APU 1100 may include any quantity and type of system interconnect in addition to or instead of fabric 1160, which facilitates data and control transmission across any number and type of directly or indirectly linked components, which may be internal or external to APU 1100. In at least one embodiment, I / O interface 1170 represents any number and type of I / O interface (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc. In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1170. In at least one embodiment, peripheral devices coupled to I / O interface 1170 may include, but are not limited to, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0103] In at least one embodiment, display controller AMD92 displays images on one or more display devices, such as liquid crystal display ("LCD") devices. In at least one embodiment, multimedia engine 1194 includes any quantity and type of circuitry related to multimedia, such as, but not limited to, a video decoder, a video encoder, and an image signal processor. In at least one embodiment, memory controller 1180 facilitates data transfer between APU 1100 and unified system memory 1190. In at least one embodiment, core complex 1110 and graphics complex 1140 share unified system memory 1190.

[0104] In at least one embodiment, the APU 1100 implements a memory subsystem including, but not limited to, any quantity and type of memory controller 1180 and memory devices (e.g., shared memory 1154) that may be dedicated to one component or shared among multiple components. In at least one embodiment, the APU 1100 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 1228, L3 cache 1130, and L2 cache 1142), each of which may be private to any number of components (e.g., cores 1120, core complexes 1110, SIMD units 1152, compute units 1150, and graphics complexes 1140) or shared among any number of components.

[0105] FIG. 12 illustrates a CPU 1200 according to at least one embodiment. In at least one embodiment, the CPU 1200 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of the processes 400 in FIG. 4 . In at least one embodiment, the CPU 1200 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the CPU 1200 may be configured to execute application programs. In at least one embodiment, the CPU 1200 may be configured to execute main control software, such as an operating system. In at least one embodiment, the CPU 1200 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1200 may be configured to execute host executable code derived from CUDA source code, and the external GPU may be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, CPU 1200 includes, but is not limited to, any number of core complexes 1210, a fabric 1260, an I / O interface 1270, and a memory controller 1280.

[0106] In at least one embodiment, core complex 1210 includes, but is not limited to, cores 1220(1)-1220(4) and an L3 cache 1230. In at least one embodiment, core complex 1210 may include, but is not limited to, any number of cores 1220 and any number and type of caches in any combination. In at least one embodiment, cores 1220 are configured to execute instructions of a particular ISA. In at least one embodiment, each core 1220 is a CPU core.

[0107] In at least one embodiment, each core 1220 includes, but is not limited to, a fetch / decode unit 1222, an integer execution engine 1224, a floating-point execution engine 1226, and an L2 cache 1228. In at least one embodiment, the fetch / decode unit 1222 fetches instructions, decodes such instructions, generates micro-ops, and dispatches separate micro-instructions to the integer execution engine 1224 and the floating-point execution engine 1226. In at least one embodiment, the fetch / decode unit 1222 can simultaneously dispatch one micro-instruction to the integer execution engine 1224 and another micro-instruction to the floating-point execution engine 1226. In at least one embodiment, the integer execution engine 1224 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1226 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch decode unit 1222 dispatches microinstructions to a single execution engine that replaces both the integer execution engine 1224 and the floating-point execution engine 1226 .

[0108] In at least one embodiment, each core 1220(i), where i is an integer representing a particular instance of core 1220, may access an L2 cache 1228(i) included in core 1220(i). In at least one embodiment, each core 1220 included in a core complex 1210(j), where j is an integer representing a particular instance of core complex 1210, is connected to the other cores 1220 in core complex 1210(j) via an L3 cache 1230(j) included in core complex 1210(j). In at least one embodiment, a core 1220 included in a core complex 1210(j), where j is an integer representing a particular instance of core complex 1210, may access all of the L3 caches 1230(j) included in core complex 1210(j). In at least one embodiment, L3 cache 1230 may include, without limitation, any number of slices.

[0109] In at least one embodiment, fabric 1260 is a system interconnect that facilitates data and control transmission across core complexes 1210(1) through 1210(N) (where N is an integer greater than 0), I / O interface 1270, and memory controller 1280. In at least one embodiment, CPU 1200 may include any quantity and type of system interconnect in addition to or instead of fabric 1260, which facilitates data and control transmission across any number and type of directly or indirectly linked components, which may be internal or external to CPU 1200. In at least one embodiment, I / O interface 1270 represents any number and type of I / O interface (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1270. In at least one embodiment, peripheral devices coupled to I / O interface 1270 may include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0110] In at least one embodiment, memory controller 1280 facilitates data transfer between CPU 1200 and system memory 1290. In at least one embodiment, core complex 1210 and graphics complex 1240 share system memory 1290. In at least one embodiment, CPU 1200 implements a memory subsystem including, but not limited to, any quantity and type of memory controller 1280 and memory devices, which may be dedicated to one component or shared among multiple components. In at least one embodiment, CPU 1200 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 1228 and L3 cache 1230), each of which may be private to any number of components (e.g., core 1220 and core complex 1210) or shared among any number of components.

[0111] FIG. 13 illustrates an exemplary accelerator integration slice 1390 according to at least one embodiment. In at least one embodiment, the accelerator integration slice 1390 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of the processes 400 in FIG. 4 . As used herein, a “slice” comprises a designated portion of the processing resources of an accelerator integration circuit. In at least one embodiment, the accelerator integration circuit provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines included in the graphics acceleration module. The graphics processing engines may each comprise a separate GPU. Alternatively, the graphics processing engine may comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU with multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip.

[0112] Application effective address space 1382 in system memory 1314 stores process element 1383. In one embodiment, process element 1383 is stored in response to GPU call 1381 from application 1380 executing on processor 1307. Process element 1383 contains the process state of the corresponding application 1380. Work descriptor (“WD”) 1384 contained in process element 1383 may be a single job requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, WD 1384 is a pointer to a job request queue in application effective address space 1382.

[0113] The graphics acceleration module 1346 and / or individual graphics processing engines may be shared by all or a subset of the processes in the system. In at least one embodiment, infrastructure may be included for setting process state and submitting WD 1384 to the graphics acceleration module 1346 to start jobs in a virtualized environment.

[0114] In at least one embodiment, the dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 1346 or an individual graphics processing engine. Because the graphics acceleration module 1346 is owned by a single process, the hypervisor initializes the accelerator integration circuitry for the owning partition, and the operating system initializes the accelerator integration circuitry for the owning process when the graphics acceleration module 1346 is allocated.

[0115] In operation, WD fetch unit 1391 in accelerator integrated slice 1390 fetches the next WD 1384, which contains instructions for work to be performed by one or more graphics processing engines of graphics acceleration module 1346. As shown, data from WD 1384 is stored in register 1345 and may be used by memory management unit (“MMU”) 1339, interrupt management circuitry 1347, and / or context management circuitry 1348. For example, one embodiment of MMU 1339 includes segment / page walk circuitry for accessing segment / page table 1386 within OS virtual address space 1385. Interrupt management circuit 1347 may process interrupt events (“INT”) 1392 received from graphics acceleration module 1346. When performing graphics operations, effective addresses 1393 generated by the graphics processing engines are translated into real addresses by MMU 1339.

[0116] In one embodiment, the same set of registers 1345 may be replicated for each graphics processing engine and / or graphics acceleration module 1346 and initialized by the hypervisor or operating system. Each of these replicated registers may be included in the accelerator integration slice 1390. Exemplary registers that may be initialized by the hypervisor are shown in Table 1. [Table 1]

[0117] Exemplary registers that may be initialized by the operating system are shown in Table 2. [Table 2]

[0118] In one embodiment, each WD 1384 is specific to a particular graphics acceleration module 1346 and / or a particular graphics processing engine. The WD 1384 may contain all the information needed by the graphics processing engine to perform work, or the WD 1384 may be a pointer to a memory location where the application has set up a command queue for work to be completed.

[0119] 14A-14B illustrate exemplary graphics processors, according to at least one embodiment. In at least one embodiment, any of the exemplary graphics processors may be fabricated using one or more IP cores. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is for use within an SoC.

[0120] FIG. 14A illustrates an exemplary graphics processor 1410 of an SoC integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. FIG. 14B illustrates an additional exemplary graphics processor 1440 of an SoC integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor 1410 or graphics processor 1440 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of process 400 in FIG. 4. In at least one embodiment, graphics processor 1410 of FIG. 14A is a low-power graphics processor core. In at least one embodiment, graphics processor 1440 of FIG. 14B is a higher-performance graphics processor core. In at least one embodiment, each of graphics processors 1410, 1440 may be a variation of graphics processor 910 of FIG. 9.

[0121] In at least one embodiment, the graphics processor 1410 includes a vertex processor 1405 and one or more fragment processors 1415A-1415N (e.g., 1415A, 1415B, 1415C, 1415D-1415N-1, and 1415N). In at least one embodiment, the graphics processor 1410 can execute different shader programs through separate logic, whereby the vertex processor 1405 is optimized to perform operations for vertex shader programs, and one or more fragment processors 1415A-1415N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1405 performs the vertex processing stage of the 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, the fragment processor(s) 1415A-1415N use the primitive and vertex data generated by the vertex processor 1405 to create a frame buffer that is displayed on a display device. In at least one embodiment, the fragment processor(s) 1415A-1415N are optimized to execute fragment shader programs such as those provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs such as those provided in the Direct 3D API.

[0122] In at least one embodiment, the graphics processor 1410 additionally includes one or more MMUs 1420A-1420B, cache(s) 1425A-1425B, and circuit interconnect(s) 1430A-1430B. In at least one embodiment, the one or more MMUs 1420A-1420B provide virtual-to-physical address mapping for the graphics processor 1410, including the vertex processor 1405 and / or fragment processor(s) 1415A-1415N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 1425A-1425B. In at least one embodiment, one or more MMUs 1420A-1420B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 905, image processor 915, and / or video processor 920 of Figure 9, thereby allowing each processor 905-920 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1430A-1430B enable graphics processor 1410 to interface with other IP cores in the SoC, either via the SoC's internal bus or via a direct connection.

[0123] In at least one embodiment, graphics processor 1440 includes one or more MMUs 1420A-1420B, caches 1425A-1425B, and circuit interconnects 1430A-1430B of graphics processor 1410 of FIG. 14A. In at least one embodiment, the graphics processor 1440 includes one or more shader cores 1455A-1455N (e.g., 1455A, 1455B, 1455C, 1455D, 1455E, 1455F-1455N-1, and 1455N), where the one or more shader cores 1455A-1455N provide a unified shader core architecture in which a single core, or type, or cores can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1440 includes an inter-core task manager 1445 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1455A-1455N, and a tiling unit 1458 for accelerating tiling operations for tile-based rendering, where rendering operations for a scene are sub-partitioned in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0124] FIG. 15A illustrates a graphics core 1500 according to at least one embodiment. In at least one embodiment, graphics core 1500 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of process 400 in FIG. 4 ; for example, the graphics processing core may be part of GPU 116. In at least one embodiment, graphics core 1500 may be included within graphics processor 910 of FIG. 9. In at least one embodiment, graphics core 1500 may be unified shader cores 1455A-1455N, as in FIG. 14B. In at least one embodiment, graphics core 1500 includes a shared instruction cache 1502, a texture unit 1518, and a cache / shared memory 1520, which are common to execution resources within graphics core 1500. In at least one embodiment, graphics core 1500 can include multiple slices 1501A-1501N, or partitions for each core, and a graphics processor can include multiple instances of graphics core 1500. Slices 1501A-1501N can include support logic including local instruction caches 1504A-1504N, thread schedulers 1506A-1506N, thread dispatchers 1508A-1508N, and sets of registers 1510A-1510N.In at least one embodiment, slices 1501A-1501N may include a set of additional function units (“AFUs”) 1512A-1512N, floating-point units (“FPUs”) 1514A-1514N, integer arithmetic logic units (“ALUs”) 1516-1516N, address computational units (“ACUs”) 1513A-1513N, double-precision floating-point units (“DPFPUs”) 1515A-1515N, and matrix processing units (“MPUs”) 1517A-1517N.

[0125] In at least one embodiment, the FPUs 1514A-1514N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPUs 1515A-1515N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1516A-1516N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and may be configured for mixed-precision operations. In at least one embodiment, the MPUs 1517A-1517N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1517A-1517N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix-to-matrix multiplication ("GEMM"). In at least one embodiment, the AFUs 1512A-1512N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0126] FIG. 15B illustrates a general-purpose graphics processing unit (“GPGPU”) 1530 according to at least one embodiment. In at least one embodiment, the GPGPU 1530 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of process 400 in FIG. 4 ; for example, the GPGPU 1530 may be GPU 116. In at least one embodiment, the GPGPU 1530 is highly parallel and suitable for implementation on a multi-chip module. In at least one embodiment, the GPGPU 1530 may be configured to enable highly parallel compute operations to be performed by an array of GPUs. In at least one embodiment, the GPGPU 1530 may be directly linked to other instances of the GPGPU 1530 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, the GPGPU 1530 includes a host interface 1532 to enable connection with a host processor. In at least one embodiment, host interface 1532 is a PCIe interface. In at least one embodiment, host interface 1532 can be a vendor-specific communications interface or fabric. In at least one embodiment, GPGPU 1530 receives commands from a host processor and distributes execution threads associated with those commands across a set of compute clusters 1536A-1536H using global scheduler 1534. In at least one embodiment, compute clusters 1536A-1536H share cache memory 1538. In at least one embodiment, cache memory 1538 can act as a higher-level cache for cache memories within compute clusters 1536A-1536H.

[0127] In at least one embodiment, GPGPU 1530 includes memory 1544A-1544B coupled to compute clusters 1536A-1536H via a set of memory controllers 1542A-1542B. In at least one embodiment, memory 1544A-1544B can include various types of memory devices, including DRAM or graphics random access memory such as synchronous graphics random access memory ("SGRAM"), including graphics double data rate ("GDDR") memory.

[0128] In at least one embodiment, compute clusters 1536A-1536H each include a set of graphics cores, such as graphics core 1500 of FIG. 15A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with various precisions, including those suitable for computations associated with CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 1536A-1536H may be configured to perform 16-bit or 32-bit floating-point operations, and a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0129] In at least one embodiment, multiple instances of GPGPU 1530 may be configured to operate as a compute cluster. The compute clusters 1536A-1536H may implement any technically feasible communication technique for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 1530 communicate via host interface 1532. In at least one embodiment, GPGPU 1530 includes an I / O hub 1539 that couples GPGPU 1530 to a GPU link 1540 that enables direct connection to other instances of GPGPU 1530. In at least one embodiment, GPU link 1540 is coupled to a dedicated GPU-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1530. In at least one embodiment, GPU link 1540 couples to a high-speed interconnect for sending and receiving data to other GPGPUs 1530 or parallel processors. In at least one embodiment, multiple instances of GPGPU 1530 are located in separate data processing systems and communicate via a network device accessible via host interface 1532. In at least one embodiment, GPU link 1540 may be configured to allow connection to a host processor in addition to, or as an alternative to, host interface 1532. In at least one embodiment, GPGPU 1530 may be configured to execute CUDA programs.

[0130] 16A illustrates a parallel processor 1600, according to at least one embodiment. In at least one embodiment, the parallel processor 1600 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of the processes 400 in FIG. 4; for example, the parallel processor 1600 may be a GPU 116. In at least one embodiment, various components of the parallel processor 1600 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit ("ASIC"), or an FPGA.

[0131] In at least one embodiment, parallel processor 1600 includes parallel processing units 1602. In at least one embodiment, parallel processing units 1602 include I / O units 1604 that enable communication with other devices, including other instances of parallel processing units 1602. In at least one embodiment, I / O units 1604 may be directly connected to other devices. In at least one embodiment, I / O units 1604 connect to other devices through the use of a hub or switch interface, such as memory hub 1605. In at least one embodiment, the connection between memory hub 1605 and I / O units 1604 forms a communication link. In at least one embodiment, I / O units 1604 connect to host interface 1606 and memory crossbar 1616, where host interface 1606 receives commands intended to perform processing operations and memory crossbar 1616 receives commands intended to perform memory operations.

[0132] In at least one embodiment, when host interface 1606 receives command buffers via I / O unit 1604, host interface 1606 can direct work operations to implement those commands to front end 1608. In at least one embodiment, front end 1608 is coupled to scheduler 1610, which is configured to distribute commands or other work items to processing array 1612. In at least one embodiment, scheduler 1610 ensures that processing array 1612 is properly configured and in a valid state before tasks are distributed to processing array 1612. In at least one embodiment, scheduler 1610 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1610 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, allowing rapid preemption and context switching of threads executing on the processing array 1612. In at least one embodiment, host software can present workloads for scheduling on the processing array 1612 via one of multiple graphics processing bells. In at least one embodiment, the workloads can then be automatically distributed across the processing array 1612 by scheduler 1610 logic within the microcontroller that includes the scheduler 1610.

[0133] In at least one embodiment, processing array 1612 may include up to “N” clusters (e.g., cluster 1614A, cluster 1614B through cluster 1614N). In at least one embodiment, each cluster 1614A-1614N of processing array 1612 may execute multiple concurrent threads. In at least one embodiment, scheduler 1610 may allocate work to clusters 1614A-1614N of processing array 1612 using various scheduling and / or work distribution algorithms, which may vary depending on the workload occurring for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 1610 or may be partially assisted by compiler logic during compilation of program logic configured for execution by processing array 1612. In at least one embodiment, different clusters 1614A-1614N of processing array 1612 may be allocated to process different types of programs or perform different types of computations.

[0134] In at least one embodiment, processing array 1612 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 1612 is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing array 1612 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0135] In at least one embodiment, processing array 1612 is configured to perform parallel graphics processing operations. In at least one embodiment, processing array 1612 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing array 1612 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 1602 may transfer data from system memory via I / O unit 1604 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1622) during processing and then written back to system memory.

[0136] In at least one embodiment, when parallel processing unit 1602 is used to perform graphics processing, scheduler 1610 may be configured to divide the processing workload into tasks of approximately equal size to better enable distribution of graphics processing operations to multiple clusters 1614A-1614N of processing array 1612. In at least one embodiment, portions of processing array 1612 may be configured to perform different types of processing. For example, in at least one embodiment, to produce a rendered image for display, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data produced by one or more of clusters 1614A-1614N may be stored in a buffer to allow the intermediate data to be transmitted between clusters 1614A-1614N for further processing.

[0137] In at least one embodiment, processing array 1612 may receive processing tasks to be performed via scheduler 1610, which receives commands defining the processing tasks from front end 1608. In at least one embodiment, a processing task may include an index of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands that define how the data should be processed (e.g., which program should be executed). In at least one embodiment, scheduler 1610 may be configured to fetch the index corresponding to the task or may receive the index from front end 1608. In at least one embodiment, front end 1608 may be configured to ensure that processing array 1612 is configured to a valid state before a workload specified by an incoming command buffer (e.g., batch buffer, push buffer, etc.) is initiated.

[0138] In at least one embodiment, each of one or more instances of parallel processing unit 1602 can be coupled to parallel processor memory 1622. In at least one embodiment, parallel processor memory 1622 can be accessed via memory crossbar 1616, which can receive memory requests from processing array 1612 as well as I / O unit 1604. In at least one embodiment, memory crossbar 1616 can access parallel processor memory 1622 via memory interface 1618. In at least one embodiment, memory interface 1618 can include multiple partition units (e.g., partition unit 1620A, partition unit 1620B through partition unit 1620N), each of which can be coupled to a portion (e.g., a memory unit) of parallel processor memory 1622. In at least one embodiment, the number of partition units 1620A-1620N is configured to be equal to the number of memory units, such that a first partition unit 1620A has a corresponding first memory unit 1624A, a second partition unit 1620B has a corresponding memory unit 1624B, and an Nth partition unit 1620N has a corresponding Nth memory unit 1624N. In at least one embodiment, the number of partition units 1620A-1620N may not be equal to the number of memory devices.

[0139] In at least one embodiment, the memory units 1624A-1624N may include various types of memory devices, including DRAM or graphics random access memory, such as SGRAM, including GDDR memory. In at least one embodiment, the memory units 1624A-1624N may also include 3D stacked memory, including but not limited to high bandwidth memory (“HBM”). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 1622, render targets, such as frame buffers or texture maps, may be stored across the memory units 1624A-1624N, allowing the partition units 1620A-1620N to write portions of each render target in parallel. In at least one embodiment, local instances of the parallel processor memory 1622 may be eliminated in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

[0140] In at least one embodiment, any one of the clusters 1614A-1614N of the processing array 1612 can process data that is to be written to any one of the memory units 1624A-1624N in the parallel processor memory 1622. In at least one embodiment, the memory crossbar 1616 can be configured to forward the output of each cluster 1614A-1614N to any partition unit 1620A-1620N that can perform additional processing operations on the output, or to another cluster 1614A-1614N. In at least one embodiment, each cluster 1614A-1614N can communicate with a memory interface 1618 through the memory crossbar 1616 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar 1616 has a connection to a memory interface 1618 for communicating with the I / O units 1604, as well as a connection to a local instance of parallel processor memory 1622, which allows processing units in different clusters 1614A-1614N to communicate with system memory or other memory not local to the parallel processing units 1602. In at least one embodiment, the memory crossbar 1616 can use virtual channels to separate traffic streams between the clusters 1614A-1614N and the partition units 1620A-1620N.

[0141] In at least one embodiment, multiple instances of parallel processing unit 1602 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 1602 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1602 may include higher precision floating-point units relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 1602 or parallel processor 1600 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0142] FIG. 16B illustrates a processing cluster 1694, according to at least one embodiment. In at least one embodiment, the processing cluster 1694 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of the processes 400 in FIG. 4. In at least one embodiment, the processing cluster 1694 is included within a parallel processing unit. In at least one embodiment, the processing cluster 1694 is one of the processing clusters 1614A-1614N of FIG. 16. In at least one embodiment, the processing cluster 1694 may be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, a single instruction, multiple data ("SIMD") instruction issue technique is used to support the parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, single instruction, multiple thread ("SIMT") techniques are used to support parallel execution of multiple threads that are synchronized overall using a common instruction unit configured to issue instructions to a set of processing engines in each processing cluster 1694.

[0143] In at least one embodiment, operation of the processing cluster 1694 may be controlled via a pipeline manager 1632 that distributes processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 1632 receives instructions from the scheduler 1610 of FIG. 16 and manages the execution of those instructions via the graphics multiprocessor 1634 and / or the texture unit 1636. In at least one embodiment, the graphics multiprocessor 1634 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within the processing cluster 1694. In at least one embodiment, one or more instances of the graphics multiprocessor 1634 may be included within the processing cluster 1694. In at least one embodiment, the graphics multiprocessor 1634 may process data, and a data crossbar 1640 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, the pipeline manager 1632 can facilitate the distribution of the processed data by specifying a destination for the processed data to be distributed through the data crossbar 1640.

[0144] In at least one embodiment, each graphics multiprocessor 1634 in a processing cluster 1694 may include an identical set of function execution logic (e.g., arithmetic logic units, load / store units (“LSUs”), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, such that new instructions may be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and computation of various algebraic functions. In at least one embodiment, the same function unit hardware may be utilized to perform different operations, and any combination of function units may be present.

[0145] In at least one embodiment, instructions sent to processing cluster 1694 constitute threads. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread in a thread group may be assigned to a different processing engine in graphics multiprocessor 1634. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in graphics multiprocessor 1634. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during a cycle in which the thread group is processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in graphics multiprocessor 1634. In at least one embodiment, when a thread group includes more threads than the number of processing engines in graphics multiprocessor 1634, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on the graphics multiprocessor 1634.

[0146] In at least one embodiment, the graphics multiprocessor 1634 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 1634 can forgo internal cache and use cache memory (e.g., L1 cache 1648) within the processing cluster 1694. In at least one embodiment, each graphics multiprocessor 1634 also has access to a level 2 (“L2”) cache within a partition unit (e.g., partition units 1620A-1620N in FIG. 16A ), which is shared among all processing clusters 1694 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 1634 can also access off-chip global memory, which can include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing unit 1602 can be used as global memory. In at least one embodiment, processing cluster 1694 includes multiple instances of graphics multiprocessor 1634, and the graphics multiprocessors 1634 may share common instructions and data, which may be stored in L1 cache 1648.

[0147] In at least one embodiment, each processing cluster 1694 may include an MMU 1645 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 1645 may reside in memory interface 1618 of FIG. 16 . In at least one embodiment, MMU 1645 includes a set of page table entries (“PTEs”) used to map virtual addresses to physical addresses of tiles and optionally cache line indices. In at least one embodiment, MMU 1645 may include an address translation lookaside buffer (“TLB”) or cache, which may reside in graphics multiprocessor 1634, L1 cache 1648, or processing cluster 1694. In at least one embodiment, physical addresses are processed to distribute surface data access locality and enable efficient request interleaving among partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0148] In at least one embodiment, processing cluster 1694 may be configured such that each graphics multiprocessor 1634 is coupled to a texture unit 1636 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 1634 and fetched as needed from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 1634 outputs processed tasks to data crossbar 1640 to provide the processed tasks to another processing cluster 1694 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 1616. In at least one embodiment, a pre-raster operation unit (“pre-ROP”) 1642 is configured to receive data from the graphics multiprocessor 1634 and direct the data to a ROP unit, which may be co-located with a partition unit as described herein (e.g., partition units 1620A-1620N of FIG. 16 ). In at least one embodiment, pre-ROP 1642 may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0149] FIG. 16C illustrates a graphics multiprocessor 1696, according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 1696 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of the processes 400 in FIG. 4. In at least one embodiment, the graphics multiprocessor 1696 is the graphics multiprocessor 1634 of FIG. 16B. In at least one embodiment, the graphics multiprocessor 1696 couples with the pipeline manager 1632 of the processing cluster 1694. In at least one embodiment, the graphics multiprocessor 1696 has an execution pipeline including, but not limited to, an instruction cache 1652, an instruction unit 1654, an address mapping unit 1656, a register file 1658, one or more GPGPU cores 1662, and one or more LSUs 1666. The GPGPU cores 1662 and LSUs 1666 are coupled to cache memory 1672 and shared memory 1670 via a memory and cache interconnect 1668 .

[0150] In at least one embodiment, instruction cache 1652 receives a stream of instructions to execute from pipeline manager 1632. In at least one embodiment, instructions are cached in instruction cache 1652 and dispatched for execution by instruction unit 1654. In at least one embodiment, instruction unit 1654 can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group assigned to a different execution unit within GPGPU core 1662. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying addresses in the unified address space. In at least one embodiment, address mapping unit 1656 can be used to translate addresses in the unified address space into individual memory addresses that can be accessed by LSU 1666.

[0151] In at least one embodiment, register file 1658 provides a set of registers to the functional units of graphics multiprocessor 1696. In at least one embodiment, register file 1658 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores 1662, LSUs 1666) of graphics multiprocessor 1696. In at least one embodiment, register file 1658 is divided among each of the functional units such that each functional unit is allocated a dedicated portion of register file 1658. In at least one embodiment, register file 1658 is divided among different thread groups being executed by graphics multiprocessor 1696.

[0152] In at least one embodiment, GPGPU cores 1662 may each include an FPU and / or integer ALU used to execute instructions for graphics multiprocessor 1696. GPGPU cores 1662 may be of similar or different architectures. In at least one embodiment, a first portion of GPGPU core 1662 includes a single-precision FPU and integer ALU, and a second portion of GPGPU core 1662 includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or may enable variable-precision floating-point arithmetic. In at least one embodiment, graphics multiprocessor 1696 may additionally include one or more fixed-function or special-function units for performing specific functions, such as rectangle copy operations or pixel blending operations. In at least one embodiment, one or more of GPGPU cores 1662 may also include fixed or special-function logic.

[0153] In at least one embodiment, GPGPU core 1662 includes SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment, GPGPU core 1662 physically executes SIMD4, SIMD8, and SIMD16 instructions and logically executes SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU core 1662 may be generated at compile time by a shader compiler or automatically generated when executing a program written and compiled for a single program multiple data (“SPMD”) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logical unit.

[0154] In at least one embodiment, memory and cache interconnect 1668 is an interconnect network connecting each functional unit of graphics multiprocessor 1696 to register file 1658 and shared memory 1670. In at least one embodiment, memory and cache interconnect 1668 is a crossbar interconnect that allows LSU 1666 to implement load and store operations between shared memory 1670 and register file 1658. In at least one embodiment, register file 1658 can operate at the same frequency as GPGPU cores 1662, and therefore data transfers between GPGPU cores 1662 and register file 1658 are very low latency. In at least one embodiment, shared memory 1670 can be used to enable communication between threads executing on functional units within graphics multiprocessor 1696. In at least one embodiment, cache memory 1672 can be used as a data cache, for example, to cache texture data communicated between functional units and texture unit 1636. In at least one embodiment, shared memory 1670 can also be used as a managed program cache. In at least one embodiment, threads executing on GPGPU cores 1662 can programmatically store data in the shared memory in addition to the automatically cached data stored in cache memory 1672.

[0155] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated in the same package or chip as the cores and communicatively coupled to the cores via a processor bus / interconnect internal to the package or chip. In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core may allocate work to the GPU in the form of a sequence of commands / instructions contained in a WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0156] FIG. 17 illustrates a graphics processor 1700 according to at least one embodiment. In at least one embodiment, the graphics processor 1700 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of the processes 400 in FIG. 4 (e.g., the graphics processor 1700 may be a GPU 116). In at least one embodiment, the graphics processor 1700 includes a ring interconnect 1702, a pipeline front end 1704, a media engine 1737, and graphics cores 1780A-1780N. In at least one embodiment, the ring interconnect 1702 couples the graphics processor 1700 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 1700 is one of many processors incorporated within a multi-core processing system.

[0157] In at least one embodiment, graphics processor 1700 receives batches of commands via ring interconnect 1702. In at least one embodiment, the incoming commands are interpreted by command streamer 1703 in pipeline front end 1704. In at least one embodiment, graphics processor 1700 includes scalable execution logic for performing 3D geometry processing and media processing via one or more graphics cores 1780A-1780N. In at least one embodiment, for 3D geometry processing commands, command streamer 1703 supplies the commands to geometry pipeline 1736. In at least one embodiment, for at least some media processing commands, command streamer 1703 supplies the commands to video front end 1734, which couples to media engine 1737. In at least one embodiment, media engine 1737 includes a video quality engine ("VQE") 1730 for video and image post-processing and a multi-format encode / decode ("MFX") engine 1733 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, geometry pipeline 1736 and media engine 1737 each spawn execution threads for thread execution resources provided by at least one graphics core 1780A.

[0158] In at least one embodiment, graphics processor 1700 includes scalable thread execution resources characterized by modular graphics cores 1780A-1780N (sometimes referred to as core slices), each having multiple sub-cores 1750A-1750N, 1760A-1760N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 1700 can have any number of graphics cores 1780A-1780N. In at least one embodiment, graphics processor 1700 includes graphics core 1780A having at least a first sub-core 1750A and a second sub-core 1760A. In at least one embodiment, graphics processor 1700 is a low-power processor with a single sub-core (e.g., sub-core 1750A). In at least one embodiment, graphics processor 1700 includes multiple graphics cores 1780A-1780N, each including a first set of sub-cores 1750A-1750N and a second set of sub-cores 1760A-1760N. In at least one embodiment, each sub-core in the first sub-cores 1750A-1750N includes at least a first set of execution units ("EUs") 1752A-1752N and media / texture samplers 1754A-1754N. In at least one embodiment, each sub-core in the second sub-cores 1760A-1760N includes at least a second set of execution units 1762A-1762N and samplers 1764A-1764N. In at least one embodiment, each sub-core 1750A-1750N, 1760A-1760N shares a set of shared resources 1770A-1770N. In at least one embodiment, the shared resources 1770 include shared cache memory and pixel operating logic.

[0159] FIG. 18 illustrates a processor 1800 according to at least one embodiment. In at least one embodiment, the processor 1800 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of the processes 400 in FIG. 4 . In at least one embodiment, the processor 1800 may include logic circuitry for performing instructions. In at least one embodiment, the processor 1800 may perform instructions including, but not limited to, x86 instructions, AMR instructions, special instructions for ASICs, etc. In at least one embodiment, the processor 1810 may include registers for storing packed data, such as 64-bit wide MMX registers in a microprocessor enabled with MMX™ technology from Intel Corporation of Santa Clara, California. In at least one embodiment, the MMX registers, available in both integer and floating-point formats, may operate on packed data elements with SIMD and streaming SIMD extension ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (collectively referred to as "SSEx") technologies may hold such packed data operands. In at least one embodiment, processor 1810 may execute instructions to accelerate CUDA programs.

[0160] In at least one embodiment, processor 1800 includes an in-order front end (“front end”) 1801 for fetching instructions to be executed and preparing instructions to be used later in the processor pipeline. In at least one embodiment, front end 1801 may include several units. In at least one embodiment, an instruction prefetcher 1826 fetches instructions from memory and feeds the instructions to instruction decoder 1828, which decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 1828 decodes received instructions into one or more operations called “microinstructions” or “micro-operations” (also called “micro-ops” or “uops”) for execution. In at least one embodiment, instruction decoder 1828 parses instructions into opcodes and corresponding data and control fields that can be used by the microarchitecture to perform the operations. In at least one embodiment, trace cache 1830 may assemble decoded uops into program-order sequences, or traces, for execution in uop queue 1834. In at least one embodiment, when trace cache 1830 encounters a complex instruction, microcode ROM 1832 provides the uops necessary to complete the operation.

[0161] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 1828 may access the microcode ROM 1832 to implement the instruction. In at least one embodiment, an instruction may be decoded into a fewer number of micro-ops for processing in the instruction decoder 1828. In at least one embodiment, an instruction may be stored in the microcode ROM 1832 if several micro-ops are required to accomplish the operation. In at least one embodiment, the trace cache 1830 references an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer to read the microcode sequence from to complete one or more instructions from the microcode ROM 1832. In at least one embodiment, after the microcode ROM 1832 finishes sequencing micro-ops for an instruction, the machine front end 1801 may resume fetching micro-ops from the trace cache 1830.

[0162] In at least one embodiment, an out-of-order execution engine (“out-of-order engine”) 1803 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has several buffers to smooth the flow of instructions and reorder them to optimize performance as they move down the pipeline and are scheduled for execution. The out-of-order execution engine 1803 includes, but is not limited to, an allocator / register renamer 1840, a memory uop queue 1842, an integer / floating point uop queue 1844, a memory scheduler 1846, a fast scheduler 1802, a slow / general purpose floating point scheduler (“slow / general purpose FP scheduler”) 1804, and a simple floating point scheduler (“simple FP scheduler”) 1806. In at least one embodiment, the fast scheduler 1802, the slow / general purpose floating point scheduler 1804, and the simple floating point scheduler 1806 are also collectively referred to herein as "uop schedulers 1802, 1804, 1806." The allocator / register renamer 1840 allocates machine buffers and resources required by each uop to execute. In at least one embodiment, the allocator / register renamer 1840 renames logical registers upon entry into the register file. In at least one embodiment, allocator / register renamer 1840 also allocates an entry for each uop in one of two uop queues: memory uop queue 1842 for memory operations and integer / floating point uop queue 1844 for non-memory operations, before memory scheduler 1846 and uop schedulers 1802, 1804, 1806. In at least one embodiment, uop schedulers 1802, 1804, 1806 determine when uops are ready to execute based on the readiness of their dependent input register operand sources and the availability of execution resources required by the uops to complete their operations.In at least one embodiment, the fast scheduler 1802 of at least one embodiment may schedule every half of a main clock cycle, and the slow / general purpose floating point scheduler 1804 and simple floating point scheduler 1806 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 1802, 1804, 1806 arbitrate for dispatch ports to schedule uops for execution.

[0163] In at least one embodiment, execution block 1811 includes, but is not limited to, integer register file / bypass network 1808, floating point register file / bypass network (“FP register file / bypass network”) 1810, address generation units (“AGUs”) 1812 and 1814, fast ALUs 1816 and 1818, slow ALU 1820, floating point ALU (“FP”) 1822, and floating point move unit (“FP move”) 1824. In at least one embodiment, integer register file / bypass network 1808 and floating point register file / bypass network 1810 are also referred to herein as “register files 1808, 1810.” In at least one embodiment, AGUs 1812 and 1814, fast ALUs 1816 and 1818, slow ALU 1820, floating-point ALU 1822, and floating-point move unit 1824 are also referred to herein as "execution units 1812, 1814, 1816, 1818, 1820, 1822, and 1824." In at least one embodiment, an execution block may include any number and type of register files, bypass networks, address generation units, and execution units (including, but not limited to, zero), in any combination.

[0164] In at least one embodiment, register files 1808, 1810 may be located between uop schedulers 1802, 1804, 1806 and execution units 1812, 1814, 1816, 1818, 1820, 1822, and 1824. In at least one embodiment, integer register file / bypass network 1808 performs integer operations. In at least one embodiment, floating point register file / bypass network 1810 performs floating point operations. In at least one embodiment, each of register files 1808, 1810 may include, but is not limited to, a bypass network that may bypass or forward recently completed results that have not yet been written to the register file to new dependent uops. In at least one embodiment, register files 1808, 1810 may communicate data with each other. In at least one embodiment, integer register file / bypass network 1808 may include, but is not limited to, two separate register files: one register file for lower 32-bit data and a second register file for higher 32-bit data. In at least one embodiment, floating-point instructions typically have operands that are 64 to 128 bits wide, so floating-point register file / bypass network 1810 may include, but is not limited to, 128-bit wide entries.

[0165] In at least one embodiment, execution units 1812, 1814, 1816, 1818, 1820, 1822, and 1824 may execute instructions. In at least one embodiment, register files 1808 and 1810 store integer and floating-point data operand values ​​that microinstructions need to execute. In at least one embodiment, processor 1800 may include, but is not limited to, any number and combination of execution units 1812, 1814, 1816, 1818, 1820, 1822, and 1824. In at least one embodiment, floating-point ALU 1822 and floating-point move unit 1824 may perform floating-point, MMX, SIMD, AVX, and SSE, or other operations. In at least one embodiment, the floating-point ALU 1822 may include a 64-bit floating-point divider for performing, but not limited to, division, square root, and remainder micro-ops. In at least one embodiment, instructions involving floating-point values ​​may be handled by floating-point hardware. In at least one embodiment, ALU operations may be passed to the fast ALUs 1816, 1818. In at least one embodiment, the fast ALUs 1816, 1818 may perform high-speed operations with an effective latency of half a clock cycle. In at least one embodiment, the slow ALU 1820 may include integer execution hardware for long-latency type operations such as, but not limited to, multipliers, shifts, flag logic, and branching, so that most complex integer operations proceed to the slow ALU 1820. In at least one embodiment, memory load / store operations may be performed by the AGUs 1812, 1814. In at least one embodiment, fast ALU 1816, fast ALU 1818, and slow ALU 1820 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 1816, fast ALU 1818, and slow ALU 1820 may be implemented to support various data bit sizes, including 16, 32, 128, 256, etc. In at least one embodiment, floating-point ALU 1822 and floating-point move unit 1824 may be implemented to support various operands having various bit widths.In at least one embodiment, floating-point ALU 1822 and floating-point move unit 1824 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0166] In at least one embodiment, the uop schedulers 1802, 1804, 1806 dispatch dependent operations before the parent load finishes executing. In at least one embodiment, because uops may be speculatively scheduled and executed in the processor 1800, the processor 1800 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in progress in the pipeline past the scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use the incorrect data. In at least one embodiment, the dependent operations may need to be replayed, and the independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0167] In at least one embodiment, the term “register” may refer to an on-board processor storage location that may be used as part of an instruction to identify an operand. In at least one embodiment, a register may be available externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuit elements within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, or a combination of dedicated and dynamically allocated physical registers. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0168] FIG. 19 illustrates a processor 1900 according to at least one embodiment. In at least one embodiment, the processor 1900 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of the processes 400 in FIG. 4. In at least one embodiment, the processor 1900 includes, but is not limited to, one or more processor cores (“cores”) 1902A-1902N, an integrated memory controller 1914, and an integrated graphics processor 1908. In at least one embodiment, the processor 1900 may include additional cores, up to an additional processor core 1902N, represented by a dashed box. In at least one embodiment, each of the processor cores 1902A-1902N includes one or more internal cache units 1904A-1904N. In at least one embodiment, each processor core also has access to one or more shared cache units 1906.

[0169] In at least one embodiment, the internal cache units 1904A-1904N and the shared cache unit 1906 represent a cache memory hierarchy within the processor 1900. In at least one embodiment, the cache memory units 1904A-1904N may include at least one level of instruction and data cache within each processor core, and one or more levels of shared mid-level cache, such as L2, L3, level 4 (“L4”), or other levels of cache, where the highest level of cache before external memory is classified as LLC. In at least one embodiment, cache coherency logic maintains coherency between the various cache units 1906 and 1904A-1904N.

[0170] In at least one embodiment, processor 1900 may also include a set of one or more bus controller units 1916 and a system agent core 1910. In at least one embodiment, one or more bus controller units 1916 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, system agent core 1910 provides management functionality for various processor components. In at least one embodiment, system agent core 1910 includes one or more integrated memory controllers 1914 for managing access to various external memory devices (not shown).

[0171] In at least one embodiment, one or more of the processor cores 1902A-1902N include support for simultaneous multithreading. In at least one embodiment, the system agent core 1910 includes components for coordinating and operating the processor cores 1902A-1902N during multithreaded processing. In at least one embodiment, the system agent core 1910 may additionally include a power control unit (“PCU”), which includes logic and components for adjusting the power state of one or more of the processor cores 1902A-1902N and the graphics processor 1908.

[0172] In at least one embodiment, processor 1900 additionally includes a graphics processor 1908 for performing graphics processing operations. In at least one embodiment, graphics processor 1908 couples to a system agent core 1910 that includes a shared cache unit 1906 and one or more integrated memory controllers 1914. In at least one embodiment, system agent core 1910 also includes a display controller 1911 for driving graphics processor output to one or more coupled displays. In at least one embodiment, display controller 1911 may also be a separate module coupled to graphics processor 1908 via at least one interconnect or may be incorporated within graphics processor 1908.

[0173] In at least one embodiment, a ring-based interconnect unit 1912 is used to couple the internal components of processor 1900. In at least one embodiment, alternative interconnect units such as point-to-point interconnects, switched interconnects, or other techniques may be used. In at least one embodiment, graphics processor 1908 couples to ring interconnect 1912 via I / O link 1913.

[0174] In at least one embodiment, I / O link 1913 represents at least one of several types of I / O interconnect, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 1918, such as an eDRAM module. In at least one embodiment, each of processor cores 1902A-1902N and graphics processor 1908 use embedded memory module 1918 as a shared LLC.

[0175] In at least one embodiment, processor cores 1902A-1902N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, processor cores 1902A-1902N are heterogeneous in terms of ISA, where one or more of processor cores 1902A-1902N execute a common instruction set and one or more other of processor cores 1902A-1902N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, processor cores 1902A-1902N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are combined with one or more cores with lower power consumption. In at least one embodiment, processor 1900 may be implemented on one or more chips or as an SoC integrated circuit.

[0176] FIG. 20 illustrates a graphics processor core 2000 according to at least one described embodiment. In at least one embodiment, the graphics processor core 2000 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of the processes 400 in FIG. 4 ; for example, the graphics processor core 2000 may be part of the GPU 116. In at least one embodiment, the graphics processor core 2000 is included within a graphics core array. In at least one embodiment, the graphics processor core 2000, sometimes referred to as a core slice, may be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2000 is an example of a graphics core slice; the graphics processors described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2000 may include a fixed function block 2030 coupled with multiple sub-cores 2001A-2001F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed-function logic.

[0177] In at least one embodiment, fixed function block 2030 includes a geometry / fixed function pipeline 2036 that may be shared by all sub-cores in graphics processor 2000, e.g., in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry / fixed function pipeline 2036 includes a 3D fixed function pipeline, a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0178] In at least one embodiment, the fixed function block 2030 also includes a graphics SoC interface 2037, a graphics microcontroller 2038, and a media pipeline 2039. The graphics SoC interface 2037 provides an interface between the graphics core 2000 and other processor cores within the SoC integrated circuit. In at least one embodiment, the graphics microcontroller 2038 is a programmable sub-processor that is configurable to manage various functions of the graphics processor 2000, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 2039 includes logic for facilitating decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 2039 implements media operations via requests to compute logic or sampling logic within the sub-cores 2001-2001F.

[0179] In at least one embodiment, SoC interface 2037 enables graphics core 2000 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or on-package DRAM. In at least one embodiment, SoC interface 2037 can also enable communication with fixed-function devices within the SoC, such as a camera imaging pipeline, and enable and / or implement global memory atomics that may be shared between graphics core 2000 and a CPU within the SoC. In at least one embodiment, SoC interface 2037 can also implement power management controls for graphics core 2000 and enable an interface between the graphics core 2000 clock domain and other clock domains within the SoC. In at least one embodiment, SoC interface 2037 enables receipt of command buffers from a command streamer and global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores in the graphics processor. In at least one embodiment, the commands and instructions may be dispatched to a media pipeline 2039 when a media operation is to be performed, or to a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline 2036, geometry and fixed function pipeline 2014) when a graphics processing operation is to be performed.

[0180] In at least one embodiment, graphics microcontroller 2038 can be configured to perform various scheduling and management tasks for graphics core 2000. In at least one embodiment, graphics microcontroller 2038 can perform graphics and / or compute workload scheduling for various graphics parallel engines in execution unit (EU) arrays 2002A-2002F, 2004A-2004F within sub-cores 2001A-2001F. In at least one embodiment, host software running on a CPU core of an SoC including graphics core 2000 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to a command streamer, preempting existing workloads running on the engines, monitoring the progress of the workload, and notifying host software when the workload is complete. In at least one embodiment, the graphics microcontroller 2038 can also facilitate low power or idle states for the graphics core 2000, providing the graphics core 2000 with the ability to save and restore registers within the graphics core 2000 across low power state transitions independent of the operating system and / or graphics driver software on the system.

[0181] In at least one embodiment, graphics core 2000 may have up to N modular sub-cores, more or fewer than the illustrated sub-cores 2001A-2001F. For each set of N sub-cores, in at least one embodiment, graphics core 2000 may also include shared function logic 2010, shared and / or cache memory 2012, geometry / fixed function pipeline 2014, and additional fixed function logic 2016 for accelerating various graphics and compute processing operations. In at least one embodiment, shared function logic 2010 may include logic units (e.g., sampler, math, and / or inter-thread communication logic) that may be shared by each of the N sub-cores in graphics core 2000. Shared and / or cache memory 2012 may be an LLC for the N sub-cores 2001A-2001F in graphics core 2000 and may also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2014 may be included in place of geometry / fixed function pipeline 2036 in fixed function block 2030 and may include the same or similar logical units.

[0182] In at least one embodiment, graphics core 2000 includes additional fixed function logic 2016, which may include various fixed-function acceleration logic for use by graphics core 2000. In at least one embodiment, additional fixed function logic 2016 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines: a full geometry pipeline in geometry / fixed function pipeline 2016, 2036, and a cull pipeline, where the cull pipeline is an additional geometry pipeline that may be included in additional fixed function logic 2016. In at least one embodiment, the cull pipeline is a scaled-down version of the full geometry pipeline. In at least one embodiment, the full pipeline and the cull pipeline can run different instances of an application, each instance having a separate context. In at least one embodiment, position-only shading can hide long cull runs of truncated triangles, which allows shading to complete faster in some instances. For example, in at least one embodiment, the cull pipeline fetches and shades vertex position attributes without rasterizing and rendering pixels to the frame buffer, allowing the cull pipeline logic in the additional fixed-function logic 2016 to execute position shaders in parallel with the main application and produce critical results faster than the full pipeline overall. In at least one embodiment, the cull pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether they are culled. In at least one embodiment, the full pipeline (which may be referred to in this instance as the replay pipeline) can consume the visibility information and shade only visible triangles, skipping over culled triangles, which are ultimately passed to the rasterization phase.

[0183] In at least one embodiment, the additional fixed function logic 2016 may also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, to accelerate CUDA programs.

[0184] In at least one embodiment, each graphics sub-core 2001A-2001F includes a set of execution resources that can be used to perform graphics operations, media operations, and compute operations in response to requests by a graphics pipeline, a media pipeline, or a shader program. In at least one embodiment, the graphics sub-cores 2001A-2001F include a plurality of EU arrays 2002A-2002F, 2004A-2004F, thread dispatch and inter-thread communication (“TD / IC”) logic 2003A-2003F, 3D (e.g., texture) samplers 2005A-2005F, media samplers 2006A-2006F, shader processors 2007A-2007F, and shared local memory (“SLM”) 2008A-2008F. The EU arrays 2002A-2002F, 2004A-2004F each include multiple execution units that are GPGPUs capable of performing floating-point and integer / fixed-point logic operations in service of graphics, media, or compute operations, including graphics, media, or compute shader programs. In at least one embodiment, the TD / IC logic 2003A-2003F performs local thread dispatch and thread control operations for the execution units within a sub-core and facilitates communication between threads executing on the execution units of a sub-core. In at least one embodiment, the 3D samplers 2005A-2005F can read textures or other 3D graphics-related data into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sample state and texture format associated with a given texture. In at least one embodiment, media samplers 2006A-2006F can perform similar read operations based on the type and format associated with the media data.In at least one embodiment, each graphics sub-core 2001A-2001F can alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each of the sub-cores 2001A-2001F can utilize shared local memory 2008A-2008F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.

[0185] FIG. 21 illustrates a parallel processing unit (“PPU”) 2100 according to at least one embodiment. In at least one embodiment, the PPU 2100 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of the processes 400 in FIG. 4. In at least one embodiment, the PPU 2100 comprises machine-readable code that, when executed by the PPU 2100, causes the PPU 2100 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 2100 is a multi-threaded processor, which is implemented on one or more integrated circuit devices and utilizes multi-threading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) in parallel on multiple threads. In at least one embodiment, a thread refers to a thread of execution, which is an instantiation of a set of instructions configured to be executed by the PPU 2100. In at least one embodiment, PPU2100 is a GPU configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device, such as an LCD device. In at least one embodiment, PPU2100 is utilized to perform computations such as linear algebra operations and machine learning operations. FIG. 21 depicts an exemplary parallel processor for illustrative purposes only and should be construed as a non-limiting example of a processor architecture that may be implemented in at least one embodiment.

[0186] In at least one embodiment, one or more PPUs 2100 are configured to accelerate high performance computing ("HPC"), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2100 are configured to accelerate CUDA programs. In at least one embodiment, the PPUs 2100 include, but are not limited to, an I / O unit 2106, a front end unit 2110, a scheduler unit 2112, a work distribution unit 2114, a hub 2116, a crossbar ("Xbar") 2120, one or more general processing clusters ("GPC") 2118, and one or more partition units ("memory partition units") 2122. In at least one embodiment, the PPU 2100 is connected to a host processor or other PPUs 2100 via one or more high-speed GPU interconnects (“GPU interconnects”) 2108. In at least one embodiment, the PPU 2100 is connected to a host processor or other peripheral devices via a system bus or interconnect 2102. In at least one embodiment, the PPU 2100 is connected to local memory comprising one or more memory devices (“memory”) 2104. In at least one embodiment, the memory devices 2104 include, but are not limited to, one or more dynamic random access memory (DRAM) devices. In at least one embodiment, the one or more DRAM devices are configured and / or configurable as a high-bandwidth memory (“HBM”) subsystem with multiple DRAM dies stacked within each device.

[0187] In at least one embodiment, the high-speed GPU interconnect 2108 may refer to a wire-based, multi-lane communication link used by the system to scale and include one or more PPUs 2100 in combination with one or more CPUs, supporting cache coherence between the PPUs 2100 and the CPUs and CPU mastering. In at least one embodiment, data and / or commands are transmitted by the high-speed GPU interconnect 2108 through the hub 2116 to and from other units of the PPU 2100, such as one or more copy engines, a video encoder, a video decoder, a power management unit, and other components that may not be explicitly shown in FIG. 21 .

[0188] In at least one embodiment, I / O unit 2106 is configured to receive and send communications (e.g., commands, data) from a host processor (not shown in FIG. 21 ) via system bus 2102. In at least one embodiment, I / O unit 2106 communicates with the host processor directly via system bus 2102 or through one or more intermediary devices, such as a memory bridge. In at least one embodiment, I / O unit 2106 may communicate with one or more other processors, such as one or more of PPUs 2100, via system bus 2102. In at least one embodiment, I / O unit 2106 implements a PCIe interface for communication via the PCIe bus. In at least one embodiment, I / O unit 2106 implements an interface for communicating with external devices.

[0189] In at least one embodiment, I / O unit 2106 decodes packets received via system bus 2102. In at least one embodiment, at least some of the packets represent commands configured to cause PPU 2100 to perform various operations. In at least one embodiment, I / O unit 2106 transmits the decoded commands to various other units of PPU 2100 specified by the commands. In at least one embodiment, the commands are transmitted to front end unit 2110 and / or to hub 2116 or other units of PPU 2100, such as one or more copy engines, video encoders, video decoders, or power management units (not explicitly shown in FIG. 21 ). In at least one embodiment, I / O unit 2106 is configured to route communications to and between various logical units of PPU 2100.

[0190] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPU 2100 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory that is accessible (e.g., readable / writable) by both the host processor and the PPU 2100, and the host interface unit may be configured to access the buffer in system memory connected to the system bus 2102 via memory requests sent by the I / O unit 2106 over the system bus 2102. In at least one embodiment, the host processor writes the command stream to the buffer and then sends a pointer to the start of the command stream to the PPU 2100, whereupon the front end unit 2110 receives the pointer to one or more command streams and manages the one or more command streams, reading commands from the command streams and forwarding the commands to various units of the PPU 2100.

[0191] In at least one embodiment, the front end unit 2110 is coupled to a scheduler unit 2112 that configures the various GPCs 2118 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2112 is configured to track state information related to the various tasks managed by the scheduler unit 2112, where the state information may indicate which of the GPCs 2118 the task is assigned to, whether the task is active or inactive, the priority level associated with the task, etc. In at least one embodiment, the scheduler unit 2112 manages the execution of multiple tasks on one or more of the GPCs 2118.

[0192] In at least one embodiment, the scheduler unit 2112 is coupled to a work distribution unit 2114 configured to dispatch tasks for execution on the GPCs 2118. In at least one embodiment, the work distribution unit 2114 tracks the number of scheduled tasks received from the scheduler unit 2112, and the work distribution unit 2114 manages a pending task pool and an active task pool for each of the GPCs 2118. In at least one embodiment, the pending task pool may comprise a number of slots (e.g., 32 slots) containing tasks assigned to be processed by a particular GPC 2118, and the active task pool may comprise a number of slots (e.g., 4 slots) for tasks being actively processed by the GPC 2118, such that when one of the GPCs 2118 completes execution of a task, the task is removed from the active task pool for the GPC 2118 and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC 2118. In at least one embodiment, when an active task is idle on the GPC2118, such as while waiting for a data dependency to be resolved, the active task is evicted from the GPC2118 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on the GPC2118.

[0193] In at least one embodiment, work distribution unit 2114 communicates with one or more GPCs 2118 via X-bar 2120. In at least one embodiment, X-bar 2120 is an interconnection network coupling many units of PPU 2100 to other units of PPU 2100 and may be configured to couple work distribution unit 2114 to a particular GPC 2118. In at least one embodiment, one or more other units of PPU 2100 may also be connected to X-bar 2120 via hub 2116.

[0194] In at least one embodiment, tasks are managed by scheduler unit 2112 and dispatched by work distribution unit 2114 to one of the GPCs 2118. The GPC 2118 is configured to process the task and generate a result. In at least one embodiment, the result may be consumed by other tasks within the GPC 2118, routed to a different GPC 2118 via Xbar 2120, or stored in memory 2104. In at least one embodiment, the result may be written to memory 2104 via partition unit 2122, which implements a memory interface for reading and writing data to / from memory 2104. In at least one embodiment, the result may be sent to another PPU 2104 or a CPU via high-speed GPU interconnect 2108. In at least one embodiment, the PPU 2100 includes U partition units 2122 equal to, but not limited to, the number of distinct individual memory devices 2104 coupled to the PPU 2100 .

[0195] In at least one embodiment, the host processor executes a driver kernel, which implements an application programming interface ("API") that allows one or more applications executing on the host processor to schedule operations for execution on the PPU 2100. In at least one embodiment, multiple compute applications are executed concurrently by the PPU 2100, which provides isolation, quality of service ("QoS"), and independent address spaces for the multiple compute applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU 2100, and the driver kernel outputs the tasks to one or more streams that are processed by the PPU 2100. In at least one embodiment, each task comprises one or more groups of participating threads, which may be referred to as a warp. In at least one embodiment, a warp comprises multiple participating threads (e.g., 32 threads) that may be executed in parallel. In at least one embodiment, cooperating threads can refer to multiple threads that contain instructions to perform a task and exchange data through a shared memory.

[0196] FIG. 22 illustrates a GPC 2200, according to at least one embodiment. In at least one embodiment, the GPC 2200 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of the processes 400 in FIG. 4. In at least one embodiment, the GPC 2200 is the GPC 2118 of FIG. 21. In at least one embodiment, each GPC 2200 includes several hardware units for processing tasks, including, but not limited to, a pipeline manager 2202, a pre-raster operation unit (“PROP”) 2204, a raster engine 2208, a work distribution crossbar (“WDX”) 2216, an MMU 2218, one or more data processing clusters (“DPCs”) 2206, and any suitable combination of parts.

[0197] In at least one embodiment, the operation of the GPC 2200 is controlled by a pipeline manager 2202. In at least one embodiment, the pipeline manager 2202 manages the configuration of one or more DPCs 2206 to process tasks allocated to the GPC 2200. In at least one embodiment, the pipeline manager 2202 configures at least one of the one or more DPCs 2206 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, the DPC 2206 is configured to execute vertex shader programs on a programmable streaming multiprocessor (“SM”) 2214. In at least one embodiment, pipeline manager 2202 is configured to route packets received from the work distribution unit to the appropriate logical unit within GPC 2200; in at least one embodiment, some packets may be routed to a fixed function hardware unit in PROP 2204 and / or raster engine 2208, while other packets may be routed to DPC 2206 for processing by primitive engine 2212 or SM 2214. In at least one embodiment, pipeline manager 2202 configures at least one of DPC 2206 to implement a computing pipeline. In at least one embodiment, pipeline manager 2202 configures at least one of DPC 2206 to execute at least a portion of a CUDA program.

[0198] In at least one embodiment, the PROP unit 2204 is configured to route data generated by the raster engine 2208 and the DPC 2206 to a raster operation ("ROP") unit in a partition unit, such as the memory partition unit 2122 described in more detail above in conjunction with FIG. 21. In at least one embodiment, the PROP unit 2204 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, the raster engine 2208 includes several fixed-function hardware units configured to perform various raster operations, including, but not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile coalescing engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices. The plane equations are sent to a coarse raster engine to generate coverage information for the primitives (e.g., x, y coverage masks for tiles). The output of the coarse raster engine is sent to a culling engine to cull fragments associated with primitives that fail a z-test and to a clipping engine to clip fragments that are outside the view frustum. In at least one embodiment, fragments that pass clipping and culling are passed to a fine raster engine to generate attributes for the pixel fragments based on the plane equations generated by the setup engine. In at least one embodiment, the output of the raster engine 2208 includes fragments to be processed by any suitable entity, such as by a fragment shader implemented within the DPC 2206.

[0199] In at least one embodiment, each DPC 2206 included in GPC 2200 includes, but is not limited to, an M-Pipe Controller (“MPC”) 2210, a Primitive Engine 2212, one or more SMs 2214, and any suitable combination thereof. In at least one embodiment, MPC 2210 controls the operation of DPC 2206, routing packets received from pipeline manager 2202 to the appropriate units in DPC 2206. In at least one embodiment, packets related to vertices are routed to primitive engine 2212, which is configured to fetch vertex attributes associated with the vertices from memory; in contrast, packets related to shader programs may be sent to SM 2214.

[0200] In at least one embodiment, SM2214 includes a programmable streaming processor configured to process tasks represented by, but not limited to, several threads. In at least one embodiment, SM2214 is multithreaded and configured to simultaneously execute multiple threads (e.g., 32 threads) from a particular group of threads and implements a SIMD architecture, where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same set of instructions. In at least one embodiment, all threads in a group of threads execute the same instructions. In at least one embodiment, SM2214 implements a SIMT architecture, where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but individual threads in a group of threads are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp to enable concurrent processing between warps and serial execution within a warp when threads within a warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread to allow equal concurrency among all threads, within and between warps. In at least one embodiment, execution state is maintained for each individual thread, so that threads executing the same instructions can converge and run in parallel for better efficiency. At least one embodiment of SM2214 is described in further detail in conjunction with FIG. 23.

[0201] In at least one embodiment, MMU 2218 provides an interface between GPC 2200 and a memory partition unit (e.g., partition unit 2122 of FIG. 21), and MMU 2218 provides virtual to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, MMU 2218 provides one or more translation lookaside buffers (TLBs) for performing translations from virtual addresses to physical addresses in memory.

[0202] FIG. 23 illustrates a streaming multiprocessor (“SM”) 2300, according to at least one embodiment. In at least one embodiment, the SM 2300 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of the processes 400 in FIG. 4. In at least one embodiment, the SM 2300 is the SM 2214 of FIG. 22. In at least one embodiment, the SM 2300 includes, but is not limited to, an instruction cache 2302, one or more scheduler units 2304, a register file 2308, one or more processing cores (“cores”) 2310, one or more special function units (“SFUs”) 2312, one or more LSUs 2314, an interconnect network 2316, a shared memory / L1 cache 2318, and any suitable combination thereof. In at least one embodiment, the work distribution unit dispatches tasks for execution on the GPCs of the parallel processing unit (PPU), with each task being assigned to a particular data processing cluster (DPC) within the GPC, and if the task is associated with a shader program, the task is assigned to one of the SMs 2300. In at least one embodiment, the scheduler unit 2304 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to the SMs 2300. In at least one embodiment, the scheduler unit 2304 schedules the thread blocks for execution as warps of parallel threads, with each thread block being assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, scheduler unit 2304 manages multiple different thread blocks, allocates warps to the different thread blocks, and then dispatches instructions from multiple different interlocking groups to various functional units (e.g., processing cores 2310, SFUs 2312, and LSUs 2314) during each clock cycle.

[0203] In at least one embodiment, a "coordination group" may refer to a programming model for organizing groups of communicating threads, where the programming model allows developers to express the granularity at which threads are communicating, enabling richer and more efficient expression of parallel decompositions. In at least one embodiment, a coordination invocation API supports synchronization between thread blocks for the execution of parallel algorithms. In at least one embodiment, traditional programming model APIs provide a single simple construct for synchronizing coordinated threads, i.e., a barrier across all threads in a thread block (e.g., the syncthreads() function). However, in at least one embodiment, a programmer may define groups of threads at a granularity finer than a thread block and synchronize within the defined group, enabling higher performance, design flexibility, and software reuse in the form of a collective group-wide functional interface. In at least one embodiment, coordination groups allow programmers to explicitly define groups of threads at sub-block and multi-block granularity and perform collective operations, such as synchronization, on threads in the coordination group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing libraries and utility functions to safely synchronize within their local context without having to make assumptions about convergence. In at least one embodiment, the interlocking group primitive enables new patterns of interlocking parallelism, including, but not limited to, producer-consumer parallelism, opportunistic parallelism, and global synchronization across a grid of thread blocks.

[0204] In at least one embodiment, the dispatch unit 2306 is configured to send instructions to one or more of the functional units, and the scheduler unit 2304 includes, without limitation, two dispatch units 2306, allowing two different instructions from the same warp to be dispatched during each clock cycle. In at least one embodiment, each scheduler unit 2304 includes a single dispatch unit 2306 or additional dispatch units 2306.

[0205] In at least one embodiment, each SM2300 includes, in at least one embodiment, a register file 2308 that provides a set of registers to the functional units of the SM2300. In at least one embodiment, the register file 2308 is divided among each of the functional units such that each functional unit is allocated a dedicated portion of the register file 2308. In at least one embodiment, the register file 2308 is divided among the different warps being executed by the SM2300, and the register file 2308 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM2300 includes, in at least one embodiment, a plurality of, inclusive of L, processing cores 2310. In at least one embodiment, the SM2300 includes, inclusive of L, a number of individual processing cores 2310 (e.g., 128 or more). In at least one embodiment, each processing core 2310 includes, but is not limited to, fully pipelined single-precision, double-precision, and / or mixed-precision processing units, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, processing core 2310 includes, but is not limited to, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores, and 8 tensor cores.

[0206] In at least one embodiment, the tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing core 2310. In at least one embodiment, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0207] In at least one embodiment, matrix multiplication inputs A and B are 16-bit floating-point matrices, and sum matrices C and D are 16-bit floating-point or 32-bit floating-point matrices. In at least one embodiment, the tensor cores operate on 16-bit floating-point input data with a 32-bit floating-point sum. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations, resulting in a full-precision product, which is then added using 32-bit floating-point addition with other intermediate products for a 4x4x4 matrix multiplication. In at least one embodiment, the tensor cores are used to perform much larger two-dimensional or even higher-dimensional matrix operations that build up from these smaller elements. In at least one embodiment, an API such as the CUDA-C++ API exposes specialized matrix load, matrix multiply-and-add, and matrix store operations to efficiently use the tensor cores from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the warp-level interface assumes a matrix of size 16x16 that spans all 32 threads of a warp.

[0208] In at least one embodiment, each SM2300 includes M SFUs2312 that perform special functions (e.g., but not limited to, attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs2312 include, but are not limited to, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs2312 include, but are not limited to, a texture unit configured to perform texture map filtering operations. In at least one embodiment, the texture unit is configured to load texture maps (e.g., 2D arrays of texels) from memory and sample texture maps to produce sampled texture values ​​for use in shader programs executed by the SM2300. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 2318. In at least one embodiment, the texture unit implements texture operations such as filtering operations using mip maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM2300 includes, but is not limited to, two texture units.

[0209] In at least one embodiment, each SM 2300 includes, but is not limited to, N LSUs 2314 that implement load and store operations between shared memory / L1 cache 2318 and register file 2308. In at least one embodiment, each SM 2300 includes, but is not limited to, an interconnection network 2316 that connects each of the functional units to register file 2308 and connects LSUs 2314 to register file 2308 and shared memory / L1 cache 2318. In at least one embodiment, interconnection network 2316 is a crossbar that can be configured to connect any of the functional units to any of the registers in register file 2308 and connect LSUs 2314 to memory locations in register file 2308 and shared memory / L1 cache 2318.

[0210] In at least one embodiment, shared memory / L1 cache 2318 is an array of on-chip memory that enables data storage and communication between SM2300 and the primitive engines and between threads in SM2300. In at least one embodiment, shared memory / L1 cache 2318 has, but is not limited to, 128 KB of storage capacity and is in the path from SM2300 to the partition unit. In at least one embodiment, shared memory / L1 cache 2318 is used to cache reads and writes. In at least one embodiment, one or more of shared memory / L1 cache 2318, L2 cache, and memory are backing stores.

[0211] In at least one embodiment, combining data cache and shared memory functionality into a single memory block provides improved performance for both types of memory access. In at least one embodiment, the capacity is used as a cache or available for use by programs that do not use shared memory, such as when the shared memory is configured to use half the capacity and texture and load / store operations can use the remaining capacity. In at least one embodiment, the integration within the shared memory / L1 cache 2318 allows the shared memory / L1 cache 2318 to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth, low-latency access to frequently reused data. In at least one embodiment, when configured for general-purpose parallel computation, a simpler configuration may be used compared to graphics processing. In at least one embodiment, the fixed-function GPU is bypassed, creating a much simpler programming model. In at least one embodiment, and in the general-purpose parallel computation configuration, the work distribution unit directly assigns and distributes blocks of threads to the DPCs. In at least one embodiment, blocked threads execute the same program using unique thread IDs in computations to ensure each thread produces unique results, use SM2300 to execute the program and perform computations, use shared memory / L1 cache 2318 to communicate between threads, and use LSU2314 to read and write global memory through shared memory / L1 cache 2318 and memory partition unit 2314. In at least one embodiment, when configured for general-purpose parallel computation, SM2300 writes commands that scheduler unit 2304 can use to launch new work on DPCs.

[0212] In at least one embodiment, the PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smart phone (e.g., a wireless handheld device), a PDA, a digital camera, a vehicle, a head-mounted display, a handheld electronic device, etc. In at least one embodiment, the PPU is embodied on a single semiconductor substrate. In at least one embodiment, the PPU is included in an SoC with one or more other devices, such as additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter ("DAC"), etc.

[0213] In at least one embodiment, the PPU may be included on a graphics card that includes one or more memory devices. In at least one embodiment, the graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In at least one embodiment, the PPU may be an integrated GPU ("iGPU") included in the chipset of the motherboard.

[0214] Software Constructs for General-Purpose Computing The following diagram describes an exemplary software construct for implementing at least one embodiment, but is not limited to this embodiment.

[0215] FIG. 24 illustrates a software stack for a programming platform, according to at least one embodiment. In at least one embodiment, the software stack for the programming platform may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may perform some or all of process 400 in FIG. 4. In at least one embodiment, the programming platform is a platform for leveraging hardware on a computing system to accelerate computational tasks. In at least one embodiment, the programming platform may be accessible to software developers through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, the programming platform may be, but is not limited to, CUDA, Radeon Open Compute Platform (“ROCm”), OpenCL (OpenCL™ is developed by the Khronos group), SYCL, or the Intel One API.

[0216] In at least one embodiment, the programming platform's software stack 2400 provides an execution environment for applications 2401. In at least one embodiment, the applications 2401 may include any computer software capable of being run on the software stack 2400. In at least one embodiment, the applications 2401 may include, but are not limited to, artificial intelligence (“AI”) / machine learning (“ML”) applications, high performance computing (“HPC”) applications, virtual desktop infrastructure (“VDI”), or data center workloads.

[0217] In at least one embodiment, application 2401 and software stack 2400 run on hardware 2407. In at least one embodiment, hardware 2407 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of compute devices supporting a programming platform. In at least one embodiment, such as in the case of CUDA, software stack 2400 may be vendor-specific and compatible only with devices from a particular vendor(s). In at least one embodiment, such as in the case of OpenCL, software stack 2400 may be used with devices from different vendors. In at least one embodiment, hardware 2407 includes a host connected to another device that may be accessed to perform computational tasks via application programming interface (“API”) calls. In at least one embodiment, in contrast to a host in hardware 2407, which may include, but is not limited to, a CPU (but may also include a compute device) and its memory, a device in hardware 2407 may include, but is not limited to, a GPU, FPGA, AI engine, or other compute device (but may also include a CPU) and its memory.

[0218] In at least one embodiment, the programming platform's software stack 2400 includes, but is not limited to, several libraries 2403, a runtime 2405, and a device kernel driver 2406. In at least one embodiment, each of the libraries 2403 may include data and programming code used by a computer program and utilized during software development. In at least one embodiment, the libraries 2403 may include, but are not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 2403 include functionality optimized for execution on one or more types of devices. In at least one embodiment, the libraries 2403 may include, but are not limited to, functionality for performing mathematics, deep learning, and / or other types of operations on the device. In at least one embodiment, the libraries 2403 are associated with corresponding APIs 2402, which may include one or more APIs that expose the functionality implemented in the libraries 2403.

[0219] In at least one embodiment, application 2401 is written as source code that is compiled into executable code, as described in more detail below in conjunction with FIGS. 29-31. In at least one embodiment, the executable code of application 2401 may run, at least in part, on an execution environment provided by software stack 2400. In at least one embodiment, during execution of application 2401, code that needs to run on the device, as opposed to the host, may be reached. In at least one embodiment, in such cases, runtime 2405 may be called to load and launch the requisite code on the device. In at least one embodiment, runtime 2405 may include any technically feasible runtime system capable of supporting the execution of application S01.

[0220] In at least one embodiment, runtime 2405 is implemented as one or more runtime libraries associated with corresponding API(s), shown as API(s) 2404. In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory, as well as transferring data between host and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching functions on the device (sometimes referred to as "kernels" when the functions are global functions callable from the host) and setting attribute values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0221] In at least one embodiment, the runtime library and corresponding API(s) 2404 may be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs may expose a low-level set of functionality for fine-grained control of the device, while another (or any number of) APIs may expose a higher-level set of such functionality. In at least one embodiment, a high-level runtime API may be built on top of the low-level API. In at least one embodiment, one or more of the runtime APIs may be language-specific APIs layered on top of a language-agnostic runtime API.

[0222] In at least one embodiment, device kernel driver 2406 is configured to facilitate communication with the underlying device. In at least one embodiment, device kernel driver 2406 may provide low-level functionality upon which APIs, such as API(s) 2404 and / or other software rely. In at least one embodiment, device kernel driver 2406 may be configured to compile intermediate representation (“IR”) code into binary code at runtime. In at least one embodiment, in the case of CUDA, device kernel driver 2406 may compile non-hardware-specific Parallel Thread Execution (“PTX”) IR code into binary code for a particular target device at runtime (with caching of the compiled binary code), which may also be referred to as “finalizing” the code. In at least one embodiment, doing so may allow the finalized code to run on the target device, which may not have been present when the source code was initially compiled into PTX code. Alternatively, in at least one embodiment, the device source code can be compiled into binary code offline without requiring the device kernel driver 2406 to compile the IR code at runtime.

[0223] Figure 25 illustrates a CUDA implementation of software stack 2400 of Figure 24, according to at least one embodiment. In at least one embodiment, CUDA software stack 2500, upon which application 2501 may be launched, includes CUDA library 2503, CUDA runtime 2505, CUDA driver 2507, and device kernel driver 2508. In at least one embodiment, CUDA software stack 2500 executes on hardware 2509, which may include a GPU that supports CUDA and is developed by NVIDIA Corporation of Santa Clara, California.

[0224] In at least one embodiment, application 2501, CUDA runtime 2505, and device kernel driver 2508 may perform functionality similar to application 2401, runtime 2405, and device kernel driver 2406, respectively, described above in conjunction with FIG. 24. In at least one embodiment, CUDA driver 2507 includes a library (libcuda.so) that implements CUDA driver API 2506. In at least one embodiment, similar to CUDA runtime API 2504 implemented by the CUDA runtime library (cudart), CUDA driver API 2506 may expose functionality for, among other things, but not limited to, memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 2506 differs from the CUDA runtime API 2504 in that the CUDA runtime API 2504 simplifies device code management by providing implicit initialization, context management (similar to processes), and module management (similar to dynamically loaded libraries). In at least one embodiment, in contrast to the high-level CUDA runtime API 2504, the CUDA driver API 2506 is a low-level API that provides more fine-grained control of the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 2506 may expose functionality for context management not exposed by the CUDA runtime API 2504. In at least one embodiment, the CUDA driver API 2506 is also language-independent, e.g., supports OpenCL in addition to the CUDA runtime API 2504. Additionally, in at least one embodiment, the development libraries including the CUDA runtime 2505 may be considered separate from the driver components including the user-mode CUDA driver 2507 and the kernel-mode device driver 2508 (sometimes referred to as the "display" driver).

[0225] In at least one embodiment, CUDA libraries 2503 may include, but are not limited to, mathematics libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries that may be utilized by parallel computing applications, such as application 2501. In at least one embodiment, CUDA libraries 2503 may include, among other things, mathematics libraries, such as the cuBLAS library, which is an implementation of the Basic Linear Algebra Subprograms (“BLAS”) for performing linear algebra operations, the cuFFT library for computing fast Fourier transforms (“FFTs”), and the cuRAND library for generating random numbers. In at least one embodiment, CUDA libraries 2503 may include, among other deep learning libraries, such as the cuDNN library of primitives for deep neural networks and the TensorRT platform for high-performance deep learning inference.

[0226] Figure 26 illustrates a ROCm implementation of software stack 2400 of Figure 24, according to at least one embodiment. In at least one embodiment, ROCm software stack 2600, upon which application 2601 may be launched, includes language runtime 2603, system runtime 2605, thunk 2607, and ROCm kernel driver 2608. In at least one embodiment, ROCm software stack 2600 executes on hardware 2609, which may include a GPU, which supports ROCm and is developed by AMD Corporation of Santa Clara, California.

[0227] In at least one embodiment, application 2601 may perform functionality similar to application 2401 described above in conjunction with FIG. 24. Additionally, in at least one embodiment, language runtime 2603 and system runtime 2605 may perform functionality similar to runtime 2405 described above in conjunction with FIG. 24. In at least one embodiment, language runtime 2603 and system runtime 2605 differ in that system runtime 2605 is a language-agnostic runtime that implements ROCr system runtime API 2604 and utilizes the Heterogeneous System Architecture ("HSA") runtime API. In at least one embodiment, the HSA runtime API is a thin user-mode API that exposes an interface for accessing and interacting with an AMD GPU, including functions for, among other things, memory management, execution control via architected dispatch of the kernel, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, the language runtime 2603, as opposed to the system runtime 2605, is an implementation of a language-specific runtime API 2602 layered on top of the ROCr system runtime API 2604. In at least one embodiment, the language runtime API may include, but is not limited to, the Heterogeneous Compute Interface for Portability ("HIP") language runtime API, the Heterogeneous Compute Compiler ("HCC") language runtime API, or the OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA facilities, and in at least one embodiment, the HIP language runtime API includes functionality similar to the functionality of the CUDA runtime API 2504 described above in conjunction with FIG. 25, such as functionality for memory management, execution control, device management, error handling, and synchronization, among others.

[0228] In at least one embodiment, thunk (ROCt) 2607 is an interface 2606 that can be used to interact with an underlying ROCm driver 2608. In at least one embodiment, ROCm driver 2608 is a ROCk driver that is a combination of an AMDGPU driver and an HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that implements functionality similar to device kernel driver 2406 described above in conjunction with FIG. 24. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to more effectively share system resources through hardware features.

[0229] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 2600 above the language runtime 2603 and may provide functionality similar to the CUDA library 2503 described above in conjunction with FIG. 25. In at least one embodiment, the various libraries may include, but are not limited to, mathematics, deep learning, and / or other libraries, such as, among others, a hipBLAS library that implements functionality similar to that of CUDA cuBLAS, a rocFFT library for computing FFTs that are similar to CUDA cuFFT, and the like.

[0230] Figure 27 illustrates an OpenCL implementation of software stack 2400 of Figure 24, according to at least one embodiment. In at least one embodiment, OpenCL software stack 2700, upon which application 2701 may be launched, includes OpenCL framework 2710, OpenCL runtime 2706, and driver 2707. In at least one embodiment, OpenCL software stack 2700 executes on non-vendor-specific hardware 2509. In at least one embodiment, OpenCL is supported by devices developed by different vendors, and therefore, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

[0231] In at least one embodiment, application 2701, OpenCL runtime 2706, device kernel driver 2707, and hardware 2708 may perform functionality similar to application 2401, runtime 2405, device kernel driver 2406, and hardware 2407, respectively, described above in conjunction with Figure 24. In at least one embodiment, application 2701 further includes an OpenCL kernel 2702 having code to be executed on the device.

[0232] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform layer API and a runtime API, shown as platform API 2703 and runtime API 2705. In at least one embodiment, the runtime API 2705 uses contexts to manage the execution of kernels on devices. In at least one embodiment, each identified device may be associated with a respective context, and the runtime API 2705 may use each context to manage command queues, program objects, and kernel objects for that device, among other things, and share memory objects. In at least one embodiment, the platform API 2703 exposes functions that allow device contexts to be used to, among other things, select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices. In at least one embodiment, the OpenCL framework also provides various built-in functions (not shown), including, among other things, mathematical functions, relational functions, and image processing functions.

[0233] In at least one embodiment, a compiler 2704 is also included in OpenCL framework 2710. In at least one embodiment, source code may be compiled offline prior to executing an application or online while the application is running. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment may be compiled online by compiler 2704, which is included to represent any number of compilers that may be used to compile source code and / or IR code into binary code, such as Standard Portable Intermediate Representation ("SPIR-V") code. Alternatively, in at least one embodiment, OpenCL applications may be compiled offline prior to executing such applications.

[0234] Figure 28 illustrates software supported by a programming platform, according to at least one embodiment. In at least one embodiment, programming platform 2804 may be included in or be part of one or more of the systems disclosed in Figures 1-3 and may implement some or all of process 400 in Figure 4. In at least one embodiment, programming platform 2804 is configured to support various programming models 2803, middleware and / or libraries 2802, and frameworks 2801 on which application 2800 may rely. In at least one embodiment, application 2800 may be an AI / ML application implemented using a deep learning framework, such as, for example, MXNet, PyTorch, or TensorFlow, which may rely on libraries, such as cuDNN, the NVIDIA Collective Communications Library (“NCCL”), and / or the NVIDIA Developer Data Loading Library (“DALI®”) CUDA library, to provide accelerated computing on the underlying hardware.

[0235] In at least one embodiment, programming platform 2804 may be one of the CUDA, ROCm, or OpenCL platforms described above in conjunction with FIGS. 25, 26, and 27, respectively. In at least one embodiment, programming platform 2804 supports multiple programming models 2803, which are abstractions of the underlying computing system that allow expression of algorithms and data structures. In at least one embodiment, programming model 2803 may expose features of the underlying hardware to improve performance. In at least one embodiment, programming model 2803 may include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism (“C++AMP”), Open Multi-Processing (“OpenMP”), Open Accelerators (“OpenACC”), and / or Vulcan Compute.

[0236] In at least one embodiment, libraries and / or middleware 2802 provide implementations of the abstractions in programming model 2804. In at least one embodiment, such libraries include data and programming code that can be used by computer programs and utilized during software development. In at least one embodiment, such middleware includes software that provides services to applications beyond software available from programming platform 2804. In at least one embodiment, libraries and / or middleware 2802 may include, but are not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Additionally, in at least one embodiment, libraries and / or middleware 2802 may include NCCL and ROCm Communication Collectives Library (“RCCL”) libraries that provide communication routines for GPUs, MIOpen libraries for deep learning acceleration, and / or Eigen libraries for linear algebra, matrix and vector operations, geometric transforms, numerical solvers, and related algorithms.

[0237] In at least one embodiment, application frameworks 2801 depend on libraries and / or middleware 2802. In at least one embodiment, each of application frameworks 2801 is a software framework used to implement a standard structure of application software. Returning to the AI / ML example described above, in at least one embodiment, the AI / ML application may be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or the MxNet deep learning framework.

[0238] Figure 29 illustrates compiling code for execution on one of the programming platforms of Figures 24-27, according to at least one embodiment. In at least one embodiment, compiler 2901 receives source code 2900, which includes both host code and device code. In at least one embodiment, compiler 2901 is configured to convert source code 2900 into host executable code 2902 for execution on the host and device executable code 2903 for execution on the device. In at least one embodiment, source code 2900 may be compiled either offline prior to execution of the application or online while the application is running.

[0239] In at least one embodiment, source code 2900 may include code in any programming language supported by compiler 2901, such as C++, C, Fortran, etc. In at least one embodiment, source code 2900 may be included in a single source file having a mixture of host code and device code, with the location of the device code indicated therein. In at least one embodiment, the single source file may be a .cu file containing CUDA code or a .hip.cpp file containing HIP code. Alternatively, in at least one embodiment, source code 2900 may include multiple source code files rather than a single source file in which the host code and device code are separated.

[0240] In at least one embodiment, compiler 2901 is configured to compile source code 2900 into host executable code 2902 for execution on a host and device executable code 2903 for execution on a device. In at least one embodiment, compiler 2901 performs operations including parsing source code 2900 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment in which source code 2900 comprises a single source file, compiler 2901 may separate the device code from the host code in such a single source file, compile the device code and host code into device executable code 2903 and host executable code 2902, respectively, and link the device executable code 2903 and host executable code 2902 together in the single file, as described in more detail below with respect to FIG.

[0241] In at least one embodiment, host executable code 2902 and device executable code 2903 may be in any suitable format, such as binary code and / or IR code. In at least one embodiment, in the case of CUDA, host executable code 2902 may include native object code and device executable code 2903 may include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both host executable code 2902 and device executable code 2903 may include target binary code.

[0242] FIG. 30 is a more detailed diagram of compiling code for execution on one of the programming platforms of FIGS. 24-27, according to at least one embodiment. In at least one embodiment, one of the programming platforms of FIGS. 24-27 may be included in or be part of one or more systems disclosed in FIGS. 1-3 and may implement some of all of process 400 in FIG. 4, e.g., first compiler 106 and second compiler 110. In at least one embodiment, compiler 3001 is configured to receive source code 3000, compile source code 3000, and output executable file 3010. In at least one embodiment, source code 3000 is a single source file, such as a .cu file, a .hip.cpp file, or another formatted file, that includes both host code and device code. In at least one embodiment, compiler 3001 may be, but is not limited to, the NVIDIA CUDA compiler (“NVCC”) for compiling CUDA code in .cu files, or the HCC compiler for compiling HIP code in .hip.cpp files.

[0243] In at least one embodiment, compiler 3001 includes compiler front end 3002, host compiler 3005, device compiler 3006, and linker 3009. In at least one embodiment, compiler front end 3002 is configured to separate device code 3004 from host code 3003 in source code 3000. In at least one embodiment, device code 3004 is compiled by device compiler 3006 into device executable code 3008, which may include binary code or IR code, as described. In at least one embodiment, separately, host code 3003 is compiled by host compiler 3005 into host executable code 3007. In at least one embodiment, for NVCC, host compiler 3005 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 3006 may be, but is not limited to, a Low Level Virtual Machine ("LLVM")-based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both host compiler 3005 and device compiler 3006 may be, but are not limited to, LLVM-based compilers that output target binary code.

[0244] In at least one embodiment, after compiling source code 3000 into host executable code 3007 and device executable code 3008, linker 3009 links host executable code 3007 and device executable code 3008 together in executable file 3010. In at least one embodiment, the native object code for the host and the PTX or binary code for the device may be linked together in an Executable and Linkable Format (“ELF”) file, which is a container format used to store object code.

[0245] 31 illustrates translating source code prior to compiling the source code, according to at least one embodiment. In at least one embodiment, source code 3100 is passed through a translation tool 3101, which translates source code 3100 into translated source code 3102. In at least one embodiment, a compiler 3103 is used to compile translated source code 3102 into host executable code 3104 and device executable code 3105, in a process similar to the compilation of source code 2900 by compiler 2901 into host executable code 2902 and device executable code 2903, as described above in conjunction with FIG. 29.

[0246] In at least one embodiment, the translation performed by translation tool 3101 is used to port source code 3100 for execution in an environment different from the environment in which it was originally intended to run. In at least one embodiment, translation tool 3101 may include, but is not limited to, a HIP translator used to "hipify" CUDA code targeted for a CUDA platform into HIP code that can be compiled and executed on the ROCm platform. In at least one embodiment, the translation of source code 3100 may include parsing source code 3100 and converting calls to API(s) provided by one programming model (e.g., CUDA) into corresponding calls to API(s) provided by another programming model (e.g., HIP), as described in more detail below in conjunction with Figures 32A-33. Returning to the example of hipfifying CUDA code, in at least one embodiment, calls to the CUDA runtime API, CUDA driver API, and / or CUDA libraries may be converted to corresponding HIP API calls. In at least one embodiment, the automatic translation performed by translation tool 3101 may sometimes be incomplete and require additional manual effort to fully port source code 3100.

[0247] Configuring GPUs for general-purpose computing The following diagram describes an exemplary architecture for compiling and executing compute source code according to, but not limited to, at least one embodiment.

[0248] 32A illustrates a system 32A00 configured to compile and execute CUDA source code 3210 using different types of processing units, according to at least one embodiment. In at least one embodiment, system 32A00 may be included in or be part of one or more of the systems disclosed in FIGS. 1-3 and may implement some or all of process 400 in FIG. 4, e.g., first compiler 106 and second compiler 110. In at least one embodiment, system 32A00 includes, but is not limited to, CUDA source code 3210, CUDA compiler 3250, host executable code 3270(1), host executable code 3270(2), CUDA device executable code 3284, CPU 3290, CUDA-enabled GPU 3294, GPU 3292, CUDA to HIP translation tool 3220, HIP source code 3230, HIP compiler driver 3240, HCC 3260, and HCC device executable code 3282.

[0249] In at least one embodiment, the CUDA source code 3210 is a set of human-readable code in the CUDA programming language. In at least one embodiment, the CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension to the C++ programming language, including, but not limited to, mechanisms for defining device code and distinguishing device code from host code. In at least one embodiment, the device code is source code that is executable in parallel on a device after compilation. In at least one embodiment, the device can be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU3290, GPU32192, or another GPGPU. In at least one embodiment, the host code is source code that is executable on a host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU3290.

[0250] In at least one embodiment, CUDA source code 3210 includes, but is not limited to, any number (including zero) of global functions 3212, any number (including zero) of device functions 3214, any number (including zero) of host functions 3216, and any number (including zero) of host / device functions 3218. In at least one embodiment, global functions 3212, device functions 3214, host functions 3216, and host / device functions 3218 may be intermixed in CUDA source code 3210. In at least one embodiment, each of global functions 3212 is executable on a device and callable from a host. In at least one embodiment, one or more of global functions 3212 may therefore serve as entry points to a device. In at least one embodiment, each of global functions 3212 is a kernel. In at least one embodiment, and in a technique known as dynamic parallelism, one or more of the global functions 3212 define a kernel, which is executable on a device and callable from such a device. In at least one embodiment, a kernel is executed N times in parallel by N different threads on the device during execution, where N is any positive integer.

[0251] In at least one embodiment, each of the device functions 3214 executes on a device and is callable only from such device. In at least one embodiment, each of the host functions 3216 executes on a host and is callable only from such host. In at least one embodiment, each of the host / device functions 3216 defines both a host version of the function that executes on a host and is callable only from such host, and a device version of the function that executes on a device and is callable only from such device.

[0252] In at least one embodiment, CUDA source code 3210 may include, but is not limited to, any number of calls to any number of functions defined via CUDA runtime API 3202. In at least one embodiment, CUDA runtime API 3202 may include, but is not limited to, any number of functions that execute on the host to allocate and deallocate device memory, transfer data between host memory and device memory, manage systems with multiple devices, etc. In at least one embodiment, CUDA source code 3210 may also include, but is not limited to, any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API designed for use by CUDA code. In at least one embodiment, a CUDA API may include, but is not limited to, CUDA runtime API 3202, a CUDA driver API, an API for any number of CUDA libraries, etc. In at least one embodiment, and relative to the CUDA Runtime API 3202, the CUDA Driver API is a lower level API, but provides finer grained control of the device. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cuRAND, cuDNN, etc.

[0253] In at least one embodiment, CUDA compiler 3250 compiles input CUDA code (e.g., CUDA source code 3210) to generate host executable code 3270(1) and CUDA device executable code 3284. In at least one embodiment, CUDA compiler 3250 is NVCC. In at least one embodiment, host executable code 3270(1) is a compiled version of host code contained in the input source code that is executable on CPU 3290. In at least one embodiment, CPU 3290 can be any processor optimized for sequential instruction processing.

[0254] In at least one embodiment, the CUDA device executable code 3284 is a compiled version of device code included in the input source code that is executable on a CUDA-enabled GPU 3294. In at least one embodiment, the CUDA device executable code 3284 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3284 includes IR code, such as, but not limited to, PTX code, which is further compiled at runtime by a device driver into binary code for a particular target device (e.g., a CUDA-enabled GPU 3294). In at least one embodiment, the CUDA-enabled GPU 3294 can be any processor that is optimized for parallel instruction processing and supports CUDA. In at least one embodiment, the CUDA-enabled GPU 3294 is developed by NVIDIA Corporation of Santa Clara, California.

[0255] In at least one embodiment, the CUDA to HIP translation tool 3220 is configured to translate the CUDA source code 3210 into functionally similar HIP source code 3230. In at least one embodiment, the HIP source code 3230 is a collection of human-readable code in the HIP programming language. In at least one embodiment, the HIP code is human-readable code in the HIP programming language. In at least one embodiment, the HIP programming language is an extension to the C++ programming language that includes, but is not limited to, a functionally similar version of the CUDA mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, but is not limited to, a mechanism(s) for defining global functions 3212, but such HIP programming languages ​​may lack support for dynamic parallelism, and therefore, global functions 3212 defined in the HIP code may only be callable from the host.

[0256] In at least one embodiment, HIP source code 3230 includes, but is not limited to, any number of global functions 3212 (including zero), any number of device functions 3214 (including zero), any number of host functions 3216 (including zero), and any number of host / device functions 3218 (including zero). In at least one embodiment, HIP source code 3230 may also include any number of calls to any number of functions specified in HIP runtime API 3232. In at least one embodiment, HIP runtime API 3232 includes, but is not limited to, functionally similar versions of a subset of functions included in CUDA runtime API 3202. In at least one embodiment, HIP source code 3230 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, the HIP API may be any API designed for use by HIP code and / or ROCm. In at least one embodiment, the HIP APIs include, but are not limited to, a HIP runtime API 3232, a HIP driver API, an API for any number of HIP libraries, an API for any number of ROCm libraries, and the like.

[0257] In at least one embodiment, the CUDA to HIP translation tool 3220 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax and converts any number of other CUDA calls in the CUDA code into any number of other functionally similar HIP calls. In at least one embodiment, the CUDA calls are calls to functions specified in the CUDA API and the HIP calls are calls to functions specified in the HIP API. In at least one embodiment, the CUDA to HIP translation tool 3220 converts any number of calls to functions specified in the CUDA runtime API 3202 into any number of calls to functions specified in the HIP runtime API 3232.

[0258] In at least one embodiment, the CUDA to HIP translation tool 3220 is a tool known as hipify-perl, which performs a text-based translation process. In at least one embodiment, the CUDA to HIP translation tool 3220 is a tool known as hipify-clang, which performs a more complex and robust translation process for hipify-perl that involves parsing the CUDA code using clang (a compiler front end) and then translating the resulting symbols. In at least one embodiment, properly converting CUDA code to HIP code may require modifications (e.g., manual edits) in addition to the modifications performed by the CUDA to HIP translation tool 3220.

[0259] In at least one embodiment, HIP compiler driver 3240 is a front end that determines a target device 3246 and then configures a compiler compatible with target device 3246 to compile HIP source code 3230. In at least one embodiment, target device 3246 is a processor optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver 3240 may determine target device 3246 in any technically feasible manner.

[0260] In at least one embodiment, if target device 3246 is compatible with CUDA (e.g., CUDA-enabled GPU 3294), HIP compiler driver 3240 generates HIP / NVCC compile commands 3242. In at least one embodiment, and as described in more detail in conjunction with FIG. 32B, HIP / NVCC compile commands 3242 configure CUDA compiler 3250 to compile HIP source code 3230 using, without limitation, HIP-to-CUDA translation headers and CUDA runtime libraries. In at least one embodiment, and in response to HIP / NVCC compile commands 3242, CUDA compiler 3250 generates host executable code 3270(1) and CUDA device executable code 3284.

[0261] In at least one embodiment, if target device 3246 is not CUDA compatible, HIP compiler driver 3240 generates HIP / HCC compile commands 3244. In at least one embodiment, and as described in more detail in conjunction with FIG. 32C , HIP / HCC compile commands 3244 configure HCC 3260 to compile HIP source code 3230 using, but not limited to, HCC headers and HIP / HCC runtime libraries. In at least one embodiment, and in response to HIP / HCC compile commands 3244, HCC 3260 generates host executable code 3270(2) and HCC device executable code 3282. In at least one embodiment, HCC device executable code 3282 is a compiled version of device code included in HIP source code 3230 that is executable on GPU 3292. In at least one embodiment, the GPU3292 may be any processor that is optimized for parallel instruction processing, is not CUDA compatible, and is HCC compatible. In at least one embodiment, the GPU3292 is developed by AMD Corporation of Santa Clara, Calif. In at least one embodiment, the GPU3292 is a non-CUDA GPU3292.

[0262] For illustrative purposes only, three different flows that may be implemented in at least one embodiment for compiling CUDA source code 3210 for execution on CPU 3290 and different devices are illustrated in Figure 32A. In at least one embodiment, a direct CUDA flow compiles CUDA source code 3210 for execution on CPU 3290 and CUDA-enabled GPU 3294 without translating CUDA source code 3210 into HIP source code 3230. In at least one embodiment, an indirect CUDA flow translates CUDA source code 3210 into HIP source code 3230 and then compiles HIP source code 3230 for execution on CPU 3290 and CUDA-enabled GPU 3294. In at least one embodiment, the CUDA / HCC flow translates CUDA source code 3210 into HIP source code 3230 and then compiles the HIP source code 3230 for execution on the CPU 3290 and GPU 3292.

[0263] A direct CUDA flow that may be implemented in at least one embodiment is illustrated via dashed lines and a series of bubbles annotated A1-A3. In at least one embodiment, and as illustrated by the bubble annotated A1, a CUDA compiler 3250 receives CUDA source code 3210 and a CUDA compile command 3248 that configures the CUDA compiler 3250 to compile the CUDA source code 3210. In at least one embodiment, the CUDA source code 3210 used in the direct CUDA flow is written in the CUDA programming language, which is based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to the CUDA compile command 3248, the CUDA compiler 3250 generates host executable code 3270(1) and CUDA device executable code 3284 (illustrated by the bubble annotated A2). In at least one embodiment, and as illustrated by the bubble annotated A3, host executable code 3270(1) and CUDA device executable code 3284 may execute on CPU 3290 and CUDA-enabled GPU 3294, respectively. In at least one embodiment, CUDA device executable code 3284 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3284 includes, but is not limited to, PTX code, which is further compiled at runtime into binary code for a particular target device.

[0264] An indirect CUDA flow that may be implemented in at least one embodiment is illustrated via a dotted line and a series of bubbles annotated B1-B6. In at least one embodiment, and as illustrated by the bubble annotated B1, a CUDA to HIP translation tool 3220 receives CUDA source code 3210. In at least one embodiment, and as illustrated by the bubble annotated B2, the CUDA to HIP translation tool 3220 translates the CUDA source code 3210 into HIP source code 3230. In at least one embodiment, and as illustrated by the bubble annotated B3, a HIP compiler driver 3240 receives the HIP source code 3230 and determines that the target device 3246 is CUDA-capable.

[0265] In at least one embodiment, and as illustrated by the bubble annotated B4, HIP compiler driver 3240 generates HIP / NVCC compile command 3242 and sends both HIP / NVCC compile command 3242 and HIP source code 3230 to CUDA compiler 3250. In at least one embodiment, and as described in more detail in conjunction with FIG. 32B, HIP / NVCC compile command 3242 configures CUDA compiler 3250 to compile HIP source code 3230 using, but not limited to, HIP-to-CUDA translation headers and CUDA runtime libraries. In at least one embodiment, and in response to HIP / NVCC compile command 3242, CUDA compiler 3250 generates host executable code 3270(1) and CUDA device executable code 3284 (illustrated by the bubble annotated B5). In at least one embodiment, and as illustrated by the bubble annotated B6, host executable code 3270(1) and CUDA device executable code 3284 may execute on CPU 3290 and CUDA-enabled GPU 3294, respectively. In at least one embodiment, CUDA device executable code 3284 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3284 includes, but is not limited to, PTX code, which is further compiled at runtime into binary code for a particular target device.

[0266] A CUDA / HCC flow that may be implemented in at least one embodiment is illustrated via a solid line and a series of bubbles annotated C1-C6. In at least one embodiment, and as illustrated by the bubble annotated C1, a CUDA to HIP translation tool 3220 receives CUDA source code 3210. In at least one embodiment, and as illustrated by the bubble annotated C2, the CUDA to HIP translation tool 3220 translates the CUDA source code 3210 into HIP source code 3230. In at least one embodiment, and as illustrated by the bubble annotated C3, a HIP compiler driver 3240 receives the HIP source code 3230 and determines that the target device 3246 is not CUDA-capable.

[0267] In at least one embodiment, HIP compiler driver 3240 generates HIP / HCC compile command 3244 and sends both HIP / HCC compile command 3244 and HIP source code 3230 to HCC 3260 (illustrated by the bubble annotated C4). In at least one embodiment, and as described in more detail in conjunction with FIG. 32C, HIP / HCC compile command 3244 configures HCC 3260 to compile HIP source code 3230 using, but not limited to, HCC headers and HIP / HCC runtime libraries. In at least one embodiment, and in response to HIP / HCC compile command 3244, HCC 3260 generates host executable code 3270(2) and HCC device executable code 3282 (illustrated by the bubble annotated C5). In at least one embodiment, and as illustrated by the bubble annotated C6, host executable code 3270(2) and HCC device executable code 3282 may execute on CPU 3290 and GPU 3292, respectively.

[0268] In at least one embodiment, after CUDA source code 3210 is translated into HIP source code 3230, HIP compiler driver 3240 can then be used to generate executable code for either CUDA-enabled GPU 3294 or GPU 3292 without re-running CUDA to HIP translation tool 3220. In at least one embodiment, CUDA to HIP translation tool 3220 translates CUDA source code 3210 into HIP source code 3230, which is then stored in memory. In at least one embodiment, HIP compiler driver 3240 then configures HCC 3260 to generate host executable code 3270(2) and HCC device executable code 3282 based on HIP source code 3230. In at least one embodiment, the HIP compiler driver 3240 then configures the CUDA compiler 3250 to generate host executable code 3270(1) and CUDA device executable code 3284 based on the stored HIP source code 3230.

[0269] Figure 32B illustrates a system 3204 configured to compile and execute the CUDA source code 3210 of Figure 32A using a CPU 3290 and a CUDA-enabled GPU 3294, according to at least one embodiment. In at least one embodiment, system 3204 includes, but is not limited to, CUDA source code 3210, a CUDA to HIP translation tool 3220, HIP source code 3230, a HIP compiler driver 3240, a CUDA compiler 3250, host executable code 3270(1), CUDA device executable code 3284, a CPU 3290, and a CUDA-enabled GPU 3294.

[0270] 32A , CUDA source code 3210 includes, but is not limited to, any number of global functions 3212 (including zero), any number of device functions 3214 (including zero), any number of host functions 3216 (including zero), and any number of host / device functions 3218. In at least one embodiment, CUDA source code 3210 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0271] In at least one embodiment, CUDA to HIP translation tool 3220 translates CUDA source code 3210 into HIP source code 3230. In at least one embodiment, CUDA to HIP translation tool 3220 converts each kernel call in CUDA source code 3210 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in CUDA source code 3210 into any number of other functionally similar HIP calls.

[0272] In at least one embodiment, HIP compiler driver 3240 determines that target device 3246 is CUDA-enabled and generates HIP / NVCC compile commands 3242. In at least one embodiment, HIP compiler driver 3240 then configures CUDA compiler 3250 via HIP / NVCC compile commands 3242 to compile HIP source code 3230. In at least one embodiment, HIP compiler driver 3240, as part of configuring CUDA compiler 3250, provides access to a HIP-to-CUDA translation header 3252. In at least one embodiment, HIP-to-CUDA translation header 3252 translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs into any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, CUDA compiler 3250 uses HIP-to-CUDA translation header 3252 in conjunction with CUDA runtime library 3254 corresponding to CUDA runtime API 3202 to generate host executable code 3270(1) and CUDA device executable code 3284. In at least one embodiment, host executable code 3270(1) and CUDA device executable code 3284 may then be executed on CPU 3290 and CUDA-enabled GPU 3294, respectively. In at least one embodiment, CUDA device executable code 3284 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3284 includes, but is not limited to, PTX code and is further compiled at runtime into binary code for a particular target device.

[0273] Figure 32C illustrates a system 3206 configured to compile and execute the CUDA source code 3210 of Figure 32A using a CPU 3290 and a non-CUDA GPU 3292, according to at least one embodiment. In at least one embodiment, system 3206 includes, but is not limited to, CUDA source code 3210, a CUDA to HIP translation tool 3220, HIP source code 3230, a HIP compiler driver 3240, an HCC 3260, host executable code 3270(2), an HCC device executable code 3282, a CPU 3290, and a GPU 3292.

[0274] 32A , CUDA source code 3210 includes, but is not limited to, any number of global functions 3212 (including zero), any number of device functions 3214 (including zero), any number of host functions 3216 (including zero), and any number of host / device functions 3218. In at least one embodiment, CUDA source code 3210 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0275] In at least one embodiment, CUDA to HIP translation tool 3220 translates CUDA source code 3210 into HIP source code 3230. In at least one embodiment, CUDA to HIP translation tool 3220 converts each kernel call in CUDA source code 3210 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in source code 3210 into any number of other functionally similar HIP calls.

[0276] In at least one embodiment, HIP compiler driver 3240 then determines that target device 3246 is not CUDA-enabled and generates HIP / HCC compile commands 3244. In at least one embodiment, HIP compiler driver 3240 then configures HCC 3260 to execute HIP / HCC compile commands 3244 to compile HIP source code 3230. In at least one embodiment, HIP / HCC compile commands 3244 configure HCC 3260 to use, without limitation, HIP / HCC runtime library 3258 and HCC headers 3256 to generate host executable code 3270(2) and HCC device executable code 3282. In at least one embodiment, HIP / HCC runtime library 3258 corresponds to HIP runtime API 3232. In at least one embodiment, HCC header 3256 includes, without limitation, any number and type of interoperability mechanisms for the HIP and HCC. In at least one embodiment, host executable code 3270(2) and HCC device executable code 3282 may execute on CPU 3290 and GPU 3292, respectively.

[0277] FIG. 33 illustrates an exemplary kernel translated by the CUDA to HIP translation tool 3220 of FIG. 32C , according to at least one embodiment. In at least one embodiment, the CUDA source code 3210 partitions the overall problem that a given kernel is designed to solve into relatively coarse-grained subproblems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads. In at least one embodiment, each subproblem is partitioned into relatively finer pieces that can be solved in parallel and in concert by threads within the thread block. In at least one embodiment, the threads within a thread block can coordinate by sharing data through shared memory and by synchronizing execution to coordinate memory accesses.

[0278] In at least one embodiment, the CUDA source code 3210 organizes the thread blocks associated with a given kernel into a one-dimensional, two-dimensional, or three-dimensional grid of thread blocks, where in at least one embodiment each thread block includes, but is not limited to, any number of threads and the grid includes, but is not limited to, any number of thread blocks.

[0279] In at least one embodiment, a kernel is a function in device code that is defined using the "__global__" declaration specifier. In at least one embodiment, the dimensions of the grid in which the kernel will execute for a given kernel call and associated stream are specified using CUDA kernel invocation syntax 3310. In at least one embodiment, CUDA kernel invocation syntax 3310 includes the following syntax: "KernelName<<<GridSize,BlockSize,SharedMemorySize,Stream> >>(KernelArguments);". In at least one embodiment, the execution configuration syntax is a "<<<...>>>" construct inserted between the kernel name ("KernelName") and the parenthesized list of kernel arguments ("KernelArguments"). In at least one embodiment, the CUDA kernel launch syntax 3310 includes, but is not limited to, CUDA launch function syntax instead of execution configuration syntax.

[0280] In at least one embodiment, "GridSize" is of type dim3 and specifies the dimensions and size of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure including, but not limited to, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z defaults to 1. In at least one embodiment, if y is not specified, y defaults to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the dimensions and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing a kernel is given a unique thread ID that is accessible within the kernel through a built-in variable (e.g., "threadIdx").

[0281] In at least one embodiment, and with respect to CUDA kernel invocation syntax 3310, "SharedMemorySize" is an optional argument that specifies the number of bytes in shared memory that will be dynamically allocated per thread block for a given kernel call, in addition to statically allocated memory. In at least one embodiment, and with respect to CUDA kernel invocation syntax 3310, SharedMemorySize defaults to 0. In at least one embodiment, and with respect to CUDA kernel invocation syntax 3310, "Stream" is an optional argument that specifies the associated stream and defaults to 0 to specify the default stream. In at least one embodiment, a stream is a sequence of commands (possibly issued by different host threads) that execute in order. In at least one embodiment, different streams may execute commands out of order or concurrently with respect to each other.

[0282] In at least one embodiment, CUDA source code 3210 includes, but is not limited to, a kernel definition and a main function for an exemplary kernel "MatAdd." In at least one embodiment, the main function is host code that executes on the host and includes, but is not limited to, a kernel call that causes the kernel MatAdd to execute on the device. In at least one embodiment, and as shown, the kernel MatAdd adds two matrices A and B of size N×N, where N is a positive integer, and stores the result in matrix C. In at least one embodiment, the main function defines a threadsPerBlock variable as 16×16 and a numBlocks variable as N / 16×N / 16. In at least one embodiment, the main function then defines the kernel call "MatAdd<<<numBlocks,threadsPerBlock> >>(A,B,C);." In at least one embodiment, and in accordance with CUDA kernel invocation syntax 3310, the kernel MatAdd is executed using a grid of thread blocks having dimensions N / 16 x N / 16, where each thread block has dimensions 16 x 16. In at least one embodiment, each thread block includes 256 threads, and the grid is created with enough blocks to have one thread per matrix element, and each thread in such grid executes the kernel MatAdd to perform one pairwise addition.

[0283] In at least one embodiment, while translating CUDA source code 3210 into HIP source code 3230, CUDA to HIP translation tool 3220 translates each kernel call in CUDA source code 3210 from CUDA kernel launch syntax 3310 to HIP kernel launch syntax 3320 and converts any number of other CUDA calls in source code 3210 into any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax 3320 is specified as "hipLaunchKernelGGL(KernelName, GridSize, BlockSize, SharedMemorySize, Stream, KernelArguments);". In at least one embodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments have the same meaning in HIP kernel invocation syntax 3320 as in CUDA kernel invocation syntax 3310 (described earlier herein). In at least one embodiment, the arguments SharedMemorySize and Stream are required in HIP kernel invocation syntax 3320 and optional in CUDA kernel invocation syntax 3310.

[0284] In at least one embodiment, the portion of HIP source code 3230 illustrated in FIG. 33 is identical to the portion of CUDA source code 3210 illustrated in FIG. 33, except for the kernel call that causes kernel MatAdd to execute on the device. In at least one embodiment, kernel MatAdd is defined in HIP source code 3230 with the same "__global__" declaration specifier that kernel MatAdd is defined in CUDA source code 3210. In at least one embodiment, the kernel call in HIP source code 3230 is "hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);", while the corresponding kernel call in CUDA source code 3210 is "MatAdd<<<numBlocks,threadsPerBlock> >>(A,B,C);".

[0285] FIG. 34 illustrates the non-CUDA GPU 3292 of FIG. 32C in more detail, according to at least one embodiment. In at least one embodiment, GPU 3292 is developed by AMD Corporation of Santa Clara. In at least one embodiment, GPU 3292 may be configured to perform compute operations in a highly parallel manner. In at least one embodiment, GPU 3292 is configured to execute graphics pipeline operations such as drawing commands, pixel operations, geometric calculations, and other operations related to rendering an image to a display. In at least one embodiment, GPU 3292 is configured to execute non-graphics related operations. In at least one embodiment, GPU 3292 is configured to execute both graphics related and non-graphics related operations. In at least one embodiment, GPU 3292 may be configured to execute device code included in HIP source code 3230.

[0286] In at least one embodiment, GPU 3292 includes, but is not limited to, a number of programmable processing units 3420, a command processor 3410, an L2 cache 3422, a memory controller 3470, a DMA engine 3480(1), a system memory controller 3482, a DMA engine 3480(2), and a GPU controller 3484. In at least one embodiment, each programmable processing unit 3420 includes, but is not limited to, a workload manager 3430 and a number of compute units 3440. In at least one embodiment, command processor 3410 reads commands from one or more command queues (not shown) and distributes the commands to workload manager 3430. In at least one embodiment, for each programmable processing unit 3420, the associated workload manager 3430 distributes work to the compute units 3440 included in the programmable processing unit 3420. In at least one embodiment, each compute unit 3440 may execute any number of thread blocks, but each thread block executes on a single compute unit 3440. In at least one embodiment, a workgroup is a thread block.

[0287] In at least one embodiment, each compute unit 3440 includes, but is not limited to, any number of SIMD units 3450 and shared memory 3460. In at least one embodiment, each SIMD unit 3450 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each SIMD unit 3450 includes, but is not limited to, a vector ALU 3452 and a vector register file 3454. In at least one embodiment, each SIMD unit 3450 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication may be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize with each other and communicate via shared memory 3460.

[0288] In at least one embodiment, the programmable processing units 3420 are referred to as "shader engines." In at least one embodiment, each programmable processing unit 3420 includes any amount of dedicated graphics hardware in addition to, but not limited to, compute units 3440. In at least one embodiment, each programmable processing unit 3420 includes, but is not limited to, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of render back ends, a workload manager 3430, and any number of compute units 3440.

[0289] In at least one embodiment, the compute units 3440 share an L2 cache 3422. In at least one embodiment, the L2 cache 3422 is partitioned. In at least one embodiment, the GPU memory 3490 is accessible by all of the compute units 3440 in the GPU 3292. In at least one embodiment, the memory controller 3470 and the system memory controller 3482 facilitate data transfers between the GPU 3292 and a host, and the DMA engine 3480(1) enables asynchronous memory transfers between the GPU 3292 and such a host. In at least one embodiment, the memory controller 3470 and the GPU controller 3484 facilitate data transfers between the GPU 3292 and other GPUs 3292, and the DMA engine 3480(2) enables asynchronous memory transfers between the GPU 3292 and other GPUs 3292.

[0290] In at least one embodiment, GPU 3292 includes any quantity and type of system interconnects facilitating data and control transmission across any number and type of directly or indirectly linked components, which may be internal or external to GPU 3292, without limitation. In at least one embodiment, GPU 3292 includes any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices, without limitation. In at least one embodiment, GPU 3292 may include any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU 3292 implements a memory subsystem, including any quantity and type of memory controllers (e.g., memory controller 3470 and system memory controller 3482) and memory devices (e.g., shared memory 3460), which may be dedicated to one component or shared among multiple components. In at least one embodiment, GPU 3292 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 3422), each of which may be private to or shared among any number of components (e.g., SIMD unit 3450, compute unit 3440, and programmable processing unit 3420).

[0291] FIG. 35 illustrates how threads of an exemplary CUDA grid 3520 are mapped to the different compute units 3440 of FIG. 34, according to at least one embodiment. In at least one embodiment, and for illustrative purposes only, the grid 3520 has a GridSize of BX×BY×1 and a BlockSize of TX×TY×1. In at least one embodiment, the grid 3520 therefore includes, but is not limited to, (BX*BY) thread blocks 3530, and each thread block 3530 includes, but is not limited to, (TX*TY) threads 3540. The threads 3540 are illustrated in FIG. 35 as squiggly arrows.

[0292] In at least one embodiment, grid 3520 is mapped to programmable processing unit 3420(1), which may include, but is not limited to, compute units 3440(1) through 3440(C). In at least one embodiment, and as shown, (BJ*BY) thread blocks 3530 are mapped to compute unit 3440(1), and the remaining thread blocks 3530 are mapped to compute unit 3440(2). In at least one embodiment, each thread block 3530 may include, but is not limited to, any number of warps, with each warp mapped to a different SIMD unit 3450 in FIG. 34.

[0293] In at least one embodiment, warps in a given thread block 3530 may synchronize with each other and communicate through shared memory 3460 included in the associated compute unit 3440. For example, and in at least one embodiment, warps in thread block 3530(BJ,1) may synchronize with each other and communicate through shared memory 3460(1). For example, and in at least one embodiment, warps in thread block 3530(BJ+1,1) may synchronize with each other and communicate through shared memory 3460(2).

[0294] FIG. 36 illustrates how to migrate existing CUDA code to Data Parallel C++ code, according to at least one embodiment. Data Parallel C++ (DPC++) may refer to an open, standards-based alternative to single-architecture, proprietary languages, allowing developers to reuse code across hardware targets (CPUs and accelerators such as GPUs and FPGAs) and to perform custom tuning for specific accelerators. DPC++ uses similar and / or identical C and C++ constructs that conform to ISO C++, with which developers may be familiar. DPC++ incorporates the SYCL standard from the Khronos Group to support data parallelism and heterogeneous programming. SYCL refers to a cross-platform abstraction layer based on the underlying concepts, portability, and efficiency of OpenCL, allowing code for heterogeneous processors to be written in a "single-source" style using standard C++. SYCL can enable single-source development, where C++ template functions contain both host and device code, allowing developers to build complex algorithms using OpenCL acceleration and then reuse them across their source code for different types of data.

[0295] In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code that can be deployed across a variety of hardware targets. In at least one embodiment, a DPC++ compiler is used to generate DPC++ applications that can be deployed across a variety of hardware targets, and DPC++ compatibility tools can be used to migrate CUDA applications to DPC++ multi-platform programs. In at least one embodiment, a DPC++ base toolkit includes a DPC++ compiler for deploying applications across a variety of hardware targets, a DPC++ library for increasing productivity and performance across CPUs, GPUs, and FPGAs, a DPC++ compatibility tool for migrating CUDA applications to multi-platform applications, or any suitable combination thereof.

[0296] In at least one embodiment, the DPC++ programming model is utilized solely for one or more aspects related to programming the CPU and accelerator by using modern C++ features to express parallelism using a programming language called Data Parallel C++. The DPC++ programming language is utilized for code reuse for the host (e.g., CPU) and accelerator (e.g., GPU or FPGA), using a single source language, and execution and memory dependencies can be clearly communicated. Mapping within the DPC++ code can be used to migrate applications to run on the hardware or set of hardware devices that best accelerate the workload. Even on platforms that do not have available accelerators, a host may be available to simplify development and debugging of device code.

[0297] In at least one embodiment, CUDA source code 3600 is provided as input to a DPC++ compatibility tool 3602 to generate a human-readable DPC++ 3604. In at least one embodiment, the human-readable DPC++ 3604 includes inline comments generated by the DPC++ compatibility tool 3602 that guide the developer as to how and / or where to modify the DPC++ code to complete the coding and tuning for desired performance 3606, thereby generating DPC++ source code 3608.

[0298] In at least one embodiment, CUDA source code 3600 is or includes a set of human-readable source code in the CUDA programming language. In at least one embodiment, CUDA source code 3600 is human-readable source code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension to the C++ programming language that includes, but is not limited to, mechanisms for defining device code and distinguishing device code from host code. In at least one embodiment, device code is source code that, after compilation, is executable on a device (e.g., a GPU or FPGA) and may run on one or more processor cores of the device or may include a more parallelizable workflow. In at least one embodiment, the device may be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU, GPU, or another GPGPU. In at least one embodiment, host code is source code that, after compilation, is executable on a host. In at least one embodiment, some or all of the host code and device code may execute in parallel across the CPU and GPU / FPGA. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU. The CUDA source code 3600 described with respect to FIG. 36 may follow CUDA source code described elsewhere herein.

[0299] In at least one embodiment, DPC++ compatibility tool 3602 refers to an executable tool, program, application, or any other suitable type of tool used to facilitate the migration of CUDA source code 3600 to DPC++ source code 3608. In at least one embodiment, DPC++ compatibility tool 3602 is a command-line based code migration tool available as part of the DPC++ toolkit used to port existing CUDA source to DPC++. In at least one embodiment, DPC++ compatibility tool 3602 converts some or all of the source code of a CUDA application from CUDA to DPC++ and generates a resulting file written at least partially in DPC++, called a human-readable DPC++ 3604. In at least one embodiment, the human-readable DPC++ 3604 includes comments generated by DPC++ compatibility tool 3602 to indicate where user intervention may be required. In at least one embodiment, user intervention is required when CUDA source code 3600 calls a CUDA API that does not have a similar DPC++ API; other instances where user intervention is required are described in more detail below.

[0300] In at least one embodiment, a workflow for migrating CUDA source code 3600 (e.g., an application or portions thereof) includes creating one or more compilation database files, migrating CUDA to DPC++ using a DPC++ compatibility tool 3602, completing and validating the migration, thereby generating DPC++ source code 3608, and compiling the DPC++ source code 3608 with a DPC++ compiler to generate a DPC++ application. In at least one embodiment, the compatibility tool provides a utility that intercepts commands used when a Makefile executes and stores them in a compilation database file. In at least one embodiment, the file is stored in JSON format. In at least one embodiment, an intercept-built command converts Makefile commands into DPC-compatible commands.

[0301] In at least one embodiment, intercept-build is a utility script that intercepts the build process, captures compilation options, macro definitions, and include paths, and writes this data to a compilation database file. In at least one embodiment, the compilation database file is a JSON file. In at least one embodiment, the DPC++ compatibility tool 3602 parses the compilation database and applies options when migrating input sources. In at least one embodiment, use of intercept-build is optional but highly recommended for Make or CMake-based environments. In at least one embodiment, the migration database includes commands, directories, and files, where the commands may include required compilation flags, the directories may include paths to header files, and the files may include paths to CUDA files.

[0302] In at least one embodiment, the DPC++ compatibility tool 3602 migrates CUDA code (e.g., applications) written in CUDA to DPC++ by generating DPC++ whenever possible. In at least one embodiment, the DPC++ compatibility tool 3602 is available as part of a tool kit. In at least one embodiment, the DPC++ tool kit includes an intercept-build tool. In at least one embodiment, the intercept-built tool creates a compilation database that captures compilation commands to migrate CUDA files. In at least one embodiment, the compilation database generated by the intercept-built tool is used by the DPC++ compatibility tool 3602 to migrate the CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated as is. In at least one embodiment, DPC++ compatibility tool 3602 generates a human-readable DPC++ 3604, which may be DPC++ code that, when generated by DPC++ compatibility tool 3602, may not compile with the DPC++ compiler and may require additional plumbing to identify portions of code that were not correctly migrated, which may involve manual intervention, such as by a developer. In at least one embodiment, DPC++ compatibility tool 3602 provides hints or tools embedded in the code to help a developer manually migrate additional code that may not be automatically migrated. In at least one embodiment, migration is a one-time activity for a source file, project, or application.

[0303] In at least one embodiment, the DPC++ compatibility tool 36002 may successfully migrate all portions of CUDA code to DPC++, with only an optional step to manually review and tune the performance of the generated DPC++ source code. In at least one embodiment, the DPC++ compatibility tool 3602 directly generates DPC++ source code 3608 that is compiled by a DPC++ compiler without requiring or utilizing human intervention to modify the DPC++ code generated by the DPC++ compatibility tool 3602. In at least one embodiment, the DPC++ compatibility tool generates compilable DPC++ code that may be optionally tuned by a developer for performance, readability, maintainability, various other considerations, or any combination thereof.

[0304] In at least one embodiment, one or more CUDA source files are at least partially migrated to DPC++ source files using DPC++ compatibility tool 3602. In at least one embodiment, the CUDA source code includes one or more header files, which may include CUDA header files. In at least one embodiment, the CUDA source files include<cuda.h> Header files can be used to print text<stdio.h> In at least one embodiment, a portion of a vector addition kernel CUDA source file may be written as follows or related to the following:

number

number

[0305] In at least one embodiment, and with respect to the CUDA source files presented above, the DPC++ compatibility tool 3602 parses the CUDA source code and replaces header files with appropriate DPC++ and SYCL header files. In at least one embodiment, the DPC++ header files include helper declarations. In CUDA, there is the concept of a thread ID; correspondingly, in DPC++ or SYCL, there is a local identifier for each element.

[0306] In at least one embodiment, and with respect to the CUDA source file presented above, there are two vectors A and B that are initialized, and the vector addition result is put into vector C as part of VectorAddKernel(). In at least one embodiment, DPC++ compatibility tool 3602 converts CUDA thread IDs used to index work elements to SYCL standard addressing for work elements via local IDs as part of migrating CUDA code to DPC++ code. In at least one embodiment, the DPC++ code generated by DPC++ compatibility tool 3602 can be optimized, for example, by reducing the dimensionality of nd_item, thereby increasing memory and / or processor utilization.

[0307] In at least one embodiment, and with respect to the CUDA source files presented above, memory allocation is migrated. In at least one embodiment, cudaMalloc() is migrated to a unified shared memory SYCL call malloc_device(), to which a device and context are passed, relying on SYCL concepts such as platform, device, context, and queue. In at least one embodiment, a SYCL platform can have multiple devices (e.g., host and GPU devices), a device can have multiple queues to which jobs can be submitted, each device can have a context, and a context can have multiple devices and manage shared memory objects.

[0308] In at least one embodiment, and with respect to the CUDA source file presented above, the main() function invokes or calls VectorAddKernel() to add two vectors A and B together and store the result in vector C. In at least one embodiment, the CUDA code to invoke VectorAddKernel() is replaced by DPC++ code to submit the kernel to a command queue for execution. In at least one embodiment, the command group handler cgh passes the data, synchronization, and computation to be submitted to the queue, and parallel_for is called for the number of global elements and the number of work items in the work group for which VectorAddKernel() is called.

[0309] In at least one embodiment, and with respect to the CUDA source files presented above, CUDA calls to copy device memory and then free memory for vectors A, B, and C are migrated to corresponding DPC++ calls. In at least one embodiment, C++ code (e.g., standard ISO C++ code for printing a vector of floating-point variables) is migrated as is without modification by DPC++ compatibility tool 3602. In at least one embodiment, DPC++ compatibility tool 3602 modifies CUDA APIs for memory setup and / or host calls to execute the kernel on the acceleration device. In at least one embodiment, and with respect to the CUDA source files presented above, a corresponding human-readable DPC++ 3604 (which may be compiled, for example) is written as follows or relates to the following:

number

number

number

[0310] In at least one embodiment, human-readable DPC++ 3604 refers to the output generated by DPC++ compatibility tool 3602 and may be optimized in one way or another. In at least one embodiment, human-readable DPC++ 3604 generated by DPC++ compatibility tool 3602 may be manually edited by a developer after migration to make it more maintainable, for performance, or other considerations. In at least one embodiment, DPC++ code generated by DPC++ compatibility tool 3602, such as the disclosed DPC++, may be optimized by removing repeated calls to get_current_device() and / or get_default_context() for each malloc_device() call. In at least one embodiment, the DPC++ code generated above uses a three-dimensional nd_range, which may be refactored to use only a single dimension, thereby reducing memory usage. In at least one embodiment, a developer may manually edit the DPC++ code generated by DPC++ compatibility tool 3602 and replace the use of uniform shared memory with accessors. In at least one embodiment, DPC++ compatibility tool 3602 has options to change how it migrates CUDA code to DPC++ code. In at least one embodiment, DPC++ compatibility tool 3602 is verbose because it uses a generic template to migrate CUDA code to DPC++ code that works for many cases.

[0311] In at least one embodiment, the CUDA to DPC++ migration workflow includes steps for preparing for migration using an intercept-build script, steps for performing the migration of the CUDA project to DPC++ using DPC++ compatibility tools 3602, steps for manually reviewing and editing the migrated source files for completion and correctness, and steps for compiling the final DPC++ code to generate a DPC++ application. In at least one embodiment, manual review of the DPC++ source code may be required in one or more scenarios, including, but not limited to, the migrated APIs not returning error codes (CUDA code can return error codes, which can then be consumed by the application, but SYCL uses exceptions to report errors and therefore does not use error codes to surface errors), CUDA compute-capability dependent logic is not supported by DPC++, and statements may not be removed. In at least one embodiment, scenarios where DPC++ code requires manual intervention may include, but are not limited to, error code logic being replaced with (*,0) code or commented out, equivalent DPC++ API not being available, CUDA compute power dependent logic, hardware dependent API (clock()), missing features, unsupported APIs, execution time measurement logic, addressing built-in vector type conflicts, cuBLAS API migration, etc.

[0312] In at least one embodiment, one or more techniques described herein utilize a oneAPI programming model. In at least one embodiment, the oneAPI programming model refers to a programming model for interacting with various compute accelerator architectures. In at least one embodiment, the oneAPI refers to an application programming interface (API) designed to interact with various compute accelerator architectures. In at least one embodiment, the oneAPI programming model utilizes the DPC++ programming language. In at least one embodiment, the DPC++ programming language refers to a high-level language for data-parallel programming productivity. In at least one embodiment, the DPC++ programming language is based at least in part on the C and / or C++ programming languages. In at least one embodiment, the oneAPI programming model is a programming model such as that developed by Intel Corporation of Santa Clara, California.

[0313] In at least one embodiment, oneAPI and / or the oneAPI programming model are utilized to interact with various accelerator architectures, GPU architectures, processor architectures, and / or variations thereof. In at least one embodiment, oneAPI includes a set of libraries that implement various functionality. In at least one embodiment, oneAPI includes at least a oneAPI DPC++ library, a oneAPI math kernel library, a oneAPI data analysis library, a oneAPI deep neural network library, a oneAPI collective communication library, a oneAPI threading building blocks library, a oneAPI video processing library, and / or variations thereof.

[0314] In at least one embodiment, the oneAPI DPC++ library, also referred to as oneDPL, is a library that implements algorithms and functions for accelerating DPC++ kernel programming. In at least one embodiment, oneDPL implements one or more standard template library (STL) functions. In at least one embodiment, oneDPL implements one or more parallel STL functions. In at least one embodiment, oneDPL provides a set of library classes and functions, such as parallel algorithms, iterators, function object classes, range-based APIs, and / or variations thereof. In at least one embodiment, oneDPL implements one or more classes and / or functions of the C++ standard library. In at least one embodiment, oneDPL implements one or more random number generator functions.

[0315] In at least one embodiment, the oneAPI Math Kernel Library, also referred to as oneMKL, is a library that implements various optimized and parallelized routines for various mathematical functions and / or operations. In at least one embodiment, oneMKL implements one or more Basic Linear Algebra Subprograms (BLAS) and / or linear algebra package (LAPACK) dense linear algebra routines. In at least one embodiment, oneMKL implements one or more sparse BLAS linear algebra routines. In at least one embodiment, oneMKL implements one or more random number generators (RNGs). In at least one embodiment, oneMKL implements one or more vector mathematics (VM) routines for mathematical operations on vectors. In at least one embodiment, oneMKL implements one or more fast Fourier transform (FFT) functions.

[0316] In at least one embodiment, the oneAPI Data Analysis Library, also referred to as oneDAL, is a library that implements various data analysis applications and distributed computation. In at least one embodiment, oneDAL implements various algorithms for pre-processing, transformation, analysis, modeling, validation, and decision-making for data analysis in batch, online, and distributed computational modes. In at least one embodiment, oneDAL implements various C++ and / or Java APIs and various connectors to one or more data sources. In at least one embodiment, oneDAL implements DPC++ API extensions to the traditional C++ interface to enable GPU usage for various algorithms.

[0317] In at least one embodiment, the oneAPI Deep Neural Network Library, also referred to as oneDNN, is a library that implements various deep learning functions. In at least one embodiment, oneDNN implements various neural network, machine learning, and deep learning functions, algorithms, and / or variations thereof.

[0318] In at least one embodiment, the oneAPI Collective Communication Library, also referred to as oneCCL, is a library that implements various applications for deep learning and machine learning workloads. In at least one embodiment, oneCCL builds on lower-level communication middleware, such as the message passing interface (MPI) and libfabric. In at least one embodiment, oneCCL enables a set of deep learning-specific optimizations, such as prioritization, persistent behavior, out-of-order execution, and / or variations thereof. In at least one embodiment, oneCCL implements various CPU and GPU capabilities.

[0319] In at least one embodiment, the oneAPI Threading Building Blocks library, also referred to as oneTBB, is a library that implements various parallelized processes for various applications. In at least one embodiment, oneTBB is utilized for task-based shared parallel programming on a host. In at least one embodiment, oneTBB implements general parallel algorithms. In at least one embodiment, oneTBB implements concurrent containers. In at least one embodiment, oneTBB implements a scalable memory allocator. In at least one embodiment, oneTBB implements a work-stealing task scheduler. In at least one embodiment, oneTBB implements low-level synchronization primitives. In at least one embodiment, oneTBB is compiler independent and usable on various processors, such as GPUs, PPUs, CPUs, and / or variations thereof.

[0320] In at least one embodiment, the oneAPI Video Processing Library, also referred to as oneVPL, is a library utilized to accelerate video processing in one or more applications. In at least one embodiment, oneVPL implements various video decoding, encoding, and processing functions. In at least one embodiment, oneVPL implements various functions for media pipelines on CPUs, GPUs, and other accelerators. In at least one embodiment, oneVPL implements device discovery and selection in media-centric and video analytics workloads. In at least one embodiment, oneVPL implements API primitives for zero-copy buffer sharing.

[0321] In at least one embodiment, the oneAPI programming model utilizes the DPC++ programming language. In at least one embodiment, the DPC++ programming language is a programming language that includes, but is not limited to, a functionally similar version of the CUDA mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, the DPC++ programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, one or more CUDA programming model operations are implemented using the oneAPI programming model using the DPC++ programming language.

[0322] It should be noted that while the exemplary embodiments described herein may relate to the CUDA programming model, the techniques described herein may be utilized with any suitable programming model, such as HIP, oneAPI (e.g., using oneAPI-based programming to perform or implement the methods disclosed herein), and / or variations thereof.

[0323] In at least one embodiment, one or more components of the systems and / or processors disclosed above can be in communication with one or more CPUs, ASICs, GPUs, FPGAs, or other hardware, circuit elements, or integrated circuit components, including, for example, an upscaler or upsampler for upscaling an image, an image blender or image blender component for blending, mixing, or adding images together, a sampler for sampling an image (e.g., as part of a DSP), a neural network circuit configured to implement an upscaler for upscaling an image (e.g., from a low-resolution image to a high-resolution image), or other hardware for modifying or generating an image, frame, or video to adjust its resolution, size, or pixels, and one or more components of the systems and / or processors disclosed above can use the components described in this disclosure to implement the methods, operations, or instructions for generating or modifying images.

[0324] At least one embodiment of the present disclosure may be described in view of the following provisions. Clause Set 1 1. One or more circuits for performing an operation to indicate one or more non-zero values ​​in one or more matrices of data. A processor comprising: 2. The processor of clause 1, wherein the one or more circuits are for indicating the one or more non-zero values ​​by at least causing the one or more processors to store the one or more non-zero index values ​​in memory accessible to the one or more graphics processing cores. 3. The processor of clause 1 or 2, wherein the operation to direct includes one or more circuits generating instructions that cause the one or more processors to store the one or more non-zero-valued indices in memory that is accessible to one or more threads when performing one or more sparse matrix multiplication operations in parallel. 4. The processor of any one of clauses 1 to 3, wherein the operation is a sparse matrix multiplication operation, and the one or more circuits are for implementing a compiler to generate executable instructions for ...

Claims

1. Identifying one or more non-zero values ​​in one or more matrices of data; and generating one or more data structures to perform matrix multiplication based at least in part on the one or more non-zero values; Circuitry that causes a compiler to generate one or more instructions Equipped with the one or more instructions are for causing the compiler to receive one or more first instructions along with sparsity information for the one or more matrices of data, and to compile the one or more first instructions to generate one or more second instructions executable by a graphics processing unit (GPU) to perform the matrix multiplication with the sparsity information.

2. 2. The processor of claim 1, wherein the circuit element is for at least identifying the one or more non-zero values ​​by causing one or more processors to store index values ​​of the one or more non-zero values ​​in memory accessible to one or more graphics processing cores.

3. 2. The processor of claim 1, wherein the one or more instructions to identify comprises generating an instruction that causes one or more processors to store the one or more non-zero-valued indices in a memory that is accessible to one or more threads when executing one or more sparse matrix multiplication operations in parallel.

4. 2. The processor of claim 1, wherein the matrix multiplication is a sparse matrix multiplication operation, and wherein the circuit elements are for implementing the compiler to generate executable instructions for performing the sparse matrix multiplication operation.

5. 2. The processor of claim 1, wherein the matrix multiplication is a sparse matrix operation including a half-precision matrix multiply-accumulate (HMMA) operation, an integer matrix multiply-accumulate (IMMA) operation, a single-precision matrix multiply operation, or a floating-point multiply-accumulate operation.

6. 2. The processor of claim 1, wherein the one or more instructions to identify are to cause the compiler to modify a directed acyclic graph (DAG) interface to receive one or more first instructions along with sparsity information for the one or more matrices of data.

7. 2. The processor of claim 1, wherein identifying one or more non-zero values ​​in one or more matrices of data includes causing the circuit elements to execute the compiler to generate operands to be used by one or more graphics processing cores to perform the matrix multiplication, the operands including index information for the one or more non-zero values.

8. 1. A system comprising a memory for storing instructions generated by a compiler, the instructions being such that, upon execution by one or more processors, the system: Identifying one or more non-zero values ​​in one or more matrices of data; and generating one or more data structures to perform matrix multiplication based at least in part on the one or more non-zero values; This causes the instructions are for causing the compiler to receive one or more first instructions along with sparsity information and compile the one or more first instructions to generate one or more second instructions executable by a graphics processing unit (GPU) to perform the matrix multiplication with the sparsity information.

9. 9. The system of claim 8, wherein identifying includes causing one or more processors to store the one or more non-zero index values ​​in memory accessible to one or more graphics processing cores.

10. 10. The system of claim 8, wherein the system is for generating instructions that cause one or more processors to store the one or more non-zero indices in memory accessible to one or more threads when performing the matrix multiplication in parallel.

11. 9. The system of claim 8, wherein the matrix multiplication is a sparse matrix multiplication operation, the system is for receiving one or more instructions to perform the sparse matrix multiplication operation, and the system is for generating executable instructions to be used by one or more drivers to perform the sparse matrix multiplication operation.

12. 9. The system of claim 8, wherein the matrix multiplication is a sparse matrix operation including a half-precision matrix multiply-accumulate (HMMA) operation, an integer matrix multiply-accumulate (IMMA) operation, a single-precision matrix multiply operation, or a floating-point multiply-accumulate operation.

13. 10. The system of claim 8, wherein the instructions to identify include causing the compiler to modify a directed acyclic graph (DAG) interface to receive one or more instructions along with sparsity information for the one or more matrices of data.

14. 10. The system of claim 8, wherein identifying one or more non-zero values ​​in one or more matrices of data includes causing circuit elements implementing the compiler to generate operands to be used by one or more graphics processing cores to perform the matrix multiplication, the operands including index information for the one or more matrices.

15. 1. A machine-readable medium storing one or more instructions generated by a compiler, the one or more instructions, when executed by one or more processors, causing the one or more processors to at least: Identifying one or more non-zero values ​​in one or more matrices of data; and generating one or more data structures to perform matrix multiplication based at least in part on the one or more non-zero values; This causes the one or more instructions are for causing the compiler to receive one or more first instructions along with sparsity information and compile the one or more first instructions to generate one or more second instructions executable by a graphics processing unit (GPU) to perform the matrix multiplication with the sparsity information.

16. 16. The machine-readable medium of claim 15, wherein identifying includes causing one or more processors to store the one or more non-zero index values ​​in memory accessible to one or more graphics processing cores.

17. 16. The machine-readable medium of claim 15, wherein the system is for generating instructions that cause one or more processors to store the one or more non-zero indices in memory accessible to one or more threads when performing the matrix multiplication in parallel.

18. 16. The machine-readable medium of claim 15, wherein the matrix multiplication is a sparse matrix multiplication operation, and wherein performing the sparse matrix multiplication operation comprises generating executable instructions to be used by one or more drivers to perform the sparse matrix multiplication operation.

19. 16. The machine-readable medium of claim 15, wherein the matrix multiplication is a sparse matrix operation that includes performing a half-precision matrix multiply-accumulate (HMMA) operation, an integer matrix multiply-accumulate (IMMA) operation, a single-precision matrix multiply operation, or a multiply-accumulate operation.

20. 16. The machine-readable medium of claim 15, wherein the one or more instructions to identify cause the compiler to modify a directed acyclic graph (DAG) interface to receive one or more instructions with sparsity information.

21. 16. The machine-readable medium of claim 15, wherein identifying one or more non-zero values ​​in one or more matrices of data comprises causing the compiler to generate operands to be used by one or more graphics processing cores to perform the matrix multiplication involving sparse matrices.

22. Identifying, by a processor, one or more non-zero values ​​in one or more matrices of data; and generating, by the processor, one or more data structures to perform matrix multiplication based at least in part on the one or more non-zero values; generating instructions by a compiler Including, The method comprises: receiving, at the compiler, one or more first instructions along with sparsity information; compiling the one or more first instructions to generate one or more second instructions executable by a graphics processing unit (GPU) to perform the matrix multiplication with the sparsity information; The method further comprises:

23. The method comprises: storing, by the processor, the one or more non-zero index values ​​in memory accessible to one or more graphics processing cores; 23. The method of claim 22, further comprising:

24. The method comprises: generating instructions that cause one or more processors to store the one or more non-zero indexes in memory accessible to one or more threads when performing the matrix multiplication in parallel; 23. The method of claim 22, further comprising:

25. wherein the matrix multiplication is a sparse matrix multiplication operation, and the method comprises: receiving one or more instructions for performing the sparse matrix multiplication operation by the processor; generating, by the processor, executable instructions to be used by one or more drivers of one or more graphics processing units to perform the sparse matrix multiplication operation; 23. The method of claim 22, further comprising:

26. The method comprises: performing, by the processor, a sparse matrix operation including a half-precision matrix multiply-accumulate (HMMA) operation, an integer matrix multiply-accumulate (IMMA) operation, a single-precision matrix multiply operation, or a floating-point multiply-accumulate operation; 23. The method of claim 22, further comprising:

27. The method comprises: modifying, by the compiler, a directed acyclic graph (DAG) interface to receive one or more instructions along with sparsity information for the one or more matrices.

23. The method of claim 22, further comprising:

28. The method comprises: generating operands to be used by one or more graphics processing cores to perform one or more of the matrix multiplications involving sparse matrices, the operands including index information for non-zero elements of the one or more matrices; storing the operands in an arithmetic logic unit (ALU) accessible to the one or more processing cores; 23. The method of claim 22, further comprising:

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