Method, system, and computer program product for managing multiple tracks in a cache

Abstract

A computer program product is provided for managing a plurality of tracks in storage in a cache. An active track data structure indicates a plurality of tracks in the cache having an active status. An active bit in a cache control block for the track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made from the cache control block for the track whether the track is active or inactive to determine processing for the cache control block.

Description

[Technical Field]

[0001] The present invention relates to a computer program product, system, and method for maintaining an active track data structure to determine the active track in a cache for a process. [Background technology]

[0002] A cache management system within a storage controller buffers tracks in a storage device, such as memory, that has been recently accessed as a result of read and write operations on a faster-access storage device than the storage device that stores the requested track. Subsequent read requests for tracks in the faster-access cache memory are returned at a faster rate than returning requested tracks from slower-access storage, thus reducing read latency. The cache management system can also return completion for write requests when modified tracks intended for the storage device are written to the cache memory, but before the modified tracks are written out to a storage device, such as a hard disk drive. Write latency to a storage device is typically significantly longer than the latency of writing to the cache memory. Therefore, using a cache also reduces write latency.

[0003] Storage controller microcode may experience a fault condition due to hardware or software problems. Upon initialization after such a fault, a warm start process may be implemented to collect data, debug, and perform data recovery of cached data, particularly modified data in the cache. To collect debug data and perform data recovery, the warm start recovery process generates a table of active tracks. Active tracks are tracks that have been in some processing state, identified using user counts, lock counts, modification counts, waiters, etc. As part of a warm start or other recovery process, the determined active tracks may be validated, cleaned (or discarded), state-saved, or a combination thereof. Inactive cache tracks cannot be addressed as part of a warm start or recovery.

[0004] To determine the active tracks for inclusion in the active entry table, the warm start process can scan the entire cache by processing all entries in the cache directory (scatter index table, etc.). This scan can be done in parallel, with different processors processing one chunk of the cache directory in parallel until all chunks have been processed. The entire cache directory is processed during a warm start. As the cache size increases, if the number of processors and memory speed do not scale as well, the time to scan the entire cache directory increases linearly as the size of the cache increases.

[0005] There is a need in the art for improved techniques for determining the active track in a cache for a process during a recovery operation. Summary of the Invention

[0006] A computer program product is provided for managing multiple tracks in storage in a cache. An active track data structure indicates multiple tracks in the cache that have an active status. An active bit in a cache control block for the track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination of whether the track is active or inactive is made from the cache control block for the track to determine processing for the cache control block.

[0007] The above embodiment provides an optimization by setting an active bit in the cache control block to indicate that the track is active, which avoids the need to obtain a lock to access the active track data structure to determine whether the active track data structure needs to be locked and to update when there is a status change with respect to the cache control block. Further indicating in the active track data structure whether the track has an active status allows the system to quickly determine whether the track is active from the active track data structure.

[0008] In a further embodiment, the determination from the cache control block of whether the track is active is made in response to obtaining a lock on the cache control block, and the indication that the track is active is made in the active track data structure in response to determining from the cache control block that the track is not active, and the active bit in the cache control block for the track is set to indicate active.

[0009] According to the above embodiment, even if the cache control block indicates that a track is active, an indication that the track is actually active may be made in the active track data structure, which may occur if other information indicates that the track is active even though the cache control block indicates that the track is active. The active bit in the cache control block is set to indicate active to match changes made to the active track data structure, allowing a determination of whether a track is active or inactive without having to lock the active track data structure to determine whether the track is active or inactive.

[0010] In a further embodiment, determining from the cache control block whether the track is active is performed in response to releasing a lock on the cache control block for the track. Usage information for the cache control block is processed to determine whether the track is active in response to an active bit for the track indicating that the track is active. In response to determining that processing the usage information indicates that the track is inactive, indicating in an active track data structure that the track is inactive and setting the active bit in the cache control block for the track to indicate inactivity is performed.

[0011] According to the above embodiment, the usage information independent of the cache control block is used to verify whether the active indication of the active bit in the cache control block is correct based on the independent usage information. Thus, if the active bit indicates active but the usage information indicates inactive, both the active track data structure and the active bit in the cache control block are updated to indicate inactive in order to keep this information synchronized.

[0012] In a further embodiment, the active track data structure includes a bitmap including a plurality of bits for cache control blocks, one bit for each cache control block indicating whether the track identified by the cache control block is active or inactive.

[0013] In a further embodiment, the bits of the bitmap are implemented within a cache line. A lock is obtained for a cache line with a portion of the bitmap including one bit for a cache control block. A bit in the bitmap for the cache control block is set to indicate active or inactive in response to locking the cache line. The lock for the cache line is released in response to setting the bit for the cache control block.

[0014] According to the above embodiment, by implementing multiple bits of the active track data structure in a bitmap within a cache line, multiple portions of the bitmap within different cache lines may be accessed in parallel by independently holding different locks for different cache lines in order for multiple processes to concurrently determine whether different tracks are indicated as active in the active track data structure bitmap. This improves the operation of scanning the active track data structure bitmap to determine the active track during operations where this needs to be determined, such as during recovery.

[0015] In a further embodiment, in response to initiating an operation to demote a track from the cache and an active bit in a cache control block for the track to demote the indication of activity, the track to be demoted is indicated in the active track data structure as inactive, and the active bit in the cache control block for the track to be demoted is set to indicate inactivity.

[0016] In the above embodiment, to ensure that the inactive or active track status is always kept up to date, when demoting a track from the cache, the active track data structure and the active bit in the cache control block are both set to indicate that the bit for the track being demoted is inactive.

[0017] A computer program product is further provided for managing a plurality of tracks in storage within a cache. An active track data structure indicates a plurality of tracks in the cache that have an active status. The active track data structure is processed to determine the indicated active tracks. Recovery operations of state saving, validation, and / or discarding are performed on the determined and indicated active tracks.

[0018] According to the above embodiment, an active track data structure indicating active and inactive tracks is used during recovery operations to determine the active track on which the recovery operation is performed. Using the active track data structure avoids the need to scan and process tracks in cache and other information to determine whether a track is active or not.

[0019] In a further embodiment, in response to determining that there are no available cache control blocks to allocate for the track to be added to the cache, an alternate block structure is created to represent the cache control block for the track to be added to the cache. An indication of the alternate block structure in a cache directory index is made while also indicating the cache control block. The alternate block structure is indicated in a queue. In response to a recovery process, determining the alternate block structure indicated in the queue and removing the determined alternate block structure from the cache directory index is made.

[0020] According to the above embodiment, alternate block structures are used to represent unavailable cache control blocks for adding to the cache. The alternate block structures can be converted to cache control blocks when resources become available for allocation to cache control blocks. The queue of indicated alternate block structures is used during the recovery process to enable the immediate determination of such alternate block structures, also known as fake cache control blocks, to remove from the cache directory index.

[0021] In a further embodiment, the track utilization information in the cache control block for the indicated active track is processed to determine whether the track indicated as active in the active track data structure is active, and the recovery operation is performed with respect to the track indicated as active in the active track data structure that is also determined to be active from the track utilization information.

[0022] According to the above embodiment, even if a track indicated in the cache control block is active, this status can be overridden by processing the track utilization information to determine whether the track is active or inactive so that it is not only indicated as active in the active track data structure, but recovery operations are performed only on tracks that are determined to be active from the track utilization information.

[0023] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 illustrates one embodiment of a computing environment. [Figure 2] FIG. 2 illustrates one embodiment of a cache control block. [Figure 3] FIG. 1 illustrates one embodiment of operations for processing a request to add a track to a cache. [Figure 4] FIG. 1 illustrates one embodiment of an operation for locking a cache control block to access a track in a cache. [Figure 5] FIG. 1 illustrates one embodiment of an operation to release a lock on a cache control block. [Figure 6] FIG. 1 illustrates one embodiment of an operation to demote a cache control block from a cache. [Figure 7] FIG. 1 illustrates one embodiment of an operation for initiating a recovery process. [Figure 8] FIG. 10 illustrates one embodiment of an operation by a processor assigned to chuck cache lines to perform a recovery process to determine an active track. [Figure 9] FIG. 2 illustrates a computing environment in which the components of FIG. 1 are implemented. DETAILED DESCRIPTION OF THE INVENTION

[0025] In a current implementation, the entire cache or cache directory is scanned to determine the active track in the cache for a process during a recovery operation after a failure. The described embodiments provide an improvement to computer caching techniques for determining the active track in a cache as part of an initialization or recovery operation. The described embodiments provide an active track data structure that indicates whether a track in the cache is active. During normal input / output (I / O) operations, an active bit in a cache control block, which indicates whether the active track data structure indicates that the cache control block is active, is used to determine whether to update the active track data structure to indicate active or inactive status. The use of the active bit in the cache control block optimizes processing operations by avoiding the need to obtain a lock to access the active track data structure to determine whether a bit in the active track data structure for a cache control block needs to be updated when there is a status change for the cache control block.

[0026] The described embodiments actively update the active track data structure during generation of I / O operations to the cache to accurately reflect whether a track is inactive or active. During recovery operations such as a warm start, the active track data structure may be processed to determine which active tracks will undergo recovery operations such as state saves, validations, discards, etc.; tracks that are inactive will not undergo recovery operations. The described embodiments avoid the need to scan the entire cache or cache directory to determine which active tracks to process during recovery operations.

[0027] FIG. 1 illustrates one embodiment of a computing environment. Multiple hosts 1021, 1022, . . . , 102 n Hosts 1021, 1022, ..., 1023 may send input / output (I / O) requests to a storage controller 104 over a network 106 to access data (e.g., logical unit numbers, logical devices, logical subsystems, etc.) in multiple volumes 108 in storage 110. The storage controller 104 includes one or more processors 112 and a memory 114 including a cache 116 that caches data for the storage 110. The processor 112 may comprise a separate central processing unit (CPU), a single core or a group of cores on a single CPU, or a group of processing resources on one or more CPUs. The cache 116 is used by the hosts 1021, 1022, ..., 1024. n and buffers data transferred between the volumes 108 in the storage 110 .

[0028] The memory 114 is connected to the hosts 1021, 1022, . . . , 102 n a storage manager 118 for managing the transfer of tracks transferred between the hosts 1021, 1022, . . . , 102; n and a cache manager 120 for managing data transferred between the storage 110 and the cache 116; and a recovery process 121 for performing initialization of the storage controller 104, such as may occur if the storage controller 104 operating system abnormally terminates or is otherwise restarted. A track may comprise any unit of data configured within the storage 110, such as a track, a logical block address (LBA), a storage cell, a group of cells (e.g., a column, row, or array of cells), a sector, a segment, etc., which may be part of a larger group of tracks, such as a volume, a logical device, etc.

[0029] In a specific implementation, such as with the International Business Machines Corporation ("IBM") Z / OS® operating system, each segment may have an associated descriptor called a cache segment control block (CSCB), and one of the CSCBs is cast as a cache control block called a cache directory control block (CDCB). The cache 116 may be divided into 4K segments. Each track in the cache may have up to 17 CSCBs. One of the CSCBs in the track is designated as a cache control block, also called a CDCB (cache directory control block), and holds all track-related control information. There is one cache control block for each track in the cache 116, providing metadata on the track in the cache 116. (Z / OS is a registered trademark of IBM worldwide.)

[0030] The recovery process 121 performs system initialization of the storage controller 104 to recover state information from existing data structures, providing faster initialization and recovery than a cold start. In enterprise storage controllers, such as the IBM DS8000™ storage controller, the recovery process, called a "warm start," can be used as both a debugging mechanism and a recovery method. The recovery process 121 can initiate a state save operation to collect state save data. This state save data can include data structures deemed necessary to analyze the problems and conditions that required recovery. The recovery process 121 can restart data structures within the storage controller 104, rebuild linked lists, and restore the storage controller 104 to a more known state. During recovery, there is a period during which I / O is blocked and must therefore be redriven. (DS8000 is a trademark of IBM worldwide.)

[0031] The cache manager 120 maintains cache management information 122 in memory 114 to manage read (unmodified) and write (modified) tracks in the cache 116. The cache management information 122 includes a least recently used (LRU) cache list 124, a cache directory 126, and a cache control block 200 that indicate which tracks in the cache 116 are to be demoted from the cache 116. i or the segment descriptor index in the cache control block 200 iThe cache 116 may include a cache directory 126 that provides the location of multiple segments in the cache or one segment identified in the cache directory 126; an active track data structure 128 that indicates multiple active tracks in the cache 116; a fake cache control block queue 130 that indicates cache control blocks represented by an alternate data structure when there are no remaining cache control blocks to allocate; and an active track table 132 that is generated during the recovery process 121 to indicate active tracks in the cache 116 for recovery processing.

[0032] In one embodiment, the active track data structure 128 includes a bitmap with one bit for each segment in the cache 116. A track may be allocated multiple segments in the cache 116, and the cache control block 200 for a track may be allocated multiple segments. i a cache control block 200 containing metadata for the track; i can reside in one of the segments allocated to the track. i The bit in the bitmap 128 corresponding to the track can be set to indicate whether the track is active or inactive. i The bits in the Active Track Data Structure 128 bitmap that represent segments that do not have a cache control block 200 are left unused. i This can be implemented in cache lines that need to be locked to process multiple bits to determine if they are active or not.

[0033] The cache directory 126 stores cache control blocks 200 for the tracks in the cache 116. i, and may represent an alternative data structure, also known as a fake cache control block, that represents a cache control block when there are no longer any segments to allocate for a track to be added to the cache. In such cases, a fake cache control block is added to the cache directory 126 so that there is only one pending request to allocate a cache control block for one track. The data for the track for which the fake cache control block is created is stored in the cache control block 200. i The fake cache control block is not stored in the cache 116 until it is allocated to replace the fake cache control block. The fake cache control block is a cache control block 200 with a fake flag 210 and an identifier 202. i The task control block may be implemented as a task control block (TCB) that can hold information.

[0034] In particular embodiments, the cache directory 126 may be implemented as a scatter index table where a track address or cache control block identifier is hashed to an entry in the table. If the cache 116 has data for that cache control block or track, the entry in the cache directory 126 to which the value hashes corresponds to the cache control block 200 for that track. i It will have a pointer to the location in the cache 116 where the segment is stored.

[0035] 1 as program code that is loaded into memory 114 and executed by one or more of processors 112. Alternatively, some or all of the functionality may be implemented as microcode or firmware in a hardware device within storage controller 104, such as in an Application Specific Integrated Circuit (ASIC).

[0036] Storage 110 may comprise one or more storage devices known in the art, such as a solid-state storage device (SSD) comprised of solid-state electronic components, NAND storage cells, Electrically Erasable Programmable Read-Only Memory (EEPROM), flash memory, flash disks, random access memory (RAM) devices, storage-class memory (SCM), phase change memory (PCM), resistive random access memory (RRAM), spin transfer torque memory (STM-RAM), conductive bridging RAM (CBRAM), magnetic hard disk drives, optical disks, tape, etc. Storage devices may be further configured into arrays of devices, such as Just a Bunch of Disks (JBOD), Direct Access Storage Devices (DASD), Redundant Array of Independent Disks (RAID) arrays, virtualization devices, etc. Additionally, storage devices may comprise heterogeneous storage devices from different suppliers or from the same supplier.

[0037] Memory 114 may comprise any suitable volatile or non-volatile memory device, including those described above.

[0038] The network 106 may comprise a storage area network (SAN), a local area network (LAN), a wide area network (WAN), the Internet, an intranet, etc. Alternatively, the hosts 1021, 1022, . . . , 102 n may be connected to the storage controller 104 through a bus interface, such as a Peripheral Component Interconnect (PCI) bus interface and other interfaces known in the art.

[0039] FIG. 2 shows a cache control block 200 for one of the tracks in cache 116. i 2 illustrates an embodiment of one instance of cache control block 200. i Cache control block identifier 202, such as an index value of cache control block 200; i a cache list 204 indicating the track associated with the cache; the position in the LRU cache list 206 at which the track is indicated; an active bit 208 indicating whether the track is indicated as active in the active track data structure 128; a fake flag indicating whether the cache control block 202 is not actually implemented using cache segments, but instead is implemented using an alternative data structure such as a task control block; usage information 212 providing usage statistics about the tracks in the cache, such as active user count, active write count, lock count, modify count, waiters, etc.; and i The information includes, but is not limited to, a demote status 214 that indicates whether the track identified by the cache address is to be demoted from the cache 116. Further information is stored in the cache control block 200, not described herein, which is used to manage the tracks in the cache 116. iIt may be included within.

[0040] The active bit 208 provides an optimization to indicate whether the active track data structure 128 indicates that the track is active. This is done by the cache control block 200. i This allows a process to determine whether a track is active without having to acquire a lock on the cache line to read a bit in active track data structure 128. This allows a process in normal operation to determine whether a bit in active track data structure 128 needs to be reset without having to lock the cache line whose bit it is reading to determine whether the bit is active or inactive.

[0041] Figure 3 shows hosts 1021, 1022, . . . , 102 n 3 illustrates one embodiment of operations performed by cache manager 120 to process a request to add a track to cache 116 from one of the cache control blocks 200. Upon receiving a request to add a track to cache 116 (at block 300), cache manager 120 processes the request. i A determination is made whether there is an available segment in cache 116 to allocate to the new cache control block 200. If there is an available segment (at block 302), a new cache control block 200 is created (at block 304). i The track is allocated (at block 304) and indicated in the cache directory 126 for the track. The track can then be added to the cache 116. The cache control block 200 for the track is then added (at block 302). iIf there are no available segments or cache segment control blocks to allocate to a cache control block, the cache manager 120 creates (at block 306) an alternate block structure, such as a task control block, to represent the cache control block, also known as a fake cache control block. This fake cache control block may be represented in the cache directory 126. A fake flag 210 in the alternate block data structure indicates that the cache control block 200 i The cache control block is set (at block 308) to indicate that it is a fake or placeholder until a segment is available to allocate for it. An alternative block structure for the fake cache control block is indicated (at block 310) in the fake cache control block queue 130.

[0042] 3, information about fake cache control blocks is shown in fake queue 130 to enable fast determination of fake cache control blocks during warm start or recovery processing, which enables fast determination of fake cache control blocks that are discarded because no data exists in cache 116 for the fake cache control blocks.

[0043] FIG. 4 illustrates the cache control block 200 for accessing tracks in the cache 116. i 1 illustrates one embodiment of operations performed by cache manager 120 to lock a cache control block 200. i When the cache manager 120 initiates an operation (at block 400) to acquire a lock on the cache control block 200 for access, i The cache control block 200 acquires (at block 402) a lock on the cache directory 126, which may be acquired through the cache directory 126. iIf the active bit 208 for a cache control block 200 indicates that it is active, i is the correct setting to be accessed, so control ends. If (at block 404) the active bit 208 indicates that it is inactive, and (at block 406) the fake flag 210 indicates that the cache control block, such as the TCB, is not fake, then the cache manager 120 reads the cache control block 200. i A lock is acquired (at block 408) on the cache line containing the bit in the active track data structure 128 for the cache control block 200. The bit in the locked cache line is then stored in the cache control block 200. i and is set (at block 410) to indicate that the track is active because it is being accessed. Cache Control Block 200 i The active bit 208 in the cache control block 200 in the active track data structure 128 is also set to indicate that it is active. i The lock on the cache line containing the set bit is then released. If (at block 406) the fake flag 210 indicates that the cache control block is composed of another data structure rather than a cache segment, the control terminates without taking further action.

[0044] 4, the cache control block 200 is used to access tracks in the cache 116. iWhen the active track data structure 128 is accessed, a determination is made as to whether the active bit in the active track data structure 128 needs to be updated. In a particular embodiment, to determine whether an update is required, an exclusive lock is obtained on the cache line having the bit to be updated by checking the active bit 208 in the cache control block to determine whether the active track data structure 128 actually needs to be updated. This optimization avoids the need to lock the active track data structure 128 and access the bit in the active track data structure 128 by first checking whether the active bit actually needs to be set. Additionally, the active track data structure 128 is updated with the latest information regarding the active status for the track to maintain the active track data structure 128 with the latest information regarding the active track status, further optimizing warm start or recovery operations.

[0045] FIG. 5 shows the cache control block 200 after completing an access to a track in the cache 116. i Cache Control Block 200 i Upon initiating (at block 500) an operation to release the lock for the cache manager 120, the cache manager 120 releases (at block 502) the lock. i If the active bit 208 for the cache control block 200 indicates that it is inactive, iSince access to the cache control block 200 is being relinquished, that is the correct state, and control ends. If (at block 504) the active bit 208 indicates that it is active, the cache manager 120 processes (at block 506) the cache control block usage information 212, such as the active user count, write count, modification flags, etc., to determine whether the track is active based on the usage information 212. (at block 508) i If is in fact active, control exits because the active track data structure 128 indicates an active state.

[0046] If the usage information 212 indicates that the track is not active, negating the active bit 208 (at block 508), the cache manager 120 updates the cache control block 200. i The cache line containing the bit in the active track data structure 128 for the cache is locked (at block 510) and the cache control block 200 i The cache control block 200 sets (at block 512) a bit in the locked cache line for the i The active bit 208 in is set (at block 514) to indicate inactivity. The lock on the cache line is then released (at block 516).

[0047] According to the operational embodiment of FIG. 5, track / cache control block 200 iWhen the cache manager 120 releases access to a track, a determination is made as to whether the active bit in the active track data structure 128 needs to be updated to indicate inactivity by checking the active bit 208 in the cache control block to determine whether the active track data structure 128 actually needs to be updated to indicate inactivity. This optimization avoids the need to lock the active track data structure 128 and access the bit in the active track data structure 128 by checking whether the active bit 208 indicates that the bit in the active track data structure 128 needs to be reset. Furthermore, if the active bit 208 indicates that the track is inactive, the cache manager 120 verifies that other usage information 212 indicates that the track is still active, even though the active track data structure 128 / active bit 208 indicates that the track is not active. If a track is determined to be active, even if the active bit 208 and active track data structure 128 indicate that the track is inactive, the information 208, 212 must be reset to indicate that the track is active for the track to reflect the current status of the track based on the usage information 212. This updates the active track data structure 128 with the most current information regarding the active status for the track to optimize warm start or recovery operations.

[0048] FIG. 6 illustrates the process of removing a cache control block 200 from the cache 116, using the cache list 124, etc., to select the least recently used track to remove from the cache 116. i 1 illustrates one embodiment of operations performed by the cache manager 120 to demote a corresponding track from the cache 116 to the cache control block 200. iand initiating (at block 600) an operation to demote the corresponding track, the cache control block 200 (at block 602) i is inactive, the cache control block 200 i If the active bit 208 for the cache control block 200 indicates i and the track is demoted (at block 604). If the active bit 208 indicates that it is active, and if the fake flag 210 indicates that the cache control block is fake (at block 606), then a lock is acquired on the fake cache control block queue 130 and the fake cache control block indication is removed from the fake queue 130 (at block 608). At this point, the allocated cache control block 200 in the cache 116 is demoted because the cache control block is fake, i.e., is an alternate data structure such as a TCB. i Or, since the track does not exist, control ends without demoting the information.

[0049] (at block 606) Cache Control Block 200 i If the fake flag 210 does not indicate that the top demote is fake, the cache manager 120 sets the cache control block 200 i The cache line containing the bit in the active track data structure 128 for the cache is locked (at block 612) and the cache control block 200 i The bit in the locked cache line for the cache control block 200 is set (at block 614) to indicate inactivity. i The active bit 208 in the cache control block 200 is set (at block 616) to indicate inactivity. The lock on the cache line is then released (at block 618). Control is then passed from the cache 116 to the cache control block 200. iand proceeds to block 604 to demote the corresponding track. The cache directory 126 then i may similarly be updated to indicate that the data is not present in the cache 116 for that item.

[0050] 6, the active track data structure 128 updates the cache control block 200 when the cache control block is demoted from the cache 116. i is updated to show that it is inactive.

[0051] 7 illustrates one embodiment of operations performed by recovery process 121 to initiate recovery or warm start initialization of storage controller 104. Upon initiating recovery (at block 700), chunks of cache lines that implement bits of active track data structure 128 are assigned (at block 702) to processors 112, which allows for parallel and concurrent processing of chunks of cache lines that implement active track data structure 128 to reduce latency of the recovery process. Recovery process 121 also removes (at block 704) from cache directory 126 any fake cache control blocks that are listed in fake cache control block queue 130.

[0052] 8 illustrates one embodiment of the operations performed by each processor 112 assigned a chunk of cache lines with active track data structure 128 to execute recovery process 121. This allows for parallel processing of active track data structure 128 during recovery operations by having different processors 112 execute recovery process 121 to process active track data structure 128 cache lines in parallel. Once one of processors 112 has been assigned a chunk of cache lines with bits of active track data structure 128 to execute recovery process 121 (at block 800), a loop of operations is performed at blocks 802-822 for each cache line i assigned to processor 112. For each cache line i, recovery process 121 performs a loop of operations at blocks 804-820 for each bit j in the cache line. At block 806, the recovery process 121 resets (at block 806) the cache directory lock for the cache control block corresponding to bit j in cache line i to an unlocked state. i If bit j indicates that the track is active, then cache control block usage information 212, including active user count, write count, modification flags, etc., is processed (at block 810) to determine whether the track is actually active.

[0053] (at block 812) Cache Control Block 200 i If bit j is active, then the cache control block is indicated (at block 814) in the active track table 132 for recovery processing such as state saving, validation, discarding, etc. The cache control block 200 corresponding to bit j is then iIf the track is not active based on usage information 212, and if the track is not empty or does not need to be discarded (at block 816), control proceeds to block 814 which points to a cache control block in active track table 132 for recovery processing. If the track is empty or needs to be discarded (at block 816), control proceeds to block 814 which points to a cache control block in active track table 132 for recovery processing. i is discarded from the cache and the cache control block 200 i A reference to a cache 116 location in an entry in the cache directory 126 for that cache is stored in its cache control block 200. i and is removed / invalidated to indicate that no cached data for the track exists. From block 814 or 818, control passes to block 820, which processes the next bit j+1 in cache line i. After processing all bits in cache line i, control passes to block 822, which processes the next cache line in the active track data structure 128 assigned to the processor 112, until all assigned cache lines have been processed.

[0054] All active cache control blocks 200 for the active track i After forming the active track table 132, the recovery process 121 may then determine whether to perform a state save for later debugging, validate the data, clean the data, or discard the data, etc., by creating an active cache control block 200 that indicates the state of the active track table 132. i The recovery process is then performed (at block 822).

[0055] 8 embodiment, concurrently executing recovery process 121 can determine the active cache control block using active track data structure 128 to form active entry table 132. This technique uses active track data structure 128 to determine which tracks are active and then calculates the active cache control block 200. i The technique optimizes the process of determining the active track, and has substantially less latency than techniques that scan all tracks in cache directory 126 to determine the active track. By maintaining one bit for every cache segment in the cache, including cache control block segments, active track data structure 128 requires substantially less scanning than scanning all entries in cache directory 126.

[0056] The present invention may be a system, method, and / or computer program product that may include one or more computer-readable storage media having computer-readable program instructions thereon for causing a processor to perform aspects of the present invention.

[0057] A computer-readable storage medium may be a tangible device that can contain and store instructions for use by an instruction-execution device, such as, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge-in-groove structures on which instructions are recorded, and any suitable combination of the above. Computer-readable storage media, as used herein, are not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, or electrical signals transmitted through other transmission media (e.g., light pulses passing through fiber optic cable) or wires.

[0058] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may comprise copper transmission cables, fiber optic transmission cables, wireless transmission cables, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage on a computer-readable storage medium within the respective computing / processing device.

[0059] The computer-readable program instructions for carrying out the operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java®, Smalltalk®, C++®, or the like, and procedural programming languages ​​such as the "C"® programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, electronic circuitry, including, for example, programmable logic circuitry, a field-programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry to implement aspects of the present invention.

[0060] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0061] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, when executed by the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored in a computer-readable storage medium, and the computer-readable program instructions may direct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium in which the instructions are stored constitutes an article of manufacture containing instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0062] The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps performed on the computer, other programmable data processing apparatus, or other device to generate a computer-implemented process, such that the instructions, executed on the computer, other programmable data processing apparatus, or other device, implement the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0063] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions described in the blocks may occur out of the order described in the figures. For example, two blocks shown in succession may, in fact, be executed substantially in parallel, or the blocks may sometimes be executed in reverse order, depending on the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a dedicated hardware-based system that performs the specified functions or operations or executes a combination of dedicated hardware and computer instructions.

[0064] In the described embodiment, the variables i, j, n, etc., when used with different elements, can refer to the same or different instances of that element.

[0065] Hosts 1021, 1022, ..., 102 nThe computational components of FIG. 1 , including the processor 102 and storage controller 104, may be implemented in one or more computer systems, such as computer system 902 shown in FIG. 9 . Computer system / server 902 may be described in the general context of computer system-executable instructions, such as program modules, executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform particular tasks or implement particular abstract data types. Computer system / server 902 may also be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in local and remote computer system storage media, including memory storage devices.

[0066] As shown in Figure 9, computer system / server 902 is shown in the form of a general-purpose computing device. Components of computer system / server 902 may include, but are not limited to, one or more processors or processing units 904, a system memory 906, and a bus 908 that couples various system components, including the system memory 906, to the processor 904. Bus 908 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example and not limitation, such architectures include an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0067] Computer system / server 902 typically includes a variety of computer system-readable media, which can be any available media that can be accessed by computer system / server 902 and includes both volatile and nonvolatile, removable and non-removable media.

[0068] System memory 906 may include computer-system-readable media in the form of volatile memory, such as random access memory (RAM) 910 and / or cache memory 912. Computer system / server 902 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 913 may be provided for reading from and writing to non-removable, non-volatile magnetic media (not shown, typically referred to as a "hard drive"). Although not shown, a magnetic disk drive may be provided for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), and an optical disk drive may be provided for reading from or writing to removable, non-volatile optical disks, such as CD-ROMs, DVD-ROMs, or other optical media. In such cases, each may be connected to bus 908 by one or more data media interfaces. As further shown and described below, memory 906 may include at least one program product having a set (e.g., at least one) of program modules configured to perform functions of embodiments of the present invention.

[0069] A program / utility 914 having a set (at least one) of program modules 916 may be stored in memory 906, as well as an operating system, one or more application programs, other program modules, and program data, by way of example and not limitation. Each of the operating system, one or more application programs, other program modules, and program data, or any combination thereof, may include implementation aspects of a networked environment. Components of computer 902 may be implemented as program modules 916 that generally perform the functions and / or methods of embodiments of the invention described herein. The system of FIG. 1 may be implemented with one or more computer systems 902, and when the system is implemented with multiple computer systems 902, the computer systems may communicate over a network.

[0070] The computer system / server 902 may also communicate with one or more external devices 918, such as a keyboard, pointing device, display 920, etc.; one or more devices that allow a user to interact with the computer system / server 902; or any device (e.g., a network card, modem, etc.) that allows the computer system / server 902 to communicate with one or more other computing devices, or a combination thereof. Such communication may occur through an input / output (I / O) interface 922. Additionally, the computer system / server 902 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or a combination thereof, via a network adapter 924. As shown, the network adapter 924 communicates with other components of the computer system / server 902 via a bus 908. Although not shown, it should be understood that other hardware and / or software components may be used in conjunction with the computer system / server 902. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems.

[0071] The terms “an embodiment,” “embodiment,” “embodiments,” “the embodiment,” “the embodiment,” “the embodiments,” “one or more embodiments,” “some embodiments,” and “one embodiment” mean “one or more (but not all) embodiments of the present invention(s),” unless expressly specified otherwise.

[0072] The terms "including," "comprising," "having," and variations thereof, unless expressly specified otherwise, mean "including but not limited to."

[0073] An enumerated list of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise.

[0074] The terms "a," "an," and "the" mean "one or more" unless expressly specified otherwise.

[0075] Devices that are in communication with each other are not necessarily in continuous communication with each other unless expressly specified otherwise. Further, devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries.

[0076] A description of an embodiment having several components in communication with each other does not imply that all such components are required, but rather, various optional components are described to illustrate various possible embodiments of the present invention.

[0077] When a single device or article is described herein, it will be readily apparent that two or more devices / articles (whether working together or not) may be used in place of the single device / article. Similarly, when two or more devices or articles (whether working together or not) are described herein, it will be readily apparent that the single device / article may be used in place of two or more devices or articles, or that a different number of devices / articles may be used in place of the number of devices or programs shown. The functionality and / or features of a device may alternatively be embodied by one or more other devices not expressly described as having such functionality / features. As such, other embodiments of the invention need not be included in the device itself.

[0078] The above description of various embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto. The above specification, examples, and data provide a complete description of the manufacture and use of the compositions of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims appended hereto.

Claims

1. A computer program product comprising a computer-readable storage medium having recorded thereon a computer program for managing a plurality of tracks in storage in a cache, the computer program comprising: maintaining an active track data structure indicating a plurality of tracks in said cache having an active status; setting an active bit in a cache control block for a track to indicate active for the track indicated as active in the active track data structure; and responsive to processing the cache control block, causing a computer program product to perform operations including determining from the cache control block for the track whether the track is active or inactive to determine a disposition for the cache control block.

2. 2. The computer program product of claim 1, wherein the processing the cache control block includes acquiring or releasing a lock on the cache control block.

3. The determining from the cache control block whether the track is active is performed in response to obtaining a lock on the cache control block, the operation comprising: In response to determining from the cache control block that the track is not active, indicating in the active track data structure that the track is active; and setting the active bit in the cache control block for the track to indicate that it is active; 10. The computer program product of claim 1, further comprising:

4. The determining from the cache control block whether the track is active is performed in response to releasing a lock on the cache control block for the track, the operation comprising: processing utilization information for the cache control block, whereby, in response to the active bit for the track indicating that the track is active, determining whether the track is active; and in response to determining that the processing of the usage information indicates that the track is inactive; indicating in the active track data structure that the track is inactive; and setting the active bit in the cache control block for the track to indicate inactivity; To execute 10. The computer program product of claim 1, further comprising:

5. 2. The computer program product of claim 1, wherein the active track data structure includes a bitmap including a plurality of bits for a plurality of cache control blocks, one bit for a cache control block indicating whether a track identified by the cache control block is active or inactive.

6. The plurality of bits of the bitmap are implemented in cache lines, and the operation comprises: acquiring a lock on a cache line having a portion of the bitmap that includes a bit for the cache control block; setting the bit in the bitmap for the cache control block to indicate active or inactive in response to locking the cache line; and Releasing the lock on the cache line in response to setting the bit for the cache control block.

6. The computer program product of claim 5, further comprising:

7. The operation is in response to initiating an operation to demote a track from the cache and the active bit in a cache control block for the track to demote its indication of being active; Indicating in the active track data structure that the track to be demoted is inactive; and setting the active bit in the cache control block for the track to be demoted to indicate inactivity; 10. The computer program product of claim 1, further comprising:

8. A computer program product comprising a computer-readable storage medium having recorded thereon a computer program for managing a plurality of tracks in storage in a cache, the computer program, when executed, maintaining an active track data structure indicating a plurality of tracks in said cache having an active status; processing the active track data structure to determine an indicated active track; and and performing operations including performing recovery operations on the determined and indicated active tracks to preserve state, validate, and / or discard the determined and indicated active tracks.

9. 9. The computer program product of claim 8, wherein said processing said active track data structure and said causing said recovery operation to be performed is part of a recovery process during initialization of a system including said cache after a system failure.

10. The operation is creating an alternative block structure to represent a cache control block for the track to be added to the cache in response to determining that there is no available cache control block to allocate for the track to be added to the cache; indicating the alternate block structure in a cache directory index while also indicating the cache control block; indicating said alternative block structure in a queue; determining an alternative block structure indicated in the queue in response to the recovery process; and removing the determined alternative block structure from the cache directory index.

10. The computer program product of claim 9, further comprising:

11. The active track data structure includes a bitmap including a plurality of bits for a plurality of cache control blocks, one bit for each cache control block indicating whether the track identified by the cache control block is active or inactive, and the operation comprises:

9. The computer program product of claim 8, further comprising allocating groups of cache lines containing predetermined portions of the bitmap to different processors that process in parallel to determine an indicated active track, determine whether to save the state, save the state, and remove the indicated active track.

12. The operation is 9. The computer program product of claim 8, further comprising processing track utilization information in a cache control block for the indicated active track, thereby determining whether the track indicated as active in the active track data structure is active, and wherein the recovery operation is performed with respect to a track indicated as active in the active track data structure that is also determined to be active from the track utilization information.

13. 1. A system for managing a plurality of tracks in storage in a cache, comprising: at least one processor; and a computer-readable storage medium having computer-readable program code that, when executed by the at least one processor, maintaining an active track data structure indicating a plurality of tracks in said cache having an active status; setting an active bit in a cache control block for a track to indicate active for the track indicated as active in the active track data structure; and In response to processing the cache control block, the system performs operations including determining from the cache control block for the track whether the track is active or inactive to determine a process for the cache control block.

14. The determining from the cache control block whether the track is active is performed in response to obtaining a lock on the cache control block, the operation comprising: In response to determining from the cache control block that the track is not active, indicating in the active track data structure that the track is active; and setting the active bit in the cache control block for the track to indicate that it is active; The system of claim 13 further comprising:

15. The determining from the cache control block whether the track is active is performed in response to releasing a lock on the cache control block for the track, the operation comprising: processing utilization information for the cache control block, whereby, in response to the active bit for the track indicating that the track is active, determining whether the track is active; and in response to determining that the processing of the usage information indicates that the track is inactive; indicating in the active track data structure that the track is inactive; and setting the active bit in the cache control block for the track to indicate inactivity; To carry out The system of claim 13 further comprising:

16. The active track data structure includes a bitmap including a plurality of bits for a plurality of cache control blocks, one bit for each cache control block indicating whether a track identified by the cache control block is active or inactive, the plurality of bits of the bitmap being implemented within a cache line, and the operation comprising: acquiring a lock on a cache line having a portion of the bitmap that includes a bit for the cache control block; setting the bit in the bitmap for the cache control block to indicate active or inactive in response to locking the cache line; and Releasing the lock on the cache line in response to setting the bit for the cache control block. The system of claim 13 further comprising:

17. The operation is in response to initiating an operation to demote a track from the cache and the active bit in a cache control block for the track to demote its indication of being active; Indicating in the active track data structure that the track to be demoted is inactive; and setting the active bit in the cache control block for the track to be demoted to indicate inactivity; The system of claim 13 further comprising:

18. 1. A system for managing a plurality of tracks in storage in a cache, comprising: at least one processor; and a computer-readable storage medium having computer-readable program code that, when executed by the at least one processor, maintaining an active track data structure indicating a plurality of tracks in said cache having an active status; processing the active track data structure to determine an indicated active track; and and performing operations on the determined and indicated active tracks, including performing recovery operations that preserve, validate, and / or discard the state of the determined and indicated active tracks.

19. The operation is creating an alternative block structure to represent a cache control block for the track to be added to the cache in response to determining that there is no available cache control block to allocate for the track to be added to the cache; indicating the alternate block structure in a cache directory index while also indicating the cache control block; indicating said alternative block structure in a queue; said processing said active track data structure and said performing said recovery operation is part of a recovery process during initialization of a system including said cache after a system failure, and determining an alternate block structure indicated in said queue in response to said recovery process; and removing the determined alternative block structure from the cache directory index.

20. The system of claim 18, further comprising:

20. The operation is 20. The system of claim 18, further comprising processing track utilization information in a cache control block for the indicated active track, thereby determining whether the track indicated as active in the active track data structure is active, and wherein the recovery operation is performed with respect to a track indicated as active in the active track data structure that is also determined to be active from the track utilization information.

21. 1. A method for managing a plurality of tracks in storage in a cache, comprising: maintaining an active track data structure indicating a plurality of tracks in said cache having an active status; setting an active bit in a cache control block for a track to indicate active for said track indicated as active in said active track data structure; determining from the cache control block for the track whether the track is active or inactive to determine a process for the cache control block in response to processing the cache control block; and performing an operation on the established active track, the operation including performing a recovery operation that saves state, validates, and / or discards the established active track.

22. The determining from the cache control block whether the track is active is performed in response to releasing a lock on the cache control block for the track, the operation comprising: processing utilization information for the cache control block, whereby, in response to the active bit for the track indicating that the track is active, determining whether the track is active; and in response to determining that the processing of the usage information indicates that the track is inactive; indicating in the active track data structure that the track is inactive; and setting the active bit in the cache control block for the track to indicate inactivity; To carry out 22. The method of claim 21 further comprising:

23. The active track data structure includes a bitmap including a plurality of bits for a plurality of cache control blocks, one bit for each cache control block indicating whether a track identified by the cache control block is active or inactive, the plurality of bits of the bitmap being implemented within a cache line, and the operation comprising: acquiring a lock on a cache line having a portion of the bitmap that includes a bit for the cache control block; setting the bit in the bitmap for the cache control block to indicate active or inactive in response to locking the cache line; and Releasing the lock on the cache line in response to setting the bit for the cache control block.

22. The method of claim 21 further comprising:

24. in response to a recovery process during initialization of a system including said cache after a system failure; processing the active track data structure to determine an indicated active track; and 22. The method of claim 21, further comprising performing a recovery operation on the determined and indicated active track to perform state saving, validation, and / or discarding.

25. creating an alternative block structure to represent a cache control block for the track to be added to the cache in response to determining that there is no available cache control block to allocate for the track to be added to the cache; indicating the alternate block structure in a cache directory index while also indicating the cache control block; indicating said alternative block structure in a queue; determining an alternative block structure indicated in the queue in response to the recovery process; and removing the determined alternative block structure from the cache directory index.

25. The method of claim 24, further comprising:

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